CPUMR3Db.cpp@ 85972

Last change on this file since 85972 was 85578, checked in by vboxsync, 4 years ago
VMM: Added method for getting at the CPU database. [doxyfix]
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1	/* $Id: CPUMR3Db.cpp 85578 2020-07-31 13:07:50Z vboxsync $ */
2	/** @file
3	* CPUM - CPU database part.
4	*/
5
6	/*
7	* Copyright (C) 2013-2020 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_CPUM
23	#include <VBox/vmm/cpum.h>
24	#include "CPUMInternal.h"
25	#include <VBox/vmm/vm.h>
26	#include <VBox/vmm/mm.h>
27
28	#include <VBox/err.h>
29	#include <iprt/asm-amd64-x86.h>
30	#include <iprt/mem.h>
31	#include <iprt/string.h>
32
33
34	/*********************************************************************************************************************************
35	* Defined Constants And Macros *
36	*********************************************************************************************************************************/
37	/** @def NULL_ALONE
38	* For eliminating an unnecessary data dependency in standalone builds (for
39	* VBoxSVC). */
40	/** @def ZERO_ALONE
41	* For eliminating an unnecessary data size dependency in standalone builds (for
42	* VBoxSVC). */
43	#ifndef CPUM_DB_STANDALONE
44	# define NULL_ALONE(a_aTable) a_aTable
45	# define ZERO_ALONE(a_cTable) a_cTable
46	#else
47	# define NULL_ALONE(a_aTable) NULL
48	# define ZERO_ALONE(a_cTable) 0
49	#endif
50
51
52	/** @name Short macros for the MSR range entries.
53	*
54	* These are rather cryptic, but this is to reduce the attack on the right
55	* margin.
56	*
57	* @{ */
58	/** Alias one MSR onto another (a_uTarget). */
59	#define MAL(a_uMsr, a_szName, a_uTarget) \
60	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_MsrAlias, kCpumMsrWrFn_MsrAlias, 0, a_uTarget, 0, 0, a_szName)
61	/** Functions handles everything. */
62	#define MFN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
63	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
64	/** Functions handles everything, with GP mask. */
65	#define MFG(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrGpMask) \
66	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, a_fWrGpMask, a_szName)
67	/** Function handlers, read-only. */
68	#define MFO(a_uMsr, a_szName, a_enmRdFnSuff) \
69	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_ReadOnly, 0, 0, 0, UINT64_MAX, a_szName)
70	/** Function handlers, ignore all writes. */
71	#define MFI(a_uMsr, a_szName, a_enmRdFnSuff) \
72	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_IgnoreWrite, 0, 0, UINT64_MAX, 0, a_szName)
73	/** Function handlers, with value. */
74	#define MFV(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue) \
75	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, 0, 0, a_szName)
76	/** Function handlers, with write ignore mask. */
77	#define MFW(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_fWrIgnMask) \
78	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, a_fWrIgnMask, 0, a_szName)
79	/** Function handlers, extended version. */
80	#define MFX(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
81	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
82	/** Function handlers, with CPUMCPU storage variable. */
83	#define MFS(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember) \
84	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
85	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, 0, 0, a_szName)
86	/** Function handlers, with CPUMCPU storage variable, ignore mask and GP mask. */
87	#define MFZ(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_CpumCpuMember, a_fWrIgnMask, a_fWrGpMask) \
88	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, \
89	RT_OFFSETOF(CPUMCPU, a_CpumCpuMember), 0, a_fWrIgnMask, a_fWrGpMask, a_szName)
90	/** Read-only fixed value. */
91	#define MVO(a_uMsr, a_szName, a_uValue) \
92	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
93	/** Read-only fixed value, ignores all writes. */
94	#define MVI(a_uMsr, a_szName, a_uValue) \
95	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
96	/** Read fixed value, ignore writes outside GP mask. */
97	#define MVG(a_uMsr, a_szName, a_uValue, a_fWrGpMask) \
98	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, 0, a_fWrGpMask, a_szName)
99	/** Read fixed value, extended version with both GP and ignore masks. */
100	#define MVX(a_uMsr, a_szName, a_uValue, a_fWrIgnMask, a_fWrGpMask) \
101	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
102	/** The short form, no CPUM backing. */
103	#define MSN(a_uMsr, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
104	RINT(a_uMsr, a_uMsr, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
105	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
106
107	/** Range: Functions handles everything. */
108	#define RFN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff) \
109	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, 0, 0, 0, a_szName)
110	/** Range: Read fixed value, read-only. */
111	#define RVO(a_uFirst, a_uLast, a_szName, a_uValue) \
112	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_ReadOnly, 0, a_uValue, 0, UINT64_MAX, a_szName)
113	/** Range: Read fixed value, ignore writes. */
114	#define RVI(a_uFirst, a_uLast, a_szName, a_uValue) \
115	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_FixedValue, kCpumMsrWrFn_IgnoreWrite, 0, a_uValue, UINT64_MAX, 0, a_szName)
116	/** Range: The short form, no CPUM backing. */
117	#define RSN(a_uFirst, a_uLast, a_szName, a_enmRdFnSuff, a_enmWrFnSuff, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask) \
118	RINT(a_uFirst, a_uLast, kCpumMsrRdFn_##a_enmRdFnSuff, kCpumMsrWrFn_##a_enmWrFnSuff, 0, \
119	a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName)
120
121	/** Internal form used by the macros. */
122	#ifdef VBOX_WITH_STATISTICS
123	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
124	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName, \
125	{ 0 }, { 0 }, { 0 }, { 0 } }
126	#else
127	# define RINT(a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName) \
128	{ a_uFirst, a_uLast, a_enmRdFn, a_enmWrFn, a_offCpumCpu, 0, a_uInitOrReadValue, a_fWrIgnMask, a_fWrGpMask, a_szName }
129	#endif
130	/** @} */
131
132	#ifndef CPUM_DB_STANDALONE
133
134	#include "cpus/Intel_Core_i7_6700K.h"
135	#include "cpus/Intel_Core_i7_5600U.h"
136	#include "cpus/Intel_Core_i7_3960X.h"
137	#include "cpus/Intel_Core_i5_3570.h"
138	#include "cpus/Intel_Core_i7_2635QM.h"
139	#include "cpus/Intel_Xeon_X5482_3_20GHz.h"
140	#include "cpus/Intel_Core2_X6800_2_93GHz.h"
141	#include "cpus/Intel_Core2_T7600_2_33GHz.h"
142	#include "cpus/Intel_Core_Duo_T2600_2_16GHz.h"
143	#include "cpus/Intel_Pentium_M_processor_2_00GHz.h"
144	#include "cpus/Intel_Pentium_4_3_00GHz.h"
145	#include "cpus/Intel_Pentium_N3530_2_16GHz.h"
146	#include "cpus/Intel_Atom_330_1_60GHz.h"
147	#include "cpus/Intel_80486.h"
148	#include "cpus/Intel_80386.h"
149	#include "cpus/Intel_80286.h"
150	#include "cpus/Intel_80186.h"
151	#include "cpus/Intel_8086.h"
152
153	#include "cpus/AMD_Ryzen_7_1800X_Eight_Core.h"
154	#include "cpus/AMD_FX_8150_Eight_Core.h"
155	#include "cpus/AMD_Phenom_II_X6_1100T.h"
156	#include "cpus/Quad_Core_AMD_Opteron_2384.h"
157	#include "cpus/AMD_Athlon_64_X2_Dual_Core_4200.h"
158	#include "cpus/AMD_Athlon_64_3200.h"
159
160	#include "cpus/VIA_QuadCore_L4700_1_2_GHz.h"
161
162	#include "cpus/ZHAOXIN_KaiXian_KX_U5581_1_8GHz.h"
163
164	#include "cpus/Hygon_C86_7185_32_core.h"
165
166
167	/**
168	* The database entries.
169	*
170	* 1. The first entry is special. It is the fallback for unknown
171	* processors. Thus, it better be pretty representative.
172	*
173	* 2. The first entry for a CPU vendor is likewise important as it is
174	* the default entry for that vendor.
175	*
176	* Generally we put the most recent CPUs first, since these tend to have the
177	* most complicated and backwards compatible list of MSRs.
178	*/
179	static CPUMDBENTRY const * const g_apCpumDbEntries[] =
180	{
181	#ifdef VBOX_CPUDB_Intel_Core_i7_6700K_h
182	&g_Entry_Intel_Core_i7_6700K,
183	#endif
184	#ifdef VBOX_CPUDB_Intel_Core_i7_5600U_h
185	&g_Entry_Intel_Core_i7_5600U,
186	#endif
187	#ifdef VBOX_CPUDB_Intel_Core_i5_3570_h
188	&g_Entry_Intel_Core_i5_3570,
189	#endif
190	#ifdef VBOX_CPUDB_Intel_Core_i7_3960X_h
191	&g_Entry_Intel_Core_i7_3960X,
192	#endif
193	#ifdef VBOX_CPUDB_Intel_Core_i7_2635QM_h
194	&g_Entry_Intel_Core_i7_2635QM,
195	#endif
196	#ifdef VBOX_CPUDB_Intel_Pentium_N3530_2_16GHz_h
197	&g_Entry_Intel_Pentium_N3530_2_16GHz,
198	#endif
199	#ifdef VBOX_CPUDB_Intel_Atom_330_1_60GHz_h
200	&g_Entry_Intel_Atom_330_1_60GHz,
201	#endif
202	#ifdef VBOX_CPUDB_Intel_Pentium_M_processor_2_00GHz_h
203	&g_Entry_Intel_Pentium_M_processor_2_00GHz,
204	#endif
205	#ifdef VBOX_CPUDB_Intel_Xeon_X5482_3_20GHz_h
206	&g_Entry_Intel_Xeon_X5482_3_20GHz,
207	#endif
208	#ifdef VBOX_CPUDB_Intel_Core2_X6800_2_93GHz_h
209	&g_Entry_Intel_Core2_X6800_2_93GHz,
210	#endif
211	#ifdef VBOX_CPUDB_Intel_Core2_T7600_2_33GHz_h
212	&g_Entry_Intel_Core2_T7600_2_33GHz,
213	#endif
214	#ifdef VBOX_CPUDB_Intel_Core_Duo_T2600_2_16GHz_h
215	&g_Entry_Intel_Core_Duo_T2600_2_16GHz,
216	#endif
217	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
218	&g_Entry_Intel_Pentium_4_3_00GHz,
219	#endif
220	#ifdef VBOX_CPUDB_Intel_Pentium_4_3_00GHz_h
221	&g_Entry_Intel_Pentium_4_3_00GHz,
222	#endif
223	/** @todo pentium, pentium mmx, pentium pro, pentium II, pentium III */
224	#ifdef VBOX_CPUDB_Intel_80486_h
225	&g_Entry_Intel_80486,
226	#endif
227	#ifdef VBOX_CPUDB_Intel_80386_h
228	&g_Entry_Intel_80386,
229	#endif
230	#ifdef VBOX_CPUDB_Intel_80286_h
231	&g_Entry_Intel_80286,
232	#endif
233	#ifdef VBOX_CPUDB_Intel_80186_h
234	&g_Entry_Intel_80186,
235	#endif
236	#ifdef VBOX_CPUDB_Intel_8086_h
237	&g_Entry_Intel_8086,
238	#endif
239
240	#ifdef VBOX_CPUDB_AMD_Ryzen_7_1800X_Eight_Core_h
241	&g_Entry_AMD_Ryzen_7_1800X_Eight_Core,
242	#endif
243	#ifdef VBOX_CPUDB_AMD_FX_8150_Eight_Core_h
244	&g_Entry_AMD_FX_8150_Eight_Core,
245	#endif
246	#ifdef VBOX_CPUDB_AMD_Phenom_II_X6_1100T_h
247	&g_Entry_AMD_Phenom_II_X6_1100T,
248	#endif
249	#ifdef VBOX_CPUDB_Quad_Core_AMD_Opteron_2384_h
250	&g_Entry_Quad_Core_AMD_Opteron_2384,
251	#endif
252	#ifdef VBOX_CPUDB_AMD_Athlon_64_X2_Dual_Core_4200_h
253	&g_Entry_AMD_Athlon_64_X2_Dual_Core_4200,
254	#endif
255	#ifdef VBOX_CPUDB_AMD_Athlon_64_3200_h
256	&g_Entry_AMD_Athlon_64_3200,
257	#endif
258
259	#ifdef VBOX_CPUDB_ZHAOXIN_KaiXian_KX_U5581_1_8GHz_h
260	&g_Entry_ZHAOXIN_KaiXian_KX_U5581_1_8GHz,
261	#endif
262
263	#ifdef VBOX_CPUDB_VIA_QuadCore_L4700_1_2_GHz_h
264	&g_Entry_VIA_QuadCore_L4700_1_2_GHz,
265	#endif
266
267	#ifdef VBOX_CPUDB_NEC_V20_h
268	&g_Entry_NEC_V20,
269	#endif
270
271	#ifdef VBOX_CPUDB_Hygon_C86_7185_32_core_h
272	&g_Entry_Hygon_C86_7185_32_core,
273	#endif
274	};
275
276
277	/**
278	* Returns the number of entries in the CPU database.
279	*
280	* @returns Number of entries.
281	* @sa PFNCPUMDBGETENTRIES
282	*/
283	VMMR3DECL(uint32_t) CPUMR3DbGetEntries(void)
284	{
285	return RT_ELEMENTS(g_apCpumDbEntries);
286	}
287
288
289	/**
290	* Returns CPU database entry for the given index.
291	*
292	* @returns Pointer the CPU database entry, NULL if index is out of bounds.
293	* @param idxCpuDb The index (0..CPUMR3DbGetEntries).
294	* @sa PFNCPUMDBGETENTRYBYINDEX
295	*/
296	VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByIndex(uint32_t idxCpuDb)
297	{
298	AssertReturn(idxCpuDb <= RT_ELEMENTS(g_apCpumDbEntries), NULL);
299	return g_apCpumDbEntries[idxCpuDb];
300	}
301
302
303	/**
304	* Returns CPU database entry with the given name.
305	*
306	* @returns Pointer the CPU database entry, NULL if not found.
307	* @param pszName The name of the profile to return.
308	* @sa PFNCPUMDBGETENTRYBYNAME
309	*/
310	VMMR3DECL(PCCPUMDBENTRY) CPUMR3DbGetEntryByName(const char *pszName)
311	{
312	AssertPtrReturn(pszName, NULL);
313	AssertReturn(*pszName, NULL);
314	for (size_t i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
315	if (strcmp(g_apCpumDbEntries[i]->pszName, pszName) == 0)
316	return g_apCpumDbEntries[i];
317	return NULL;
318	}
319
320
321
322	/**
323	* Binary search used by cpumR3MsrRangesInsert and has some special properties
324	* wrt to mismatches.
325	*
326	* @returns Insert location.
327	* @param paMsrRanges The MSR ranges to search.
328	* @param cMsrRanges The number of MSR ranges.
329	* @param uMsr What to search for.
330	*/
331	static uint32_t cpumR3MsrRangesBinSearch(PCCPUMMSRRANGE paMsrRanges, uint32_t cMsrRanges, uint32_t uMsr)
332	{
333	if (!cMsrRanges)
334	return 0;
335
336	uint32_t iStart = 0;
337	uint32_t iLast = cMsrRanges - 1;
338	for (;;)
339	{
340	uint32_t i = iStart + (iLast - iStart + 1) / 2;
341	if ( uMsr >= paMsrRanges[i].uFirst
342	&& uMsr <= paMsrRanges[i].uLast)
343	return i;
344	if (uMsr < paMsrRanges[i].uFirst)
345	{
346	if (i <= iStart)
347	return i;
348	iLast = i - 1;
349	}
350	else
351	{
352	if (i >= iLast)
353	{
354	if (i < cMsrRanges)
355	i++;
356	return i;
357	}
358	iStart = i + 1;
359	}
360	}
361	}
362
363
364	/**
365	* Ensures that there is space for at least @a cNewRanges in the table,
366	* reallocating the table if necessary.
367	*
368	* @returns Pointer to the MSR ranges on success, NULL on failure. On failure
369	* @a *ppaMsrRanges is freed and set to NULL.
370	* @param pVM The cross context VM structure. If NULL,
371	* use the process heap, otherwise the VM's hyper heap.
372	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
373	* @param cMsrRanges The current number of ranges.
374	* @param cNewRanges The number of ranges to be added.
375	*/
376	static PCPUMMSRRANGE cpumR3MsrRangesEnsureSpace(PVM pVM, PCPUMMSRRANGE *ppaMsrRanges, uint32_t cMsrRanges, uint32_t cNewRanges)
377	{
378	uint32_t cMsrRangesAllocated;
379	if (!pVM)
380	cMsrRangesAllocated = RT_ALIGN_32(cMsrRanges, 16);
381	else
382	{
383	/*
384	* We're using the hyper heap now, but when the range array was copied over to it from
385	* the host-context heap, we only copy the exact size and not the ensured size.
386	* See @bugref{7270}.
387	*/
388	cMsrRangesAllocated = cMsrRanges;
389	}
390	if (cMsrRangesAllocated < cMsrRanges + cNewRanges)
391	{
392	void *pvNew;
393	uint32_t cNew = RT_ALIGN_32(cMsrRanges + cNewRanges, 16);
394	if (pVM)
395	{
396	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
397	Assert(cMsrRanges == pVM->cpum.s.GuestInfo.cMsrRanges);
398
399	size_t cb = cMsrRangesAllocated * sizeof(**ppaMsrRanges);
400	size_t cbNew = cNew * sizeof(**ppaMsrRanges);
401	int rc = MMR3HyperRealloc(pVM, *ppaMsrRanges, cb, 32, MM_TAG_CPUM_MSRS, cbNew, &pvNew);
402	if (RT_FAILURE(rc))
403	{
404	*ppaMsrRanges = NULL;
405	pVM->cpum.s.GuestInfo.paMsrRangesR0 = NIL_RTR0PTR;
406	LogRel(("CPUM: cpumR3MsrRangesEnsureSpace: MMR3HyperRealloc failed. rc=%Rrc\n", rc));
407	return NULL;
408	}
409	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
410	}
411	else
412	{
413	pvNew = RTMemRealloc(ppaMsrRanges, cNew sizeof(**ppaMsrRanges));
414	if (!pvNew)
415	{
416	RTMemFree(*ppaMsrRanges);
417	*ppaMsrRanges = NULL;
418	return NULL;
419	}
420	}
421	*ppaMsrRanges = (PCPUMMSRRANGE)pvNew;
422	}
423
424	if (pVM)
425	{
426	/* Update the R0 pointer. */
427	Assert(ppaMsrRanges == &pVM->cpum.s.GuestInfo.paMsrRangesR3);
428	pVM->cpum.s.GuestInfo.paMsrRangesR0 = MMHyperR3ToR0(pVM, *ppaMsrRanges);
429	}
430
431	return *ppaMsrRanges;
432	}
433
434
435	/**
436	* Inserts a new MSR range in into an sorted MSR range array.
437	*
438	* If the new MSR range overlaps existing ranges, the existing ones will be
439	* adjusted/removed to fit in the new one.
440	*
441	* @returns VBox status code.
442	* @retval VINF_SUCCESS
443	* @retval VERR_NO_MEMORY
444	*
445	* @param pVM The cross context VM structure. If NULL,
446	* use the process heap, otherwise the VM's hyper heap.
447	* @param ppaMsrRanges The variable pointing to the ranges (input/output).
448	* Must be NULL if using the hyper heap.
449	* @param pcMsrRanges The variable holding number of ranges. Must be NULL
450	* if using the hyper heap.
451	* @param pNewRange The new range.
452	*/
453	int cpumR3MsrRangesInsert(PVM pVM, PCPUMMSRRANGE ppaMsrRanges, uint32_t pcMsrRanges, PCCPUMMSRRANGE pNewRange)
454	{
455	Assert(pNewRange->uLast >= pNewRange->uFirst);
456	Assert(pNewRange->enmRdFn > kCpumMsrRdFn_Invalid && pNewRange->enmRdFn < kCpumMsrRdFn_End);
457	Assert(pNewRange->enmWrFn > kCpumMsrWrFn_Invalid && pNewRange->enmWrFn < kCpumMsrWrFn_End);
458
459	/*
460	* Validate and use the VM's MSR ranges array if we are using the hyper heap.
461	*/
462	if (pVM)
463	{
464	AssertReturn(!ppaMsrRanges, VERR_INVALID_PARAMETER);
465	AssertReturn(!pcMsrRanges, VERR_INVALID_PARAMETER);
466
467	ppaMsrRanges = &pVM->cpum.s.GuestInfo.paMsrRangesR3;
468	pcMsrRanges = &pVM->cpum.s.GuestInfo.cMsrRanges;
469	}
470	else
471	{
472	AssertReturn(ppaMsrRanges, VERR_INVALID_POINTER);
473	AssertReturn(pcMsrRanges, VERR_INVALID_POINTER);
474	}
475
476	uint32_t cMsrRanges = *pcMsrRanges;
477	PCPUMMSRRANGE paMsrRanges = *ppaMsrRanges;
478
479	/*
480	* Optimize the linear insertion case where we add new entries at the end.
481	*/
482	if ( cMsrRanges > 0
483	&& paMsrRanges[cMsrRanges - 1].uLast < pNewRange->uFirst)
484	{
485	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
486	if (!paMsrRanges)
487	return VERR_NO_MEMORY;
488	paMsrRanges[cMsrRanges] = *pNewRange;
489	*pcMsrRanges += 1;
490	}
491	else
492	{
493	uint32_t i = cpumR3MsrRangesBinSearch(paMsrRanges, cMsrRanges, pNewRange->uFirst);
494	Assert(i == cMsrRanges \|\| pNewRange->uFirst <= paMsrRanges[i].uLast);
495	Assert(i == 0 \|\| pNewRange->uFirst > paMsrRanges[i - 1].uLast);
496
497	/*
498	* Adding an entirely new entry?
499	*/
500	if ( i >= cMsrRanges
501	\|\| pNewRange->uLast < paMsrRanges[i].uFirst)
502	{
503	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
504	if (!paMsrRanges)
505	return VERR_NO_MEMORY;
506	if (i < cMsrRanges)
507	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
508	paMsrRanges[i] = *pNewRange;
509	*pcMsrRanges += 1;
510	}
511	/*
512	* Replace existing entry?
513	*/
514	else if ( pNewRange->uFirst == paMsrRanges[i].uFirst
515	&& pNewRange->uLast == paMsrRanges[i].uLast)
516	paMsrRanges[i] = *pNewRange;
517	/*
518	* Splitting an existing entry?
519	*/
520	else if ( pNewRange->uFirst > paMsrRanges[i].uFirst
521	&& pNewRange->uLast < paMsrRanges[i].uLast)
522	{
523	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 2);
524	if (!paMsrRanges)
525	return VERR_NO_MEMORY;
526	if (i < cMsrRanges)
527	memmove(&paMsrRanges[i + 2], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
528	paMsrRanges[i + 1] = *pNewRange;
529	paMsrRanges[i + 2] = paMsrRanges[i];
530	paMsrRanges[i ].uLast = pNewRange->uFirst - 1;
531	paMsrRanges[i + 2].uFirst = pNewRange->uLast + 1;
532	*pcMsrRanges += 2;
533	}
534	/*
535	* Complicated scenarios that can affect more than one range.
536	*
537	* The current code does not optimize memmove calls when replacing
538	* one or more existing ranges, because it's tedious to deal with and
539	* not expected to be a frequent usage scenario.
540	*/
541	else
542	{
543	/* Adjust start of first match? */
544	if ( pNewRange->uFirst <= paMsrRanges[i].uFirst
545	&& pNewRange->uLast < paMsrRanges[i].uLast)
546	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
547	else
548	{
549	/* Adjust end of first match? */
550	if (pNewRange->uFirst > paMsrRanges[i].uFirst)
551	{
552	Assert(paMsrRanges[i].uLast >= pNewRange->uFirst);
553	paMsrRanges[i].uLast = pNewRange->uFirst - 1;
554	i++;
555	}
556	/* Replace the whole first match (lazy bird). */
557	else
558	{
559	if (i + 1 < cMsrRanges)
560	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
561	cMsrRanges = *pcMsrRanges -= 1;
562	}
563
564	/* Do the new range affect more ranges? */
565	while ( i < cMsrRanges
566	&& pNewRange->uLast >= paMsrRanges[i].uFirst)
567	{
568	if (pNewRange->uLast < paMsrRanges[i].uLast)
569	{
570	/* Adjust the start of it, then we're done. */
571	paMsrRanges[i].uFirst = pNewRange->uLast + 1;
572	break;
573	}
574
575	/* Remove it entirely. */
576	if (i + 1 < cMsrRanges)
577	memmove(&paMsrRanges[i], &paMsrRanges[i + 1], (cMsrRanges - i - 1) * sizeof(paMsrRanges[0]));
578	cMsrRanges = *pcMsrRanges -= 1;
579	}
580	}
581
582	/* Now, perform a normal insertion. */
583	paMsrRanges = cpumR3MsrRangesEnsureSpace(pVM, ppaMsrRanges, cMsrRanges, 1);
584	if (!paMsrRanges)
585	return VERR_NO_MEMORY;
586	if (i < cMsrRanges)
587	memmove(&paMsrRanges[i + 1], &paMsrRanges[i], (cMsrRanges - i) * sizeof(paMsrRanges[0]));
588	paMsrRanges[i] = *pNewRange;
589	*pcMsrRanges += 1;
590	}
591	}
592
593	return VINF_SUCCESS;
594	}
595
596
597	/**
598	* Reconciles CPUID info with MSRs (selected ones).
599	*
600	* @returns VBox status code.
601	* @param pVM The cross context VM structure.
602	*/
603	int cpumR3MsrReconcileWithCpuId(PVM pVM)
604	{
605	PCCPUMMSRRANGE papToAdd[10];
606	uint32_t cToAdd = 0;
607
608	/*
609	* The IA32_FLUSH_CMD MSR was introduced in MCUs for CVS-2018-3646 and associates.
610	*/
611	if (pVM->cpum.s.GuestFeatures.fFlushCmd && !cpumLookupMsrRange(pVM, MSR_IA32_FLUSH_CMD))
612	{
613	static CPUMMSRRANGE const s_FlushCmd =
614	{
615	/.uFirst =/ MSR_IA32_FLUSH_CMD,
616	/.uLast =/ MSR_IA32_FLUSH_CMD,
617	/.enmRdFn =/ kCpumMsrRdFn_WriteOnly,
618	/.enmWrFn =/ kCpumMsrWrFn_Ia32FlushCmd,
619	/.offCpumCpu =/ UINT16_MAX,
620	/.fReserved =/ 0,
621	/.uValue =/ 0,
622	/.fWrIgnMask =/ 0,
623	/.fWrGpMask =/ ~MSR_IA32_FLUSH_CMD_F_L1D,
624	/.szName = / "IA32_FLUSH_CMD"
625	};
626	papToAdd[cToAdd++] = &s_FlushCmd;
627	}
628
629	/*
630	* The MSR_IA32_ARCH_CAPABILITIES was introduced in various spectre MCUs, or at least
631	* documented in relation to such.
632	*/
633	if (pVM->cpum.s.GuestFeatures.fArchCap && !cpumLookupMsrRange(pVM, MSR_IA32_ARCH_CAPABILITIES))
634	{
635	static CPUMMSRRANGE const s_ArchCaps =
636	{
637	/.uFirst =/ MSR_IA32_ARCH_CAPABILITIES,
638	/.uLast =/ MSR_IA32_ARCH_CAPABILITIES,
639	/.enmRdFn =/ kCpumMsrRdFn_Ia32ArchCapabilities,
640	/.enmWrFn =/ kCpumMsrWrFn_ReadOnly,
641	/.offCpumCpu =/ UINT16_MAX,
642	/.fReserved =/ 0,
643	/.uValue =/ 0,
644	/.fWrIgnMask =/ 0,
645	/.fWrGpMask =/ UINT64_MAX,
646	/.szName = / "IA32_ARCH_CAPABILITIES"
647	};
648	papToAdd[cToAdd++] = &s_ArchCaps;
649	}
650
651	/*
652	* Do the adding.
653	*/
654	for (uint32_t i = 0; i < cToAdd; i++)
655	{
656	PCCPUMMSRRANGE pRange = papToAdd[i];
657	LogRel(("CPUM: MSR/CPUID reconciliation insert: %#010x %s\n", pRange->uFirst, pRange->szName));
658	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
659	pRange);
660	if (RT_FAILURE(rc))
661	return rc;
662	}
663	return VINF_SUCCESS;
664	}
665
666
667	/**
668	* Worker for cpumR3MsrApplyFudge that applies one table.
669	*
670	* @returns VBox status code.
671	* @param pVM The cross context VM structure.
672	* @param paRanges Array of MSRs to fudge.
673	* @param cRanges Number of MSRs in the array.
674	*/
675	static int cpumR3MsrApplyFudgeTable(PVM pVM, PCCPUMMSRRANGE paRanges, size_t cRanges)
676	{
677	for (uint32_t i = 0; i < cRanges; i++)
678	if (!cpumLookupMsrRange(pVM, paRanges[i].uFirst))
679	{
680	LogRel(("CPUM: MSR fudge: %#010x %s\n", paRanges[i].uFirst, paRanges[i].szName));
681	int rc = cpumR3MsrRangesInsert(NULL /* pVM */, &pVM->cpum.s.GuestInfo.paMsrRangesR3, &pVM->cpum.s.GuestInfo.cMsrRanges,
682	&paRanges[i]);
683	if (RT_FAILURE(rc))
684	return rc;
685	}
686	return VINF_SUCCESS;
687	}
688
689
690	/**
691	* Fudges the MSRs that guest are known to access in some odd cases.
692	*
693	* A typical example is a VM that has been moved between different hosts where
694	* for instance the cpu vendor differs.
695	*
696	* Another example is older CPU profiles (e.g. Atom Bonnet) for newer CPUs (e.g.
697	* Atom Silvermont), where features reported thru CPUID aren't present in the
698	* MSRs (e.g. AMD64_TSC_AUX).
699	*
700	*
701	* @returns VBox status code.
702	* @param pVM The cross context VM structure.
703	*/
704	int cpumR3MsrApplyFudge(PVM pVM)
705	{
706	/*
707	* Basic.
708	*/
709	static CPUMMSRRANGE const s_aFudgeMsrs[] =
710	{
711	MFO(0x00000000, "IA32_P5_MC_ADDR", Ia32P5McAddr),
712	MFX(0x00000001, "IA32_P5_MC_TYPE", Ia32P5McType, Ia32P5McType, 0, 0, UINT64_MAX),
713	MVO(0x00000017, "IA32_PLATFORM_ID", 0),
714	MFN(0x0000001b, "IA32_APIC_BASE", Ia32ApicBase, Ia32ApicBase),
715	MVI(0x0000008b, "BIOS_SIGN", 0),
716	MFX(0x000000fe, "IA32_MTRRCAP", Ia32MtrrCap, ReadOnly, 0x508, 0, 0),
717	MFX(0x00000179, "IA32_MCG_CAP", Ia32McgCap, ReadOnly, 0x005, 0, 0),
718	MFX(0x0000017a, "IA32_MCG_STATUS", Ia32McgStatus, Ia32McgStatus, 0, ~(uint64_t)UINT32_MAX, 0),
719	MFN(0x000001a0, "IA32_MISC_ENABLE", Ia32MiscEnable, Ia32MiscEnable),
720	MFN(0x000001d9, "IA32_DEBUGCTL", Ia32DebugCtl, Ia32DebugCtl),
721	MFO(0x000001db, "P6_LAST_BRANCH_FROM_IP", P6LastBranchFromIp),
722	MFO(0x000001dc, "P6_LAST_BRANCH_TO_IP", P6LastBranchToIp),
723	MFO(0x000001dd, "P6_LAST_INT_FROM_IP", P6LastIntFromIp),
724	MFO(0x000001de, "P6_LAST_INT_TO_IP", P6LastIntToIp),
725	MFS(0x00000277, "IA32_PAT", Ia32Pat, Ia32Pat, Guest.msrPAT),
726	MFZ(0x000002ff, "IA32_MTRR_DEF_TYPE", Ia32MtrrDefType, Ia32MtrrDefType, GuestMsrs.msr.MtrrDefType, 0, ~(uint64_t)0xc07),
727	MFN(0x00000400, "IA32_MCi_CTL_STATUS_ADDR_MISC", Ia32McCtlStatusAddrMiscN, Ia32McCtlStatusAddrMiscN),
728	};
729	int rc = cpumR3MsrApplyFudgeTable(pVM, &s_aFudgeMsrs[0], RT_ELEMENTS(s_aFudgeMsrs));
730	AssertLogRelRCReturn(rc, rc);
731
732	/*
733	* XP might mistake opterons and other newer CPUs for P4s.
734	*/
735	if (pVM->cpum.s.GuestFeatures.uFamily >= 0xf)
736	{
737	static CPUMMSRRANGE const s_aP4FudgeMsrs[] =
738	{
739	MFX(0x0000002c, "P4_EBC_FREQUENCY_ID", IntelP4EbcFrequencyId, IntelP4EbcFrequencyId, 0xf12010f, UINT64_MAX, 0),
740	};
741	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aP4FudgeMsrs[0], RT_ELEMENTS(s_aP4FudgeMsrs));
742	AssertLogRelRCReturn(rc, rc);
743	}
744
745	if (pVM->cpum.s.GuestFeatures.fRdTscP)
746	{
747	static CPUMMSRRANGE const s_aRdTscPFudgeMsrs[] =
748	{
749	MFX(0xc0000103, "AMD64_TSC_AUX", Amd64TscAux, Amd64TscAux, 0, 0, ~(uint64_t)UINT32_MAX),
750	};
751	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aRdTscPFudgeMsrs[0], RT_ELEMENTS(s_aRdTscPFudgeMsrs));
752	AssertLogRelRCReturn(rc, rc);
753	}
754
755	/*
756	* Windows 10 incorrectly writes to MSR_IA32_TSX_CTRL without checking
757	* CPUID.ARCH_CAP(EAX=7h,ECX=0):EDX[bit 29] or the MSR feature bits in
758	* MSR_IA32_ARCH_CAPABILITIES[bit 7], see @bugref{9630}.
759	* Ignore writes to this MSR and return 0 on reads.
760	*/
761	if (pVM->cpum.s.GuestFeatures.fArchCap)
762	{
763	static CPUMMSRRANGE const s_aTsxCtrl[] =
764	{
765	MVI(MSR_IA32_TSX_CTRL, "IA32_TSX_CTRL", 0),
766	};
767	rc = cpumR3MsrApplyFudgeTable(pVM, &s_aTsxCtrl[0], RT_ELEMENTS(s_aTsxCtrl));
768	AssertLogRelRCReturn(rc, rc);
769	}
770
771	return rc;
772	}
773
774
775	/**
776	* Do we consider @a enmConsider a better match for @a enmTarget than
777	* @a enmFound?
778	*
779	* Only called when @a enmConsider isn't exactly what we're looking for.
780	*
781	* @returns true/false.
782	* @param enmConsider The new microarch to consider.
783	* @param enmTarget The target microarch.
784	* @param enmFound The best microarch match we've found thus far.
785	*/
786	DECLINLINE(bool) cpumR3DbIsBetterMarchMatch(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
787	{
788	Assert(enmConsider != enmTarget);
789
790	/*
791	* If we've got an march match, don't bother with enmConsider.
792	*/
793	if (enmFound == enmTarget)
794	return false;
795
796	/*
797	* Found is below: Pick 'consider' if it's closer to the target or above it.
798	*/
799	if (enmFound < enmTarget)
800	return enmConsider > enmFound;
801
802	/*
803	* Found is above: Pick 'consider' if it's also above (paranoia: or equal)
804	* and but closer to the target.
805	*/
806	return enmConsider >= enmTarget && enmConsider < enmFound;
807	}
808
809
810	/**
811	* Do we consider @a enmConsider a better match for @a enmTarget than
812	* @a enmFound?
813	*
814	* Only called for intel family 06h CPUs.
815	*
816	* @returns true/false.
817	* @param enmConsider The new microarch to consider.
818	* @param enmTarget The target microarch.
819	* @param enmFound The best microarch match we've found thus far.
820	*/
821	static bool cpumR3DbIsBetterIntelFam06Match(CPUMMICROARCH enmConsider, CPUMMICROARCH enmTarget, CPUMMICROARCH enmFound)
822	{
823	/* Check intel family 06h claims. */
824	AssertReturn(enmConsider >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmConsider <= kCpumMicroarch_Intel_P6_Core_Atom_End,
825	false);
826	AssertReturn(enmTarget >= kCpumMicroarch_Intel_P6_Core_Atom_First && enmTarget <= kCpumMicroarch_Intel_P6_Core_Atom_End,
827	false);
828
829	/* Put matches out of the way. */
830	if (enmConsider == enmTarget)
831	return true;
832	if (enmFound == enmTarget)
833	return false;
834
835	/* If found isn't a family 06h march, whatever we're considering must be a better choice. */
836	if ( enmFound < kCpumMicroarch_Intel_P6_Core_Atom_First
837	\|\| enmFound > kCpumMicroarch_Intel_P6_Core_Atom_End)
838	return true;
839
840	/*
841	* The family 06h stuff is split into three categories:
842	* - Common P6 heritage
843	* - Core
844	* - Atom
845	*
846	* Determin which of the three arguments are Atom marchs, because that's
847	* all we need to make the right choice.
848	*/
849	bool const fConsiderAtom = enmConsider >= kCpumMicroarch_Intel_Atom_First;
850	bool const fTargetAtom = enmTarget >= kCpumMicroarch_Intel_Atom_First;
851	bool const fFoundAtom = enmFound >= kCpumMicroarch_Intel_Atom_First;
852
853	/*
854	* Want atom:
855	*/
856	if (fTargetAtom)
857	{
858	/* Pick the atom if we've got one of each.*/
859	if (fConsiderAtom != fFoundAtom)
860	return fConsiderAtom;
861	/* If we haven't got any atoms under consideration, pick a P6 or the earlier core.
862	Note! Not entirely sure Dothan is the best choice, but it'll do for now. */
863	if (!fConsiderAtom)
864	{
865	if (enmConsider > enmFound)
866	return enmConsider <= kCpumMicroarch_Intel_P6_M_Dothan;
867	return enmFound > kCpumMicroarch_Intel_P6_M_Dothan;
868	}
869	/* else: same category, default comparison rules. */
870	Assert(fConsiderAtom && fFoundAtom);
871	}
872	/*
873	* Want non-atom:
874	*/
875	/* Pick the non-atom if we've got one of each. */
876	else if (fConsiderAtom != fFoundAtom)
877	return fFoundAtom;
878	/* If we've only got atoms under consideration, pick the older one just to pick something. */
879	else if (fConsiderAtom)
880	return enmConsider < enmFound;
881	else
882	Assert(!fConsiderAtom && !fFoundAtom);
883
884	/*
885	* Same basic category. Do same compare as caller.
886	*/
887	return cpumR3DbIsBetterMarchMatch(enmConsider, enmTarget, enmFound);
888	}
889
890
891	int cpumR3DbGetCpuInfo(const char *pszName, PCPUMINFO pInfo)
892	{
893	CPUMDBENTRY const *pEntry = NULL;
894	int rc;
895
896	if (!strcmp(pszName, "host"))
897	{
898	/*
899	* Create a CPU database entry for the host CPU. This means getting
900	* the CPUID bits from the real CPU and grabbing the closest matching
901	* database entry for MSRs.
902	*/
903	rc = CPUMR3CpuIdDetectUnknownLeafMethod(&pInfo->enmUnknownCpuIdMethod, &pInfo->DefCpuId);
904	if (RT_FAILURE(rc))
905	return rc;
906	rc = CPUMR3CpuIdCollectLeaves(&pInfo->paCpuIdLeavesR3, &pInfo->cCpuIdLeaves);
907	if (RT_FAILURE(rc))
908	return rc;
909	pInfo->fMxCsrMask = CPUMR3DeterminHostMxCsrMask();
910
911	/* Lookup database entry for MSRs. */
912	CPUMCPUVENDOR const enmVendor = CPUMR3CpuIdDetectVendorEx(pInfo->paCpuIdLeavesR3[0].uEax,
913	pInfo->paCpuIdLeavesR3[0].uEbx,
914	pInfo->paCpuIdLeavesR3[0].uEcx,
915	pInfo->paCpuIdLeavesR3[0].uEdx);
916	uint32_t const uStd1Eax = pInfo->paCpuIdLeavesR3[1].uEax;
917	uint8_t const uFamily = ASMGetCpuFamily(uStd1Eax);
918	uint8_t const uModel = ASMGetCpuModel(uStd1Eax, enmVendor == CPUMCPUVENDOR_INTEL);
919	uint8_t const uStepping = ASMGetCpuStepping(uStd1Eax);
920	CPUMMICROARCH const enmMicroarch = CPUMR3CpuIdDetermineMicroarchEx(enmVendor, uFamily, uModel, uStepping);
921
922	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
923	{
924	CPUMDBENTRY const *pCur = g_apCpumDbEntries[i];
925	if ((CPUMCPUVENDOR)pCur->enmVendor == enmVendor)
926	{
927	/* Match against Family, Microarch, model and stepping. Except
928	for family, always match the closer with preference given to
929	the later/older ones. */
930	if (pCur->uFamily == uFamily)
931	{
932	if (pCur->enmMicroarch == enmMicroarch)
933	{
934	if (pCur->uModel == uModel)
935	{
936	if (pCur->uStepping == uStepping)
937	{
938	/* Perfect match. */
939	pEntry = pCur;
940	break;
941	}
942
943	if ( !pEntry
944	\|\| pEntry->uModel != uModel
945	\|\| pEntry->enmMicroarch != enmMicroarch
946	\|\| pEntry->uFamily != uFamily)
947	pEntry = pCur;
948	else if ( pCur->uStepping >= uStepping
949	? pCur->uStepping < pEntry->uStepping \|\| pEntry->uStepping < uStepping
950	: pCur->uStepping > pEntry->uStepping)
951	pEntry = pCur;
952	}
953	else if ( !pEntry
954	\|\| pEntry->enmMicroarch != enmMicroarch
955	\|\| pEntry->uFamily != uFamily)
956	pEntry = pCur;
957	else if ( pCur->uModel >= uModel
958	? pCur->uModel < pEntry->uModel \|\| pEntry->uModel < uModel
959	: pCur->uModel > pEntry->uModel)
960	pEntry = pCur;
961	}
962	else if ( !pEntry
963	\|\| pEntry->uFamily != uFamily)
964	pEntry = pCur;
965	/* Special march matching rules applies to intel family 06h. */
966	else if ( enmVendor == CPUMCPUVENDOR_INTEL
967	&& uFamily == 6
968	? cpumR3DbIsBetterIntelFam06Match(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch)
969	: cpumR3DbIsBetterMarchMatch(pCur->enmMicroarch, enmMicroarch, pEntry->enmMicroarch))
970	pEntry = pCur;
971	}
972	/* We don't do closeness matching on family, we use the first
973	entry for the CPU vendor instead. (P4 workaround.) */
974	else if (!pEntry)
975	pEntry = pCur;
976	}
977	}
978
979	if (pEntry)
980	LogRel(("CPUM: Matched host CPU %s %#x/%#x/%#x %s with CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
981	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
982	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor), pEntry->uFamily, pEntry->uModel,
983	pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
984	else
985	{
986	pEntry = g_apCpumDbEntries[0];
987	LogRel(("CPUM: No matching processor database entry %s %#x/%#x/%#x %s, falling back on '%s'\n",
988	CPUMR3CpuVendorName(enmVendor), uFamily, uModel, uStepping, CPUMR3MicroarchName(enmMicroarch),
989	pEntry->pszName));
990	}
991	}
992	else
993	{
994	/*
995	* We're supposed to be emulating a specific CPU that is included in
996	* our CPU database. The CPUID tables needs to be copied onto the
997	* heap so the caller can modify them and so they can be freed like
998	* in the host case above.
999	*/
1000	for (unsigned i = 0; i < RT_ELEMENTS(g_apCpumDbEntries); i++)
1001	if (!strcmp(pszName, g_apCpumDbEntries[i]->pszName))
1002	{
1003	pEntry = g_apCpumDbEntries[i];
1004	break;
1005	}
1006	if (!pEntry)
1007	{
1008	LogRel(("CPUM: Cannot locate any CPU by the name '%s'\n", pszName));
1009	return VERR_CPUM_DB_CPU_NOT_FOUND;
1010	}
1011
1012	pInfo->cCpuIdLeaves = pEntry->cCpuIdLeaves;
1013	if (pEntry->cCpuIdLeaves)
1014	{
1015	/* Must allocate a multiple of 16 here, matching cpumR3CpuIdEnsureSpace. */
1016	size_t cbExtra = sizeof(pEntry->paCpuIdLeaves[0]) * (RT_ALIGN(pEntry->cCpuIdLeaves, 16) - pEntry->cCpuIdLeaves);
1017	pInfo->paCpuIdLeavesR3 = (PCPUMCPUIDLEAF)RTMemDupEx(pEntry->paCpuIdLeaves,
1018	sizeof(pEntry->paCpuIdLeaves[0]) * pEntry->cCpuIdLeaves,
1019	cbExtra);
1020	if (!pInfo->paCpuIdLeavesR3)
1021	return VERR_NO_MEMORY;
1022	}
1023	else
1024	pInfo->paCpuIdLeavesR3 = NULL;
1025
1026	pInfo->enmUnknownCpuIdMethod = pEntry->enmUnknownCpuId;
1027	pInfo->DefCpuId = pEntry->DefUnknownCpuId;
1028	pInfo->fMxCsrMask = pEntry->fMxCsrMask;
1029
1030	LogRel(("CPUM: Using CPU DB entry '%s' (%s %#x/%#x/%#x %s)\n",
1031	pEntry->pszName, CPUMR3CpuVendorName((CPUMCPUVENDOR)pEntry->enmVendor),
1032	pEntry->uFamily, pEntry->uModel, pEntry->uStepping, CPUMR3MicroarchName(pEntry->enmMicroarch) ));
1033	}
1034
1035	pInfo->fMsrMask = pEntry->fMsrMask;
1036	pInfo->iFirstExtCpuIdLeaf = 0; /* Set by caller. */
1037	pInfo->uScalableBusFreq = pEntry->uScalableBusFreq;
1038	pInfo->paCpuIdLeavesR0 = NIL_RTR0PTR;
1039	pInfo->paMsrRangesR0 = NIL_RTR0PTR;
1040
1041	/*
1042	* Copy the MSR range.
1043	*/
1044	uint32_t cMsrs = 0;
1045	PCPUMMSRRANGE paMsrs = NULL;
1046
1047	PCCPUMMSRRANGE pCurMsr = pEntry->paMsrRanges;
1048	uint32_t cLeft = pEntry->cMsrRanges;
1049	while (cLeft-- > 0)
1050	{
1051	rc = cpumR3MsrRangesInsert(NULL /* pVM */, &paMsrs, &cMsrs, pCurMsr);
1052	if (RT_FAILURE(rc))
1053	{
1054	Assert(!paMsrs); /* The above function frees this. */
1055	RTMemFree(pInfo->paCpuIdLeavesR3);
1056	pInfo->paCpuIdLeavesR3 = NULL;
1057	return rc;
1058	}
1059	pCurMsr++;
1060	}
1061
1062	pInfo->paMsrRangesR3 = paMsrs;
1063	pInfo->cMsrRanges = cMsrs;
1064	return VINF_SUCCESS;
1065	}
1066
1067
1068	/**
1069	* Insert an MSR range into the VM.
1070	*
1071	* If the new MSR range overlaps existing ranges, the existing ones will be
1072	* adjusted/removed to fit in the new one.
1073	*
1074	* @returns VBox status code.
1075	* @param pVM The cross context VM structure.
1076	* @param pNewRange Pointer to the MSR range being inserted.
1077	*/
1078	VMMR3DECL(int) CPUMR3MsrRangesInsert(PVM pVM, PCCPUMMSRRANGE pNewRange)
1079	{
1080	AssertReturn(pVM, VERR_INVALID_PARAMETER);
1081	AssertReturn(pNewRange, VERR_INVALID_PARAMETER);
1082
1083	return cpumR3MsrRangesInsert(pVM, NULL /* ppaMsrRanges /, NULL / pcMsrRanges */, pNewRange);
1084	}
1085
1086
1087	/**
1088	* Register statistics for the MSRs.
1089	*
1090	* This must not be called before the MSRs have been finalized and moved to the
1091	* hyper heap.
1092	*
1093	* @returns VBox status code.
1094	* @param pVM The cross context VM structure.
1095	*/
1096	int cpumR3MsrRegStats(PVM pVM)
1097	{
1098	/*
1099	* Global statistics.
1100	*/
1101	PCPUM pCpum = &pVM->cpum.s;
1102	STAM_REL_REG(pVM, &pCpum->cMsrReads, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Reads",
1103	STAMUNIT_OCCURENCES, "All RDMSRs making it to CPUM.");
1104	STAM_REL_REG(pVM, &pCpum->cMsrReadsRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsRaisingGP",
1105	STAMUNIT_OCCURENCES, "RDMSR raising #GPs, except unknown MSRs.");
1106	STAM_REL_REG(pVM, &pCpum->cMsrReadsUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/ReadsUnknown",
1107	STAMUNIT_OCCURENCES, "RDMSR on unknown MSRs (raises #GP).");
1108	STAM_REL_REG(pVM, &pCpum->cMsrWrites, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/Writes",
1109	STAMUNIT_OCCURENCES, "All WRMSRs making it to CPUM.");
1110	STAM_REL_REG(pVM, &pCpum->cMsrWritesRaiseGp, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesRaisingGP",
1111	STAMUNIT_OCCURENCES, "WRMSR raising #GPs, except unknown MSRs.");
1112	STAM_REL_REG(pVM, &pCpum->cMsrWritesToIgnoredBits, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesToIgnoredBits",
1113	STAMUNIT_OCCURENCES, "Writing of ignored bits.");
1114	STAM_REL_REG(pVM, &pCpum->cMsrWritesUnknown, STAMTYPE_COUNTER, "/CPUM/MSR-Totals/WritesUnknown",
1115	STAMUNIT_OCCURENCES, "WRMSR on unknown MSRs (raises #GP).");
1116
1117
1118	# ifdef VBOX_WITH_STATISTICS
1119	/*
1120	* Per range.
1121	*/
1122	PCPUMMSRRANGE paRanges = pVM->cpum.s.GuestInfo.paMsrRangesR3;
1123	uint32_t cRanges = pVM->cpum.s.GuestInfo.cMsrRanges;
1124	for (uint32_t i = 0; i < cRanges; i++)
1125	{
1126	char szName[160];
1127	ssize_t cchName;
1128
1129	if (paRanges[i].uFirst == paRanges[i].uLast)
1130	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%s",
1131	paRanges[i].uFirst, paRanges[i].szName);
1132	else
1133	cchName = RTStrPrintf(szName, sizeof(szName), "/CPUM/MSRs/%#010x-%#010x-%s",
1134	paRanges[i].uFirst, paRanges[i].uLast, paRanges[i].szName);
1135
1136	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-reads");
1137	STAMR3Register(pVM, &paRanges[i].cReads, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, szName, STAMUNIT_OCCURENCES, "RDMSR");
1138
1139	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-writes");
1140	STAMR3Register(pVM, &paRanges[i].cWrites, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR");
1141
1142	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-GPs");
1143	STAMR3Register(pVM, &paRanges[i].cGps, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "#GPs");
1144
1145	RTStrCopy(&szName[cchName], sizeof(szName) - cchName, "-ign-bits-writes");
1146	STAMR3Register(pVM, &paRanges[i].cIgnoredBits, STAMTYPE_COUNTER, STAMVISIBILITY_USED, szName, STAMUNIT_OCCURENCES, "WRMSR w/ ignored bits");
1147	}
1148	# endif /* VBOX_WITH_STATISTICS */
1149
1150	return VINF_SUCCESS;
1151	}
1152
1153	#endif /* !CPUM_DB_STANDALONE */
1154

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source: vbox/trunk/src/VBox/VMM/VMMR3/CPUMR3Db.cpp@ 85972

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