VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 58591

Last change on this file since 58591 was 58126, checked in by vboxsync, 9 years ago

VMM: Fixed almost all the Doxygen warnings.

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1/* $Id: DBGFDisas.cpp 58126 2015-10-08 20:59:48Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, Disassembler.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*********************************************************************************************************************************
20* Header Files *
21*********************************************************************************************************************************/
22#define LOG_GROUP LOG_GROUP_DBGF
23#include <VBox/vmm/dbgf.h>
24#include <VBox/vmm/selm.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/hm.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/cpum.h>
29#ifdef VBOX_WITH_RAW_MODE
30# include <VBox/vmm/patm.h>
31#endif
32#include "DBGFInternal.h"
33#include <VBox/dis.h>
34#include <VBox/err.h>
35#include <VBox/param.h>
36#include <VBox/vmm/vm.h>
37#include <VBox/vmm/uvm.h>
38#include "internal/pgm.h"
39
40#include <VBox/log.h>
41#include <iprt/assert.h>
42#include <iprt/string.h>
43#include <iprt/alloca.h>
44#include <iprt/ctype.h>
45
46
47/*********************************************************************************************************************************
48* Structures and Typedefs *
49*********************************************************************************************************************************/
50/**
51 * Structure used when disassembling and instructions in DBGF.
52 * This is used so the reader function can get the stuff it needs.
53 */
54typedef struct
55{
56 /** The core structure. */
57 DISCPUSTATE Cpu;
58 /** The cross context VM structure. */
59 PVM pVM;
60 /** The cross context virtual CPU structure. */
61 PVMCPU pVCpu;
62 /** The address space for resolving symbol. */
63 RTDBGAS hDbgAs;
64 /** Pointer to the first byte in the segment. */
65 RTGCUINTPTR GCPtrSegBase;
66 /** Pointer to the byte after the end of the segment. (might have wrapped!) */
67 RTGCUINTPTR GCPtrSegEnd;
68 /** The size of the segment minus 1. */
69 RTGCUINTPTR cbSegLimit;
70 /** The guest paging mode. */
71 PGMMODE enmMode;
72 /** Pointer to the current page - R3 Ptr. */
73 void const *pvPageR3;
74 /** Pointer to the current page - GC Ptr. */
75 RTGCPTR GCPtrPage;
76 /** Pointer to the next instruction (relative to GCPtrSegBase). */
77 RTGCUINTPTR GCPtrNext;
78 /** The lock information that PGMPhysReleasePageMappingLock needs. */
79 PGMPAGEMAPLOCK PageMapLock;
80 /** Whether the PageMapLock is valid or not. */
81 bool fLocked;
82 /** 64 bits mode or not. */
83 bool f64Bits;
84 /** Read original unpatched bytes from the patch manager. */
85 bool fUnpatchedBytes;
86 /** Set when fUnpatchedBytes is active and we encounter patched bytes. */
87 bool fPatchedInstr;
88} DBGFDISASSTATE, *PDBGFDISASSTATE;
89
90
91/*********************************************************************************************************************************
92* Internal Functions *
93*********************************************************************************************************************************/
94static FNDISREADBYTES dbgfR3DisasInstrRead;
95
96
97
98/**
99 * Calls the disassembler with the proper reader functions and such for disa
100 *
101 * @returns VBox status code.
102 * @param pVM The cross context VM structure.
103 * @param pVCpu The cross context virtual CPU structure.
104 * @param pSelInfo The selector info.
105 * @param enmMode The guest paging mode.
106 * @param fFlags DBGF_DISAS_FLAGS_XXX.
107 * @param GCPtr The GC pointer (selector offset).
108 * @param pState The disas CPU state.
109 */
110static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
111 RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
112{
113 pState->GCPtrSegBase = pSelInfo->GCPtrBase;
114 pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
115 pState->cbSegLimit = pSelInfo->cbLimit;
116 pState->enmMode = enmMode;
117 pState->GCPtrPage = 0;
118 pState->pvPageR3 = NULL;
119 pState->hDbgAs = !HMIsEnabled(pVM)
120 ? DBGF_AS_RC_AND_GC_GLOBAL
121 : DBGF_AS_GLOBAL;
122 pState->pVM = pVM;
123 pState->pVCpu = pVCpu;
124 pState->fLocked = false;
125 pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
126#ifdef VBOX_WITH_RAW_MODE
127 pState->fUnpatchedBytes = RT_BOOL(fFlags & DBGF_DISAS_FLAGS_UNPATCHED_BYTES);
128 pState->fPatchedInstr = false;
129#endif
130
131 DISCPUMODE enmCpuMode;
132 switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
133 {
134 default:
135 AssertFailed();
136 case DBGF_DISAS_FLAGS_DEFAULT_MODE:
137 enmCpuMode = pState->f64Bits
138 ? DISCPUMODE_64BIT
139 : pSelInfo->u.Raw.Gen.u1DefBig
140 ? DISCPUMODE_32BIT
141 : DISCPUMODE_16BIT;
142 break;
143 case DBGF_DISAS_FLAGS_16BIT_MODE:
144 case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
145 enmCpuMode = DISCPUMODE_16BIT;
146 break;
147 case DBGF_DISAS_FLAGS_32BIT_MODE:
148 enmCpuMode = DISCPUMODE_32BIT;
149 break;
150 case DBGF_DISAS_FLAGS_64BIT_MODE:
151 enmCpuMode = DISCPUMODE_64BIT;
152 break;
153 }
154
155 uint32_t cbInstr;
156 int rc = DISInstrWithReader(GCPtr,
157 enmCpuMode,
158 dbgfR3DisasInstrRead,
159 &pState->Cpu,
160 &pState->Cpu,
161 &cbInstr);
162 if (RT_SUCCESS(rc))
163 {
164 pState->GCPtrNext = GCPtr + cbInstr;
165 return VINF_SUCCESS;
166 }
167
168 /* cleanup */
169 if (pState->fLocked)
170 {
171 PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
172 pState->fLocked = false;
173 }
174 return rc;
175}
176
177
178#if 0
179/**
180 * Calls the disassembler for disassembling the next instruction.
181 *
182 * @returns VBox status code.
183 * @param pState The disas CPU state.
184 */
185static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
186{
187 uint32_t cbInstr;
188 int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
189 if (RT_SUCCESS(rc))
190 {
191 pState->GCPtrNext = GCPtr + cbInstr;
192 return VINF_SUCCESS;
193 }
194 return rc;
195}
196#endif
197
198
199/**
200 * Done with the disassembler state, free associated resources.
201 *
202 * @param pState The disas CPU state ++.
203 */
204static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
205{
206 if (pState->fLocked)
207 {
208 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
209 pState->fLocked = false;
210 }
211}
212
213
214/**
215 * @callback_method_impl{FNDISREADBYTES}
216 *
217 * @remarks The source is relative to the base address indicated by
218 * DBGFDISASSTATE::GCPtrSegBase.
219 */
220static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
221{
222 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
223 for (;;)
224 {
225 RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
226
227 /*
228 * Need to update the page translation?
229 */
230 if ( !pState->pvPageR3
231 || (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
232 {
233 int rc = VINF_SUCCESS;
234
235 /* translate the address */
236 pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
237 if ( !HMIsEnabled(pState->pVM)
238 && MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
239 {
240 pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
241 if (!pState->pvPageR3)
242 rc = VERR_INVALID_POINTER;
243 }
244 else
245 {
246 if (pState->fLocked)
247 PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
248
249 if (pState->enmMode <= PGMMODE_PROTECTED)
250 rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
251 else
252 rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
253 pState->fLocked = RT_SUCCESS_NP(rc);
254 }
255 if (RT_FAILURE(rc))
256 {
257 pState->pvPageR3 = NULL;
258 return rc;
259 }
260 }
261
262 /*
263 * Check the segment limit.
264 */
265 if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
266 return VERR_OUT_OF_SELECTOR_BOUNDS;
267
268 /*
269 * Calc how much we can read, maxing out the read.
270 */
271 uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
272 if (!pState->f64Bits)
273 {
274 RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
275 if (cb > cbSeg && cbSeg)
276 cb = cbSeg;
277 }
278 if (cb > cbMaxRead)
279 cb = cbMaxRead;
280
281#ifdef VBOX_WITH_RAW_MODE
282 /*
283 * Read original bytes from PATM if asked to do so.
284 */
285 if (pState->fUnpatchedBytes)
286 {
287 size_t cbRead = cb;
288 int rc = PATMR3ReadOrgInstr(pState->pVM, GCPtr, &pDis->abInstr[offInstr], cbRead, &cbRead);
289 if (RT_SUCCESS(rc))
290 {
291 pState->fPatchedInstr = true;
292 if (cbRead >= cbMinRead)
293 {
294 pDis->cbCachedInstr = offInstr + (uint8_t)cbRead;
295 return rc;
296 }
297
298 cbMinRead -= (uint8_t)cbRead;
299 cbMaxRead -= (uint8_t)cbRead;
300 cb -= (uint8_t)cbRead;
301 offInstr += (uint8_t)cbRead;
302 GCPtr += cbRead;
303 if (!cb)
304 continue;
305 }
306 }
307#endif /* VBOX_WITH_RAW_MODE */
308
309 /*
310 * Read and advance,
311 */
312 memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
313 offInstr += (uint8_t)cb;
314 if (cb >= cbMinRead)
315 {
316 pDis->cbCachedInstr = offInstr;
317 return VINF_SUCCESS;
318 }
319 cbMaxRead -= (uint8_t)cb;
320 cbMinRead -= (uint8_t)cb;
321 }
322}
323
324
325/**
326 * @callback_method_impl{FNDISGETSYMBOL}
327 */
328static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
329 char *pszBuf, size_t cchBuf, RTINTPTR *poff, void *pvUser)
330{
331 PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
332 PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
333
334 /*
335 * Address conversion
336 */
337 DBGFADDRESS Addr;
338 int rc;
339 /* Start with CS. */
340 if ( DIS_FMT_SEL_IS_REG(u32Sel)
341 ? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
342 : pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
343 rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
344 /* In long mode everything but FS and GS is easy. */
345 else if ( pState->Cpu.uCpuMode == DISCPUMODE_64BIT
346 && DIS_FMT_SEL_IS_REG(u32Sel)
347 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
348 && DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
349 {
350 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
351 rc = VINF_SUCCESS;
352 }
353 /* Here's a quick hack to catch patch manager SS relative access. */
354 else if ( DIS_FMT_SEL_IS_REG(u32Sel)
355 && DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
356 && pSelInfo->GCPtrBase == 0
357 && pSelInfo->cbLimit >= UINT32_MAX
358#ifdef VBOX_WITH_RAW_MODE
359 && PATMIsPatchGCAddr(pState->pVM, pState->Cpu.uInstrAddr)
360#endif
361 )
362 {
363 DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
364 rc = VINF_SUCCESS;
365 }
366 else
367 {
368 /** @todo implement a generic solution here. */
369 rc = VERR_SYMBOL_NOT_FOUND;
370 }
371
372 /*
373 * If we got an address, try resolve it into a symbol.
374 */
375 if (RT_SUCCESS(rc))
376 {
377 RTDBGSYMBOL Sym;
378 RTGCINTPTR off;
379 rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr, RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL,
380 &off, &Sym, NULL /*phMod*/);
381 if (RT_SUCCESS(rc))
382 {
383 /*
384 * Return the symbol and offset.
385 */
386 size_t cchName = strlen(Sym.szName);
387 if (cchName >= cchBuf)
388 cchName = cchBuf - 1;
389 memcpy(pszBuf, Sym.szName, cchName);
390 pszBuf[cchName] = '\0';
391
392 *poff = off;
393 }
394 }
395 return rc;
396}
397
398
399/**
400 * Disassembles the one instruction according to the specified flags and
401 * address, internal worker executing on the EMT of the specified virtual CPU.
402 *
403 * @returns VBox status code.
404 * @param pVM The cross context VM structure.
405 * @param pVCpu The cross context virtual CPU structure.
406 * @param Sel The code selector. This used to determine the 32/16 bit ness and
407 * calculation of the actual instruction address.
408 * @param pGCPtr Pointer to the variable holding the code address
409 * relative to the base of Sel.
410 * @param fFlags Flags controlling where to start and how to format.
411 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
412 * @param pszOutput Output buffer.
413 * @param cbOutput Size of the output buffer.
414 * @param pcbInstr Where to return the size of the instruction.
415 */
416static DECLCALLBACK(int)
417dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
418 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr)
419{
420 VMCPU_ASSERT_EMT(pVCpu);
421 RTGCPTR GCPtr = *pGCPtr;
422 int rc;
423
424 /*
425 * Get the Sel and GCPtr if fFlags requests that.
426 */
427 PCCPUMCTXCORE pCtxCore = NULL;
428 PCCPUMSELREG pSRegCS = NULL;
429 if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
430 {
431 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
432 Sel = pCtxCore->cs.Sel;
433 pSRegCS = &pCtxCore->cs;
434 GCPtr = pCtxCore->rip;
435 }
436 else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
437 {
438 fFlags |= DBGF_DISAS_FLAGS_HYPER;
439 pCtxCore = CPUMGetHyperCtxCore(pVCpu);
440 Sel = pCtxCore->cs.Sel;
441 GCPtr = pCtxCore->rip;
442 }
443 /*
444 * Check if the selector matches the guest CS, use the hidden
445 * registers from that if they are valid. Saves time and effort.
446 */
447 else
448 {
449 pCtxCore = CPUMGetGuestCtxCore(pVCpu);
450 if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
451 pSRegCS = &pCtxCore->cs;
452 else
453 pCtxCore = NULL;
454 }
455
456 /*
457 * Read the selector info - assume no stale selectors and nasty stuff like that.
458 *
459 * Note! We CANNOT load invalid hidden selector registers since that would
460 * mean that log/debug statements or the debug will influence the
461 * guest state and make things behave differently.
462 */
463 DBGFSELINFO SelInfo;
464 const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
465 bool fRealModeAddress = false;
466
467 if ( pSRegCS
468 && CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
469 {
470 SelInfo.Sel = Sel;
471 SelInfo.SelGate = 0;
472 SelInfo.GCPtrBase = pSRegCS->u64Base;
473 SelInfo.cbLimit = pSRegCS->u32Limit;
474 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
475 ? DBGFSELINFO_FLAGS_LONG_MODE
476 : enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
477 ? DBGFSELINFO_FLAGS_PROT_MODE
478 : DBGFSELINFO_FLAGS_REAL_MODE;
479
480 SelInfo.u.Raw.au32[0] = 0;
481 SelInfo.u.Raw.au32[1] = 0;
482 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
483 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
484 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
485 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
486 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
487 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
488 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
489 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
490 fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
491 }
492 else if (Sel == DBGF_SEL_FLAT)
493 {
494 SelInfo.Sel = Sel;
495 SelInfo.SelGate = 0;
496 SelInfo.GCPtrBase = 0;
497 SelInfo.cbLimit = ~0;
498 SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
499 ? DBGFSELINFO_FLAGS_LONG_MODE
500 : enmMode != PGMMODE_REAL
501 ? DBGFSELINFO_FLAGS_PROT_MODE
502 : DBGFSELINFO_FLAGS_REAL_MODE;
503 SelInfo.u.Raw.au32[0] = 0;
504 SelInfo.u.Raw.au32[1] = 0;
505 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
506 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
507
508 pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
509 if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
510 {
511 /* Assume the current CS defines the execution mode. */
512 SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
513 SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
514 SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
515 SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
516 SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
517 SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
518 }
519 else
520 {
521 pSRegCS = NULL;
522 SelInfo.u.Raw.Gen.u1Present = 1;
523 SelInfo.u.Raw.Gen.u1Granularity = 1;
524 SelInfo.u.Raw.Gen.u1DefBig = 1;
525 SelInfo.u.Raw.Gen.u1DescType = 1;
526 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
527 }
528 }
529 else if ( !(fFlags & DBGF_DISAS_FLAGS_HYPER)
530 && ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
531 || enmMode == PGMMODE_REAL
532 || (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
533 )
534 )
535 { /* V86 mode or real mode - real mode addressing */
536 SelInfo.Sel = Sel;
537 SelInfo.SelGate = 0;
538 SelInfo.GCPtrBase = Sel * 16;
539 SelInfo.cbLimit = ~0;
540 SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
541 SelInfo.u.Raw.au32[0] = 0;
542 SelInfo.u.Raw.au32[1] = 0;
543 SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
544 SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
545 SelInfo.u.Raw.Gen.u1Present = 1;
546 SelInfo.u.Raw.Gen.u1Granularity = 1;
547 SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
548 SelInfo.u.Raw.Gen.u1DescType = 1;
549 SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
550 fRealModeAddress = true;
551 }
552 else
553 {
554 if (!(fFlags & DBGF_DISAS_FLAGS_HYPER))
555 rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
556 else
557 rc = SELMR3GetShadowSelectorInfo(pVM, Sel, &SelInfo);
558 if (RT_FAILURE(rc))
559 {
560 RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
561 return rc;
562 }
563 }
564
565 /*
566 * Disassemble it.
567 */
568 DBGFDISASSTATE State;
569 rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
570 if (RT_FAILURE(rc))
571 {
572 if (State.Cpu.cbCachedInstr)
573 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Cpu.cbCachedInstr, State.Cpu.abInstr);
574 else
575 RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
576 return rc;
577 }
578
579 /*
580 * Format it.
581 */
582 char szBuf[512];
583 DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
584 DIS_FMT_FLAGS_RELATIVE_BRANCH,
585 fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
586 &SelInfo);
587
588#ifdef VBOX_WITH_RAW_MODE
589 /*
590 * Patched instruction annotations.
591 */
592 char szPatchAnnotations[256];
593 szPatchAnnotations[0] = '\0';
594 if (fFlags & DBGF_DISAS_FLAGS_ANNOTATE_PATCHED)
595 PATMR3DbgAnnotatePatchedInstruction(pVM, GCPtr, State.Cpu.cbInstr, szPatchAnnotations, sizeof(szPatchAnnotations));
596#endif
597
598 /*
599 * Print it to the user specified buffer.
600 */
601 size_t cch;
602 if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
603 {
604 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
605 cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
606 else if (fRealModeAddress)
607 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
608 else if (Sel == DBGF_SEL_FLAT)
609 {
610 if (enmMode >= PGMMODE_AMD64)
611 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
612 else
613 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
614 }
615 else
616 {
617 if (enmMode >= PGMMODE_AMD64)
618 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
619 else
620 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
621 }
622 }
623 else
624 {
625 uint32_t cbInstr = State.Cpu.cbInstr;
626 uint8_t const *pabInstr = State.Cpu.abInstr;
627 if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
628 cch = RTStrPrintf(pszOutput, cbOutput, "%.*Rhxs%*s %s",
629 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
630 szBuf);
631 else if (fRealModeAddress)
632 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.*Rhxs%*s %s",
633 Sel, (unsigned)GCPtr,
634 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
635 szBuf);
636 else if (Sel == DBGF_SEL_FLAT)
637 {
638 if (enmMode >= PGMMODE_AMD64)
639 cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.*Rhxs%*s %s",
640 GCPtr,
641 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
642 szBuf);
643 else
644 cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.*Rhxs%*s %s",
645 (uint32_t)GCPtr,
646 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
647 szBuf);
648 }
649 else
650 {
651 if (enmMode >= PGMMODE_AMD64)
652 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.*Rhxs%*s %s",
653 Sel, GCPtr,
654 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
655 szBuf);
656 else
657 cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.*Rhxs%*s %s",
658 Sel, (uint32_t)GCPtr,
659 cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
660 szBuf);
661 }
662 }
663
664#ifdef VBOX_WITH_RAW_MODE
665 if (szPatchAnnotations[0] && cch + 1 < cbOutput)
666 RTStrPrintf(pszOutput + cch, cbOutput - cch, " ; %s", szPatchAnnotations);
667#endif
668
669 if (pcbInstr)
670 *pcbInstr = State.Cpu.cbInstr;
671
672 dbgfR3DisasInstrDone(&State);
673 return VINF_SUCCESS;
674}
675
676
677/**
678 * Disassembles the one instruction according to the specified flags and address.
679 *
680 * @returns VBox status code.
681 * @param pUVM The user mode VM handle.
682 * @param idCpu The ID of virtual CPU.
683 * @param Sel The code selector. This used to determine the 32/16 bit ness and
684 * calculation of the actual instruction address.
685 * @param GCPtr The code address relative to the base of Sel.
686 * @param fFlags Flags controlling where to start and how to format.
687 * A combination of the DBGF_DISAS_FLAGS_* \#defines.
688 * @param pszOutput Output buffer. This will always be properly
689 * terminated if @a cbOutput is greater than zero.
690 * @param cbOutput Size of the output buffer.
691 * @param pcbInstr Where to return the size of the instruction.
692 *
693 * @remarks May have to switch to the EMT of the virtual CPU in order to do
694 * address conversion.
695 */
696VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
697 char *pszOutput, uint32_t cbOutput, uint32_t *pcbInstr)
698{
699 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
700 *pszOutput = '\0';
701 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
702 PVM pVM = pUVM->pVM;
703 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
704 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
705 AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
706 AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
707
708 /*
709 * Optimize the common case where we're called on the EMT of idCpu since
710 * we're using this all the time when logging.
711 */
712 int rc;
713 PVMCPU pVCpu = VMMGetCpu(pVM);
714 if ( pVCpu
715 && pVCpu->idCpu == idCpu)
716 rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
717 else
718 rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
719 pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
720 return rc;
721}
722
723
724/**
725 * Disassembles the current guest context instruction.
726 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
727 *
728 * @returns VBox status code.
729 * @param pVCpu The cross context virtual CPU structure.
730 * @param pszOutput Output buffer. This will always be properly
731 * terminated if @a cbOutput is greater than zero.
732 * @param cbOutput Size of the output buffer.
733 * @thread EMT(pVCpu)
734 */
735VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
736{
737 AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
738 *pszOutput = '\0';
739 Assert(VMCPU_IS_EMT(pVCpu));
740
741 RTGCPTR GCPtr = 0;
742 return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
743 DBGF_DISAS_FLAGS_CURRENT_GUEST | DBGF_DISAS_FLAGS_DEFAULT_MODE
744 | DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
745 pszOutput, cbOutput, NULL);
746}
747
748
749/**
750 * Disassembles the current guest context instruction and writes it to the log.
751 * All registers and data will be displayed. Addresses will be attempted resolved to symbols.
752 *
753 * @returns VBox status code.
754 * @param pVCpu The cross context virtual CPU structure.
755 * @param pszPrefix Short prefix string to the disassembly string. (optional)
756 * @thread EMT(pVCpu)
757 */
758VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
759{
760 char szBuf[256];
761 szBuf[0] = '\0';
762 int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
763 if (RT_FAILURE(rc))
764 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
765 if (pszPrefix && *pszPrefix)
766 {
767 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
768 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
769 else
770 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
771 }
772 else
773 RTLogPrintf("%s\n", szBuf);
774 return rc;
775}
776
777
778
779/**
780 * Disassembles the specified guest context instruction and writes it to the log.
781 * Addresses will be attempted resolved to symbols.
782 *
783 * @returns VBox status code.
784 * @param pVCpu The cross context virtual CPU structure of the calling
785 * EMT.
786 * @param Sel The code selector. This used to determine the 32/16
787 * bit-ness and calculation of the actual instruction
788 * address.
789 * @param GCPtr The code address relative to the base of Sel.
790 * @param pszPrefix Short prefix string to the disassembly string.
791 * (optional)
792 * @thread EMT(pVCpu)
793 */
794VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
795{
796 Assert(VMCPU_IS_EMT(pVCpu));
797
798 char szBuf[256];
799 RTGCPTR GCPtrTmp = GCPtr;
800 int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
801 &szBuf[0], sizeof(szBuf), NULL);
802 if (RT_FAILURE(rc))
803 RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
804 if (pszPrefix && *pszPrefix)
805 {
806 if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
807 RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
808 else
809 RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
810 }
811 else
812 RTLogPrintf("%s\n", szBuf);
813 return rc;
814}
815
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