DBGFDisas.cpp@ 45525

Last change on this file since 45525 was 45276, checked in by vboxsync, 12 years ago

Ring-1 compression patches, courtesy of trivirt AG:

main: diff to remove the hwvirt requirement for QNX
rem: diff for dealing with raw ring 0/1 selectors and general changes to allowed guest execution states
vmm: changes for using the guest's TSS selector index as our hypervisor TSS selector (makes str safe) (VBOX_WITH_SAFE_STR )
vmm: changes for dealing with guest ring 1 code (VBOX_WITH_RAW_RING1)
vmm: change to emulate smsw in RC/R0 (QNX uses this old style instruction a lot so going to qemu for emulation is very expensive)
vmm: change (hack) to kick out patm virtual handlers in case they conflict with guest GDT/TSS write monitors; we should allow multiple handlers per page, but that change would be rather invasive

Property svn:eol-style set to native
Property svn:keywords set to Id Revision

File size: 25.9 KB

Line
1	/* $Id: DBGFDisas.cpp 45276 2013-04-02 08:17:11Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DBGF
22	#include <VBox/vmm/dbgf.h>
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/pgm.h>
26	#include <VBox/vmm/cpum.h>
27	#include "DBGFInternal.h"
28	#include <VBox/dis.h>
29	#include <VBox/err.h>
30	#include <VBox/param.h>
31	#include <VBox/vmm/vm.h>
32	#include <VBox/vmm/uvm.h>
33	#include "internal/pgm.h"
34
35	#include <VBox/log.h>
36	#include <iprt/assert.h>
37	#include <iprt/string.h>
38	#include <iprt/alloca.h>
39	#include <iprt/ctype.h>
40
41
42	/*******************************************************************************
43	* Structures and Typedefs *
44	*******************************************************************************/
45	/**
46	* Structure used when disassembling and instructions in DBGF.
47	* This is used so the reader function can get the stuff it needs.
48	*/
49	typedef struct
50	{
51	/** The core structure. */
52	DISCPUSTATE Cpu;
53	/** Pointer to the VM. */
54	PVM pVM;
55	/** Pointer to the VMCPU. */
56	PVMCPU pVCpu;
57	/** The address space for resolving symbol. */
58	RTDBGAS hAs;
59	/** Pointer to the first byte in the segment. */
60	RTGCUINTPTR GCPtrSegBase;
61	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
62	RTGCUINTPTR GCPtrSegEnd;
63	/** The size of the segment minus 1. */
64	RTGCUINTPTR cbSegLimit;
65	/** The guest paging mode. */
66	PGMMODE enmMode;
67	/** Pointer to the current page - R3 Ptr. */
68	void const *pvPageR3;
69	/** Pointer to the current page - GC Ptr. */
70	RTGCPTR GCPtrPage;
71	/** Pointer to the next instruction (relative to GCPtrSegBase). */
72	RTGCUINTPTR GCPtrNext;
73	/** The lock information that PGMPhysReleasePageMappingLock needs. */
74	PGMPAGEMAPLOCK PageMapLock;
75	/** Whether the PageMapLock is valid or not. */
76	bool fLocked;
77	/** 64 bits mode or not. */
78	bool f64Bits;
79	} DBGFDISASSTATE, *PDBGFDISASSTATE;
80
81
82	/*******************************************************************************
83	* Internal Functions *
84	*******************************************************************************/
85	static FNDISREADBYTES dbgfR3DisasInstrRead;
86
87
88
89	/**
90	* Calls the disassembler with the proper reader functions and such for disa
91	*
92	* @returns VBox status code.
93	* @param pVM Pointer to the VM.
94	* @param pVCpu Pointer to the VMCPU.
95	* @param pSelInfo The selector info.
96	* @param enmMode The guest paging mode.
97	* @param fFlags DBGF_DISAS_FLAGS_XXX.
98	* @param GCPtr The GC pointer (selector offset).
99	* @param pState The disas CPU state.
100	*/
101	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
102	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
103	{
104	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
105	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
106	pState->cbSegLimit = pSelInfo->cbLimit;
107	pState->enmMode = enmMode;
108	pState->GCPtrPage = 0;
109	pState->pvPageR3 = NULL;
110	pState->hAs = pSelInfo->fFlags & DBGFSELINFO_FLAGS_HYPER /** @todo Deal more explicitly with RC in DBGFR3Disas. /
111	? DBGF_AS_RC_AND_GC_GLOBAL
112	: DBGF_AS_GLOBAL;
113	pState->pVM = pVM;
114	pState->pVCpu = pVCpu;
115	pState->fLocked = false;
116	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
117
118	DISCPUMODE enmCpuMode;
119	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
120	{
121	default:
122	AssertFailed();
123	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
124	enmCpuMode = pState->f64Bits
125	? DISCPUMODE_64BIT
126	: pSelInfo->u.Raw.Gen.u1DefBig
127	? DISCPUMODE_32BIT
128	: DISCPUMODE_16BIT;
129	break;
130	case DBGF_DISAS_FLAGS_16BIT_MODE:
131	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
132	enmCpuMode = DISCPUMODE_16BIT;
133	break;
134	case DBGF_DISAS_FLAGS_32BIT_MODE:
135	enmCpuMode = DISCPUMODE_32BIT;
136	break;
137	case DBGF_DISAS_FLAGS_64BIT_MODE:
138	enmCpuMode = DISCPUMODE_64BIT;
139	break;
140	}
141
142	uint32_t cbInstr;
143	int rc = DISInstrWithReader(GCPtr,
144	enmCpuMode,
145	dbgfR3DisasInstrRead,
146	&pState->Cpu,
147	&pState->Cpu,
148	&cbInstr);
149	if (RT_SUCCESS(rc))
150	{
151	pState->GCPtrNext = GCPtr + cbInstr;
152	return VINF_SUCCESS;
153	}
154
155	/* cleanup */
156	if (pState->fLocked)
157	{
158	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
159	pState->fLocked = false;
160	}
161	return rc;
162	}
163
164
165	#if 0
166	/**
167	* Calls the disassembler for disassembling the next instruction.
168	*
169	* @returns VBox status code.
170	* @param pState The disas CPU state.
171	*/
172	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
173	{
174	uint32_t cbInstr;
175	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
176	if (RT_SUCCESS(rc))
177	{
178	pState->GCPtrNext = GCPtr + cbInstr;
179	return VINF_SUCCESS;
180	}
181	return rc;
182	}
183	#endif
184
185
186	/**
187	* Done with the disassembler state, free associated resources.
188	*
189	* @param pState The disas CPU state ++.
190	*/
191	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
192	{
193	if (pState->fLocked)
194	{
195	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
196	pState->fLocked = false;
197	}
198	}
199
200
201	/**
202	* @callback_method_impl{FNDISREADBYTES}
203	*
204	* @remarks The source is relative to the base address indicated by
205	* DBGFDISASSTATE::GCPtrSegBase.
206	*/
207	static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
208	{
209	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
210	for (;;)
211	{
212	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
213
214	/*
215	* Need to update the page translation?
216	*/
217	if ( !pState->pvPageR3
218	\|\| (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
219	{
220	int rc = VINF_SUCCESS;
221
222	/* translate the address */
223	pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
224	if (MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
225	{
226	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
227	if (!pState->pvPageR3)
228	rc = VERR_INVALID_POINTER;
229	}
230	else
231	{
232	if (pState->fLocked)
233	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
234
235	if (pState->enmMode <= PGMMODE_PROTECTED)
236	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
237	else
238	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
239	pState->fLocked = RT_SUCCESS_NP(rc);
240	}
241	if (RT_FAILURE(rc))
242	{
243	pState->pvPageR3 = NULL;
244	return rc;
245	}
246	}
247
248	/*
249	* Check the segment limit.
250	*/
251	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
252	return VERR_OUT_OF_SELECTOR_BOUNDS;
253
254	/*
255	* Calc how much we can read, maxing out the read.
256	*/
257	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
258	if (!pState->f64Bits)
259	{
260	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
261	if (cb > cbSeg && cbSeg)
262	cb = cbSeg;
263	}
264	if (cb > cbMaxRead)
265	cb = cbMaxRead;
266
267	/*
268	* Read and advance,
269	*/
270	memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
271	offInstr += (uint8_t)cb;
272	if (cb >= cbMinRead)
273	{
274	pDis->cbCachedInstr = offInstr;
275	return VINF_SUCCESS;
276	}
277	cbMaxRead -= (uint8_t)cb;
278	cbMinRead -= (uint8_t)cb;
279	}
280	}
281
282
283	/**
284	* @copydoc FNDISGETSYMBOL
285	*/
286	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress, char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
287	{
288	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
289	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
290	DBGFADDRESS Addr;
291	RTDBGSYMBOL Sym;
292	RTGCINTPTR off;
293	int rc;
294
295	if ( DIS_FMT_SEL_IS_REG(u32Sel)
296	? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
297	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
298	{
299	rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
300	if (RT_SUCCESS(rc))
301	rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hAs, &Addr, &off, &Sym, NULL /phMod/);
302	}
303	else
304	rc = VERR_SYMBOL_NOT_FOUND; /** @todo implement this */
305	if (RT_SUCCESS(rc))
306	{
307	size_t cchName = strlen(Sym.szName);
308	if (cchName >= cchBuf)
309	cchName = cchBuf - 1;
310	memcpy(pszBuf, Sym.szName, cchName);
311	pszBuf[cchName] = '\0';
312
313	*poff = off;
314	}
315
316	return rc;
317	}
318
319
320	/**
321	* Disassembles the one instruction according to the specified flags and
322	* address, internal worker executing on the EMT of the specified virtual CPU.
323	*
324	* @returns VBox status code.
325	* @param pVM Pointer to the VM.
326	* @param pVCpu Pointer to the VMCPU.
327	* @param Sel The code selector. This used to determine the 32/16 bit ness and
328	* calculation of the actual instruction address.
329	* @param pGCPtr Pointer to the variable holding the code address
330	* relative to the base of Sel.
331	* @param fFlags Flags controlling where to start and how to format.
332	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
333	* @param pszOutput Output buffer.
334	* @param cbOutput Size of the output buffer.
335	* @param pcbInstr Where to return the size of the instruction.
336	*/
337	static DECLCALLBACK(int)
338	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
339	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
340	{
341	VMCPU_ASSERT_EMT(pVCpu);
342	RTGCPTR GCPtr = *pGCPtr;
343	int rc;
344
345	/*
346	* Get the Sel and GCPtr if fFlags requests that.
347	*/
348	PCCPUMCTXCORE pCtxCore = NULL;
349	PCCPUMSELREG pSRegCS = NULL;
350	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
351	{
352	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
353	Sel = pCtxCore->cs.Sel;
354	pSRegCS = &pCtxCore->cs;
355	GCPtr = pCtxCore->rip;
356	}
357	else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
358	{
359	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
360	Sel = pCtxCore->cs.Sel;
361	GCPtr = pCtxCore->rip;
362	}
363	/*
364	* Check if the selector matches the guest CS, use the hidden
365	* registers from that if they are valid. Saves time and effort.
366	*/
367	else
368	{
369	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
370	if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
371	pSRegCS = &pCtxCore->cs;
372	else
373	pCtxCore = NULL;
374	}
375
376	/*
377	* Read the selector info - assume no stale selectors and nasty stuff like that.
378	*
379	* Note! We CANNOT load invalid hidden selector registers since that would
380	* mean that log/debug statements or the debug will influence the
381	* guest state and make things behave differently.
382	*/
383	DBGFSELINFO SelInfo;
384	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
385	bool fRealModeAddress = false;
386
387	if ( pSRegCS
388	&& CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
389	{
390	SelInfo.Sel = Sel;
391	SelInfo.SelGate = 0;
392	SelInfo.GCPtrBase = pSRegCS->u64Base;
393	SelInfo.cbLimit = pSRegCS->u32Limit;
394	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
395	? DBGFSELINFO_FLAGS_LONG_MODE
396	: enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
397	? DBGFSELINFO_FLAGS_PROT_MODE
398	: DBGFSELINFO_FLAGS_REAL_MODE;
399
400	SelInfo.u.Raw.au32[0] = 0;
401	SelInfo.u.Raw.au32[1] = 0;
402	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
403	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
404	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
405	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
406	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
407	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
408	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
409	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
410	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
411	}
412	else if (Sel == DBGF_SEL_FLAT)
413	{
414	SelInfo.Sel = Sel;
415	SelInfo.SelGate = 0;
416	SelInfo.GCPtrBase = 0;
417	SelInfo.cbLimit = ~0;
418	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
419	? DBGFSELINFO_FLAGS_LONG_MODE
420	: enmMode != PGMMODE_REAL
421	? DBGFSELINFO_FLAGS_PROT_MODE
422	: DBGFSELINFO_FLAGS_REAL_MODE;
423	SelInfo.u.Raw.au32[0] = 0;
424	SelInfo.u.Raw.au32[1] = 0;
425	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
426	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
427
428	pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
429	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
430	{
431	/* Assume the current CS defines the execution mode. */
432	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
433	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
434	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
435	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
436	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
437	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
438	}
439	else
440	{
441	pSRegCS = NULL;
442	SelInfo.u.Raw.Gen.u1Present = 1;
443	SelInfo.u.Raw.Gen.u1Granularity = 1;
444	SelInfo.u.Raw.Gen.u1DefBig = 1;
445	SelInfo.u.Raw.Gen.u1DescType = 1;
446	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
447	}
448	}
449	else if ( !(fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
450	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
451	\|\| enmMode == PGMMODE_REAL
452	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
453	)
454	)
455	{ /* V86 mode or real mode - real mode addressing */
456	SelInfo.Sel = Sel;
457	SelInfo.SelGate = 0;
458	SelInfo.GCPtrBase = Sel * 16;
459	SelInfo.cbLimit = ~0;
460	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
461	SelInfo.u.Raw.au32[0] = 0;
462	SelInfo.u.Raw.au32[1] = 0;
463	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
464	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
465	SelInfo.u.Raw.Gen.u1Present = 1;
466	SelInfo.u.Raw.Gen.u1Granularity = 1;
467	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
468	SelInfo.u.Raw.Gen.u1DescType = 1;
469	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
470	fRealModeAddress = true;
471	}
472	else
473	{
474	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
475	if (RT_FAILURE(rc))
476	{
477	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
478	return rc;
479	}
480	}
481
482	/*
483	* Disassemble it.
484	*/
485	DBGFDISASSTATE State;
486	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
487	if (RT_FAILURE(rc))
488	{
489	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
490	return rc;
491	}
492
493	/*
494	* Format it.
495	*/
496	char szBuf[512];
497	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
498	DIS_FMT_FLAGS_RELATIVE_BRANCH,
499	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
500	&SelInfo);
501
502	/*
503	* Print it to the user specified buffer.
504	*/
505	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
506	{
507	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
508	RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
509	else if (fRealModeAddress)
510	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
511	else if (Sel == DBGF_SEL_FLAT)
512	{
513	if (enmMode >= PGMMODE_AMD64)
514	RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
515	else
516	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
517	}
518	else
519	{
520	if (enmMode >= PGMMODE_AMD64)
521	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
522	else
523	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
524	}
525	}
526	else
527	{
528	uint32_t cbInstr = State.Cpu.cbInstr;
529	uint8_t const *pabInstr = State.Cpu.abInstr;
530	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
531	RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
532	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
533	szBuf);
534	else if (fRealModeAddress)
535	RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
536	Sel, (unsigned)GCPtr,
537	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
538	szBuf);
539	else if (Sel == DBGF_SEL_FLAT)
540	{
541	if (enmMode >= PGMMODE_AMD64)
542	RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
543	GCPtr,
544	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
545	szBuf);
546	else
547	RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
548	(uint32_t)GCPtr,
549	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
550	szBuf);
551	}
552	else
553	{
554	if (enmMode >= PGMMODE_AMD64)
555	RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
556	Sel, GCPtr,
557	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
558	szBuf);
559	else
560	RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
561	Sel, (uint32_t)GCPtr,
562	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
563	szBuf);
564	}
565	}
566
567	if (pcbInstr)
568	*pcbInstr = State.Cpu.cbInstr;
569
570	dbgfR3DisasInstrDone(&State);
571	return VINF_SUCCESS;
572	}
573
574
575	/**
576	* Disassembles the one instruction according to the specified flags and address.
577	*
578	* @returns VBox status code.
579	* @param pUVM The user mode VM handle.
580	* @param idCpu The ID of virtual CPU.
581	* @param Sel The code selector. This used to determine the 32/16 bit ness and
582	* calculation of the actual instruction address.
583	* @param GCPtr The code address relative to the base of Sel.
584	* @param fFlags Flags controlling where to start and how to format.
585	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
586	* @param pszOutput Output buffer. This will always be properly
587	* terminated if @a cbOutput is greater than zero.
588	* @param cbOutput Size of the output buffer.
589	* @param pcbInstr Where to return the size of the instruction.
590	*
591	* @remarks May have to switch to the EMT of the virtual CPU in order to do
592	* address conversion.
593	*/
594	VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
595	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
596	{
597	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
598	*pszOutput = '\0';
599	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
600	PVM pVM = pUVM->pVM;
601	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
602	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
603	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
604	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
605
606	/*
607	* Optimize the common case where we're called on the EMT of idCpu since
608	* we're using this all the time when logging.
609	*/
610	int rc;
611	PVMCPU pVCpu = VMMGetCpu(pVM);
612	if ( pVCpu
613	&& pVCpu->idCpu == idCpu)
614	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
615	else
616	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
617	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
618	return rc;
619	}
620
621
622	/**
623	* Disassembles the current guest context instruction.
624	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
625	*
626	* @returns VBox status code.
627	* @param pVCpu Pointer to the VMCPU.
628	* @param pszOutput Output buffer. This will always be properly
629	* terminated if @a cbOutput is greater than zero.
630	* @param cbOutput Size of the output buffer.
631	* @thread EMT(pVCpu)
632	*/
633	VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
634	{
635	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
636	*pszOutput = '\0';
637	Assert(VMCPU_IS_EMT(pVCpu));
638
639	RTGCPTR GCPtr = 0;
640	return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
641	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE,
642	pszOutput, cbOutput, NULL);
643	}
644
645
646	/**
647	* Disassembles the current guest context instruction and writes it to the log.
648	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
649	*
650	* @returns VBox status code.
651	* @param pVCpu Pointer to the VMCPU.
652	* @param pszPrefix Short prefix string to the disassembly string. (optional)
653	* @thread EMT(pVCpu)
654	*/
655	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
656	{
657	char szBuf[256];
658	szBuf[0] = '\0';
659	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
660	if (RT_FAILURE(rc))
661	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
662	if (pszPrefix && *pszPrefix)
663	{
664	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
665	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
666	else
667	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
668	}
669	else
670	RTLogPrintf("%s\n", szBuf);
671	return rc;
672	}
673
674
675
676	/**
677	* Disassembles the specified guest context instruction and writes it to the log.
678	* Addresses will be attempted resolved to symbols.
679	*
680	* @returns VBox status code.
681	* @param pVCpu Pointer to the VMCPU, defaults to CPU 0 if NULL.
682	* @param Sel The code selector. This used to determine the 32/16 bit-ness and
683	* calculation of the actual instruction address.
684	* @param GCPtr The code address relative to the base of Sel.
685	* @param pszPrefix Short prefix string to the disassembly string. (optional)
686	* @thread EMT(pVCpu)
687	*/
688	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
689	{
690	Assert(VMCPU_IS_EMT(pVCpu));
691
692	char szBuf[256];
693	RTGCPTR GCPtrTmp = GCPtr;
694	int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
695	&szBuf[0], sizeof(szBuf), NULL);
696	if (RT_FAILURE(rc))
697	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
698	if (pszPrefix && *pszPrefix)
699	{
700	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
701	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
702	else
703	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
704	}
705	else
706	RTLogPrintf("%s\n", szBuf);
707	return rc;
708	}
709

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source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 45525

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