DBGFDisas.cpp@ 48729

Last change on this file since 48729 was 47889, checked in by vboxsync, 11 years ago
cpumguestinstr: always print what the disassembler returns, and make it return the cached instruction bytes on failure.
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1	/* $Id: DBGFDisas.cpp 47889 2013-08-20 11:15:31Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2013 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/*******************************************************************************
19	* Header Files *
20	*******************************************************************************/
21	#define LOG_GROUP LOG_GROUP_DBGF
22	#include <VBox/vmm/dbgf.h>
23	#include <VBox/vmm/selm.h>
24	#include <VBox/vmm/mm.h>
25	#include <VBox/vmm/hm.h>
26	#include <VBox/vmm/pgm.h>
27	#include <VBox/vmm/cpum.h>
28	#ifdef VBOX_WITH_RAW_MODE
29	# include <VBox/vmm/patm.h>
30	#endif
31	#include "DBGFInternal.h"
32	#include <VBox/dis.h>
33	#include <VBox/err.h>
34	#include <VBox/param.h>
35	#include <VBox/vmm/vm.h>
36	#include <VBox/vmm/uvm.h>
37	#include "internal/pgm.h"
38
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/string.h>
42	#include <iprt/alloca.h>
43	#include <iprt/ctype.h>
44
45
46	/*******************************************************************************
47	* Structures and Typedefs *
48	*******************************************************************************/
49	/**
50	* Structure used when disassembling and instructions in DBGF.
51	* This is used so the reader function can get the stuff it needs.
52	*/
53	typedef struct
54	{
55	/** The core structure. */
56	DISCPUSTATE Cpu;
57	/** Pointer to the VM. */
58	PVM pVM;
59	/** Pointer to the VMCPU. */
60	PVMCPU pVCpu;
61	/** The address space for resolving symbol. */
62	RTDBGAS hDbgAs;
63	/** Pointer to the first byte in the segment. */
64	RTGCUINTPTR GCPtrSegBase;
65	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
66	RTGCUINTPTR GCPtrSegEnd;
67	/** The size of the segment minus 1. */
68	RTGCUINTPTR cbSegLimit;
69	/** The guest paging mode. */
70	PGMMODE enmMode;
71	/** Pointer to the current page - R3 Ptr. */
72	void const *pvPageR3;
73	/** Pointer to the current page - GC Ptr. */
74	RTGCPTR GCPtrPage;
75	/** Pointer to the next instruction (relative to GCPtrSegBase). */
76	RTGCUINTPTR GCPtrNext;
77	/** The lock information that PGMPhysReleasePageMappingLock needs. */
78	PGMPAGEMAPLOCK PageMapLock;
79	/** Whether the PageMapLock is valid or not. */
80	bool fLocked;
81	/** 64 bits mode or not. */
82	bool f64Bits;
83	/** Read original unpatched bytes from the patch manager. */
84	bool fUnpatchedBytes;
85	/** Set when fUnpatchedBytes is active and we encounter patched bytes. */
86	bool fPatchedInstr;
87	} DBGFDISASSTATE, *PDBGFDISASSTATE;
88
89
90	/*******************************************************************************
91	* Internal Functions *
92	*******************************************************************************/
93	static FNDISREADBYTES dbgfR3DisasInstrRead;
94
95
96
97	/**
98	* Calls the disassembler with the proper reader functions and such for disa
99	*
100	* @returns VBox status code.
101	* @param pVM Pointer to the VM.
102	* @param pVCpu Pointer to the VMCPU.
103	* @param pSelInfo The selector info.
104	* @param enmMode The guest paging mode.
105	* @param fFlags DBGF_DISAS_FLAGS_XXX.
106	* @param GCPtr The GC pointer (selector offset).
107	* @param pState The disas CPU state.
108	*/
109	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
110	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
111	{
112	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
113	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
114	pState->cbSegLimit = pSelInfo->cbLimit;
115	pState->enmMode = enmMode;
116	pState->GCPtrPage = 0;
117	pState->pvPageR3 = NULL;
118	pState->hDbgAs = !HMIsEnabled(pVM)
119	? DBGF_AS_RC_AND_GC_GLOBAL
120	: DBGF_AS_GLOBAL;
121	pState->pVM = pVM;
122	pState->pVCpu = pVCpu;
123	pState->fLocked = false;
124	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
125	#ifdef VBOX_WITH_RAW_MODE
126	pState->fUnpatchedBytes = RT_BOOL(fFlags & DBGF_DISAS_FLAGS_UNPATCHED_BYTES);
127	pState->fPatchedInstr = false;
128	#endif
129
130	DISCPUMODE enmCpuMode;
131	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
132	{
133	default:
134	AssertFailed();
135	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
136	enmCpuMode = pState->f64Bits
137	? DISCPUMODE_64BIT
138	: pSelInfo->u.Raw.Gen.u1DefBig
139	? DISCPUMODE_32BIT
140	: DISCPUMODE_16BIT;
141	break;
142	case DBGF_DISAS_FLAGS_16BIT_MODE:
143	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
144	enmCpuMode = DISCPUMODE_16BIT;
145	break;
146	case DBGF_DISAS_FLAGS_32BIT_MODE:
147	enmCpuMode = DISCPUMODE_32BIT;
148	break;
149	case DBGF_DISAS_FLAGS_64BIT_MODE:
150	enmCpuMode = DISCPUMODE_64BIT;
151	break;
152	}
153
154	uint32_t cbInstr;
155	int rc = DISInstrWithReader(GCPtr,
156	enmCpuMode,
157	dbgfR3DisasInstrRead,
158	&pState->Cpu,
159	&pState->Cpu,
160	&cbInstr);
161	if (RT_SUCCESS(rc))
162	{
163	pState->GCPtrNext = GCPtr + cbInstr;
164	return VINF_SUCCESS;
165	}
166
167	/* cleanup */
168	if (pState->fLocked)
169	{
170	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
171	pState->fLocked = false;
172	}
173	return rc;
174	}
175
176
177	#if 0
178	/**
179	* Calls the disassembler for disassembling the next instruction.
180	*
181	* @returns VBox status code.
182	* @param pState The disas CPU state.
183	*/
184	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
185	{
186	uint32_t cbInstr;
187	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
188	if (RT_SUCCESS(rc))
189	{
190	pState->GCPtrNext = GCPtr + cbInstr;
191	return VINF_SUCCESS;
192	}
193	return rc;
194	}
195	#endif
196
197
198	/**
199	* Done with the disassembler state, free associated resources.
200	*
201	* @param pState The disas CPU state ++.
202	*/
203	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
204	{
205	if (pState->fLocked)
206	{
207	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
208	pState->fLocked = false;
209	}
210	}
211
212
213	/**
214	* @callback_method_impl{FNDISREADBYTES}
215	*
216	* @remarks The source is relative to the base address indicated by
217	* DBGFDISASSTATE::GCPtrSegBase.
218	*/
219	static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
220	{
221	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
222	for (;;)
223	{
224	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
225
226	/*
227	* Need to update the page translation?
228	*/
229	if ( !pState->pvPageR3
230	\|\| (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
231	{
232	int rc = VINF_SUCCESS;
233
234	/* translate the address */
235	pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
236	if ( !HMIsEnabled(pState->pVM)
237	&& MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
238	{
239	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
240	if (!pState->pvPageR3)
241	rc = VERR_INVALID_POINTER;
242	}
243	else
244	{
245	if (pState->fLocked)
246	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
247
248	if (pState->enmMode <= PGMMODE_PROTECTED)
249	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
250	else
251	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
252	pState->fLocked = RT_SUCCESS_NP(rc);
253	}
254	if (RT_FAILURE(rc))
255	{
256	pState->pvPageR3 = NULL;
257	return rc;
258	}
259	}
260
261	/*
262	* Check the segment limit.
263	*/
264	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
265	return VERR_OUT_OF_SELECTOR_BOUNDS;
266
267	/*
268	* Calc how much we can read, maxing out the read.
269	*/
270	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
271	if (!pState->f64Bits)
272	{
273	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
274	if (cb > cbSeg && cbSeg)
275	cb = cbSeg;
276	}
277	if (cb > cbMaxRead)
278	cb = cbMaxRead;
279
280	#ifdef VBOX_WITH_RAW_MODE
281	/*
282	* Read original bytes from PATM if asked to do so.
283	*/
284	if (pState->fUnpatchedBytes)
285	{
286	size_t cbRead = cb;
287	int rc = PATMR3ReadOrgInstr(pState->pVM, GCPtr, &pDis->abInstr[offInstr], cbRead, &cbRead);
288	if (RT_SUCCESS(rc))
289	{
290	pState->fPatchedInstr = true;
291	if (cbRead >= cbMinRead)
292	{
293	pDis->cbCachedInstr = offInstr + (uint8_t)cbRead;
294	return rc;
295	}
296
297	cbMinRead -= (uint8_t)cbRead;
298	cbMaxRead -= (uint8_t)cbRead;
299	cb -= (uint8_t)cbRead;
300	offInstr += (uint8_t)cbRead;
301	GCPtr += cbRead;
302	if (!cb)
303	continue;
304	}
305	}
306	#endif /* VBOX_WITH_RAW_MODE */
307
308	/*
309	* Read and advance,
310	*/
311	memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
312	offInstr += (uint8_t)cb;
313	if (cb >= cbMinRead)
314	{
315	pDis->cbCachedInstr = offInstr;
316	return VINF_SUCCESS;
317	}
318	cbMaxRead -= (uint8_t)cb;
319	cbMinRead -= (uint8_t)cb;
320	}
321	}
322
323
324	/**
325	* @copydoc FNDISGETSYMBOL
326	*/
327	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pCpu, uint32_t u32Sel, RTUINTPTR uAddress,
328	char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
329	{
330	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pCpu;
331	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
332
333	/*
334	* Address conversion
335	*/
336	DBGFADDRESS Addr;
337	int rc;
338	/* Start with CS. */
339	if ( DIS_FMT_SEL_IS_REG(u32Sel)
340	? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
341	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
342	rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
343	/* In long mode everything but FS and GS is easy. */
344	else if ( pState->Cpu.uCpuMode == DISCPUMODE_64BIT
345	&& DIS_FMT_SEL_IS_REG(u32Sel)
346	&& DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
347	&& DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
348	{
349	DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
350	rc = VINF_SUCCESS;
351	}
352	/* Here's a quick hack to catch patch manager SS relative access. */
353	else if ( DIS_FMT_SEL_IS_REG(u32Sel)
354	&& DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
355	&& pSelInfo->GCPtrBase == 0
356	&& pSelInfo->cbLimit >= UINT32_MAX
357	&& PATMIsPatchGCAddr(pState->pVM, pState->Cpu.uInstrAddr))
358	{
359	DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
360	rc = VINF_SUCCESS;
361	}
362	else
363	{
364	/** @todo implement a generic solution here. */
365	rc = VERR_SYMBOL_NOT_FOUND;
366	}
367
368	/*
369	* If we got an address, try resolve it into a symbol.
370	*/
371	if (RT_SUCCESS(rc))
372	{
373	RTDBGSYMBOL Sym;
374	RTGCINTPTR off;
375	rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr, RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL,
376	&off, &Sym, NULL /phMod/);
377	if (RT_SUCCESS(rc))
378	{
379	/*
380	* Return the symbol and offset.
381	*/
382	size_t cchName = strlen(Sym.szName);
383	if (cchName >= cchBuf)
384	cchName = cchBuf - 1;
385	memcpy(pszBuf, Sym.szName, cchName);
386	pszBuf[cchName] = '\0';
387
388	*poff = off;
389	}
390	}
391	return rc;
392	}
393
394
395	/**
396	* Disassembles the one instruction according to the specified flags and
397	* address, internal worker executing on the EMT of the specified virtual CPU.
398	*
399	* @returns VBox status code.
400	* @param pVM Pointer to the VM.
401	* @param pVCpu Pointer to the VMCPU.
402	* @param Sel The code selector. This used to determine the 32/16 bit ness and
403	* calculation of the actual instruction address.
404	* @param pGCPtr Pointer to the variable holding the code address
405	* relative to the base of Sel.
406	* @param fFlags Flags controlling where to start and how to format.
407	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
408	* @param pszOutput Output buffer.
409	* @param cbOutput Size of the output buffer.
410	* @param pcbInstr Where to return the size of the instruction.
411	*/
412	static DECLCALLBACK(int)
413	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
414	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
415	{
416	VMCPU_ASSERT_EMT(pVCpu);
417	RTGCPTR GCPtr = *pGCPtr;
418	int rc;
419
420	/*
421	* Get the Sel and GCPtr if fFlags requests that.
422	*/
423	PCCPUMCTXCORE pCtxCore = NULL;
424	PCCPUMSELREG pSRegCS = NULL;
425	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
426	{
427	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
428	Sel = pCtxCore->cs.Sel;
429	pSRegCS = &pCtxCore->cs;
430	GCPtr = pCtxCore->rip;
431	}
432	else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
433	{
434	fFlags \|= DBGF_DISAS_FLAGS_HYPER;
435	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
436	Sel = pCtxCore->cs.Sel;
437	GCPtr = pCtxCore->rip;
438	}
439	/*
440	* Check if the selector matches the guest CS, use the hidden
441	* registers from that if they are valid. Saves time and effort.
442	*/
443	else
444	{
445	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
446	if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
447	pSRegCS = &pCtxCore->cs;
448	else
449	pCtxCore = NULL;
450	}
451
452	/*
453	* Read the selector info - assume no stale selectors and nasty stuff like that.
454	*
455	* Note! We CANNOT load invalid hidden selector registers since that would
456	* mean that log/debug statements or the debug will influence the
457	* guest state and make things behave differently.
458	*/
459	DBGFSELINFO SelInfo;
460	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
461	bool fRealModeAddress = false;
462
463	if ( pSRegCS
464	&& CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
465	{
466	SelInfo.Sel = Sel;
467	SelInfo.SelGate = 0;
468	SelInfo.GCPtrBase = pSRegCS->u64Base;
469	SelInfo.cbLimit = pSRegCS->u32Limit;
470	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
471	? DBGFSELINFO_FLAGS_LONG_MODE
472	: enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
473	? DBGFSELINFO_FLAGS_PROT_MODE
474	: DBGFSELINFO_FLAGS_REAL_MODE;
475
476	SelInfo.u.Raw.au32[0] = 0;
477	SelInfo.u.Raw.au32[1] = 0;
478	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
479	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
480	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
481	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
482	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
483	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
484	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
485	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
486	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
487	}
488	else if (Sel == DBGF_SEL_FLAT)
489	{
490	SelInfo.Sel = Sel;
491	SelInfo.SelGate = 0;
492	SelInfo.GCPtrBase = 0;
493	SelInfo.cbLimit = ~0;
494	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
495	? DBGFSELINFO_FLAGS_LONG_MODE
496	: enmMode != PGMMODE_REAL
497	? DBGFSELINFO_FLAGS_PROT_MODE
498	: DBGFSELINFO_FLAGS_REAL_MODE;
499	SelInfo.u.Raw.au32[0] = 0;
500	SelInfo.u.Raw.au32[1] = 0;
501	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
502	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
503
504	pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
505	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
506	{
507	/* Assume the current CS defines the execution mode. */
508	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
509	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
510	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
511	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
512	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
513	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
514	}
515	else
516	{
517	pSRegCS = NULL;
518	SelInfo.u.Raw.Gen.u1Present = 1;
519	SelInfo.u.Raw.Gen.u1Granularity = 1;
520	SelInfo.u.Raw.Gen.u1DefBig = 1;
521	SelInfo.u.Raw.Gen.u1DescType = 1;
522	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
523	}
524	}
525	else if ( !(fFlags & DBGF_DISAS_FLAGS_HYPER)
526	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
527	\|\| enmMode == PGMMODE_REAL
528	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
529	)
530	)
531	{ /* V86 mode or real mode - real mode addressing */
532	SelInfo.Sel = Sel;
533	SelInfo.SelGate = 0;
534	SelInfo.GCPtrBase = Sel * 16;
535	SelInfo.cbLimit = ~0;
536	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
537	SelInfo.u.Raw.au32[0] = 0;
538	SelInfo.u.Raw.au32[1] = 0;
539	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
540	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
541	SelInfo.u.Raw.Gen.u1Present = 1;
542	SelInfo.u.Raw.Gen.u1Granularity = 1;
543	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
544	SelInfo.u.Raw.Gen.u1DescType = 1;
545	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
546	fRealModeAddress = true;
547	}
548	else
549	{
550	if (!(fFlags & DBGF_DISAS_FLAGS_HYPER))
551	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
552	else
553	rc = SELMR3GetShadowSelectorInfo(pVM, Sel, &SelInfo);
554	if (RT_FAILURE(rc))
555	{
556	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
557	return rc;
558	}
559	}
560
561	/*
562	* Disassemble it.
563	*/
564	DBGFDISASSTATE State;
565	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
566	if (RT_FAILURE(rc))
567	{
568	if (State.Cpu.cbCachedInstr)
569	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Cpu.cbCachedInstr, State.Cpu.abInstr);
570	else
571	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
572	return rc;
573	}
574
575	/*
576	* Format it.
577	*/
578	char szBuf[512];
579	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
580	DIS_FMT_FLAGS_RELATIVE_BRANCH,
581	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
582	&SelInfo);
583
584	#ifdef VBOX_WITH_RAW_MODE
585	/*
586	* Patched instruction annotations.
587	*/
588	char szPatchAnnotations[256];
589	szPatchAnnotations[0] = '\0';
590	if (fFlags & DBGF_DISAS_FLAGS_ANNOTATE_PATCHED)
591	PATMR3DbgAnnotatePatchedInstruction(pVM, GCPtr, State.Cpu.cbInstr, szPatchAnnotations, sizeof(szPatchAnnotations));
592	#endif
593
594	/*
595	* Print it to the user specified buffer.
596	*/
597	size_t cch;
598	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
599	{
600	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
601	cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
602	else if (fRealModeAddress)
603	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
604	else if (Sel == DBGF_SEL_FLAT)
605	{
606	if (enmMode >= PGMMODE_AMD64)
607	cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
608	else
609	cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
610	}
611	else
612	{
613	if (enmMode >= PGMMODE_AMD64)
614	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
615	else
616	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
617	}
618	}
619	else
620	{
621	uint32_t cbInstr = State.Cpu.cbInstr;
622	uint8_t const *pabInstr = State.Cpu.abInstr;
623	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
624	cch = RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
625	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
626	szBuf);
627	else if (fRealModeAddress)
628	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
629	Sel, (unsigned)GCPtr,
630	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
631	szBuf);
632	else if (Sel == DBGF_SEL_FLAT)
633	{
634	if (enmMode >= PGMMODE_AMD64)
635	cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
636	GCPtr,
637	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
638	szBuf);
639	else
640	cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
641	(uint32_t)GCPtr,
642	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
643	szBuf);
644	}
645	else
646	{
647	if (enmMode >= PGMMODE_AMD64)
648	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
649	Sel, GCPtr,
650	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
651	szBuf);
652	else
653	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
654	Sel, (uint32_t)GCPtr,
655	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
656	szBuf);
657	}
658	}
659
660	#ifdef VBOX_WITH_RAW_MODE
661	if (szPatchAnnotations[0] && cch + 1 < cbOutput)
662	RTStrPrintf(pszOutput + cch, cbOutput - cch, " ; %s", szPatchAnnotations);
663	#endif
664
665	if (pcbInstr)
666	*pcbInstr = State.Cpu.cbInstr;
667
668	dbgfR3DisasInstrDone(&State);
669	return VINF_SUCCESS;
670	}
671
672
673	/**
674	* Disassembles the one instruction according to the specified flags and address.
675	*
676	* @returns VBox status code.
677	* @param pUVM The user mode VM handle.
678	* @param idCpu The ID of virtual CPU.
679	* @param Sel The code selector. This used to determine the 32/16 bit ness and
680	* calculation of the actual instruction address.
681	* @param GCPtr The code address relative to the base of Sel.
682	* @param fFlags Flags controlling where to start and how to format.
683	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
684	* @param pszOutput Output buffer. This will always be properly
685	* terminated if @a cbOutput is greater than zero.
686	* @param cbOutput Size of the output buffer.
687	* @param pcbInstr Where to return the size of the instruction.
688	*
689	* @remarks May have to switch to the EMT of the virtual CPU in order to do
690	* address conversion.
691	*/
692	VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
693	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
694	{
695	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
696	*pszOutput = '\0';
697	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
698	PVM pVM = pUVM->pVM;
699	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
700	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
701	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
702	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
703
704	/*
705	* Optimize the common case where we're called on the EMT of idCpu since
706	* we're using this all the time when logging.
707	*/
708	int rc;
709	PVMCPU pVCpu = VMMGetCpu(pVM);
710	if ( pVCpu
711	&& pVCpu->idCpu == idCpu)
712	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
713	else
714	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 8,
715	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr);
716	return rc;
717	}
718
719
720	/**
721	* Disassembles the current guest context instruction.
722	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
723	*
724	* @returns VBox status code.
725	* @param pVCpu Pointer to the VMCPU.
726	* @param pszOutput Output buffer. This will always be properly
727	* terminated if @a cbOutput is greater than zero.
728	* @param cbOutput Size of the output buffer.
729	* @thread EMT(pVCpu)
730	*/
731	VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
732	{
733	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
734	*pszOutput = '\0';
735	Assert(VMCPU_IS_EMT(pVCpu));
736
737	RTGCPTR GCPtr = 0;
738	return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
739	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE
740	\| DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
741	pszOutput, cbOutput, NULL);
742	}
743
744
745	/**
746	* Disassembles the current guest context instruction and writes it to the log.
747	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
748	*
749	* @returns VBox status code.
750	* @param pVCpu Pointer to the VMCPU.
751	* @param pszPrefix Short prefix string to the disassembly string. (optional)
752	* @thread EMT(pVCpu)
753	*/
754	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
755	{
756	char szBuf[256];
757	szBuf[0] = '\0';
758	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
759	if (RT_FAILURE(rc))
760	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
761	if (pszPrefix && *pszPrefix)
762	{
763	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
764	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
765	else
766	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
767	}
768	else
769	RTLogPrintf("%s\n", szBuf);
770	return rc;
771	}
772
773
774
775	/**
776	* Disassembles the specified guest context instruction and writes it to the log.
777	* Addresses will be attempted resolved to symbols.
778	*
779	* @returns VBox status code.
780	* @param pVCpu Pointer to the VMCPU, defaults to CPU 0 if NULL.
781	* @param Sel The code selector. This used to determine the 32/16 bit-ness and
782	* calculation of the actual instruction address.
783	* @param GCPtr The code address relative to the base of Sel.
784	* @param pszPrefix Short prefix string to the disassembly string. (optional)
785	* @thread EMT(pVCpu)
786	*/
787	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
788	{
789	Assert(VMCPU_IS_EMT(pVCpu));
790
791	char szBuf[256];
792	RTGCPTR GCPtrTmp = GCPtr;
793	int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
794	&szBuf[0], sizeof(szBuf), NULL);
795	if (RT_FAILURE(rc))
796	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
797	if (pszPrefix && *pszPrefix)
798	{
799	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
800	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
801	else
802	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
803	}
804	else
805	RTLogPrintf("%s\n", szBuf);
806	return rc;
807	}
808

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source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 48729

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