DBGFDisas.cpp@ 64551

Last change on this file since 64551 was 64499, checked in by vboxsync, 8 years ago
VMM/DBGFDisas: Add method internal to VMM which returns a very small part of the disassembler state along with the string (used by the control flow graph generator)
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1	/* $Id: DBGFDisas.cpp 64499 2016-11-01 09:06:26Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2016 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_DBGF
23	#include <VBox/vmm/dbgf.h>
24	#include <VBox/vmm/selm.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/hm.h>
27	#include <VBox/vmm/pgm.h>
28	#include <VBox/vmm/cpum.h>
29	#ifdef VBOX_WITH_RAW_MODE
30	# include <VBox/vmm/patm.h>
31	#endif
32	#include "DBGFInternal.h"
33	#include <VBox/dis.h>
34	#include <VBox/err.h>
35	#include <VBox/param.h>
36	#include <VBox/vmm/vm.h>
37	#include <VBox/vmm/uvm.h>
38
39	#include <VBox/log.h>
40	#include <iprt/assert.h>
41	#include <iprt/string.h>
42	#include <iprt/alloca.h>
43	#include <iprt/ctype.h>
44
45
46	/*********************************************************************************************************************************
47	* Structures and Typedefs *
48	*********************************************************************************************************************************/
49	/**
50	* Structure used when disassembling and instructions in DBGF.
51	* This is used so the reader function can get the stuff it needs.
52	*/
53	typedef struct
54	{
55	/** The core structure. */
56	DISCPUSTATE Cpu;
57	/** The cross context VM structure. */
58	PVM pVM;
59	/** The cross context virtual CPU structure. */
60	PVMCPU pVCpu;
61	/** The address space for resolving symbol. */
62	RTDBGAS hDbgAs;
63	/** Pointer to the first byte in the segment. */
64	RTGCUINTPTR GCPtrSegBase;
65	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
66	RTGCUINTPTR GCPtrSegEnd;
67	/** The size of the segment minus 1. */
68	RTGCUINTPTR cbSegLimit;
69	/** The guest paging mode. */
70	PGMMODE enmMode;
71	/** Pointer to the current page - R3 Ptr. */
72	void const *pvPageR3;
73	/** Pointer to the current page - GC Ptr. */
74	RTGCPTR GCPtrPage;
75	/** Pointer to the next instruction (relative to GCPtrSegBase). */
76	RTGCUINTPTR GCPtrNext;
77	/** The lock information that PGMPhysReleasePageMappingLock needs. */
78	PGMPAGEMAPLOCK PageMapLock;
79	/** Whether the PageMapLock is valid or not. */
80	bool fLocked;
81	/** 64 bits mode or not. */
82	bool f64Bits;
83	/** Read original unpatched bytes from the patch manager. */
84	bool fUnpatchedBytes;
85	/** Set when fUnpatchedBytes is active and we encounter patched bytes. */
86	bool fPatchedInstr;
87	} DBGFDISASSTATE, *PDBGFDISASSTATE;
88
89
90	/*********************************************************************************************************************************
91	* Internal Functions *
92	*********************************************************************************************************************************/
93	static FNDISREADBYTES dbgfR3DisasInstrRead;
94
95
96
97	/**
98	* Calls the disassembler with the proper reader functions and such for disa
99	*
100	* @returns VBox status code.
101	* @param pVM The cross context VM structure.
102	* @param pVCpu The cross context virtual CPU structure.
103	* @param pSelInfo The selector info.
104	* @param enmMode The guest paging mode.
105	* @param fFlags DBGF_DISAS_FLAGS_XXX.
106	* @param GCPtr The GC pointer (selector offset).
107	* @param pState The disas CPU state.
108	*/
109	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
110	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
111	{
112	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
113	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
114	pState->cbSegLimit = pSelInfo->cbLimit;
115	pState->enmMode = enmMode;
116	pState->GCPtrPage = 0;
117	pState->pvPageR3 = NULL;
118	pState->hDbgAs = !HMIsEnabled(pVM)
119	? DBGF_AS_RC_AND_GC_GLOBAL
120	: DBGF_AS_GLOBAL;
121	pState->pVM = pVM;
122	pState->pVCpu = pVCpu;
123	pState->fLocked = false;
124	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
125	#ifdef VBOX_WITH_RAW_MODE
126	pState->fUnpatchedBytes = RT_BOOL(fFlags & DBGF_DISAS_FLAGS_UNPATCHED_BYTES);
127	pState->fPatchedInstr = false;
128	#endif
129
130	DISCPUMODE enmCpuMode;
131	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
132	{
133	default:
134	AssertFailed();
135	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
136	enmCpuMode = pState->f64Bits
137	? DISCPUMODE_64BIT
138	: pSelInfo->u.Raw.Gen.u1DefBig
139	? DISCPUMODE_32BIT
140	: DISCPUMODE_16BIT;
141	break;
142	case DBGF_DISAS_FLAGS_16BIT_MODE:
143	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
144	enmCpuMode = DISCPUMODE_16BIT;
145	break;
146	case DBGF_DISAS_FLAGS_32BIT_MODE:
147	enmCpuMode = DISCPUMODE_32BIT;
148	break;
149	case DBGF_DISAS_FLAGS_64BIT_MODE:
150	enmCpuMode = DISCPUMODE_64BIT;
151	break;
152	}
153
154	uint32_t cbInstr;
155	int rc = DISInstrWithReader(GCPtr,
156	enmCpuMode,
157	dbgfR3DisasInstrRead,
158	&pState->Cpu,
159	&pState->Cpu,
160	&cbInstr);
161	if (RT_SUCCESS(rc))
162	{
163	pState->GCPtrNext = GCPtr + cbInstr;
164	return VINF_SUCCESS;
165	}
166
167	/* cleanup */
168	if (pState->fLocked)
169	{
170	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
171	pState->fLocked = false;
172	}
173	return rc;
174	}
175
176
177	#if 0
178	/**
179	* Calls the disassembler for disassembling the next instruction.
180	*
181	* @returns VBox status code.
182	* @param pState The disas CPU state.
183	*/
184	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
185	{
186	uint32_t cbInstr;
187	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
188	if (RT_SUCCESS(rc))
189	{
190	pState->GCPtrNext = GCPtr + cbInstr;
191	return VINF_SUCCESS;
192	}
193	return rc;
194	}
195	#endif
196
197
198	/**
199	* Done with the disassembler state, free associated resources.
200	*
201	* @param pState The disas CPU state ++.
202	*/
203	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
204	{
205	if (pState->fLocked)
206	{
207	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
208	pState->fLocked = false;
209	}
210	}
211
212
213	/**
214	* @callback_method_impl{FNDISREADBYTES}
215	*
216	* @remarks The source is relative to the base address indicated by
217	* DBGFDISASSTATE::GCPtrSegBase.
218	*/
219	static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
220	{
221	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
222	for (;;)
223	{
224	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
225
226	/*
227	* Need to update the page translation?
228	*/
229	if ( !pState->pvPageR3
230	\|\| (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
231	{
232	int rc = VINF_SUCCESS;
233
234	/* translate the address */
235	pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
236	if ( !HMIsEnabled(pState->pVM)
237	&& MMHyperIsInsideArea(pState->pVM, pState->GCPtrPage))
238	{
239	pState->pvPageR3 = MMHyperRCToR3(pState->pVM, (RTRCPTR)pState->GCPtrPage);
240	if (!pState->pvPageR3)
241	rc = VERR_INVALID_POINTER;
242	}
243	else
244	{
245	if (pState->fLocked)
246	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
247
248	if (pState->enmMode <= PGMMODE_PROTECTED)
249	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
250	else
251	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
252	pState->fLocked = RT_SUCCESS_NP(rc);
253	}
254	if (RT_FAILURE(rc))
255	{
256	pState->pvPageR3 = NULL;
257	return rc;
258	}
259	}
260
261	/*
262	* Check the segment limit.
263	*/
264	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
265	return VERR_OUT_OF_SELECTOR_BOUNDS;
266
267	/*
268	* Calc how much we can read, maxing out the read.
269	*/
270	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
271	if (!pState->f64Bits)
272	{
273	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
274	if (cb > cbSeg && cbSeg)
275	cb = cbSeg;
276	}
277	if (cb > cbMaxRead)
278	cb = cbMaxRead;
279
280	#ifdef VBOX_WITH_RAW_MODE
281	/*
282	* Read original bytes from PATM if asked to do so.
283	*/
284	if (pState->fUnpatchedBytes)
285	{
286	size_t cbRead = cb;
287	int rc = PATMR3ReadOrgInstr(pState->pVM, GCPtr, &pDis->abInstr[offInstr], cbRead, &cbRead);
288	if (RT_SUCCESS(rc))
289	{
290	pState->fPatchedInstr = true;
291	if (cbRead >= cbMinRead)
292	{
293	pDis->cbCachedInstr = offInstr + (uint8_t)cbRead;
294	return rc;
295	}
296
297	cbMinRead -= (uint8_t)cbRead;
298	cbMaxRead -= (uint8_t)cbRead;
299	cb -= (uint8_t)cbRead;
300	offInstr += (uint8_t)cbRead;
301	GCPtr += cbRead;
302	if (!cb)
303	continue;
304	}
305	}
306	#endif /* VBOX_WITH_RAW_MODE */
307
308	/*
309	* Read and advance,
310	*/
311	memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
312	offInstr += (uint8_t)cb;
313	if (cb >= cbMinRead)
314	{
315	pDis->cbCachedInstr = offInstr;
316	return VINF_SUCCESS;
317	}
318	cbMaxRead -= (uint8_t)cb;
319	cbMinRead -= (uint8_t)cb;
320	}
321	}
322
323
324	/**
325	* @callback_method_impl{FNDISGETSYMBOL}
326	*/
327	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
328	char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
329	{
330	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
331	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
332
333	/*
334	* Address conversion
335	*/
336	DBGFADDRESS Addr;
337	int rc;
338	/* Start with CS. */
339	if ( DIS_FMT_SEL_IS_REG(u32Sel)
340	? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
341	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
342	rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
343	/* In long mode everything but FS and GS is easy. */
344	else if ( pState->Cpu.uCpuMode == DISCPUMODE_64BIT
345	&& DIS_FMT_SEL_IS_REG(u32Sel)
346	&& DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
347	&& DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
348	{
349	DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
350	rc = VINF_SUCCESS;
351	}
352	/* Here's a quick hack to catch patch manager SS relative access. */
353	else if ( DIS_FMT_SEL_IS_REG(u32Sel)
354	&& DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
355	&& pSelInfo->GCPtrBase == 0
356	&& pSelInfo->cbLimit >= UINT32_MAX
357	#ifdef VBOX_WITH_RAW_MODE
358	&& PATMIsPatchGCAddr(pState->pVM, pState->Cpu.uInstrAddr)
359	#endif
360	)
361	{
362	DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
363	rc = VINF_SUCCESS;
364	}
365	else
366	{
367	/** @todo implement a generic solution here. */
368	rc = VERR_SYMBOL_NOT_FOUND;
369	}
370
371	/*
372	* If we got an address, try resolve it into a symbol.
373	*/
374	if (RT_SUCCESS(rc))
375	{
376	RTDBGSYMBOL Sym;
377	RTGCINTPTR off;
378	rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr, RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL,
379	&off, &Sym, NULL /phMod/);
380	if (RT_SUCCESS(rc))
381	{
382	/*
383	* Return the symbol and offset.
384	*/
385	size_t cchName = strlen(Sym.szName);
386	if (cchName >= cchBuf)
387	cchName = cchBuf - 1;
388	memcpy(pszBuf, Sym.szName, cchName);
389	pszBuf[cchName] = '\0';
390
391	*poff = off;
392	}
393	}
394	return rc;
395	}
396
397
398	/**
399	* Disassembles the one instruction according to the specified flags and
400	* address, internal worker executing on the EMT of the specified virtual CPU.
401	*
402	* @returns VBox status code.
403	* @param pVM The cross context VM structure.
404	* @param pVCpu The cross context virtual CPU structure.
405	* @param Sel The code selector. This used to determine the 32/16 bit ness and
406	* calculation of the actual instruction address.
407	* @param pGCPtr Pointer to the variable holding the code address
408	* relative to the base of Sel.
409	* @param fFlags Flags controlling where to start and how to format.
410	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
411	* @param pszOutput Output buffer.
412	* @param cbOutput Size of the output buffer.
413	* @param pcbInstr Where to return the size of the instruction.
414	* @param pDisState Where to store the disassembler state into.
415	*/
416	static DECLCALLBACK(int)
417	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
418	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr, PDBGFDISSTATE pDisState)
419	{
420	VMCPU_ASSERT_EMT(pVCpu);
421	RTGCPTR GCPtr = *pGCPtr;
422	int rc;
423
424	/*
425	* Get the Sel and GCPtr if fFlags requests that.
426	*/
427	PCCPUMCTXCORE pCtxCore = NULL;
428	PCCPUMSELREG pSRegCS = NULL;
429	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
430	{
431	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
432	Sel = pCtxCore->cs.Sel;
433	pSRegCS = &pCtxCore->cs;
434	GCPtr = pCtxCore->rip;
435	}
436	else if (fFlags & DBGF_DISAS_FLAGS_CURRENT_HYPER)
437	{
438	fFlags \|= DBGF_DISAS_FLAGS_HYPER;
439	pCtxCore = CPUMGetHyperCtxCore(pVCpu);
440	Sel = pCtxCore->cs.Sel;
441	GCPtr = pCtxCore->rip;
442	}
443	/*
444	* Check if the selector matches the guest CS, use the hidden
445	* registers from that if they are valid. Saves time and effort.
446	*/
447	else
448	{
449	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
450	if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
451	pSRegCS = &pCtxCore->cs;
452	else
453	pCtxCore = NULL;
454	}
455
456	/*
457	* Read the selector info - assume no stale selectors and nasty stuff like that.
458	*
459	* Note! We CANNOT load invalid hidden selector registers since that would
460	* mean that log/debug statements or the debug will influence the
461	* guest state and make things behave differently.
462	*/
463	DBGFSELINFO SelInfo;
464	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
465	bool fRealModeAddress = false;
466
467	if ( pSRegCS
468	&& CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
469	{
470	SelInfo.Sel = Sel;
471	SelInfo.SelGate = 0;
472	SelInfo.GCPtrBase = pSRegCS->u64Base;
473	SelInfo.cbLimit = pSRegCS->u32Limit;
474	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
475	? DBGFSELINFO_FLAGS_LONG_MODE
476	: enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
477	? DBGFSELINFO_FLAGS_PROT_MODE
478	: DBGFSELINFO_FLAGS_REAL_MODE;
479
480	SelInfo.u.Raw.au32[0] = 0;
481	SelInfo.u.Raw.au32[1] = 0;
482	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
483	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
484	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
485	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
486	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
487	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
488	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
489	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
490	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
491	}
492	else if (Sel == DBGF_SEL_FLAT)
493	{
494	SelInfo.Sel = Sel;
495	SelInfo.SelGate = 0;
496	SelInfo.GCPtrBase = 0;
497	SelInfo.cbLimit = ~(RTGCUINTPTR)0;
498	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
499	? DBGFSELINFO_FLAGS_LONG_MODE
500	: enmMode != PGMMODE_REAL
501	? DBGFSELINFO_FLAGS_PROT_MODE
502	: DBGFSELINFO_FLAGS_REAL_MODE;
503	SelInfo.u.Raw.au32[0] = 0;
504	SelInfo.u.Raw.au32[1] = 0;
505	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
506	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
507
508	pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
509	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
510	{
511	/* Assume the current CS defines the execution mode. */
512	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
513	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
514	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
515	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
516	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
517	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
518	}
519	else
520	{
521	pSRegCS = NULL;
522	SelInfo.u.Raw.Gen.u1Present = 1;
523	SelInfo.u.Raw.Gen.u1Granularity = 1;
524	SelInfo.u.Raw.Gen.u1DefBig = 1;
525	SelInfo.u.Raw.Gen.u1DescType = 1;
526	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
527	}
528	}
529	else if ( !(fFlags & DBGF_DISAS_FLAGS_HYPER)
530	&& ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
531	\|\| enmMode == PGMMODE_REAL
532	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE
533	)
534	)
535	{ /* V86 mode or real mode - real mode addressing */
536	SelInfo.Sel = Sel;
537	SelInfo.SelGate = 0;
538	SelInfo.GCPtrBase = Sel * 16;
539	SelInfo.cbLimit = ~(RTGCUINTPTR)0;
540	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
541	SelInfo.u.Raw.au32[0] = 0;
542	SelInfo.u.Raw.au32[1] = 0;
543	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
544	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
545	SelInfo.u.Raw.Gen.u1Present = 1;
546	SelInfo.u.Raw.Gen.u1Granularity = 1;
547	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
548	SelInfo.u.Raw.Gen.u1DescType = 1;
549	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
550	fRealModeAddress = true;
551	}
552	else
553	{
554	if (!(fFlags & DBGF_DISAS_FLAGS_HYPER))
555	rc = SELMR3GetSelectorInfo(pVM, pVCpu, Sel, &SelInfo);
556	else
557	rc = SELMR3GetShadowSelectorInfo(pVM, Sel, &SelInfo);
558	if (RT_FAILURE(rc))
559	{
560	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
561	return rc;
562	}
563	}
564
565	/*
566	* Disassemble it.
567	*/
568	DBGFDISASSTATE State;
569	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
570	if (RT_FAILURE(rc))
571	{
572	if (State.Cpu.cbCachedInstr)
573	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Cpu.cbCachedInstr, State.Cpu.abInstr);
574	else
575	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
576	return rc;
577	}
578
579	/*
580	* Format it.
581	*/
582	char szBuf[512];
583	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
584	DIS_FMT_FLAGS_RELATIVE_BRANCH,
585	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
586	&SelInfo);
587
588	#ifdef VBOX_WITH_RAW_MODE
589	/*
590	* Patched instruction annotations.
591	*/
592	char szPatchAnnotations[256];
593	szPatchAnnotations[0] = '\0';
594	if (fFlags & DBGF_DISAS_FLAGS_ANNOTATE_PATCHED)
595	PATMR3DbgAnnotatePatchedInstruction(pVM, GCPtr, State.Cpu.cbInstr, szPatchAnnotations, sizeof(szPatchAnnotations));
596	#endif
597
598	/*
599	* Print it to the user specified buffer.
600	*/
601	size_t cch;
602	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
603	{
604	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
605	cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
606	else if (fRealModeAddress)
607	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
608	else if (Sel == DBGF_SEL_FLAT)
609	{
610	if (enmMode >= PGMMODE_AMD64)
611	cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
612	else
613	cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
614	}
615	else
616	{
617	if (enmMode >= PGMMODE_AMD64)
618	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
619	else
620	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
621	}
622	}
623	else
624	{
625	uint32_t cbInstr = State.Cpu.cbInstr;
626	uint8_t const *pabInstr = State.Cpu.abInstr;
627	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
628	cch = RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
629	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
630	szBuf);
631	else if (fRealModeAddress)
632	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
633	Sel, (unsigned)GCPtr,
634	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
635	szBuf);
636	else if (Sel == DBGF_SEL_FLAT)
637	{
638	if (enmMode >= PGMMODE_AMD64)
639	cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
640	GCPtr,
641	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
642	szBuf);
643	else
644	cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
645	(uint32_t)GCPtr,
646	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
647	szBuf);
648	}
649	else
650	{
651	if (enmMode >= PGMMODE_AMD64)
652	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
653	Sel, GCPtr,
654	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
655	szBuf);
656	else
657	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
658	Sel, (uint32_t)GCPtr,
659	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
660	szBuf);
661	}
662	}
663
664	#ifdef VBOX_WITH_RAW_MODE
665	if (szPatchAnnotations[0] && cch + 1 < cbOutput)
666	RTStrPrintf(pszOutput + cch, cbOutput - cch, " ; %s", szPatchAnnotations);
667	#endif
668
669	if (pcbInstr)
670	*pcbInstr = State.Cpu.cbInstr;
671
672	if (pDisState)
673	{
674	pDisState->pCurInstr = State.Cpu.pCurInstr;
675	pDisState->cbInstr = State.Cpu.cbInstr;
676	pDisState->Param1 = State.Cpu.Param1;
677	pDisState->Param2 = State.Cpu.Param2;
678	pDisState->Param3 = State.Cpu.Param3;
679	pDisState->Param4 = State.Cpu.Param4;
680	}
681
682	dbgfR3DisasInstrDone(&State);
683	return VINF_SUCCESS;
684	}
685
686
687	/**
688	* Disassembles the one instruction according to the specified flags and address
689	* returning part of the disassembler state.
690	*
691	* @returns VBox status code.
692	* @param pUVM The user mode VM handle.
693	* @param idCpu The ID of virtual CPU.
694	* @param pAddr The code address.
695	* @param fFlags Flags controlling where to start and how to format.
696	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
697	* @param pszOutput Output buffer. This will always be properly
698	* terminated if @a cbOutput is greater than zero.
699	* @param cbOutput Size of the output buffer.
700	* @param pDisState The disassembler state to fill in.
701	*
702	* @remarks May have to switch to the EMT of the virtual CPU in order to do
703	* address conversion.
704	*/
705	DECLHIDDEN(int) dbgfR3DisasInstrStateEx(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddr, uint32_t fFlags,
706	char *pszOutput, uint32_t cbOutput, PDBGFDISSTATE pDisState)
707	{
708	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
709	*pszOutput = '\0';
710	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
711	PVM pVM = pUVM->pVM;
712	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
713	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
714	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
715	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
716
717	/*
718	* Optimize the common case where we're called on the EMT of idCpu since
719	* we're using this all the time when logging.
720	*/
721	int rc;
722	PVMCPU pVCpu = VMMGetCpu(pVM);
723	if ( pVCpu
724	&& pVCpu->idCpu == idCpu)
725	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
726	else
727	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
728	pVM, VMMGetCpuById(pVM, idCpu), pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
729	return rc;
730	}
731
732	/**
733	* Disassembles the one instruction according to the specified flags and address.
734	*
735	* @returns VBox status code.
736	* @param pUVM The user mode VM handle.
737	* @param idCpu The ID of virtual CPU.
738	* @param Sel The code selector. This used to determine the 32/16 bit ness and
739	* calculation of the actual instruction address.
740	* @param GCPtr The code address relative to the base of Sel.
741	* @param fFlags Flags controlling where to start and how to format.
742	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
743	* @param pszOutput Output buffer. This will always be properly
744	* terminated if @a cbOutput is greater than zero.
745	* @param cbOutput Size of the output buffer.
746	* @param pcbInstr Where to return the size of the instruction.
747	*
748	* @remarks May have to switch to the EMT of the virtual CPU in order to do
749	* address conversion.
750	*/
751	VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
752	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
753	{
754	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
755	*pszOutput = '\0';
756	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
757	PVM pVM = pUVM->pVM;
758	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
759	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
760	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
761	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
762
763	/*
764	* Optimize the common case where we're called on the EMT of idCpu since
765	* we're using this all the time when logging.
766	*/
767	int rc;
768	PVMCPU pVCpu = VMMGetCpu(pVM);
769	if ( pVCpu
770	&& pVCpu->idCpu == idCpu)
771	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
772	else
773	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
774	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
775	return rc;
776	}
777
778
779	/**
780	* Disassembles the current guest context instruction.
781	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
782	*
783	* @returns VBox status code.
784	* @param pVCpu The cross context virtual CPU structure.
785	* @param pszOutput Output buffer. This will always be properly
786	* terminated if @a cbOutput is greater than zero.
787	* @param cbOutput Size of the output buffer.
788	* @thread EMT(pVCpu)
789	*/
790	VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
791	{
792	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
793	*pszOutput = '\0';
794	Assert(VMCPU_IS_EMT(pVCpu));
795
796	RTGCPTR GCPtr = 0;
797	return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
798	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE
799	\| DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
800	pszOutput, cbOutput, NULL, NULL);
801	}
802
803
804	/**
805	* Disassembles the current guest context instruction and writes it to the log.
806	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
807	*
808	* @returns VBox status code.
809	* @param pVCpu The cross context virtual CPU structure.
810	* @param pszPrefix Short prefix string to the disassembly string. (optional)
811	* @thread EMT(pVCpu)
812	*/
813	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
814	{
815	char szBuf[256];
816	szBuf[0] = '\0';
817	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
818	if (RT_FAILURE(rc))
819	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
820	if (pszPrefix && *pszPrefix)
821	{
822	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
823	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
824	else
825	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
826	}
827	else
828	RTLogPrintf("%s\n", szBuf);
829	return rc;
830	}
831
832
833
834	/**
835	* Disassembles the specified guest context instruction and writes it to the log.
836	* Addresses will be attempted resolved to symbols.
837	*
838	* @returns VBox status code.
839	* @param pVCpu The cross context virtual CPU structure of the calling
840	* EMT.
841	* @param Sel The code selector. This used to determine the 32/16
842	* bit-ness and calculation of the actual instruction
843	* address.
844	* @param GCPtr The code address relative to the base of Sel.
845	* @param pszPrefix Short prefix string to the disassembly string.
846	* (optional)
847	* @thread EMT(pVCpu)
848	*/
849	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
850	{
851	Assert(VMCPU_IS_EMT(pVCpu));
852
853	char szBuf[256];
854	RTGCPTR GCPtrTmp = GCPtr;
855	int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
856	&szBuf[0], sizeof(szBuf), NULL, NULL);
857	if (RT_FAILURE(rc))
858	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
859	if (pszPrefix && *pszPrefix)
860	{
861	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
862	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
863	else
864	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
865	}
866	else
867	RTLogPrintf("%s\n", szBuf);
868	return rc;
869	}
870

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source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 64551

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