DBGFDisas.cpp@ 80239

Last change on this file since 80239 was 80191, checked in by vboxsync, 5 years ago
VMM/r3: Refactored VMCPU enumeration in preparation that aCpus will be replaced with a pointer array. Removed two raw-mode offset members from the CPUM and CPUMCPU sub-structures. bugref:9217 bugref:9517
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1	/* $Id: DBGFDisas.cpp 80191 2019-08-08 00:36:57Z vboxsync $ */
2	/** @file
3	* DBGF - Debugger Facility, Disassembler.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define VBOX_BUGREF_9217_PART_I
23	#define LOG_GROUP LOG_GROUP_DBGF
24	#include <VBox/vmm/dbgf.h>
25	#include <VBox/vmm/selm.h>
26	#include <VBox/vmm/mm.h>
27	#include <VBox/vmm/hm.h>
28	#include <VBox/vmm/pgm.h>
29	#include <VBox/vmm/cpum.h>
30	#include "DBGFInternal.h"
31	#include <VBox/dis.h>
32	#include <VBox/err.h>
33	#include <VBox/param.h>
34	#include <VBox/vmm/vm.h>
35	#include <VBox/vmm/uvm.h>
36
37	#include <VBox/log.h>
38	#include <iprt/assert.h>
39	#include <iprt/string.h>
40	#include <iprt/alloca.h>
41	#include <iprt/ctype.h>
42
43
44	/*********************************************************************************************************************************
45	* Structures and Typedefs *
46	*********************************************************************************************************************************/
47	/**
48	* Structure used when disassembling and instructions in DBGF.
49	* This is used so the reader function can get the stuff it needs.
50	*/
51	typedef struct
52	{
53	/** The core structure. */
54	DISCPUSTATE Cpu;
55	/** The cross context VM structure. */
56	PVM pVM;
57	/** The cross context virtual CPU structure. */
58	PVMCPU pVCpu;
59	/** The address space for resolving symbol. */
60	RTDBGAS hDbgAs;
61	/** Pointer to the first byte in the segment. */
62	RTGCUINTPTR GCPtrSegBase;
63	/** Pointer to the byte after the end of the segment. (might have wrapped!) */
64	RTGCUINTPTR GCPtrSegEnd;
65	/** The size of the segment minus 1. */
66	RTGCUINTPTR cbSegLimit;
67	/** The guest paging mode. */
68	PGMMODE enmMode;
69	/** Pointer to the current page - R3 Ptr. */
70	void const *pvPageR3;
71	/** Pointer to the current page - GC Ptr. */
72	RTGCPTR GCPtrPage;
73	/** Pointer to the next instruction (relative to GCPtrSegBase). */
74	RTGCUINTPTR GCPtrNext;
75	/** The lock information that PGMPhysReleasePageMappingLock needs. */
76	PGMPAGEMAPLOCK PageMapLock;
77	/** Whether the PageMapLock is valid or not. */
78	bool fLocked;
79	/** 64 bits mode or not. */
80	bool f64Bits;
81	} DBGFDISASSTATE, *PDBGFDISASSTATE;
82
83
84	/*********************************************************************************************************************************
85	* Internal Functions *
86	*********************************************************************************************************************************/
87	static FNDISREADBYTES dbgfR3DisasInstrRead;
88
89
90
91	/**
92	* Calls the disassembler with the proper reader functions and such for disa
93	*
94	* @returns VBox status code.
95	* @param pVM The cross context VM structure.
96	* @param pVCpu The cross context virtual CPU structure.
97	* @param pSelInfo The selector info.
98	* @param enmMode The guest paging mode.
99	* @param fFlags DBGF_DISAS_FLAGS_XXX.
100	* @param GCPtr The GC pointer (selector offset).
101	* @param pState The disas CPU state.
102	*/
103	static int dbgfR3DisasInstrFirst(PVM pVM, PVMCPU pVCpu, PDBGFSELINFO pSelInfo, PGMMODE enmMode,
104	RTGCPTR GCPtr, uint32_t fFlags, PDBGFDISASSTATE pState)
105	{
106	pState->GCPtrSegBase = pSelInfo->GCPtrBase;
107	pState->GCPtrSegEnd = pSelInfo->cbLimit + 1 + (RTGCUINTPTR)pSelInfo->GCPtrBase;
108	pState->cbSegLimit = pSelInfo->cbLimit;
109	pState->enmMode = enmMode;
110	pState->GCPtrPage = 0;
111	pState->pvPageR3 = NULL;
112	pState->hDbgAs = DBGF_AS_GLOBAL;
113	pState->pVM = pVM;
114	pState->pVCpu = pVCpu;
115	pState->fLocked = false;
116	pState->f64Bits = enmMode >= PGMMODE_AMD64 && pSelInfo->u.Raw.Gen.u1Long;
117
118	DISCPUMODE enmCpuMode;
119	switch (fFlags & DBGF_DISAS_FLAGS_MODE_MASK)
120	{
121	default:
122	AssertFailed();
123	RT_FALL_THRU();
124	case DBGF_DISAS_FLAGS_DEFAULT_MODE:
125	enmCpuMode = pState->f64Bits
126	? DISCPUMODE_64BIT
127	: pSelInfo->u.Raw.Gen.u1DefBig
128	? DISCPUMODE_32BIT
129	: DISCPUMODE_16BIT;
130	break;
131	case DBGF_DISAS_FLAGS_16BIT_MODE:
132	case DBGF_DISAS_FLAGS_16BIT_REAL_MODE:
133	enmCpuMode = DISCPUMODE_16BIT;
134	break;
135	case DBGF_DISAS_FLAGS_32BIT_MODE:
136	enmCpuMode = DISCPUMODE_32BIT;
137	break;
138	case DBGF_DISAS_FLAGS_64BIT_MODE:
139	enmCpuMode = DISCPUMODE_64BIT;
140	break;
141	}
142
143	uint32_t cbInstr;
144	int rc = DISInstrWithReader(GCPtr,
145	enmCpuMode,
146	dbgfR3DisasInstrRead,
147	&pState->Cpu,
148	&pState->Cpu,
149	&cbInstr);
150	if (RT_SUCCESS(rc))
151	{
152	pState->GCPtrNext = GCPtr + cbInstr;
153	return VINF_SUCCESS;
154	}
155
156	/* cleanup */
157	if (pState->fLocked)
158	{
159	PGMPhysReleasePageMappingLock(pVM, &pState->PageMapLock);
160	pState->fLocked = false;
161	}
162	return rc;
163	}
164
165
166	#if 0
167	/**
168	* Calls the disassembler for disassembling the next instruction.
169	*
170	* @returns VBox status code.
171	* @param pState The disas CPU state.
172	*/
173	static int dbgfR3DisasInstrNext(PDBGFDISASSTATE pState)
174	{
175	uint32_t cbInstr;
176	int rc = DISInstr(&pState->Cpu, (void *)pState->GCPtrNext, 0, &cbInstr, NULL);
177	if (RT_SUCCESS(rc))
178	{
179	pState->GCPtrNext = GCPtr + cbInstr;
180	return VINF_SUCCESS;
181	}
182	return rc;
183	}
184	#endif
185
186
187	/**
188	* Done with the disassembler state, free associated resources.
189	*
190	* @param pState The disas CPU state ++.
191	*/
192	static void dbgfR3DisasInstrDone(PDBGFDISASSTATE pState)
193	{
194	if (pState->fLocked)
195	{
196	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
197	pState->fLocked = false;
198	}
199	}
200
201
202	/**
203	* @callback_method_impl{FNDISREADBYTES}
204	*
205	* @remarks The source is relative to the base address indicated by
206	* DBGFDISASSTATE::GCPtrSegBase.
207	*/
208	static DECLCALLBACK(int) dbgfR3DisasInstrRead(PDISCPUSTATE pDis, uint8_t offInstr, uint8_t cbMinRead, uint8_t cbMaxRead)
209	{
210	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
211	for (;;)
212	{
213	RTGCUINTPTR GCPtr = pDis->uInstrAddr + offInstr + pState->GCPtrSegBase;
214
215	/*
216	* Need to update the page translation?
217	*/
218	if ( !pState->pvPageR3
219	\|\| (GCPtr >> PAGE_SHIFT) != (pState->GCPtrPage >> PAGE_SHIFT))
220	{
221	int rc = VINF_SUCCESS;
222
223	/* translate the address */
224	pState->GCPtrPage = GCPtr & PAGE_BASE_GC_MASK;
225	if (pState->fLocked)
226	PGMPhysReleasePageMappingLock(pState->pVM, &pState->PageMapLock);
227	if (pState->enmMode <= PGMMODE_PROTECTED)
228	rc = PGMPhysGCPhys2CCPtrReadOnly(pState->pVM, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
229	else
230	rc = PGMPhysGCPtr2CCPtrReadOnly(pState->pVCpu, pState->GCPtrPage, &pState->pvPageR3, &pState->PageMapLock);
231	if (RT_SUCCESS(rc))
232	pState->fLocked = true;
233	else
234	{
235	pState->fLocked = false;
236	pState->pvPageR3 = NULL;
237	return rc;
238	}
239	}
240
241	/*
242	* Check the segment limit.
243	*/
244	if (!pState->f64Bits && pDis->uInstrAddr + offInstr > pState->cbSegLimit)
245	return VERR_OUT_OF_SELECTOR_BOUNDS;
246
247	/*
248	* Calc how much we can read, maxing out the read.
249	*/
250	uint32_t cb = PAGE_SIZE - (GCPtr & PAGE_OFFSET_MASK);
251	if (!pState->f64Bits)
252	{
253	RTGCUINTPTR cbSeg = pState->GCPtrSegEnd - GCPtr;
254	if (cb > cbSeg && cbSeg)
255	cb = cbSeg;
256	}
257	if (cb > cbMaxRead)
258	cb = cbMaxRead;
259
260	/*
261	* Read and advance,
262	*/
263	memcpy(&pDis->abInstr[offInstr], (char *)pState->pvPageR3 + (GCPtr & PAGE_OFFSET_MASK), cb);
264	offInstr += (uint8_t)cb;
265	if (cb >= cbMinRead)
266	{
267	pDis->cbCachedInstr = offInstr;
268	return VINF_SUCCESS;
269	}
270	cbMaxRead -= (uint8_t)cb;
271	cbMinRead -= (uint8_t)cb;
272	}
273	}
274
275
276	/**
277	* @callback_method_impl{FNDISGETSYMBOL}
278	*/
279	static DECLCALLBACK(int) dbgfR3DisasGetSymbol(PCDISCPUSTATE pDis, uint32_t u32Sel, RTUINTPTR uAddress,
280	char pszBuf, size_t cchBuf, RTINTPTR poff, void *pvUser)
281	{
282	PDBGFDISASSTATE pState = (PDBGFDISASSTATE)pDis;
283	PCDBGFSELINFO pSelInfo = (PCDBGFSELINFO)pvUser;
284
285	/*
286	* Address conversion
287	*/
288	DBGFADDRESS Addr;
289	int rc;
290	/* Start with CS. */
291	if ( DIS_FMT_SEL_IS_REG(u32Sel)
292	? DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_CS
293	: pSelInfo->Sel == DIS_FMT_SEL_GET_VALUE(u32Sel))
294	rc = DBGFR3AddrFromSelInfoOff(pState->pVM->pUVM, &Addr, pSelInfo, uAddress);
295	/* In long mode everything but FS and GS is easy. */
296	else if ( pState->Cpu.uCpuMode == DISCPUMODE_64BIT
297	&& DIS_FMT_SEL_IS_REG(u32Sel)
298	&& DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_GS
299	&& DIS_FMT_SEL_GET_REG(u32Sel) != DISSELREG_FS)
300	{
301	DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
302	rc = VINF_SUCCESS;
303	}
304	/* Here's a quick hack to catch patch manager SS relative access. */
305	else if ( DIS_FMT_SEL_IS_REG(u32Sel)
306	&& DIS_FMT_SEL_GET_REG(u32Sel) == DISSELREG_SS
307	&& pSelInfo->GCPtrBase == 0
308	&& pSelInfo->cbLimit >= UINT32_MAX)
309	{
310	DBGFR3AddrFromFlat(pState->pVM->pUVM, &Addr, uAddress);
311	rc = VINF_SUCCESS;
312	}
313	else
314	{
315	/** @todo implement a generic solution here. */
316	rc = VERR_SYMBOL_NOT_FOUND;
317	}
318
319	/*
320	* If we got an address, try resolve it into a symbol.
321	*/
322	if (RT_SUCCESS(rc))
323	{
324	RTDBGSYMBOL Sym;
325	RTGCINTPTR off;
326	rc = DBGFR3AsSymbolByAddr(pState->pVM->pUVM, pState->hDbgAs, &Addr,
327	RTDBGSYMADDR_FLAGS_LESS_OR_EQUAL \| RTDBGSYMADDR_FLAGS_SKIP_ABS_IN_DEFERRED,
328	&off, &Sym, NULL /phMod/);
329	if (RT_SUCCESS(rc))
330	{
331	/*
332	* Return the symbol and offset.
333	*/
334	size_t cchName = strlen(Sym.szName);
335	if (cchName >= cchBuf)
336	cchName = cchBuf - 1;
337	memcpy(pszBuf, Sym.szName, cchName);
338	pszBuf[cchName] = '\0';
339
340	*poff = off;
341	}
342	}
343	return rc;
344	}
345
346
347	/**
348	* Disassembles the one instruction according to the specified flags and
349	* address, internal worker executing on the EMT of the specified virtual CPU.
350	*
351	* @returns VBox status code.
352	* @param pVM The cross context VM structure.
353	* @param pVCpu The cross context virtual CPU structure.
354	* @param Sel The code selector. This used to determine the 32/16 bit ness and
355	* calculation of the actual instruction address.
356	* @param pGCPtr Pointer to the variable holding the code address
357	* relative to the base of Sel.
358	* @param fFlags Flags controlling where to start and how to format.
359	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
360	* @param pszOutput Output buffer.
361	* @param cbOutput Size of the output buffer.
362	* @param pcbInstr Where to return the size of the instruction.
363	* @param pDisState Where to store the disassembler state into.
364	*/
365	static DECLCALLBACK(int)
366	dbgfR3DisasInstrExOnVCpu(PVM pVM, PVMCPU pVCpu, RTSEL Sel, PRTGCPTR pGCPtr, uint32_t fFlags,
367	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr, PDBGFDISSTATE pDisState)
368	{
369	VMCPU_ASSERT_EMT(pVCpu);
370	RTGCPTR GCPtr = *pGCPtr;
371	int rc;
372
373	/*
374	* Get the Sel and GCPtr if fFlags requests that.
375	*/
376	PCCPUMCTXCORE pCtxCore = NULL;
377	PCCPUMSELREG pSRegCS = NULL;
378	if (fFlags & DBGF_DISAS_FLAGS_CURRENT_GUEST)
379	{
380	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
381	Sel = pCtxCore->cs.Sel;
382	pSRegCS = &pCtxCore->cs;
383	GCPtr = pCtxCore->rip;
384	}
385	/*
386	* Check if the selector matches the guest CS, use the hidden
387	* registers from that if they are valid. Saves time and effort.
388	*/
389	else
390	{
391	pCtxCore = CPUMGetGuestCtxCore(pVCpu);
392	if (pCtxCore->cs.Sel == Sel && Sel != DBGF_SEL_FLAT)
393	pSRegCS = &pCtxCore->cs;
394	else
395	pCtxCore = NULL;
396	}
397
398	/*
399	* Read the selector info - assume no stale selectors and nasty stuff like that.
400	*
401	* Note! We CANNOT load invalid hidden selector registers since that would
402	* mean that log/debug statements or the debug will influence the
403	* guest state and make things behave differently.
404	*/
405	DBGFSELINFO SelInfo;
406	const PGMMODE enmMode = PGMGetGuestMode(pVCpu);
407	bool fRealModeAddress = false;
408
409	if ( pSRegCS
410	&& CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
411	{
412	SelInfo.Sel = Sel;
413	SelInfo.SelGate = 0;
414	SelInfo.GCPtrBase = pSRegCS->u64Base;
415	SelInfo.cbLimit = pSRegCS->u32Limit;
416	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
417	? DBGFSELINFO_FLAGS_LONG_MODE
418	: enmMode != PGMMODE_REAL && !pCtxCore->eflags.Bits.u1VM
419	? DBGFSELINFO_FLAGS_PROT_MODE
420	: DBGFSELINFO_FLAGS_REAL_MODE;
421
422	SelInfo.u.Raw.au32[0] = 0;
423	SelInfo.u.Raw.au32[1] = 0;
424	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
425	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
426	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
427	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
428	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
429	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
430	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
431	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
432	fRealModeAddress = !!(SelInfo.fFlags & DBGFSELINFO_FLAGS_REAL_MODE);
433	}
434	else if (Sel == DBGF_SEL_FLAT)
435	{
436	SelInfo.Sel = Sel;
437	SelInfo.SelGate = 0;
438	SelInfo.GCPtrBase = 0;
439	SelInfo.cbLimit = ~(RTGCUINTPTR)0;
440	SelInfo.fFlags = PGMMODE_IS_LONG_MODE(enmMode)
441	? DBGFSELINFO_FLAGS_LONG_MODE
442	: enmMode != PGMMODE_REAL
443	? DBGFSELINFO_FLAGS_PROT_MODE
444	: DBGFSELINFO_FLAGS_REAL_MODE;
445	SelInfo.u.Raw.au32[0] = 0;
446	SelInfo.u.Raw.au32[1] = 0;
447	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
448	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
449
450	pSRegCS = &CPUMGetGuestCtxCore(pVCpu)->cs;
451	if (CPUMSELREG_ARE_HIDDEN_PARTS_VALID(pVCpu, pSRegCS))
452	{
453	/* Assume the current CS defines the execution mode. */
454	SelInfo.u.Raw.Gen.u1Present = pSRegCS->Attr.n.u1Present;
455	SelInfo.u.Raw.Gen.u1Granularity = pSRegCS->Attr.n.u1Granularity;;
456	SelInfo.u.Raw.Gen.u1DefBig = pSRegCS->Attr.n.u1DefBig;
457	SelInfo.u.Raw.Gen.u1Long = pSRegCS->Attr.n.u1Long;
458	SelInfo.u.Raw.Gen.u1DescType = pSRegCS->Attr.n.u1DescType;
459	SelInfo.u.Raw.Gen.u4Type = pSRegCS->Attr.n.u4Type;
460	}
461	else
462	{
463	pSRegCS = NULL;
464	SelInfo.u.Raw.Gen.u1Present = 1;
465	SelInfo.u.Raw.Gen.u1Granularity = 1;
466	SelInfo.u.Raw.Gen.u1DefBig = 1;
467	SelInfo.u.Raw.Gen.u1DescType = 1;
468	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
469	}
470	}
471	else if ( (pCtxCore && pCtxCore->eflags.Bits.u1VM)
472	\|\| enmMode == PGMMODE_REAL
473	\|\| (fFlags & DBGF_DISAS_FLAGS_MODE_MASK) == DBGF_DISAS_FLAGS_16BIT_REAL_MODE)
474	{ /* V86 mode or real mode - real mode addressing */
475	SelInfo.Sel = Sel;
476	SelInfo.SelGate = 0;
477	SelInfo.GCPtrBase = Sel * 16;
478	SelInfo.cbLimit = ~(RTGCUINTPTR)0;
479	SelInfo.fFlags = DBGFSELINFO_FLAGS_REAL_MODE;
480	SelInfo.u.Raw.au32[0] = 0;
481	SelInfo.u.Raw.au32[1] = 0;
482	SelInfo.u.Raw.Gen.u16LimitLow = 0xffff;
483	SelInfo.u.Raw.Gen.u4LimitHigh = 0xf;
484	SelInfo.u.Raw.Gen.u1Present = 1;
485	SelInfo.u.Raw.Gen.u1Granularity = 1;
486	SelInfo.u.Raw.Gen.u1DefBig = 0; /* 16 bits */
487	SelInfo.u.Raw.Gen.u1DescType = 1;
488	SelInfo.u.Raw.Gen.u4Type = X86_SEL_TYPE_EO;
489	fRealModeAddress = true;
490	}
491	else
492	{
493	rc = SELMR3GetSelectorInfo(pVCpu, Sel, &SelInfo);
494	if (RT_FAILURE(rc))
495	{
496	RTStrPrintf(pszOutput, cbOutput, "Sel=%04x -> %Rrc\n", Sel, rc);
497	return rc;
498	}
499	}
500
501	/*
502	* Disassemble it.
503	*/
504	DBGFDISASSTATE State;
505	rc = dbgfR3DisasInstrFirst(pVM, pVCpu, &SelInfo, enmMode, GCPtr, fFlags, &State);
506	if (RT_FAILURE(rc))
507	{
508	if (State.Cpu.cbCachedInstr)
509	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc; %.*Rhxs\n", rc, (size_t)State.Cpu.cbCachedInstr, State.Cpu.abInstr);
510	else
511	RTStrPrintf(pszOutput, cbOutput, "Disas -> %Rrc\n", rc);
512	return rc;
513	}
514
515	/*
516	* Format it.
517	*/
518	char szBuf[512];
519	DISFormatYasmEx(&State.Cpu, szBuf, sizeof(szBuf),
520	DIS_FMT_FLAGS_RELATIVE_BRANCH,
521	fFlags & DBGF_DISAS_FLAGS_NO_SYMBOLS ? NULL : dbgfR3DisasGetSymbol,
522	&SelInfo);
523
524	/*
525	* Print it to the user specified buffer.
526	*/
527	size_t cch;
528	if (fFlags & DBGF_DISAS_FLAGS_NO_BYTES)
529	{
530	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
531	cch = RTStrPrintf(pszOutput, cbOutput, "%s", szBuf);
532	else if (fRealModeAddress)
533	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %s", Sel, (unsigned)GCPtr, szBuf);
534	else if (Sel == DBGF_SEL_FLAT)
535	{
536	if (enmMode >= PGMMODE_AMD64)
537	cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %s", GCPtr, szBuf);
538	else
539	cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %s", (uint32_t)GCPtr, szBuf);
540	}
541	else
542	{
543	if (enmMode >= PGMMODE_AMD64)
544	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %s", Sel, GCPtr, szBuf);
545	else
546	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %s", Sel, (uint32_t)GCPtr, szBuf);
547	}
548	}
549	else
550	{
551	uint32_t cbInstr = State.Cpu.cbInstr;
552	uint8_t const *pabInstr = State.Cpu.abInstr;
553	if (fFlags & DBGF_DISAS_FLAGS_NO_ADDRESS)
554	cch = RTStrPrintf(pszOutput, cbOutput, "%.Rhxs%s %s",
555	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
556	szBuf);
557	else if (fRealModeAddress)
558	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%04x %.Rhxs%s %s",
559	Sel, (unsigned)GCPtr,
560	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
561	szBuf);
562	else if (Sel == DBGF_SEL_FLAT)
563	{
564	if (enmMode >= PGMMODE_AMD64)
565	cch = RTStrPrintf(pszOutput, cbOutput, "%RGv %.Rhxs%s %s",
566	GCPtr,
567	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
568	szBuf);
569	else
570	cch = RTStrPrintf(pszOutput, cbOutput, "%08RX32 %.Rhxs%s %s",
571	(uint32_t)GCPtr,
572	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
573	szBuf);
574	}
575	else
576	{
577	if (enmMode >= PGMMODE_AMD64)
578	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%RGv %.Rhxs%s %s",
579	Sel, GCPtr,
580	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
581	szBuf);
582	else
583	cch = RTStrPrintf(pszOutput, cbOutput, "%04x:%08RX32 %.Rhxs%s %s",
584	Sel, (uint32_t)GCPtr,
585	cbInstr, pabInstr, cbInstr < 8 ? (8 - cbInstr) * 3 : 0, "",
586	szBuf);
587	}
588	}
589
590	if (pcbInstr)
591	*pcbInstr = State.Cpu.cbInstr;
592
593	if (pDisState)
594	{
595	pDisState->pCurInstr = State.Cpu.pCurInstr;
596	pDisState->cbInstr = State.Cpu.cbInstr;
597	pDisState->Param1 = State.Cpu.Param1;
598	pDisState->Param2 = State.Cpu.Param2;
599	pDisState->Param3 = State.Cpu.Param3;
600	pDisState->Param4 = State.Cpu.Param4;
601	}
602
603	dbgfR3DisasInstrDone(&State);
604	return VINF_SUCCESS;
605	}
606
607
608	/**
609	* Disassembles the one instruction according to the specified flags and address
610	* returning part of the disassembler state.
611	*
612	* @returns VBox status code.
613	* @param pUVM The user mode VM handle.
614	* @param idCpu The ID of virtual CPU.
615	* @param pAddr The code address.
616	* @param fFlags Flags controlling where to start and how to format.
617	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
618	* @param pszOutput Output buffer. This will always be properly
619	* terminated if @a cbOutput is greater than zero.
620	* @param cbOutput Size of the output buffer.
621	* @param pDisState The disassembler state to fill in.
622	*
623	* @remarks May have to switch to the EMT of the virtual CPU in order to do
624	* address conversion.
625	*/
626	DECLHIDDEN(int) dbgfR3DisasInstrStateEx(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddr, uint32_t fFlags,
627	char *pszOutput, uint32_t cbOutput, PDBGFDISSTATE pDisState)
628	{
629	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
630	*pszOutput = '\0';
631	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
632	PVM pVM = pUVM->pVM;
633	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
634	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
635	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
636	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
637
638	/*
639	* Optimize the common case where we're called on the EMT of idCpu since
640	* we're using this all the time when logging.
641	*/
642	int rc;
643	PVMCPU pVCpu = VMMGetCpu(pVM);
644	if ( pVCpu
645	&& pVCpu->idCpu == idCpu)
646	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
647	else
648	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
649	pVM, VMMGetCpuById(pVM, idCpu), pAddr->Sel, &pAddr->off, fFlags, pszOutput, cbOutput, NULL, pDisState);
650	return rc;
651	}
652
653	/**
654	* Disassembles the one instruction according to the specified flags and address.
655	*
656	* @returns VBox status code.
657	* @param pUVM The user mode VM handle.
658	* @param idCpu The ID of virtual CPU.
659	* @param Sel The code selector. This used to determine the 32/16 bit ness and
660	* calculation of the actual instruction address.
661	* @param GCPtr The code address relative to the base of Sel.
662	* @param fFlags Flags controlling where to start and how to format.
663	* A combination of the DBGF_DISAS_FLAGS_* \#defines.
664	* @param pszOutput Output buffer. This will always be properly
665	* terminated if @a cbOutput is greater than zero.
666	* @param cbOutput Size of the output buffer.
667	* @param pcbInstr Where to return the size of the instruction.
668	*
669	* @remarks May have to switch to the EMT of the virtual CPU in order to do
670	* address conversion.
671	*/
672	VMMR3DECL(int) DBGFR3DisasInstrEx(PUVM pUVM, VMCPUID idCpu, RTSEL Sel, RTGCPTR GCPtr, uint32_t fFlags,
673	char pszOutput, uint32_t cbOutput, uint32_t pcbInstr)
674	{
675	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
676	*pszOutput = '\0';
677	UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
678	PVM pVM = pUVM->pVM;
679	VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
680	AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
681	AssertReturn(!(fFlags & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
682	AssertReturn((fFlags & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
683
684	/*
685	* Optimize the common case where we're called on the EMT of idCpu since
686	* we're using this all the time when logging.
687	*/
688	int rc;
689	PVMCPU pVCpu = VMMGetCpu(pVM);
690	if ( pVCpu
691	&& pVCpu->idCpu == idCpu)
692	rc = dbgfR3DisasInstrExOnVCpu(pVM, pVCpu, Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
693	else
694	rc = VMR3ReqPriorityCallWait(pVM, idCpu, (PFNRT)dbgfR3DisasInstrExOnVCpu, 9,
695	pVM, VMMGetCpuById(pVM, idCpu), Sel, &GCPtr, fFlags, pszOutput, cbOutput, pcbInstr, NULL);
696	return rc;
697	}
698
699
700	/**
701	* Disassembles the current guest context instruction.
702	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
703	*
704	* @returns VBox status code.
705	* @param pVCpu The cross context virtual CPU structure.
706	* @param pszOutput Output buffer. This will always be properly
707	* terminated if @a cbOutput is greater than zero.
708	* @param cbOutput Size of the output buffer.
709	* @thread EMT(pVCpu)
710	*/
711	VMMR3_INT_DECL(int) DBGFR3DisasInstrCurrent(PVMCPU pVCpu, char *pszOutput, uint32_t cbOutput)
712	{
713	AssertReturn(cbOutput > 0, VERR_INVALID_PARAMETER);
714	*pszOutput = '\0';
715	Assert(VMCPU_IS_EMT(pVCpu));
716
717	RTGCPTR GCPtr = 0;
718	return dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, 0, &GCPtr,
719	DBGF_DISAS_FLAGS_CURRENT_GUEST \| DBGF_DISAS_FLAGS_DEFAULT_MODE
720	\| DBGF_DISAS_FLAGS_ANNOTATE_PATCHED,
721	pszOutput, cbOutput, NULL, NULL);
722	}
723
724
725	/**
726	* Disassembles the current guest context instruction and writes it to the log.
727	* All registers and data will be displayed. Addresses will be attempted resolved to symbols.
728	*
729	* @returns VBox status code.
730	* @param pVCpu The cross context virtual CPU structure.
731	* @param pszPrefix Short prefix string to the disassembly string. (optional)
732	* @thread EMT(pVCpu)
733	*/
734	VMMR3DECL(int) DBGFR3DisasInstrCurrentLogInternal(PVMCPU pVCpu, const char *pszPrefix)
735	{
736	char szBuf[256];
737	szBuf[0] = '\0';
738	int rc = DBGFR3DisasInstrCurrent(pVCpu, &szBuf[0], sizeof(szBuf));
739	if (RT_FAILURE(rc))
740	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrCurrentLog failed with rc=%Rrc\n", rc);
741	if (pszPrefix && *pszPrefix)
742	{
743	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
744	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
745	else
746	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
747	}
748	else
749	RTLogPrintf("%s\n", szBuf);
750	return rc;
751	}
752
753
754
755	/**
756	* Disassembles the specified guest context instruction and writes it to the log.
757	* Addresses will be attempted resolved to symbols.
758	*
759	* @returns VBox status code.
760	* @param pVCpu The cross context virtual CPU structure of the calling
761	* EMT.
762	* @param Sel The code selector. This used to determine the 32/16
763	* bit-ness and calculation of the actual instruction
764	* address.
765	* @param GCPtr The code address relative to the base of Sel.
766	* @param pszPrefix Short prefix string to the disassembly string.
767	* (optional)
768	* @thread EMT(pVCpu)
769	*/
770	VMMR3DECL(int) DBGFR3DisasInstrLogInternal(PVMCPU pVCpu, RTSEL Sel, RTGCPTR GCPtr, const char *pszPrefix)
771	{
772	Assert(VMCPU_IS_EMT(pVCpu));
773
774	char szBuf[256];
775	RTGCPTR GCPtrTmp = GCPtr;
776	int rc = dbgfR3DisasInstrExOnVCpu(pVCpu->pVMR3, pVCpu, Sel, &GCPtrTmp, DBGF_DISAS_FLAGS_DEFAULT_MODE,
777	&szBuf[0], sizeof(szBuf), NULL, NULL);
778	if (RT_FAILURE(rc))
779	RTStrPrintf(szBuf, sizeof(szBuf), "DBGFR3DisasInstrLog(, %RTsel, %RGv) failed with rc=%Rrc\n", Sel, GCPtr, rc);
780	if (pszPrefix && *pszPrefix)
781	{
782	if (pVCpu->CTX_SUFF(pVM)->cCpus > 1)
783	RTLogPrintf("%s-CPU%u: %s\n", pszPrefix, pVCpu->idCpu, szBuf);
784	else
785	RTLogPrintf("%s: %s\n", pszPrefix, szBuf);
786	}
787	else
788	RTLogPrintf("%s\n", szBuf);
789	return rc;
790	}
791

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source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFDisas.cpp@ 80239

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