VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/DBGFR3Flow.cpp@ 66651

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1/* $Id: DBGFR3Flow.cpp 66104 2017-03-15 10:06:21Z vboxsync $ */
2/** @file
3 * DBGF - Debugger Facility, Control Flow Graph Interface (CFG).
4 */
5
6/*
7 * Copyright (C) 2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/** @page pg_dbgf_cfg DBGFR3Flow - Control Flow Graph Interface
20 *
21 * The control flow graph interface provides an API to disassemble
22 * guest code providing the result in a control flow graph.
23 */
24
25
26/*********************************************************************************************************************************
27* Header Files *
28*********************************************************************************************************************************/
29#define LOG_GROUP LOG_GROUP_DBGF
30#include <VBox/vmm/dbgf.h>
31#include "DBGFInternal.h"
32#include <VBox/vmm/mm.h>
33#include <VBox/vmm/uvm.h>
34#include <VBox/vmm/vm.h>
35#include <VBox/err.h>
36#include <VBox/log.h>
37
38#include <iprt/assert.h>
39#include <iprt/thread.h>
40#include <iprt/param.h>
41#include <iprt/list.h>
42#include <iprt/mem.h>
43#include <iprt/sort.h>
44#include <iprt/strcache.h>
45
46/*********************************************************************************************************************************
47* Defined Constants And Macros *
48*********************************************************************************************************************************/
49
50
51
52/*********************************************************************************************************************************
53* Structures and Typedefs *
54*********************************************************************************************************************************/
55
56/**
57 * Internal control flow graph state.
58 */
59typedef struct DBGFFLOWINT
60{
61 /** Reference counter. */
62 uint32_t volatile cRefs;
63 /** Internal reference counter for basic blocks. */
64 uint32_t volatile cRefsBb;
65 /** Flags during creation. */
66 uint32_t fFlags;
67 /** List of all basic blocks. */
68 RTLISTANCHOR LstFlowBb;
69 /** List of identified branch tables. */
70 RTLISTANCHOR LstBranchTbl;
71 /** Number of basic blocks in this control flow graph. */
72 uint32_t cBbs;
73 /** Number of branch tables in this control flow graph. */
74 uint32_t cBranchTbls;
75 /** The lowest addres of a basic block. */
76 DBGFADDRESS AddrLowest;
77 /** The highest address of a basic block. */
78 DBGFADDRESS AddrHighest;
79 /** String cache for disassembled instructions. */
80 RTSTRCACHE hStrCacheInstr;
81} DBGFFLOWINT;
82/** Pointer to an internal control flow graph state. */
83typedef DBGFFLOWINT *PDBGFFLOWINT;
84
85/**
86 * Instruction record
87 */
88typedef struct DBGFFLOWBBINSTR
89{
90 /** Instruction address. */
91 DBGFADDRESS AddrInstr;
92 /** Size of instruction. */
93 uint32_t cbInstr;
94 /** Disassembled instruction string. */
95 const char *pszInstr;
96} DBGFFLOWBBINSTR;
97/** Pointer to an instruction record. */
98typedef DBGFFLOWBBINSTR *PDBGFFLOWBBINSTR;
99
100
101/**
102 * A branch table identified by the graph processor.
103 */
104typedef struct DBGFFLOWBRANCHTBLINT
105{
106 /** Node for the list of branch tables. */
107 RTLISTNODE NdBranchTbl;
108 /** The owning control flow graph. */
109 PDBGFFLOWINT pFlow;
110 /** Reference counter. */
111 uint32_t volatile cRefs;
112 /** The general register index holding the bracnh table base. */
113 uint8_t idxGenRegBase;
114 /** Start address of the branch table. */
115 DBGFADDRESS AddrStart;
116 /** Number of valid entries in the branch table. */
117 uint32_t cSlots;
118 /** The addresses contained in the branch table - variable in size. */
119 DBGFADDRESS aAddresses[1];
120} DBGFFLOWBRANCHTBLINT;
121/** Pointer to a branch table structure. */
122typedef DBGFFLOWBRANCHTBLINT *PDBGFFLOWBRANCHTBLINT;
123
124
125/**
126 * Internal control flow graph basic block state.
127 */
128typedef struct DBGFFLOWBBINT
129{
130 /** Node for the list of all basic blocks. */
131 RTLISTNODE NdFlowBb;
132 /** The control flow graph the basic block belongs to. */
133 PDBGFFLOWINT pFlow;
134 /** Reference counter. */
135 uint32_t volatile cRefs;
136 /** Basic block end type. */
137 DBGFFLOWBBENDTYPE enmEndType;
138 /** Start address of this basic block. */
139 DBGFADDRESS AddrStart;
140 /** End address of this basic block. */
141 DBGFADDRESS AddrEnd;
142 /** Address of the block succeeding.
143 * This is valid for conditional jumps
144 * (the other target is referenced by AddrEnd+1) and
145 * unconditional jumps (not ret, iret, etc.) except
146 * if we can't infer the jump target (jmp *eax for example). */
147 DBGFADDRESS AddrTarget;
148 /** The indirect branch table identified for indirect branches. */
149 PDBGFFLOWBRANCHTBLINT pFlowBranchTbl;
150 /** Last status error code if DBGF_FLOW_BB_F_INCOMPLETE_ERR is set. */
151 int rcError;
152 /** Error message if DBGF_FLOW_BB_F_INCOMPLETE_ERR is set. */
153 char *pszErr;
154 /** Flags for this basic block. */
155 uint32_t fFlags;
156 /** Number of instructions in this basic block. */
157 uint32_t cInstr;
158 /** Maximum number of instruction records for this basic block. */
159 uint32_t cInstrMax;
160 /** Instruction records, variable in size. */
161 DBGFFLOWBBINSTR aInstr[1];
162} DBGFFLOWBBINT;
163/** Pointer to an internal control flow graph basic block state. */
164typedef DBGFFLOWBBINT *PDBGFFLOWBBINT;
165
166
167/**
168 * Control flow graph iterator state.
169 */
170typedef struct DBGFFLOWITINT
171{
172 /** Pointer to the control flow graph (holding a reference). */
173 PDBGFFLOWINT pFlow;
174 /** Next basic block to return. */
175 uint32_t idxBbNext;
176 /** Array of basic blocks sorted by the specified order - variable in size. */
177 PDBGFFLOWBBINT apBb[1];
178} DBGFFLOWITINT;
179/** Pointer to the internal control flow graph iterator state. */
180typedef DBGFFLOWITINT *PDBGFFLOWITINT;
181
182
183/**
184 * Control flow graph branch table iterator state.
185 */
186typedef struct DBGFFLOWBRANCHTBLITINT
187{
188 /** Pointer to the control flow graph (holding a reference). */
189 PDBGFFLOWINT pFlow;
190 /** Next branch table to return. */
191 uint32_t idxTblNext;
192 /** Array of branch table pointers sorted by the specified order - variable in size. */
193 PDBGFFLOWBRANCHTBLINT apBranchTbl[1];
194} DBGFFLOWBRANCHTBLITINT;
195/** Pointer to the internal control flow graph branch table iterator state. */
196typedef DBGFFLOWBRANCHTBLITINT *PDBGFFLOWBRANCHTBLITINT;
197
198/*********************************************************************************************************************************
199* Internal Functions *
200*********************************************************************************************************************************/
201
202static uint32_t dbgfR3FlowBbReleaseInt(PDBGFFLOWBBINT pFlowBb, bool fMayDestroyFlow);
203static void dbgfR3FlowBranchTblDestroy(PDBGFFLOWBRANCHTBLINT pFlowBranchTbl);
204
205
206/**
207 * Checks whether both addresses are equal.
208 *
209 * @returns true if both addresses point to the same location, false otherwise.
210 * @param pAddr1 First address.
211 * @param pAddr2 Second address.
212 */
213static bool dbgfR3FlowAddrEqual(PDBGFADDRESS pAddr1, PDBGFADDRESS pAddr2)
214{
215 return pAddr1->Sel == pAddr2->Sel
216 && pAddr1->off == pAddr2->off;
217}
218
219
220/**
221 * Checks whether the first given address is lower than the second one.
222 *
223 * @returns true if both addresses point to the same location, false otherwise.
224 * @param pAddr1 First address.
225 * @param pAddr2 Second address.
226 */
227static bool dbgfR3FlowAddrLower(PDBGFADDRESS pAddr1, PDBGFADDRESS pAddr2)
228{
229 return pAddr1->Sel == pAddr2->Sel
230 && pAddr1->off < pAddr2->off;
231}
232
233
234/**
235 * Checks whether the given basic block and address intersect.
236 *
237 * @returns true if they intersect, false otherwise.
238 * @param pFlowBb The basic block to check.
239 * @param pAddr The address to check for.
240 */
241static bool dbgfR3FlowAddrIntersect(PDBGFFLOWBBINT pFlowBb, PDBGFADDRESS pAddr)
242{
243 return (pFlowBb->AddrStart.Sel == pAddr->Sel)
244 && (pFlowBb->AddrStart.off <= pAddr->off)
245 && (pFlowBb->AddrEnd.off >= pAddr->off);
246}
247
248
249/**
250 * Returns the distance of the two given addresses.
251 *
252 * @returns Distance of the addresses.
253 * @param pAddr1 The first address.
254 * @param pAddr2 The second address.
255 */
256static RTGCUINTPTR dbgfR3FlowAddrGetDistance(PDBGFADDRESS pAddr1, PDBGFADDRESS pAddr2)
257{
258 if (pAddr1->Sel == pAddr2->Sel)
259 {
260 if (pAddr1->off >= pAddr2->off)
261 return pAddr1->off - pAddr2->off;
262 else
263 return pAddr2->off - pAddr1->off;
264 }
265 else
266 AssertFailed();
267
268 return 0;
269}
270
271
272/**
273 * Creates a new basic block.
274 *
275 * @returns Pointer to the basic block on success or NULL if out of memory.
276 * @param pThis The control flow graph.
277 * @param pAddrStart The start of the basic block.
278 * @param fFlowBbFlags Additional flags for this bascic block.
279 * @param cInstrMax Maximum number of instructions this block can hold initially.
280 */
281static PDBGFFLOWBBINT dbgfR3FlowBbCreate(PDBGFFLOWINT pThis, PDBGFADDRESS pAddrStart, uint32_t fFlowBbFlags,
282 uint32_t cInstrMax)
283{
284 PDBGFFLOWBBINT pFlowBb = (PDBGFFLOWBBINT)RTMemAllocZ(RT_OFFSETOF(DBGFFLOWBBINT, aInstr[cInstrMax]));
285 if (RT_LIKELY(pFlowBb))
286 {
287 RTListInit(&pFlowBb->NdFlowBb);
288 pFlowBb->cRefs = 1;
289 pFlowBb->enmEndType = DBGFFLOWBBENDTYPE_INVALID;
290 pFlowBb->pFlow = pThis;
291 pFlowBb->fFlags = DBGF_FLOW_BB_F_EMPTY | fFlowBbFlags;
292 pFlowBb->AddrStart = *pAddrStart;
293 pFlowBb->AddrEnd = *pAddrStart;
294 pFlowBb->rcError = VINF_SUCCESS;
295 pFlowBb->pszErr = NULL;
296 pFlowBb->cInstr = 0;
297 pFlowBb->cInstrMax = cInstrMax;
298 pFlowBb->pFlowBranchTbl = NULL;
299 ASMAtomicIncU32(&pThis->cRefsBb);
300 }
301
302 return pFlowBb;
303}
304
305
306/**
307 * Creates an empty branch table with the given size.
308 *
309 * @returns Pointer to the empty branch table on success or NULL if out of memory.
310 * @param pThis The control flow graph.
311 * @param pAddrStart The start of the branch table.
312 * @param idxGenRegBase The general register index holding the base address.
313 * @param cSlots Number of slots the table has.
314 */
315static PDBGFFLOWBRANCHTBLINT dbgfR3FlowBranchTblCreate(PDBGFFLOWINT pThis, PDBGFADDRESS pAddrStart, uint8_t idxGenRegBase, uint32_t cSlots)
316{
317 PDBGFFLOWBRANCHTBLINT pBranchTbl = (PDBGFFLOWBRANCHTBLINT)RTMemAllocZ(RT_OFFSETOF(DBGFFLOWBRANCHTBLINT, aAddresses[cSlots]));
318 if (RT_LIKELY(pBranchTbl))
319 {
320 RTListInit(&pBranchTbl->NdBranchTbl);
321 pBranchTbl->pFlow = pThis;
322 pBranchTbl->idxGenRegBase = idxGenRegBase;
323 pBranchTbl->AddrStart = *pAddrStart;
324 pBranchTbl->cSlots = cSlots;
325 pBranchTbl->cRefs = 1;
326 }
327
328 return pBranchTbl;
329}
330
331
332/**
333 * Destroys a control flow graph.
334 *
335 * @returns nothing.
336 * @param pThis The control flow graph to destroy.
337 */
338static void dbgfR3FlowDestroy(PDBGFFLOWINT pThis)
339{
340 /* Defer destruction if there are still basic blocks referencing us. */
341 PDBGFFLOWBBINT pFlowBb;
342 PDBGFFLOWBBINT pFlowBbNext;
343 RTListForEachSafe(&pThis->LstFlowBb, pFlowBb, pFlowBbNext, DBGFFLOWBBINT, NdFlowBb)
344 {
345 dbgfR3FlowBbReleaseInt(pFlowBb, false /*fMayDestroyFlow*/);
346 }
347
348 Assert(!pThis->cRefs);
349 if (!pThis->cRefsBb)
350 {
351 /* Destroy the branch tables. */
352 PDBGFFLOWBRANCHTBLINT pTbl = NULL;
353 PDBGFFLOWBRANCHTBLINT pTblNext = NULL;
354 RTListForEachSafe(&pThis->LstBranchTbl, pTbl, pTblNext, DBGFFLOWBRANCHTBLINT, NdBranchTbl)
355 {
356 dbgfR3FlowBranchTblDestroy(pTbl);
357 }
358
359 RTStrCacheDestroy(pThis->hStrCacheInstr);
360 RTMemFree(pThis);
361 }
362}
363
364
365/**
366 * Destroys a basic block.
367 *
368 * @returns nothing.
369 * @param pFlowBb The basic block to destroy.
370 * @param fMayDestroyFlow Flag whether the control flow graph container
371 * should be destroyed when there is nothing referencing it.
372 */
373static void dbgfR3FlowBbDestroy(PDBGFFLOWBBINT pFlowBb, bool fMayDestroyFlow)
374{
375 PDBGFFLOWINT pThis = pFlowBb->pFlow;
376
377 RTListNodeRemove(&pFlowBb->NdFlowBb);
378 pThis->cBbs--;
379 for (uint32_t idxInstr = 0; idxInstr < pFlowBb->cInstr; idxInstr++)
380 RTStrCacheRelease(pThis->hStrCacheInstr, pFlowBb->aInstr[idxInstr].pszInstr);
381 uint32_t cRefsBb = ASMAtomicDecU32(&pThis->cRefsBb);
382 RTMemFree(pFlowBb);
383
384 if (!cRefsBb && !pThis->cRefs && fMayDestroyFlow)
385 dbgfR3FlowDestroy(pThis);
386}
387
388
389/**
390 * Destroys a given branch table.
391 *
392 * @returns nothing.
393 * @param pFlowBranchTbl The flow branch table to destroy.
394 */
395static void dbgfR3FlowBranchTblDestroy(PDBGFFLOWBRANCHTBLINT pFlowBranchTbl)
396{
397 RTListNodeRemove(&pFlowBranchTbl->NdBranchTbl);
398 RTMemFree(pFlowBranchTbl);
399}
400
401
402/**
403 * Internal basic block release worker.
404 *
405 * @returns New reference count of the released basic block, on 0
406 * it is destroyed.
407 * @param pFlowBb The basic block to release.
408 * @param fMayDestroyFlow Flag whether the control flow graph container
409 * should be destroyed when there is nothing referencing it.
410 */
411static uint32_t dbgfR3FlowBbReleaseInt(PDBGFFLOWBBINT pFlowBb, bool fMayDestroyFlow)
412{
413 uint32_t cRefs = ASMAtomicDecU32(&pFlowBb->cRefs);
414 AssertMsg(cRefs < _1M, ("%#x %p %d\n", cRefs, pFlowBb, pFlowBb->enmEndType));
415 if (cRefs == 0)
416 dbgfR3FlowBbDestroy(pFlowBb, fMayDestroyFlow);
417 return cRefs;
418}
419
420
421/**
422 * Links the given basic block into the control flow graph.
423 *
424 * @returns nothing.
425 * @param pThis The control flow graph to link into.
426 * @param pFlowBb The basic block to link.
427 */
428DECLINLINE(void) dbgfR3FlowLink(PDBGFFLOWINT pThis, PDBGFFLOWBBINT pFlowBb)
429{
430 RTListAppend(&pThis->LstFlowBb, &pFlowBb->NdFlowBb);
431 pThis->cBbs++;
432}
433
434
435/**
436 * Links the given branch table into the control flow graph.
437 *
438 * @returns nothing.
439 * @param pThis The control flow graph to link into.
440 * @param pBranchTbl The branch table to link.
441 */
442DECLINLINE(void) dbgfR3FlowBranchTblLink(PDBGFFLOWINT pThis, PDBGFFLOWBRANCHTBLINT pBranchTbl)
443{
444 RTListAppend(&pThis->LstBranchTbl, &pBranchTbl->NdBranchTbl);
445 pThis->cBranchTbls++;
446}
447
448
449/**
450 * Returns the first unpopulated basic block of the given control flow graph.
451 *
452 * @returns The first unpopulated control flow graph or NULL if not found.
453 * @param pThis The control flow graph.
454 */
455DECLINLINE(PDBGFFLOWBBINT) dbgfR3FlowGetUnpopulatedBb(PDBGFFLOWINT pThis)
456{
457 PDBGFFLOWBBINT pFlowBb;
458 RTListForEach(&pThis->LstFlowBb, pFlowBb, DBGFFLOWBBINT, NdFlowBb)
459 {
460 if (pFlowBb->fFlags & DBGF_FLOW_BB_F_EMPTY)
461 return pFlowBb;
462 }
463
464 return NULL;
465}
466
467
468/**
469 * Returns the branch table with the given address if it exists.
470 *
471 * @returns Pointer to the branch table record or NULL if not found.
472 * @param pThis The control flow graph.
473 * @param pAddrTbl The branch table address.
474 */
475DECLINLINE(PDBGFFLOWBRANCHTBLINT) dbgfR3FlowBranchTblFindByAddr(PDBGFFLOWINT pThis, PDBGFADDRESS pAddrTbl)
476{
477 PDBGFFLOWBRANCHTBLINT pTbl;
478 RTListForEach(&pThis->LstBranchTbl, pTbl, DBGFFLOWBRANCHTBLINT, NdBranchTbl)
479 {
480 if (dbgfR3FlowAddrEqual(&pTbl->AddrStart, pAddrTbl))
481 return pTbl;
482 }
483
484 return NULL;
485}
486
487
488/**
489 * Sets the given error status for the basic block.
490 *
491 * @returns nothing.
492 * @param pFlowBb The basic block causing the error.
493 * @param rcError The error to set.
494 * @param pszFmt Format string of the error description.
495 * @param ... Arguments for the format string.
496 */
497static void dbgfR3FlowBbSetError(PDBGFFLOWBBINT pFlowBb, int rcError, const char *pszFmt, ...)
498{
499 va_list va;
500 va_start(va, pszFmt);
501
502 Assert(!(pFlowBb->fFlags & DBGF_FLOW_BB_F_INCOMPLETE_ERR));
503 pFlowBb->fFlags |= DBGF_FLOW_BB_F_INCOMPLETE_ERR;
504 pFlowBb->fFlags &= ~DBGF_FLOW_BB_F_EMPTY;
505 pFlowBb->rcError = rcError;
506 pFlowBb->pszErr = RTStrAPrintf2V(pszFmt, va);
507 va_end(va);
508}
509
510
511/**
512 * Checks whether the given control flow graph contains a basic block
513 * with the given start address.
514 *
515 * @returns true if there is a basic block with the start address, false otherwise.
516 * @param pThis The control flow graph.
517 * @param pAddr The address to check for.
518 */
519static bool dbgfR3FlowHasBbWithStartAddr(PDBGFFLOWINT pThis, PDBGFADDRESS pAddr)
520{
521 PDBGFFLOWBBINT pFlowBb;
522 RTListForEach(&pThis->LstFlowBb, pFlowBb, DBGFFLOWBBINT, NdFlowBb)
523 {
524 if (dbgfR3FlowAddrEqual(&pFlowBb->AddrStart, pAddr))
525 return true;
526 }
527 return false;
528}
529
530
531/**
532 * Splits a given basic block into two at the given address.
533 *
534 * @returns VBox status code.
535 * @param pThis The control flow graph.
536 * @param pFlowBb The basic block to split.
537 * @param pAddr The address to split at.
538 */
539static int dbgfR3FlowBbSplit(PDBGFFLOWINT pThis, PDBGFFLOWBBINT pFlowBb, PDBGFADDRESS pAddr)
540{
541 int rc = VINF_SUCCESS;
542 uint32_t idxInstrSplit;
543
544 /* If the block is empty it will get populated later so there is nothing to split,
545 * same if the start address equals. */
546 if ( pFlowBb->fFlags & DBGF_FLOW_BB_F_EMPTY
547 || dbgfR3FlowAddrEqual(&pFlowBb->AddrStart, pAddr))
548 return VINF_SUCCESS;
549
550 /* Find the instruction to split at. */
551 for (idxInstrSplit = 1; idxInstrSplit < pFlowBb->cInstr; idxInstrSplit++)
552 if (dbgfR3FlowAddrEqual(&pFlowBb->aInstr[idxInstrSplit].AddrInstr, pAddr))
553 break;
554
555 Assert(idxInstrSplit > 0);
556
557 /*
558 * Given address might not be on instruction boundary, this is not supported
559 * so far and results in an error.
560 */
561 if (idxInstrSplit < pFlowBb->cInstr)
562 {
563 /* Create new basic block. */
564 uint32_t cInstrNew = pFlowBb->cInstr - idxInstrSplit;
565 PDBGFFLOWBBINT pFlowBbNew = dbgfR3FlowBbCreate(pThis, &pFlowBb->aInstr[idxInstrSplit].AddrInstr,
566 0 /*fFlowBbFlags*/, cInstrNew);
567 if (pFlowBbNew)
568 {
569 /* Move instructions over. */
570 pFlowBbNew->cInstr = cInstrNew;
571 pFlowBbNew->AddrEnd = pFlowBb->AddrEnd;
572 pFlowBbNew->enmEndType = pFlowBb->enmEndType;
573 pFlowBbNew->AddrTarget = pFlowBb->AddrTarget;
574 pFlowBbNew->fFlags = pFlowBb->fFlags & ~DBGF_FLOW_BB_F_ENTRY;
575 pFlowBbNew->pFlowBranchTbl = pFlowBb->pFlowBranchTbl;
576 pFlowBb->pFlowBranchTbl = NULL;
577
578 /* Move any error to the new basic block and clear them in the old basic block. */
579 pFlowBbNew->rcError = pFlowBb->rcError;
580 pFlowBbNew->pszErr = pFlowBb->pszErr;
581 pFlowBb->rcError = VINF_SUCCESS;
582 pFlowBb->pszErr = NULL;
583 pFlowBb->fFlags &= ~DBGF_FLOW_BB_F_INCOMPLETE_ERR;
584
585 memcpy(&pFlowBbNew->aInstr[0], &pFlowBb->aInstr[idxInstrSplit], cInstrNew * sizeof(DBGFFLOWBBINSTR));
586 pFlowBb->cInstr = idxInstrSplit;
587 pFlowBb->enmEndType = DBGFFLOWBBENDTYPE_UNCOND;
588 pFlowBb->AddrEnd = pFlowBb->aInstr[idxInstrSplit-1].AddrInstr;
589 pFlowBb->AddrTarget = pFlowBbNew->AddrStart;
590 DBGFR3AddrAdd(&pFlowBb->AddrEnd, pFlowBb->aInstr[idxInstrSplit-1].cbInstr - 1);
591 RT_BZERO(&pFlowBb->aInstr[idxInstrSplit], cInstrNew * sizeof(DBGFFLOWBBINSTR));
592
593 dbgfR3FlowLink(pThis, pFlowBbNew);
594 }
595 else
596 rc = VERR_NO_MEMORY;
597 }
598 else
599 AssertFailedStmt(rc = VERR_INVALID_STATE); /** @todo: Proper status code. */
600
601 return rc;
602}
603
604
605/**
606 * Makes sure there is an successor at the given address splitting already existing
607 * basic blocks if they intersect.
608 *
609 * @returns VBox status code.
610 * @param pThis The control flow graph.
611 * @param pAddrSucc The guest address the new successor should start at.
612 * @param fNewBbFlags Flags for the new basic block.
613 * @param pBranchTbl Branch table candidate for this basic block.
614 */
615static int dbgfR3FlowBbSuccessorAdd(PDBGFFLOWINT pThis, PDBGFADDRESS pAddrSucc,
616 uint32_t fNewBbFlags, PDBGFFLOWBRANCHTBLINT pBranchTbl)
617{
618 PDBGFFLOWBBINT pFlowBb;
619 RTListForEach(&pThis->LstFlowBb, pFlowBb, DBGFFLOWBBINT, NdFlowBb)
620 {
621 /*
622 * The basic block must be split if it intersects with the given address
623 * and the start address does not equal the given one.
624 */
625 if (dbgfR3FlowAddrIntersect(pFlowBb, pAddrSucc))
626 return dbgfR3FlowBbSplit(pThis, pFlowBb, pAddrSucc);
627 }
628
629 int rc = VINF_SUCCESS;
630 pFlowBb = dbgfR3FlowBbCreate(pThis, pAddrSucc, fNewBbFlags, 10);
631 if (pFlowBb)
632 {
633 pFlowBb->pFlowBranchTbl = pBranchTbl;
634 dbgfR3FlowLink(pThis, pFlowBb);
635 }
636 else
637 rc = VERR_NO_MEMORY;
638
639 return rc;
640}
641
642
643/**
644 * Returns whether the parameter indicates an indirect branch.
645 *
646 * @returns Flag whether this is an indirect branch.
647 * @param pDisParam The parameter from the disassembler.
648 */
649DECLINLINE(bool) dbgfR3FlowBranchTargetIsIndirect(PDISOPPARAM pDisParam)
650{
651 bool fIndirect = true;
652
653 if ( pDisParam->fUse & (DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64)
654 || pDisParam->fUse & (DISUSE_IMMEDIATE8_REL | DISUSE_IMMEDIATE16_REL | DISUSE_IMMEDIATE32_REL | DISUSE_IMMEDIATE64_REL))
655 fIndirect = false;
656
657 return fIndirect;
658}
659
660
661/**
662 * Resolves the direct branch target address if possible from the given instruction address
663 * and instruction parameter.
664 *
665 * @returns VBox status code.
666 * @param pUVM The usermode VM handle.
667 * @param idCpu CPU id for resolving the address.
668 * @param pDisParam The parameter from the disassembler.
669 * @param pAddrInstr The instruction address.
670 * @param cbInstr Size of instruction in bytes.
671 * @param fRelJmp Flag whether this is a reltive jump.
672 * @param pAddrJmpTarget Where to store the address to the jump target on success.
673 */
674static int dbgfR3FlowQueryDirectBranchTarget(PUVM pUVM, VMCPUID idCpu, PDISOPPARAM pDisParam, PDBGFADDRESS pAddrInstr,
675 uint32_t cbInstr, bool fRelJmp, PDBGFADDRESS pAddrJmpTarget)
676{
677 int rc = VINF_SUCCESS;
678
679 Assert(!dbgfR3FlowBranchTargetIsIndirect(pDisParam));
680
681 /* Relative jumps are always from the beginning of the next instruction. */
682 *pAddrJmpTarget = *pAddrInstr;
683 DBGFR3AddrAdd(pAddrJmpTarget, cbInstr);
684
685 if (fRelJmp)
686 {
687 RTGCINTPTR iRel = 0;
688 if (pDisParam->fUse & DISUSE_IMMEDIATE8_REL)
689 iRel = (int8_t)pDisParam->uValue;
690 else if (pDisParam->fUse & DISUSE_IMMEDIATE16_REL)
691 iRel = (int16_t)pDisParam->uValue;
692 else if (pDisParam->fUse & DISUSE_IMMEDIATE32_REL)
693 iRel = (int32_t)pDisParam->uValue;
694 else if (pDisParam->fUse & DISUSE_IMMEDIATE64_REL)
695 iRel = (int64_t)pDisParam->uValue;
696 else
697 AssertFailedStmt(rc = VERR_NOT_SUPPORTED);
698
699 if (iRel < 0)
700 DBGFR3AddrSub(pAddrJmpTarget, -iRel);
701 else
702 DBGFR3AddrAdd(pAddrJmpTarget, iRel);
703 }
704 else
705 {
706 if (pDisParam->fUse & (DISUSE_IMMEDIATE8 | DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64))
707 {
708 if (DBGFADDRESS_IS_FLAT(pAddrInstr))
709 DBGFR3AddrFromFlat(pUVM, pAddrJmpTarget, pDisParam->uValue);
710 else
711 DBGFR3AddrFromSelOff(pUVM, idCpu, pAddrJmpTarget, pAddrInstr->Sel, pDisParam->uValue);
712 }
713 else
714 AssertFailedStmt(rc = VERR_INVALID_STATE);
715 }
716
717 return rc;
718}
719
720
721/**
722 * Returns the CPU mode based on the given assembler flags.
723 *
724 * @returns CPU mode.
725 * @param pUVM The user mode VM handle.
726 * @param idCpu CPU id for disassembling.
727 * @param fFlagsDisasm The flags used for disassembling.
728 */
729static CPUMMODE dbgfR3FlowGetDisasCpuMode(PUVM pUVM, VMCPUID idCpu, uint32_t fFlagsDisasm)
730{
731 CPUMMODE enmMode = CPUMMODE_INVALID;
732 uint32_t fDisasMode = fFlagsDisasm & DBGF_DISAS_FLAGS_MODE_MASK;
733 if (fDisasMode == DBGF_DISAS_FLAGS_DEFAULT_MODE)
734 enmMode = DBGFR3CpuGetMode(pUVM, idCpu);
735 else if ( fDisasMode == DBGF_DISAS_FLAGS_16BIT_MODE
736 || fDisasMode == DBGF_DISAS_FLAGS_16BIT_REAL_MODE)
737 enmMode = CPUMMODE_REAL;
738 else if (fDisasMode == DBGF_DISAS_FLAGS_32BIT_MODE)
739 enmMode = CPUMMODE_PROTECTED;
740 else if (fDisasMode == DBGF_DISAS_FLAGS_64BIT_MODE)
741 enmMode = CPUMMODE_LONG;
742 else
743 AssertFailed();
744
745 return enmMode;
746}
747
748
749/**
750 * Searches backwards in the given basic block starting the given instruction index for
751 * a mov instruction with the given register as the target where the constant looks like
752 * a pointer.
753 *
754 * @returns Flag whether a candidate was found.
755 * @param pFlowBb The basic block containing the indirect branch.
756 * @param idxRegTgt The general register the mov targets.
757 * @param cbPtr The pointer size to look for.
758 * @param pUVM The user mode VM handle.
759 * @param idCpu CPU id for disassembling.
760 * @param fFlagsDisasm The flags to use for disassembling.
761 * @param pidxInstrStart The instruction index to start searching for on input,
762 * The last instruction evaluated on output.
763 * @param pAddrDest Where to store the candidate address on success.
764 */
765static bool dbgfR3FlowSearchMovWithConstantPtrSizeBackwards(PDBGFFLOWBBINT pFlowBb, uint8_t idxRegTgt, uint32_t cbPtr,
766 PUVM pUVM, VMCPUID idCpu, uint32_t fFlagsDisasm,
767 uint32_t *pidxInstrStart, PDBGFADDRESS pAddrDest)
768{
769 bool fFound = false;
770 uint32_t idxInstrCur = *pidxInstrStart;
771 uint32_t cInstrCheck = idxInstrCur + 1;
772
773 for (;;)
774 {
775 /** @todo: Avoid to disassemble again. */
776 PDBGFFLOWBBINSTR pInstr = &pFlowBb->aInstr[idxInstrCur];
777 DBGFDISSTATE DisState;
778 char szOutput[_4K];
779
780 int rc = dbgfR3DisasInstrStateEx(pUVM, idCpu, &pInstr->AddrInstr, fFlagsDisasm,
781 &szOutput[0], sizeof(szOutput), &DisState);
782 if (RT_SUCCESS(rc))
783 {
784 if ( DisState.pCurInstr->uOpcode == OP_MOV
785 && (DisState.Param1.fUse & (DISUSE_REG_GEN16 | DISUSE_REG_GEN32 | DISUSE_REG_GEN64))
786 && DisState.Param1.Base.idxGenReg == idxRegTgt
787 /*&& DisState.Param1.cb == cbPtr*/
788 && DisState.Param2.cb == cbPtr
789 && (DisState.Param2.fUse & (DISUSE_IMMEDIATE16 | DISUSE_IMMEDIATE32 | DISUSE_IMMEDIATE64)))
790 {
791 /* Found possible candidate. */
792 fFound = true;
793 if (DBGFADDRESS_IS_FLAT(&pInstr->AddrInstr))
794 DBGFR3AddrFromFlat(pUVM, pAddrDest, DisState.Param2.uValue);
795 else
796 DBGFR3AddrFromSelOff(pUVM, idCpu, pAddrDest, pInstr->AddrInstr.Sel, DisState.Param2.uValue);
797 break;
798 }
799 }
800 else
801 break;
802
803 cInstrCheck--;
804 if (!cInstrCheck)
805 break;
806
807 idxInstrCur--;
808 }
809
810 *pidxInstrStart = idxInstrCur;
811 return fFound;
812}
813
814
815/**
816 * Verifies the given branch table candidate and adds it to the control flow graph on success.
817 *
818 * @returns VBox status code.
819 * @param pThis The flow control graph.
820 * @param pFlowBb The basic block causing the indirect branch.
821 * @param pAddrBranchTbl Address of the branch table location.
822 * @param idxGenRegBase The general register holding the base address.
823 * @param cbPtr Guest pointer size.
824 * @param pUVM The user mode VM handle.
825 * @param idCpu CPU id for disassembling.
826 *
827 * @todo Handle branch tables greater than 4KB (lazy coder).
828 */
829static int dbgfR3FlowBranchTblVerifyAdd(PDBGFFLOWINT pThis, PDBGFFLOWBBINT pFlowBb, PDBGFADDRESS pAddrBranchTbl,
830 uint8_t idxGenRegBase, uint32_t cbPtr, PUVM pUVM, VMCPUID idCpu)
831{
832 int rc = VINF_SUCCESS;
833 PDBGFFLOWBRANCHTBLINT pBranchTbl = dbgfR3FlowBranchTblFindByAddr(pThis, pAddrBranchTbl);
834
835 if (!pBranchTbl)
836 {
837 uint32_t cSlots = 0;
838 uint8_t abBuf[_4K];
839
840 rc = DBGFR3MemRead(pUVM, idCpu, pAddrBranchTbl, &abBuf[0], sizeof(abBuf));
841 if (RT_SUCCESS(rc))
842 {
843 uint8_t *pbBuf = &abBuf[0];
844 while (pbBuf < &abBuf[0] + sizeof(abBuf))
845 {
846 DBGFADDRESS AddrDest;
847 RTGCUINTPTR GCPtr = cbPtr == sizeof(uint64_t)
848 ? *(uint64_t *)pbBuf
849 : cbPtr == sizeof(uint32_t)
850 ? *(uint32_t *)pbBuf
851 : *(uint16_t *)pbBuf;
852 pbBuf += cbPtr;
853
854 if (DBGFADDRESS_IS_FLAT(pAddrBranchTbl))
855 DBGFR3AddrFromFlat(pUVM, &AddrDest, GCPtr);
856 else
857 DBGFR3AddrFromSelOff(pUVM, idCpu, &AddrDest, pAddrBranchTbl->Sel, GCPtr);
858
859 if (dbgfR3FlowAddrGetDistance(&AddrDest, &pFlowBb->AddrEnd) > _512K)
860 break;
861
862 cSlots++;
863 }
864
865 /* If there are any slots use it. */
866 if (cSlots)
867 {
868 pBranchTbl = dbgfR3FlowBranchTblCreate(pThis, pAddrBranchTbl, idxGenRegBase, cSlots);
869 if (pBranchTbl)
870 {
871 /* Get the addresses. */
872 for (unsigned i = 0; i < cSlots && RT_SUCCESS(rc); i++)
873 {
874 RTGCUINTPTR GCPtr = cbPtr == sizeof(uint64_t)
875 ? *(uint64_t *)&abBuf[i * cbPtr]
876 : cbPtr == sizeof(uint32_t)
877 ? *(uint32_t *)&abBuf[i * cbPtr]
878 : *(uint16_t *)&abBuf[i * cbPtr];
879
880 if (DBGFADDRESS_IS_FLAT(pAddrBranchTbl))
881 DBGFR3AddrFromFlat(pUVM, &pBranchTbl->aAddresses[i], GCPtr);
882 else
883 DBGFR3AddrFromSelOff(pUVM, idCpu, &pBranchTbl->aAddresses[i],
884 pAddrBranchTbl->Sel, GCPtr);
885 rc = dbgfR3FlowBbSuccessorAdd(pThis, &pBranchTbl->aAddresses[i], DBGF_FLOW_BB_F_BRANCH_TABLE,
886 pBranchTbl);
887 }
888 dbgfR3FlowBranchTblLink(pThis, pBranchTbl);
889 }
890 else
891 rc = VERR_NO_MEMORY;
892 }
893 }
894 }
895
896 if (pBranchTbl)
897 pFlowBb->pFlowBranchTbl = pBranchTbl;
898
899 return rc;
900}
901
902
903/**
904 * Checks whether the location for the branch target candidate contains a valid code address.
905 *
906 * @returns VBox status code.
907 * @param pThis The flow control graph.
908 * @param pFlowBb The basic block causing the indirect branch.
909 * @param pAddrBranchTgt Address of the branch target location.
910 * @param idxGenRegBase The general register holding the address of the location.
911 * @param cbPtr Guest pointer size.
912 * @param pUVM The user mode VM handle.
913 * @param idCpu CPU id for disassembling.
914 * @param fBranchTbl Flag whether this is a possible branch table containing multiple
915 * targets.
916 */
917static int dbgfR3FlowCheckBranchTargetLocation(PDBGFFLOWINT pThis, PDBGFFLOWBBINT pFlowBb, PDBGFADDRESS pAddrBranchTgt,
918 uint8_t idxGenRegBase, uint32_t cbPtr, PUVM pUVM, VMCPUID idCpu, bool fBranchTbl)
919{
920 int rc = VINF_SUCCESS;
921
922 if (!fBranchTbl)
923 {
924 union { uint16_t u16Val; uint32_t u32Val; uint64_t u64Val; } uVal;
925 rc = DBGFR3MemRead(pUVM, idCpu, pAddrBranchTgt, &uVal, cbPtr);
926 if (RT_SUCCESS(rc))
927 {
928 DBGFADDRESS AddrTgt;
929 RTGCUINTPTR GCPtr = cbPtr == sizeof(uint64_t)
930 ? uVal.u64Val
931 : cbPtr == sizeof(uint32_t)
932 ? uVal.u32Val
933 : uVal.u16Val;
934 if (DBGFADDRESS_IS_FLAT(pAddrBranchTgt))
935 DBGFR3AddrFromFlat(pUVM, &AddrTgt, GCPtr);
936 else
937 DBGFR3AddrFromSelOff(pUVM, idCpu, &AddrTgt, pAddrBranchTgt->Sel, GCPtr);
938
939 if (dbgfR3FlowAddrGetDistance(&AddrTgt, &pFlowBb->AddrEnd) <= _128K)
940 {
941 /* Finish the basic block. */
942 pFlowBb->AddrTarget = AddrTgt;
943 rc = dbgfR3FlowBbSuccessorAdd(pThis, &AddrTgt,
944 (pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE),
945 pFlowBb->pFlowBranchTbl);
946 }
947 else
948 rc = VERR_NOT_FOUND;
949 }
950 }
951 else
952 rc = dbgfR3FlowBranchTblVerifyAdd(pThis, pFlowBb, pAddrBranchTgt,
953 idxGenRegBase, cbPtr, pUVM, idCpu);
954
955 return rc;
956}
957
958
959/**
960 * Tries to resolve the indirect branch.
961 *
962 * @returns VBox status code.
963 * @param pThis The flow control graph.
964 * @param pFlowBb The basic block causing the indirect branch.
965 * @param pUVM The user mode VM handle.
966 * @param idCpu CPU id for disassembling.
967 * @param pDisParam The parameter from the disassembler.
968 * @param fFlagsDisasm Flags for the disassembler.
969 */
970static int dbgfR3FlowTryResolveIndirectBranch(PDBGFFLOWINT pThis, PDBGFFLOWBBINT pFlowBb, PUVM pUVM,
971 VMCPUID idCpu, PDISOPPARAM pDisParam, uint32_t fFlagsDisasm)
972{
973 Assert(dbgfR3FlowBranchTargetIsIndirect(pDisParam));
974
975 uint32_t cbPtr = 0;
976 CPUMMODE enmMode = dbgfR3FlowGetDisasCpuMode(pUVM, idCpu, fFlagsDisasm);
977
978 switch (enmMode)
979 {
980 case CPUMMODE_REAL:
981 cbPtr = sizeof(uint16_t);
982 break;
983 case CPUMMODE_PROTECTED:
984 cbPtr = sizeof(uint32_t);
985 break;
986 case CPUMMODE_LONG:
987 cbPtr = sizeof(uint64_t);
988 break;
989 default:
990 AssertMsgFailed(("Invalid CPU mode %u\n", enmMode));
991 }
992
993 if (pDisParam->fUse & DISUSE_BASE)
994 {
995 uint8_t idxRegBase = pDisParam->Base.idxGenReg;
996
997 /* Check that the used register size and the pointer size match. */
998 if ( ((pDisParam->fUse & DISUSE_REG_GEN16) && cbPtr == sizeof(uint16_t))
999 || ((pDisParam->fUse & DISUSE_REG_GEN32) && cbPtr == sizeof(uint32_t))
1000 || ((pDisParam->fUse & DISUSE_REG_GEN64) && cbPtr == sizeof(uint64_t)))
1001 {
1002 /*
1003 * Search all instructions backwards until a move to the used general register
1004 * is detected with a constant using the pointer size.
1005 */
1006 uint32_t idxInstrStart = pFlowBb->cInstr - 1 - 1; /* Don't look at the branch. */
1007 bool fCandidateFound = false;
1008 bool fBranchTbl = RT_BOOL(pDisParam->fUse & DISUSE_INDEX);
1009 DBGFADDRESS AddrBranchTgt;
1010 do
1011 {
1012 fCandidateFound = dbgfR3FlowSearchMovWithConstantPtrSizeBackwards(pFlowBb, idxRegBase, cbPtr,
1013 pUVM, idCpu, fFlagsDisasm,
1014 &idxInstrStart, &AddrBranchTgt);
1015 if (fCandidateFound)
1016 {
1017 /* Check that the address is not too far away from the instruction address. */
1018 RTGCUINTPTR offPtr = dbgfR3FlowAddrGetDistance(&AddrBranchTgt, &pFlowBb->AddrEnd);
1019 if (offPtr <= 20 * _1M)
1020 {
1021 /* Read the content at the address and check that it is near this basic block too. */
1022 int rc = dbgfR3FlowCheckBranchTargetLocation(pThis, pFlowBb, &AddrBranchTgt, idxRegBase,
1023 cbPtr, pUVM, idCpu, fBranchTbl);
1024 if (RT_SUCCESS(rc))
1025 break;
1026 fCandidateFound = false;
1027 }
1028
1029 if (idxInstrStart > 0)
1030 idxInstrStart--;
1031 }
1032 } while (idxInstrStart > 0 && !fCandidateFound);
1033 }
1034 else
1035 dbgfR3FlowBbSetError(pFlowBb, VERR_INVALID_STATE,
1036 "The base register size and selected pointer size do not match (fUse=%#x cbPtr=%u)",
1037 pDisParam->fUse, cbPtr);
1038 }
1039
1040 return VINF_SUCCESS;
1041}
1042
1043
1044/**
1045 * Tries to resolve the indirect branch.
1046 *
1047 * @returns VBox status code.
1048 * @param pThis The flow control graph.
1049 * @param pFlowBb The basic block causing the indirect branch.
1050 * @param pUVM The user mode VM handle.
1051 * @param idCpu CPU id for disassembling.
1052 * @param pDisParam The parameter from the disassembler.
1053 * @param fFlagsDisasm Flags for the disassembler.
1054 */
1055static int dbgfR3FlowBbCheckBranchTblCandidate(PDBGFFLOWINT pThis, PDBGFFLOWBBINT pFlowBb, PUVM pUVM,
1056 VMCPUID idCpu, PDISOPPARAM pDisParam, uint32_t fFlagsDisasm)
1057{
1058 int rc = VINF_SUCCESS;
1059
1060 Assert(pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE && pFlowBb->pFlowBranchTbl);
1061
1062 uint32_t cbPtr = 0;
1063 CPUMMODE enmMode = dbgfR3FlowGetDisasCpuMode(pUVM, idCpu, fFlagsDisasm);
1064
1065 switch (enmMode)
1066 {
1067 case CPUMMODE_REAL:
1068 cbPtr = sizeof(uint16_t);
1069 break;
1070 case CPUMMODE_PROTECTED:
1071 cbPtr = sizeof(uint32_t);
1072 break;
1073 case CPUMMODE_LONG:
1074 cbPtr = sizeof(uint64_t);
1075 break;
1076 default:
1077 AssertMsgFailed(("Invalid CPU mode %u\n", enmMode));
1078 }
1079
1080 if (pDisParam->fUse & DISUSE_BASE)
1081 {
1082 uint8_t idxRegBase = pDisParam->Base.idxGenReg;
1083
1084 /* Check that the used register size and the pointer size match. */
1085 if ( ((pDisParam->fUse & DISUSE_REG_GEN16) && cbPtr == sizeof(uint16_t))
1086 || ((pDisParam->fUse & DISUSE_REG_GEN32) && cbPtr == sizeof(uint32_t))
1087 || ((pDisParam->fUse & DISUSE_REG_GEN64) && cbPtr == sizeof(uint64_t)))
1088 {
1089 if (idxRegBase != pFlowBb->pFlowBranchTbl->idxGenRegBase)
1090 {
1091 /* Try to find the new branch table. */
1092 pFlowBb->pFlowBranchTbl = NULL;
1093 rc = dbgfR3FlowTryResolveIndirectBranch(pThis, pFlowBb, pUVM, idCpu, pDisParam, fFlagsDisasm);
1094 }
1095 /** @todo: else check that the base register is not modified in this basic block. */
1096 }
1097 else
1098 dbgfR3FlowBbSetError(pFlowBb, VERR_INVALID_STATE,
1099 "The base register size and selected pointer size do not match (fUse=%#x cbPtr=%u)",
1100 pDisParam->fUse, cbPtr);
1101 }
1102 else
1103 dbgfR3FlowBbSetError(pFlowBb, VERR_INVALID_STATE,
1104 "The instruction does not use a register");
1105
1106 return rc;
1107}
1108
1109
1110/**
1111 * Processes and fills one basic block.
1112 *
1113 * @returns VBox status code.
1114 * @param pUVM The user mode VM handle.
1115 * @param idCpu CPU id for disassembling.
1116 * @param pThis The control flow graph to populate.
1117 * @param pFlowBb The basic block to fill.
1118 * @param cbDisasmMax The maximum amount to disassemble.
1119 * @param fFlags Combination of DBGF_DISAS_FLAGS_*.
1120 */
1121static int dbgfR3FlowBbProcess(PUVM pUVM, VMCPUID idCpu, PDBGFFLOWINT pThis, PDBGFFLOWBBINT pFlowBb,
1122 uint32_t cbDisasmMax, uint32_t fFlags)
1123{
1124 int rc = VINF_SUCCESS;
1125 uint32_t cbDisasmLeft = cbDisasmMax ? cbDisasmMax : UINT32_MAX;
1126 DBGFADDRESS AddrDisasm = pFlowBb->AddrEnd;
1127
1128 Assert(pFlowBb->fFlags & DBGF_FLOW_BB_F_EMPTY);
1129
1130 /*
1131 * Disassemble instruction by instruction until we get a conditional or
1132 * unconditional jump or some sort of return.
1133 */
1134 while ( cbDisasmLeft
1135 && RT_SUCCESS(rc))
1136 {
1137 DBGFDISSTATE DisState;
1138 char szOutput[_4K];
1139
1140 /*
1141 * Before disassembling we have to check whether the address belongs
1142 * to another basic block and stop here.
1143 */
1144 if ( !(pFlowBb->fFlags & DBGF_FLOW_BB_F_EMPTY)
1145 && dbgfR3FlowHasBbWithStartAddr(pThis, &AddrDisasm))
1146 {
1147 pFlowBb->AddrTarget = AddrDisasm;
1148 pFlowBb->enmEndType = DBGFFLOWBBENDTYPE_UNCOND;
1149 break;
1150 }
1151
1152 pFlowBb->fFlags &= ~DBGF_FLOW_BB_F_EMPTY;
1153
1154 rc = dbgfR3DisasInstrStateEx(pUVM, idCpu, &AddrDisasm, fFlags,
1155 &szOutput[0], sizeof(szOutput), &DisState);
1156 if (RT_SUCCESS(rc))
1157 {
1158 cbDisasmLeft -= DisState.cbInstr;
1159
1160 if (pFlowBb->cInstr == pFlowBb->cInstrMax)
1161 {
1162 /* Reallocate. */
1163 RTListNodeRemove(&pFlowBb->NdFlowBb);
1164 PDBGFFLOWBBINT pFlowBbNew = (PDBGFFLOWBBINT)RTMemRealloc(pFlowBb, RT_OFFSETOF(DBGFFLOWBBINT, aInstr[pFlowBb->cInstrMax + 10]));
1165 if (pFlowBbNew)
1166 {
1167 pFlowBbNew->cInstrMax += 10;
1168 pFlowBb = pFlowBbNew;
1169 }
1170 else
1171 rc = VERR_NO_MEMORY;
1172 RTListAppend(&pThis->LstFlowBb, &pFlowBb->NdFlowBb);
1173 }
1174
1175 if (RT_SUCCESS(rc))
1176 {
1177 PDBGFFLOWBBINSTR pInstr = &pFlowBb->aInstr[pFlowBb->cInstr];
1178
1179 pInstr->AddrInstr = AddrDisasm;
1180 pInstr->cbInstr = DisState.cbInstr;
1181 pInstr->pszInstr = RTStrCacheEnter(pThis->hStrCacheInstr, &szOutput[0]);
1182 pFlowBb->cInstr++;
1183
1184 pFlowBb->AddrEnd = AddrDisasm;
1185 DBGFR3AddrAdd(&pFlowBb->AddrEnd, pInstr->cbInstr - 1);
1186 DBGFR3AddrAdd(&AddrDisasm, pInstr->cbInstr);
1187
1188 /*
1189 * Check control flow instructions and create new basic blocks
1190 * marking the current one as complete.
1191 */
1192 if (DisState.pCurInstr->fOpType & DISOPTYPE_CONTROLFLOW)
1193 {
1194 uint16_t uOpc = DisState.pCurInstr->uOpcode;
1195
1196 if ( uOpc == OP_RETN || uOpc == OP_RETF || uOpc == OP_IRET
1197 || uOpc == OP_SYSEXIT || uOpc == OP_SYSRET)
1198 pFlowBb->enmEndType = DBGFFLOWBBENDTYPE_EXIT;
1199 else if (uOpc == OP_JMP)
1200 {
1201 Assert(DisState.pCurInstr->fOpType & DISOPTYPE_UNCOND_CONTROLFLOW);
1202
1203 if (dbgfR3FlowBranchTargetIsIndirect(&DisState.Param1))
1204 {
1205 pFlowBb->enmEndType = DBGFFLOWBBENDTYPE_UNCOND_INDIRECT_JMP;
1206
1207 if (pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE)
1208 {
1209 Assert(pThis->fFlags & DBGF_FLOW_CREATE_F_TRY_RESOLVE_INDIRECT_BRANCHES);
1210
1211 /*
1212 * This basic block was already discovered by parsing a jump table and
1213 * there should be a candidate for the branch table. Check whether it uses the
1214 * same branch table.
1215 */
1216 rc = dbgfR3FlowBbCheckBranchTblCandidate(pThis, pFlowBb, pUVM, idCpu,
1217 &DisState.Param1, fFlags);
1218 }
1219 else
1220 {
1221 if (pThis->fFlags & DBGF_FLOW_CREATE_F_TRY_RESOLVE_INDIRECT_BRANCHES)
1222 rc = dbgfR3FlowTryResolveIndirectBranch(pThis, pFlowBb, pUVM, idCpu,
1223 &DisState.Param1, fFlags);
1224 else
1225 dbgfR3FlowBbSetError(pFlowBb, VERR_NOT_SUPPORTED,
1226 "Detected indirect branch and resolving it not being enabled");
1227 }
1228 }
1229 else
1230 {
1231 pFlowBb->enmEndType = DBGFFLOWBBENDTYPE_UNCOND_JMP;
1232
1233 /* Create one new basic block with the jump target address. */
1234 rc = dbgfR3FlowQueryDirectBranchTarget(pUVM, idCpu, &DisState.Param1, &pInstr->AddrInstr, pInstr->cbInstr,
1235 RT_BOOL(DisState.pCurInstr->fOpType & DISOPTYPE_RELATIVE_CONTROLFLOW),
1236 &pFlowBb->AddrTarget);
1237 if (RT_SUCCESS(rc))
1238 rc = dbgfR3FlowBbSuccessorAdd(pThis, &pFlowBb->AddrTarget,
1239 (pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE),
1240 pFlowBb->pFlowBranchTbl);
1241 }
1242 }
1243 else if (uOpc != OP_CALL)
1244 {
1245 Assert(DisState.pCurInstr->fOpType & DISOPTYPE_COND_CONTROLFLOW);
1246 pFlowBb->enmEndType = DBGFFLOWBBENDTYPE_COND;
1247
1248 /*
1249 * Create two new basic blocks, one with the jump target address
1250 * and one starting after the current instruction.
1251 */
1252 rc = dbgfR3FlowBbSuccessorAdd(pThis, &AddrDisasm,
1253 (pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE),
1254 pFlowBb->pFlowBranchTbl);
1255 if (RT_SUCCESS(rc))
1256 {
1257 rc = dbgfR3FlowQueryDirectBranchTarget(pUVM, idCpu, &DisState.Param1, &pInstr->AddrInstr, pInstr->cbInstr,
1258 RT_BOOL(DisState.pCurInstr->fOpType & DISOPTYPE_RELATIVE_CONTROLFLOW),
1259 &pFlowBb->AddrTarget);
1260 if (RT_SUCCESS(rc))
1261 rc = dbgfR3FlowBbSuccessorAdd(pThis, &pFlowBb->AddrTarget,
1262 (pFlowBb->fFlags & DBGF_FLOW_BB_F_BRANCH_TABLE),
1263 pFlowBb->pFlowBranchTbl);
1264 }
1265 }
1266
1267 if (RT_FAILURE(rc))
1268 dbgfR3FlowBbSetError(pFlowBb, rc, "Adding successor blocks failed with %Rrc", rc);
1269
1270 /* Quit disassembling. */
1271 if ( uOpc != OP_CALL
1272 || RT_FAILURE(rc))
1273 break;
1274 }
1275 }
1276 else
1277 dbgfR3FlowBbSetError(pFlowBb, rc, "Increasing basic block failed with %Rrc", rc);
1278 }
1279 else
1280 dbgfR3FlowBbSetError(pFlowBb, rc, "Disassembling the instruction failed with %Rrc", rc);
1281 }
1282
1283 return VINF_SUCCESS;
1284}
1285
1286/**
1287 * Populate all empty basic blocks.
1288 *
1289 * @returns VBox status code.
1290 * @param pUVM The user mode VM handle.
1291 * @param idCpu CPU id for disassembling.
1292 * @param pThis The control flow graph to populate.
1293 * @param pAddrStart The start address to disassemble at.
1294 * @param cbDisasmMax The maximum amount to disassemble.
1295 * @param fFlags Combination of DBGF_DISAS_FLAGS_*.
1296 */
1297static int dbgfR3FlowPopulate(PUVM pUVM, VMCPUID idCpu, PDBGFFLOWINT pThis, PDBGFADDRESS pAddrStart,
1298 uint32_t cbDisasmMax, uint32_t fFlags)
1299{
1300 int rc = VINF_SUCCESS;
1301 PDBGFFLOWBBINT pFlowBb = dbgfR3FlowGetUnpopulatedBb(pThis);
1302 DBGFADDRESS AddrEnd = *pAddrStart;
1303 DBGFR3AddrAdd(&AddrEnd, cbDisasmMax);
1304
1305 while (VALID_PTR(pFlowBb))
1306 {
1307 rc = dbgfR3FlowBbProcess(pUVM, idCpu, pThis, pFlowBb, cbDisasmMax, fFlags);
1308 if (RT_FAILURE(rc))
1309 break;
1310
1311 pFlowBb = dbgfR3FlowGetUnpopulatedBb(pThis);
1312 }
1313
1314 return rc;
1315}
1316
1317/**
1318 * Creates a new control flow graph from the given start address.
1319 *
1320 * @returns VBox status code.
1321 * @param pUVM The user mode VM handle.
1322 * @param idCpu CPU id for disassembling.
1323 * @param pAddressStart Where to start creating the control flow graph.
1324 * @param cbDisasmMax Limit the amount of bytes to disassemble, 0 for no limit.
1325 * @param fFlagsFlow Combination of DBGF_FLOW_CREATE_F_* to control the creation of the flow graph.
1326 * @param fFlagsDisasm Combination of DBGF_DISAS_FLAGS_* controlling the style of the disassembled
1327 * instructions.
1328 * @param phFlow Where to store the handle to the control flow graph on success.
1329 */
1330VMMR3DECL(int) DBGFR3FlowCreate(PUVM pUVM, VMCPUID idCpu, PDBGFADDRESS pAddressStart, uint32_t cbDisasmMax,
1331 uint32_t fFlagsFlow, uint32_t fFlagsDisasm, PDBGFFLOW phFlow)
1332{
1333 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
1334 PVM pVM = pUVM->pVM;
1335 VM_ASSERT_VALID_EXT_RETURN(pVM, VERR_INVALID_VM_HANDLE);
1336 AssertReturn(idCpu < pUVM->cCpus, VERR_INVALID_CPU_ID);
1337 AssertPtrReturn(pAddressStart, VERR_INVALID_POINTER);
1338 AssertReturn(!(fFlagsDisasm & ~DBGF_DISAS_FLAGS_VALID_MASK), VERR_INVALID_PARAMETER);
1339 AssertReturn((fFlagsDisasm & DBGF_DISAS_FLAGS_MODE_MASK) <= DBGF_DISAS_FLAGS_64BIT_MODE, VERR_INVALID_PARAMETER);
1340
1341 /* Create the control flow graph container. */
1342 int rc = VINF_SUCCESS;
1343 PDBGFFLOWINT pThis = (PDBGFFLOWINT)RTMemAllocZ(sizeof(DBGFFLOWINT));
1344 if (RT_LIKELY(pThis))
1345 {
1346 rc = RTStrCacheCreate(&pThis->hStrCacheInstr, "DBGFFLOW");
1347 if (RT_SUCCESS(rc))
1348 {
1349 pThis->cRefs = 1;
1350 pThis->cRefsBb = 0;
1351 pThis->cBbs = 0;
1352 pThis->cBranchTbls = 0;
1353 pThis->fFlags = fFlagsFlow;
1354 RTListInit(&pThis->LstFlowBb);
1355 RTListInit(&pThis->LstBranchTbl);
1356 /* Create the entry basic block and start the work. */
1357
1358 PDBGFFLOWBBINT pFlowBb = dbgfR3FlowBbCreate(pThis, pAddressStart, DBGF_FLOW_BB_F_ENTRY, 10);
1359 if (RT_LIKELY(pFlowBb))
1360 {
1361 dbgfR3FlowLink(pThis, pFlowBb);
1362 rc = dbgfR3FlowPopulate(pUVM, idCpu, pThis, pAddressStart, cbDisasmMax, fFlagsDisasm);
1363 if (RT_SUCCESS(rc))
1364 {
1365 *phFlow = pThis;
1366 return VINF_SUCCESS;
1367 }
1368 }
1369 else
1370 rc = VERR_NO_MEMORY;
1371 }
1372
1373 ASMAtomicDecU32(&pThis->cRefs);
1374 dbgfR3FlowDestroy(pThis);
1375 }
1376 else
1377 rc = VERR_NO_MEMORY;
1378
1379 return rc;
1380}
1381
1382
1383/**
1384 * Retains the control flow graph handle.
1385 *
1386 * @returns Current reference count.
1387 * @param hFlow The control flow graph handle to retain.
1388 */
1389VMMR3DECL(uint32_t) DBGFR3FlowRetain(DBGFFLOW hFlow)
1390{
1391 PDBGFFLOWINT pThis = hFlow;
1392 AssertPtrReturn(pThis, UINT32_MAX);
1393
1394 uint32_t cRefs = ASMAtomicIncU32(&pThis->cRefs);
1395 AssertMsg(cRefs > 1 && cRefs < _1M, ("%#x %p\n", cRefs, pThis));
1396 return cRefs;
1397}
1398
1399
1400/**
1401 * Releases the control flow graph handle.
1402 *
1403 * @returns Current reference count, on 0 the control flow graph will be destroyed.
1404 * @param hFlow The control flow graph handle to release.
1405 */
1406VMMR3DECL(uint32_t) DBGFR3FlowRelease(DBGFFLOW hFlow)
1407{
1408 PDBGFFLOWINT pThis = hFlow;
1409 if (!pThis)
1410 return 0;
1411 AssertPtrReturn(pThis, UINT32_MAX);
1412
1413 uint32_t cRefs = ASMAtomicDecU32(&pThis->cRefs);
1414 AssertMsg(cRefs < _1M, ("%#x %p\n", cRefs, pThis));
1415 if (cRefs == 0)
1416 dbgfR3FlowDestroy(pThis);
1417 return cRefs;
1418}
1419
1420
1421/**
1422 * Queries the basic block denoting the entry point into the control flow graph.
1423 *
1424 * @returns VBox status code.
1425 * @param hFlow The control flow graph handle.
1426 * @param phFlowBb Where to store the basic block handle on success.
1427 */
1428VMMR3DECL(int) DBGFR3FlowQueryStartBb(DBGFFLOW hFlow, PDBGFFLOWBB phFlowBb)
1429{
1430 PDBGFFLOWINT pThis = hFlow;
1431 AssertPtrReturn(pThis, VERR_INVALID_HANDLE);
1432
1433 PDBGFFLOWBBINT pFlowBb;
1434 RTListForEach(&pThis->LstFlowBb, pFlowBb, DBGFFLOWBBINT, NdFlowBb)
1435 {
1436 if (pFlowBb->fFlags & DBGF_FLOW_BB_F_ENTRY)
1437 {
1438 *phFlowBb = pFlowBb;
1439 return VINF_SUCCESS;
1440 }
1441 }
1442
1443 AssertFailed(); /* Should never get here. */
1444 return VERR_INTERNAL_ERROR;
1445}
1446
1447
1448/**
1449 * Queries a basic block in the given control flow graph which covers the given
1450 * address.
1451 *
1452 * @returns VBox status code.
1453 * @retval VERR_NOT_FOUND if there is no basic block intersecting with the address.
1454 * @param hFlow The control flow graph handle.
1455 * @param pAddr The address to look for.
1456 * @param phFlowBb Where to store the basic block handle on success.
1457 */
1458VMMR3DECL(int) DBGFR3FlowQueryBbByAddress(DBGFFLOW hFlow, PDBGFADDRESS pAddr, PDBGFFLOWBB phFlowBb)
1459{
1460 PDBGFFLOWINT pThis = hFlow;
1461 AssertPtrReturn(pThis, VERR_INVALID_HANDLE);
1462 AssertPtrReturn(pAddr, VERR_INVALID_POINTER);
1463 AssertPtrReturn(phFlowBb, VERR_INVALID_POINTER);
1464
1465 PDBGFFLOWBBINT pFlowBb;
1466 RTListForEach(&pThis->LstFlowBb, pFlowBb, DBGFFLOWBBINT, NdFlowBb)
1467 {
1468 if (dbgfR3FlowAddrIntersect(pFlowBb, pAddr))
1469 {
1470 DBGFR3FlowBbRetain(pFlowBb);
1471 *phFlowBb = pFlowBb;
1472 return VINF_SUCCESS;
1473 }
1474 }
1475
1476 return VERR_NOT_FOUND;
1477}
1478
1479
1480/**
1481 * Queries a branch table in the given control flow graph by the given address.
1482 *
1483 * @returns VBox status code.
1484 * @retval VERR_NOT_FOUND if there is no branch table with the given address.
1485 * @param hFlow The control flow graph handle.
1486 * @param pAddr The address of the branch table.
1487 * @param phFlowBranchTbl Where to store the handle to branch table on success.
1488 *
1489 * @note Call DBGFR3FlowBranchTblRelease() when the handle is not required anymore.
1490 */
1491VMMR3DECL(int) DBGFR3FlowQueryBranchTblByAddress(DBGFFLOW hFlow, PDBGFADDRESS pAddr, PDBGFFLOWBRANCHTBL phFlowBranchTbl)
1492{
1493 PDBGFFLOWINT pThis = hFlow;
1494 AssertPtrReturn(pThis, VERR_INVALID_HANDLE);
1495 AssertPtrReturn(pAddr, VERR_INVALID_POINTER);
1496 AssertPtrReturn(phFlowBranchTbl, VERR_INVALID_POINTER);
1497
1498 PDBGFFLOWBRANCHTBLINT pBranchTbl = dbgfR3FlowBranchTblFindByAddr(pThis, pAddr);
1499 if (pBranchTbl)
1500 {
1501 DBGFR3FlowBranchTblRetain(pBranchTbl);
1502 *phFlowBranchTbl = pBranchTbl;
1503 return VINF_SUCCESS;
1504 }
1505
1506 return VERR_NOT_FOUND;
1507}
1508
1509
1510/**
1511 * Returns the number of basic blcoks inside the control flow graph.
1512 *
1513 * @returns Number of basic blocks.
1514 * @param hFlow The control flow graph handle.
1515 */
1516VMMR3DECL(uint32_t) DBGFR3FlowGetBbCount(DBGFFLOW hFlow)
1517{
1518 PDBGFFLOWINT pThis = hFlow;
1519 AssertPtrReturn(pThis, 0);
1520
1521 return pThis->cBbs;
1522}
1523
1524
1525/**
1526 * Returns the number of branch tables inside the control flow graph.
1527 *
1528 * @returns Number of basic blocks.
1529 * @param hFlow The control flow graph handle.
1530 */
1531VMMR3DECL(uint32_t) DBGFR3FlowGetBranchTblCount(DBGFFLOW hFlow)
1532{
1533 PDBGFFLOWINT pThis = hFlow;
1534 AssertPtrReturn(pThis, 0);
1535
1536 return pThis->cBranchTbls;
1537}
1538
1539
1540/**
1541 * Retains the basic block handle.
1542 *
1543 * @returns Current reference count.
1544 * @param hFlowBb The basic block handle to retain.
1545 */
1546VMMR3DECL(uint32_t) DBGFR3FlowBbRetain(DBGFFLOWBB hFlowBb)
1547{
1548 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1549 AssertPtrReturn(pFlowBb, UINT32_MAX);
1550
1551 uint32_t cRefs = ASMAtomicIncU32(&pFlowBb->cRefs);
1552 AssertMsg(cRefs > 1 && cRefs < _1M, ("%#x %p %d\n", cRefs, pFlowBb, pFlowBb->enmEndType));
1553 return cRefs;
1554}
1555
1556
1557/**
1558 * Releases the basic block handle.
1559 *
1560 * @returns Current reference count, on 0 the basic block will be destroyed.
1561 * @param hFlowBb The basic block handle to release.
1562 */
1563VMMR3DECL(uint32_t) DBGFR3FlowBbRelease(DBGFFLOWBB hFlowBb)
1564{
1565 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1566 if (!pFlowBb)
1567 return 0;
1568
1569 return dbgfR3FlowBbReleaseInt(pFlowBb, true /* fMayDestroyFlow */);
1570}
1571
1572
1573/**
1574 * Returns the start address of the basic block.
1575 *
1576 * @returns Pointer to DBGF adress containing the start address of the basic block.
1577 * @param hFlowBb The basic block handle.
1578 * @param pAddrStart Where to store the start address of the basic block.
1579 */
1580VMMR3DECL(PDBGFADDRESS) DBGFR3FlowBbGetStartAddress(DBGFFLOWBB hFlowBb, PDBGFADDRESS pAddrStart)
1581{
1582 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1583 AssertPtrReturn(pFlowBb, NULL);
1584 AssertPtrReturn(pAddrStart, NULL);
1585
1586 *pAddrStart = pFlowBb->AddrStart;
1587 return pAddrStart;
1588}
1589
1590
1591/**
1592 * Returns the end address of the basic block (inclusive).
1593 *
1594 * @returns Pointer to DBGF adress containing the end address of the basic block.
1595 * @param hFlowBb The basic block handle.
1596 * @param pAddrEnd Where to store the end address of the basic block.
1597 */
1598VMMR3DECL(PDBGFADDRESS) DBGFR3FlowBbGetEndAddress(DBGFFLOWBB hFlowBb, PDBGFADDRESS pAddrEnd)
1599{
1600 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1601 AssertPtrReturn(pFlowBb, NULL);
1602 AssertPtrReturn(pAddrEnd, NULL);
1603
1604 *pAddrEnd = pFlowBb->AddrEnd;
1605 return pAddrEnd;
1606}
1607
1608
1609/**
1610 * Returns the address the last instruction in the basic block branches to.
1611 *
1612 * @returns Pointer to DBGF adress containing the branch address of the basic block.
1613 * @param hFlowBb The basic block handle.
1614 * @param pAddrTarget Where to store the branch address of the basic block.
1615 *
1616 * @note This is only valid for unconditional or conditional branches and will assert
1617 * for every other basic block type.
1618 * @note For indirect unconditional branches using a branch table this will return the start address
1619 * of the branch table.
1620 */
1621VMMR3DECL(PDBGFADDRESS) DBGFR3FlowBbGetBranchAddress(DBGFFLOWBB hFlowBb, PDBGFADDRESS pAddrTarget)
1622{
1623 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1624 AssertPtrReturn(pFlowBb, NULL);
1625 AssertPtrReturn(pAddrTarget, NULL);
1626 AssertReturn( pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_UNCOND_JMP
1627 || pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_COND
1628 || pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_UNCOND_INDIRECT_JMP,
1629 NULL);
1630
1631 if ( pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_UNCOND_INDIRECT_JMP
1632 && pFlowBb->pFlowBranchTbl)
1633 *pAddrTarget = pFlowBb->pFlowBranchTbl->AddrStart;
1634 else
1635 *pAddrTarget = pFlowBb->AddrTarget;
1636 return pAddrTarget;
1637}
1638
1639
1640/**
1641 * Returns the address of the next block following this one in the instruction stream.
1642 * (usually end address + 1).
1643 *
1644 * @returns Pointer to DBGF adress containing the following address of the basic block.
1645 * @param hFlowBb The basic block handle.
1646 * @param pAddrFollow Where to store the following address of the basic block.
1647 *
1648 * @note This is only valid for conditional branches and if the last instruction in the
1649 * given basic block doesn't change the control flow but the blocks were split
1650 * because the successor is referenced by multiple other blocks as an entry point.
1651 */
1652VMMR3DECL(PDBGFADDRESS) DBGFR3FlowBbGetFollowingAddress(DBGFFLOWBB hFlowBb, PDBGFADDRESS pAddrFollow)
1653{
1654 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1655 AssertPtrReturn(pFlowBb, NULL);
1656 AssertPtrReturn(pAddrFollow, NULL);
1657 AssertReturn( pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_UNCOND
1658 || pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_COND,
1659 NULL);
1660
1661 *pAddrFollow = pFlowBb->AddrEnd;
1662 DBGFR3AddrAdd(pAddrFollow, 1);
1663 return pAddrFollow;
1664}
1665
1666
1667/**
1668 * Returns the type of the last instruction in the basic block.
1669 *
1670 * @returns Last instruction type.
1671 * @param hFlowBb The basic block handle.
1672 */
1673VMMR3DECL(DBGFFLOWBBENDTYPE) DBGFR3FlowBbGetType(DBGFFLOWBB hFlowBb)
1674{
1675 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1676 AssertPtrReturn(pFlowBb, DBGFFLOWBBENDTYPE_INVALID);
1677
1678 return pFlowBb->enmEndType;
1679}
1680
1681
1682/**
1683 * Get the number of instructions contained in the basic block.
1684 *
1685 * @returns Number of instructions in the basic block.
1686 * @param hFlowBb The basic block handle.
1687 */
1688VMMR3DECL(uint32_t) DBGFR3FlowBbGetInstrCount(DBGFFLOWBB hFlowBb)
1689{
1690 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1691 AssertPtrReturn(pFlowBb, 0);
1692
1693 return pFlowBb->cInstr;
1694}
1695
1696
1697/**
1698 * Get flags for the given basic block.
1699 *
1700 * @returns Combination of DBGF_FLOW_BB_F_*
1701 * @param hFlowBb The basic block handle.
1702 */
1703VMMR3DECL(uint32_t) DBGFR3FlowBbGetFlags(DBGFFLOWBB hFlowBb)
1704{
1705 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1706 AssertPtrReturn(pFlowBb, 0);
1707
1708 return pFlowBb->fFlags;
1709}
1710
1711
1712/**
1713 * Queries the branch table used if the given basic block ends with an indirect branch
1714 * and has a branch table referenced.
1715 *
1716 * @returns VBox status code.
1717 * @param hFlowBb The basic block handle.
1718 * @param phBranchTbl Where to store the branch table handle on success.
1719 *
1720 * @note Release the branch table reference with DBGFR3FlowBranchTblRelease() when not required
1721 * anymore.
1722 */
1723VMMR3DECL(int) DBGFR3FlowBbQueryBranchTbl(DBGFFLOWBB hFlowBb, PDBGFFLOWBRANCHTBL phBranchTbl)
1724{
1725 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1726 AssertPtrReturn(pFlowBb, VERR_INVALID_HANDLE);
1727 AssertReturn(pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_UNCOND_INDIRECT_JMP, VERR_INVALID_STATE);
1728 AssertPtrReturn(pFlowBb->pFlowBranchTbl, VERR_INVALID_STATE);
1729 AssertPtrReturn(phBranchTbl, VERR_INVALID_POINTER);
1730
1731 DBGFR3FlowBranchTblRetain(pFlowBb->pFlowBranchTbl);
1732 *phBranchTbl = pFlowBb->pFlowBranchTbl;
1733 return VINF_SUCCESS;
1734}
1735
1736
1737/**
1738 * Returns the error status and message if the given basic block has an error.
1739 *
1740 * @returns VBox status code of the error for the basic block.
1741 * @param hFlowBb The basic block handle.
1742 * @param ppszErr Where to store the pointer to the error message - optional.
1743 */
1744VMMR3DECL(int) DBGFR3FlowBbQueryError(DBGFFLOWBB hFlowBb, const char **ppszErr)
1745{
1746 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1747 AssertPtrReturn(pFlowBb, VERR_INVALID_HANDLE);
1748
1749 if (ppszErr)
1750 *ppszErr = pFlowBb->pszErr;
1751
1752 return pFlowBb->rcError;
1753}
1754
1755
1756/**
1757 * Store the disassembled instruction as a string in the given output buffer.
1758 *
1759 * @returns VBox status code.
1760 * @param hFlowBb The basic block handle.
1761 * @param idxInstr The instruction to query.
1762 * @param pAddrInstr Where to store the guest instruction address on success, optional.
1763 * @param pcbInstr Where to store the instruction size on success, optional.
1764 * @param ppszInstr Where to store the pointer to the disassembled instruction string, optional.
1765 */
1766VMMR3DECL(int) DBGFR3FlowBbQueryInstr(DBGFFLOWBB hFlowBb, uint32_t idxInstr, PDBGFADDRESS pAddrInstr,
1767 uint32_t *pcbInstr, const char **ppszInstr)
1768{
1769 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1770 AssertPtrReturn(pFlowBb, VERR_INVALID_POINTER);
1771 AssertReturn(idxInstr < pFlowBb->cInstr, VERR_INVALID_PARAMETER);
1772
1773 if (pAddrInstr)
1774 *pAddrInstr = pFlowBb->aInstr[idxInstr].AddrInstr;
1775 if (pcbInstr)
1776 *pcbInstr = pFlowBb->aInstr[idxInstr].cbInstr;
1777 if (ppszInstr)
1778 *ppszInstr = pFlowBb->aInstr[idxInstr].pszInstr;
1779
1780 return VINF_SUCCESS;
1781}
1782
1783
1784/**
1785 * Queries the successors of the basic block.
1786 *
1787 * @returns VBox status code.
1788 * @param hFlowBb The basic block handle.
1789 * @param phFlowBbFollow Where to store the handle to the basic block following
1790 * this one (optional).
1791 * @param phFlowBbTarget Where to store the handle to the basic block being the
1792 * branch target for this one (optional).
1793 */
1794VMMR3DECL(int) DBGFR3FlowBbQuerySuccessors(DBGFFLOWBB hFlowBb, PDBGFFLOWBB phFlowBbFollow, PDBGFFLOWBB phFlowBbTarget)
1795{
1796 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1797 AssertPtrReturn(pFlowBb, VERR_INVALID_POINTER);
1798
1799 if ( phFlowBbFollow
1800 && ( pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_UNCOND
1801 || pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_COND))
1802 {
1803 DBGFADDRESS AddrStart = pFlowBb->AddrEnd;
1804 DBGFR3AddrAdd(&AddrStart, 1);
1805 int rc = DBGFR3FlowQueryBbByAddress(pFlowBb->pFlow, &AddrStart, phFlowBbFollow);
1806 AssertRC(rc);
1807 }
1808
1809 if ( phFlowBbTarget
1810 && ( pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_UNCOND_JMP
1811 || pFlowBb->enmEndType == DBGFFLOWBBENDTYPE_COND))
1812 {
1813 int rc = DBGFR3FlowQueryBbByAddress(pFlowBb->pFlow, &pFlowBb->AddrTarget, phFlowBbTarget);
1814 AssertRC(rc);
1815 }
1816
1817 return VINF_SUCCESS;
1818}
1819
1820
1821/**
1822 * Returns the number of basic blocks referencing this basic block as a target.
1823 *
1824 * @returns Number of other basic blocks referencing this one.
1825 * @param hFlowBb The basic block handle.
1826 *
1827 * @note If the given basic block references itself (loop, etc.) this will be counted as well.
1828 */
1829VMMR3DECL(uint32_t) DBGFR3FlowBbGetRefBbCount(DBGFFLOWBB hFlowBb)
1830{
1831 PDBGFFLOWBBINT pFlowBb = hFlowBb;
1832 AssertPtrReturn(pFlowBb, 0);
1833
1834 uint32_t cRefsBb = 0;
1835 PDBGFFLOWBBINT pFlowBbCur;
1836 RTListForEach(&pFlowBb->pFlow->LstFlowBb, pFlowBbCur, DBGFFLOWBBINT, NdFlowBb)
1837 {
1838 if (pFlowBbCur->fFlags & DBGF_FLOW_BB_F_INCOMPLETE_ERR)
1839 continue;
1840
1841 if ( pFlowBbCur->enmEndType == DBGFFLOWBBENDTYPE_UNCOND
1842 || pFlowBbCur->enmEndType == DBGFFLOWBBENDTYPE_COND)
1843 {
1844 DBGFADDRESS AddrStart = pFlowBb->AddrEnd;
1845 DBGFR3AddrAdd(&AddrStart, 1);
1846 if (dbgfR3FlowAddrEqual(&pFlowBbCur->AddrStart, &AddrStart))
1847 cRefsBb++;
1848 }
1849
1850 if ( ( pFlowBbCur->enmEndType == DBGFFLOWBBENDTYPE_UNCOND_JMP
1851 || pFlowBbCur->enmEndType == DBGFFLOWBBENDTYPE_COND)
1852 && dbgfR3FlowAddrEqual(&pFlowBbCur->AddrStart, &pFlowBb->AddrTarget))
1853 cRefsBb++;
1854 }
1855 return cRefsBb;
1856}
1857
1858
1859/**
1860 * Returns the basic block handles referencing the given basic block.
1861 *
1862 * @returns VBox status code.
1863 * @retval VERR_BUFFER_OVERFLOW if the array can't hold all the basic blocks.
1864 * @param hFlowBb The basic block handle.
1865 * @param paFlowBbRef Pointer to the array containing the referencing basic block handles on success.
1866 * @param cRef Number of entries in the given array.
1867 */
1868VMMR3DECL(int) DBGFR3FlowBbGetRefBb(DBGFFLOWBB hFlowBb, PDBGFFLOWBB paFlowBbRef, uint32_t cRef)
1869{
1870 RT_NOREF3(hFlowBb, paFlowBbRef, cRef);
1871 return VERR_NOT_IMPLEMENTED;
1872}
1873
1874
1875/**
1876 * Retains a reference for the given control flow graph branch table.
1877 *
1878 * @returns new reference count.
1879 * @param hFlowBranchTbl The branch table handle.
1880 */
1881VMMR3DECL(uint32_t) DBGFR3FlowBranchTblRetain(DBGFFLOWBRANCHTBL hFlowBranchTbl)
1882{
1883 PDBGFFLOWBRANCHTBLINT pFlowBranchTbl = hFlowBranchTbl;
1884 AssertPtrReturn(pFlowBranchTbl, UINT32_MAX);
1885
1886 uint32_t cRefs = ASMAtomicIncU32(&pFlowBranchTbl->cRefs);
1887 AssertMsg(cRefs > 1 && cRefs < _1M, ("%#x %p\n", cRefs, pFlowBranchTbl));
1888 return cRefs;
1889}
1890
1891
1892/**
1893 * Releases a given branch table handle.
1894 *
1895 * @returns the new reference count of the given branch table, on 0 it is destroyed.
1896 * @param hFlowBranchTbl The branch table handle.
1897 */
1898VMMR3DECL(uint32_t) DBGFR3FlowBranchTblRelease(DBGFFLOWBRANCHTBL hFlowBranchTbl)
1899{
1900 PDBGFFLOWBRANCHTBLINT pFlowBranchTbl = hFlowBranchTbl;
1901 if (!pFlowBranchTbl)
1902 return 0;
1903 AssertPtrReturn(pFlowBranchTbl, UINT32_MAX);
1904
1905 uint32_t cRefs = ASMAtomicDecU32(&pFlowBranchTbl->cRefs);
1906 AssertMsg(cRefs < _1M, ("%#x %p\n", cRefs, pFlowBranchTbl));
1907 if (cRefs == 0)
1908 dbgfR3FlowBranchTblDestroy(pFlowBranchTbl);
1909 return cRefs;
1910}
1911
1912
1913/**
1914 * Return the number of slots the branch table has.
1915 *
1916 * @returns Number of slots in the branch table.
1917 * @param hFlowBranchTbl The branch table handle.
1918 */
1919VMMR3DECL(uint32_t) DBGFR3FlowBranchTblGetSlots(DBGFFLOWBRANCHTBL hFlowBranchTbl)
1920{
1921 PDBGFFLOWBRANCHTBLINT pFlowBranchTbl = hFlowBranchTbl;
1922 AssertPtrReturn(pFlowBranchTbl, 0);
1923
1924 return pFlowBranchTbl->cSlots;
1925}
1926
1927
1928/**
1929 * Returns the start address of the branch table in the guest.
1930 *
1931 * @returns Pointer to start address of the branch table (pAddrStart).
1932 * @param hFlowBranchTbl The branch table handle.
1933 * @param pAddrStart Where to store the branch table address.
1934 */
1935VMMR3DECL(PDBGFADDRESS) DBGFR3FlowBranchTblGetStartAddress(DBGFFLOWBRANCHTBL hFlowBranchTbl, PDBGFADDRESS pAddrStart)
1936{
1937 PDBGFFLOWBRANCHTBLINT pFlowBranchTbl = hFlowBranchTbl;
1938 AssertPtrReturn(pFlowBranchTbl, NULL);
1939 AssertPtrReturn(pAddrStart, NULL);
1940
1941 *pAddrStart = pFlowBranchTbl->AddrStart;
1942 return pAddrStart;
1943}
1944
1945
1946/**
1947 * Returns one address in the branch table at the given slot index.
1948 *
1949 * @return Pointer to the address at the given slot in the given branch table.
1950 * @param hFlowBranchTbl The branch table handle.
1951 * @param idxSlot The slot the address should be returned from.
1952 * @param pAddrSlot Where to store the address.
1953 */
1954VMMR3DECL(PDBGFADDRESS) DBGFR3FlowBranchTblGetAddrAtSlot(DBGFFLOWBRANCHTBL hFlowBranchTbl, uint32_t idxSlot, PDBGFADDRESS pAddrSlot)
1955{
1956 PDBGFFLOWBRANCHTBLINT pFlowBranchTbl = hFlowBranchTbl;
1957 AssertPtrReturn(pFlowBranchTbl, NULL);
1958 AssertPtrReturn(pAddrSlot, NULL);
1959 AssertReturn(idxSlot < pFlowBranchTbl->cSlots, NULL);
1960
1961 *pAddrSlot = pFlowBranchTbl->aAddresses[idxSlot];
1962 return pAddrSlot;
1963}
1964
1965
1966/**
1967 * Query all addresses contained in the given branch table.
1968 *
1969 * @returns VBox status code.
1970 * @retval VERR_BUFFER_OVERFLOW if there is not enough space in the array to hold all addresses.
1971 * @param hFlowBranchTbl The branch table handle.
1972 * @param paAddrs Where to store the addresses on success.
1973 * @param cAddrs Number of entries the array can hold.
1974 */
1975VMMR3DECL(int) DBGFR3FlowBranchTblQueryAddresses(DBGFFLOWBRANCHTBL hFlowBranchTbl, PDBGFADDRESS paAddrs, uint32_t cAddrs)
1976{
1977 PDBGFFLOWBRANCHTBLINT pFlowBranchTbl = hFlowBranchTbl;
1978 AssertPtrReturn(pFlowBranchTbl, VERR_INVALID_HANDLE);
1979 AssertPtrReturn(paAddrs, VERR_INVALID_POINTER);
1980 AssertReturn(cAddrs > 0, VERR_INVALID_PARAMETER);
1981
1982 if (cAddrs < pFlowBranchTbl->cSlots)
1983 return VERR_BUFFER_OVERFLOW;
1984
1985 memcpy(paAddrs, &pFlowBranchTbl->aAddresses[0], pFlowBranchTbl->cSlots * sizeof(DBGFADDRESS));
1986 return VINF_SUCCESS;
1987}
1988
1989
1990/**
1991 * @callback_method_impl{FNRTSORTCMP}
1992 */
1993static DECLCALLBACK(int) dbgfR3FlowItSortCmp(void const *pvElement1, void const *pvElement2, void *pvUser)
1994{
1995 PDBGFFLOWITORDER penmOrder = (PDBGFFLOWITORDER)pvUser;
1996 PDBGFFLOWBBINT pFlowBb1 = *(PDBGFFLOWBBINT *)pvElement1;
1997 PDBGFFLOWBBINT pFlowBb2 = *(PDBGFFLOWBBINT *)pvElement2;
1998
1999 if (dbgfR3FlowAddrEqual(&pFlowBb1->AddrStart, &pFlowBb2->AddrStart))
2000 return 0;
2001
2002 if (*penmOrder == DBGFFLOWITORDER_BY_ADDR_LOWEST_FIRST)
2003 {
2004 if (dbgfR3FlowAddrLower(&pFlowBb1->AddrStart, &pFlowBb2->AddrStart))
2005 return -1;
2006 else
2007 return 1;
2008 }
2009 else
2010 {
2011 if (dbgfR3FlowAddrLower(&pFlowBb1->AddrStart, &pFlowBb2->AddrStart))
2012 return 1;
2013 else
2014 return -1;
2015 }
2016}
2017
2018
2019/**
2020 * Creates a new iterator for the given control flow graph.
2021 *
2022 * @returns VBox status code.
2023 * @param hFlow The control flow graph handle.
2024 * @param enmOrder The order in which the basic blocks are enumerated.
2025 * @param phFlowIt Where to store the handle to the iterator on success.
2026 */
2027VMMR3DECL(int) DBGFR3FlowItCreate(DBGFFLOW hFlow, DBGFFLOWITORDER enmOrder, PDBGFFLOWIT phFlowIt)
2028{
2029 int rc = VINF_SUCCESS;
2030 PDBGFFLOWINT pFlow = hFlow;
2031 AssertPtrReturn(pFlow, VERR_INVALID_POINTER);
2032 AssertPtrReturn(phFlowIt, VERR_INVALID_POINTER);
2033 AssertReturn(enmOrder > DBGFFLOWITORDER_INVALID && enmOrder < DBGFFLOWITORDER_BREADTH_FIRST,
2034 VERR_INVALID_PARAMETER);
2035 AssertReturn(enmOrder < DBGFFLOWITORDER_DEPTH_FRIST, VERR_NOT_IMPLEMENTED); /** @todo */
2036
2037 PDBGFFLOWITINT pIt = (PDBGFFLOWITINT)RTMemAllocZ(RT_OFFSETOF(DBGFFLOWITINT, apBb[pFlow->cBbs]));
2038 if (RT_LIKELY(pIt))
2039 {
2040 DBGFR3FlowRetain(hFlow);
2041 pIt->pFlow = pFlow;
2042 pIt->idxBbNext = 0;
2043 /* Fill the list and then sort. */
2044 uint32_t idxBb = 0;
2045 PDBGFFLOWBBINT pFlowBb;
2046 RTListForEach(&pFlow->LstFlowBb, pFlowBb, DBGFFLOWBBINT, NdFlowBb)
2047 {
2048 DBGFR3FlowBbRetain(pFlowBb);
2049 pIt->apBb[idxBb++] = pFlowBb;
2050 }
2051
2052 /* Sort the blocks by address. */
2053 RTSortShell(&pIt->apBb[0], pFlow->cBbs, sizeof(PDBGFFLOWBBINT), dbgfR3FlowItSortCmp, &enmOrder);
2054
2055 *phFlowIt = pIt;
2056 }
2057 else
2058 rc = VERR_NO_MEMORY;
2059
2060 return rc;
2061}
2062
2063
2064/**
2065 * Destroys a given control flow graph iterator.
2066 *
2067 * @returns nothing.
2068 * @param hFlowIt The control flow graph iterator handle.
2069 */
2070VMMR3DECL(void) DBGFR3FlowItDestroy(DBGFFLOWIT hFlowIt)
2071{
2072 PDBGFFLOWITINT pIt = hFlowIt;
2073 AssertPtrReturnVoid(pIt);
2074
2075 for (unsigned i = 0; i < pIt->pFlow->cBbs; i++)
2076 DBGFR3FlowBbRelease(pIt->apBb[i]);
2077
2078 DBGFR3FlowRelease(pIt->pFlow);
2079 RTMemFree(pIt);
2080}
2081
2082
2083/**
2084 * Returns the next basic block in the iterator or NULL if there is no
2085 * basic block left.
2086 *
2087 * @returns Handle to the next basic block in the iterator or NULL if the end
2088 * was reached.
2089 * @param hFlowIt The iterator handle.
2090 *
2091 * @note If a valid handle is returned it must be release with DBGFR3FlowBbRelease()
2092 * when not required anymore.
2093 */
2094VMMR3DECL(DBGFFLOWBB) DBGFR3FlowItNext(DBGFFLOWIT hFlowIt)
2095{
2096 PDBGFFLOWITINT pIt = hFlowIt;
2097 AssertPtrReturn(pIt, NULL);
2098
2099 PDBGFFLOWBBINT pFlowBb = NULL;
2100 if (pIt->idxBbNext < pIt->pFlow->cBbs)
2101 {
2102 pFlowBb = pIt->apBb[pIt->idxBbNext++];
2103 DBGFR3FlowBbRetain(pFlowBb);
2104 }
2105
2106 return pFlowBb;
2107}
2108
2109
2110/**
2111 * Resets the given iterator to the beginning.
2112 *
2113 * @returns VBox status code.
2114 * @param hFlowIt The iterator handle.
2115 */
2116VMMR3DECL(int) DBGFR3FlowItReset(DBGFFLOWIT hFlowIt)
2117{
2118 PDBGFFLOWITINT pIt = hFlowIt;
2119 AssertPtrReturn(pIt, VERR_INVALID_HANDLE);
2120
2121 pIt->idxBbNext = 0;
2122 return VINF_SUCCESS;
2123}
2124
2125
2126/**
2127 * @callback_method_impl{FNRTSORTCMP}
2128 */
2129static DECLCALLBACK(int) dbgfR3FlowBranchTblItSortCmp(void const *pvElement1, void const *pvElement2, void *pvUser)
2130{
2131 PDBGFFLOWITORDER penmOrder = (PDBGFFLOWITORDER)pvUser;
2132 PDBGFFLOWBRANCHTBLINT pTbl1 = *(PDBGFFLOWBRANCHTBLINT *)pvElement1;
2133 PDBGFFLOWBRANCHTBLINT pTbl2 = *(PDBGFFLOWBRANCHTBLINT *)pvElement2;
2134
2135 if (dbgfR3FlowAddrEqual(&pTbl1->AddrStart, &pTbl2->AddrStart))
2136 return 0;
2137
2138 if (*penmOrder == DBGFFLOWITORDER_BY_ADDR_LOWEST_FIRST)
2139 {
2140 if (dbgfR3FlowAddrLower(&pTbl1->AddrStart, &pTbl2->AddrStart))
2141 return -1;
2142 else
2143 return 1;
2144 }
2145 else
2146 {
2147 if (dbgfR3FlowAddrLower(&pTbl1->AddrStart, &pTbl2->AddrStart))
2148 return 1;
2149 else
2150 return -1;
2151 }
2152}
2153
2154
2155/**
2156 * Creates a new branch table iterator for the given control flow graph.
2157 *
2158 * @returns VBox status code.
2159 * @param hFlow The control flow graph handle.
2160 * @param enmOrder The order in which the basic blocks are enumerated.
2161 * @param phFlowBranchTblIt Where to store the handle to the iterator on success.
2162 */
2163VMMR3DECL(int) DBGFR3FlowBranchTblItCreate(DBGFFLOW hFlow, DBGFFLOWITORDER enmOrder,
2164 PDBGFFLOWBRANCHTBLIT phFlowBranchTblIt)
2165{
2166 int rc = VINF_SUCCESS;
2167 PDBGFFLOWINT pFlow = hFlow;
2168 AssertPtrReturn(pFlow, VERR_INVALID_POINTER);
2169 AssertPtrReturn(phFlowBranchTblIt, VERR_INVALID_POINTER);
2170 AssertReturn(enmOrder > DBGFFLOWITORDER_INVALID && enmOrder < DBGFFLOWITORDER_BREADTH_FIRST,
2171 VERR_INVALID_PARAMETER);
2172 AssertReturn(enmOrder < DBGFFLOWITORDER_DEPTH_FRIST, VERR_NOT_SUPPORTED);
2173
2174 PDBGFFLOWBRANCHTBLITINT pIt = (PDBGFFLOWBRANCHTBLITINT)RTMemAllocZ(RT_OFFSETOF(DBGFFLOWBRANCHTBLITINT, apBranchTbl[pFlow->cBranchTbls]));
2175 if (RT_LIKELY(pIt))
2176 {
2177 DBGFR3FlowRetain(hFlow);
2178 pIt->pFlow = pFlow;
2179 pIt->idxTblNext = 0;
2180 /* Fill the list and then sort. */
2181 uint32_t idxTbl = 0;
2182 PDBGFFLOWBRANCHTBLINT pFlowBranchTbl;
2183 RTListForEach(&pFlow->LstBranchTbl, pFlowBranchTbl, DBGFFLOWBRANCHTBLINT, NdBranchTbl)
2184 {
2185 DBGFR3FlowBranchTblRetain(pFlowBranchTbl);
2186 pIt->apBranchTbl[idxTbl++] = pFlowBranchTbl;
2187 }
2188
2189 /* Sort the blocks by address. */
2190 RTSortShell(&pIt->apBranchTbl[0], pFlow->cBranchTbls, sizeof(PDBGFFLOWBRANCHTBLINT), dbgfR3FlowBranchTblItSortCmp, &enmOrder);
2191
2192 *phFlowBranchTblIt = pIt;
2193 }
2194 else
2195 rc = VERR_NO_MEMORY;
2196
2197 return rc;
2198}
2199
2200
2201/**
2202 * Destroys a given control flow graph branch table iterator.
2203 *
2204 * @returns nothing.
2205 * @param hFlowBranchTblIt The control flow graph branch table iterator handle.
2206 */
2207VMMR3DECL(void) DBGFR3FlowBranchTblItDestroy(DBGFFLOWBRANCHTBLIT hFlowBranchTblIt)
2208{
2209 PDBGFFLOWBRANCHTBLITINT pIt = hFlowBranchTblIt;
2210 AssertPtrReturnVoid(pIt);
2211
2212 for (unsigned i = 0; i < pIt->pFlow->cBranchTbls; i++)
2213 DBGFR3FlowBranchTblRelease(pIt->apBranchTbl[i]);
2214
2215 DBGFR3FlowRelease(pIt->pFlow);
2216 RTMemFree(pIt);
2217}
2218
2219
2220/**
2221 * Returns the next branch table in the iterator or NULL if there is no
2222 * branch table left.
2223 *
2224 * @returns Handle to the next basic block in the iterator or NULL if the end
2225 * was reached.
2226 * @param hFlowBranchTblIt The iterator handle.
2227 *
2228 * @note If a valid handle is returned it must be release with DBGFR3FlowBranchTblRelease()
2229 * when not required anymore.
2230 */
2231VMMR3DECL(DBGFFLOWBRANCHTBL) DBGFR3FlowBranchTblItNext(DBGFFLOWBRANCHTBLIT hFlowBranchTblIt)
2232{
2233 PDBGFFLOWBRANCHTBLITINT pIt = hFlowBranchTblIt;
2234 AssertPtrReturn(pIt, NULL);
2235
2236 PDBGFFLOWBRANCHTBLINT pTbl = NULL;
2237 if (pIt->idxTblNext < pIt->pFlow->cBranchTbls)
2238 {
2239 pTbl = pIt->apBranchTbl[pIt->idxTblNext++];
2240 DBGFR3FlowBranchTblRetain(pTbl);
2241 }
2242
2243 return pTbl;
2244}
2245
2246
2247/**
2248 * Resets the given iterator to the beginning.
2249 *
2250 * @returns VBox status code.
2251 * @param hFlowBranchTblIt The iterator handle.
2252 */
2253VMMR3DECL(int) DBGFR3FlowBranchTblItReset(DBGFFLOWBRANCHTBLIT hFlowBranchTblIt)
2254{
2255 PDBGFFLOWBRANCHTBLITINT pIt = hFlowBranchTblIt;
2256 AssertPtrReturn(pIt, VERR_INVALID_HANDLE);
2257
2258 pIt->idxTblNext = 0;
2259 return VINF_SUCCESS;
2260}
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