VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 45177

Last change on this file since 45177 was 45152, checked in by vboxsync, 12 years ago

PDMCritSectRw: Early morphing stage - untested, ring-3 only.
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1/* $Id: EM.cpp 45152 2013-03-23 20:36:23Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HmExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/vmm.h>
40#include <VBox/vmm/patm.h>
41#include <VBox/vmm/csam.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iom.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/pgm.h>
47#ifdef VBOX_WITH_REM
48# include <VBox/vmm/rem.h>
49#else
50# include <VBox/vmm/iem.h>
51#endif
52#include <VBox/vmm/tm.h>
53#include <VBox/vmm/mm.h>
54#include <VBox/vmm/ssm.h>
55#include <VBox/vmm/pdmapi.h>
56#include <VBox/vmm/pdmcritsect.h>
57#include <VBox/vmm/pdmqueue.h>
58#include <VBox/vmm/hm.h>
59#include <VBox/vmm/patm.h>
60#ifdef IEM_VERIFICATION_MODE
61# include <VBox/vmm/iem.h>
62#endif
63#include "EMInternal.h"
64#include <VBox/vmm/vm.h>
65#include <VBox/vmm/uvm.h>
66#include <VBox/vmm/cpumdis.h>
67#include <VBox/dis.h>
68#include <VBox/disopcode.h>
69#include <VBox/vmm/dbgf.h>
70#include "VMMTracing.h"
71
72#include <iprt/asm.h>
73#include <iprt/string.h>
74#include <iprt/stream.h>
75#include <iprt/thread.h>
76
77
78/*******************************************************************************
79* Defined Constants And Macros *
80*******************************************************************************/
81#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
82#define EM_NOTIFY_HM
83#endif
84
85
86/*******************************************************************************
87* Internal Functions *
88*******************************************************************************/
89static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
90static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
91#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
92static const char *emR3GetStateName(EMSTATE enmState);
93#endif
94static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
95static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
96static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
97int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
98
99
100/**
101 * Initializes the EM.
102 *
103 * @returns VBox status code.
104 * @param pVM Pointer to the VM.
105 */
106VMMR3_INT_DECL(int) EMR3Init(PVM pVM)
107{
108 LogFlow(("EMR3Init\n"));
109 /*
110 * Assert alignment and sizes.
111 */
112 AssertCompileMemberAlignment(VM, em.s, 32);
113 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
114 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
115
116 /*
117 * Init the structure.
118 */
119 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
120 bool fEnabled;
121 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &fEnabled);
122 pVM->fRecompileUser = RT_SUCCESS(rc) ? !fEnabled : false;
123 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &fEnabled);
124 pVM->fRecompileSupervisor = RT_SUCCESS(rc) ? !fEnabled : false;
125 Log(("EMR3Init: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n", pVM->fRecompileUser, pVM->fRecompileSupervisor));
126
127#ifdef VBOX_WITH_REM
128 /*
129 * Initialize the REM critical section.
130 */
131 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
132 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
133 AssertRCReturn(rc, rc);
134#endif
135
136 /*
137 * Saved state.
138 */
139 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
140 NULL, NULL, NULL,
141 NULL, emR3Save, NULL,
142 NULL, emR3Load, NULL);
143 if (RT_FAILURE(rc))
144 return rc;
145
146 for (VMCPUID i = 0; i < pVM->cCpus; i++)
147 {
148 PVMCPU pVCpu = &pVM->aCpus[i];
149
150 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
151
152 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
153 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
154 pVCpu->em.s.fForceRAW = false;
155
156 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
157 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
158 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
159
160 /* Force reset of the time slice. */
161 pVCpu->em.s.u64TimeSliceStart = 0;
162
163# define EM_REG_COUNTER(a, b, c) \
164 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
165 AssertRC(rc);
166
167# define EM_REG_COUNTER_USED(a, b, c) \
168 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
169 AssertRC(rc);
170
171# define EM_REG_PROFILE(a, b, c) \
172 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
173 AssertRC(rc);
174
175# define EM_REG_PROFILE_ADV(a, b, c) \
176 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
177 AssertRC(rc);
178
179 /*
180 * Statistics.
181 */
182#ifdef VBOX_WITH_STATISTICS
183 PEMSTATS pStats;
184 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
185 if (RT_FAILURE(rc))
186 return rc;
187
188 pVCpu->em.s.pStatsR3 = pStats;
189 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
190 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
191
192 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
193 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
194
195 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
196 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
197
198 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
199 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
200 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
201 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
202 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
203 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
204 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
205 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
206 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
207 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
208 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
261 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
262 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
263 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
264 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
270
271 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
272 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
273
274 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
315 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
316 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
317 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
324
325 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
326 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
327 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
343 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
344 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
345 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
346 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
347 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
348 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
349 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
350 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
351 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
352 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
353
354 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
355 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
356 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
357 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
358
359 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
360 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
361 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
362 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
363 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
364 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
365 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
366 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
367 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 write instructions.");
368 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 write instructions.");
369 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 write instructions.");
370 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 write instructions.");
371 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 write instructions.");
372 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 read instructions.");
373 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 read instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 read instructions.");
375 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 read instructions.");
376 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 read instructions.");
377 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
378 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
379 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
380 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
381 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
382 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
383 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
384 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
385 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
386
387 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
388 pVCpu->em.s.pCliStatTree = 0;
389
390 /* these should be considered for release statistics. */
391 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
392 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
393 EM_REG_PROFILE(&pVCpu->em.s.StatHmEntry, "/PROF/CPU%d/EM/HmEnter", "Profiling Hardware Accelerated Mode entry overhead.");
394 EM_REG_PROFILE(&pVCpu->em.s.StatHmExec, "/PROF/CPU%d/EM/HmExec", "Profiling Hardware Accelerated Mode execution.");
395 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
396 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
397 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
398 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
399 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
400 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
401
402#endif /* VBOX_WITH_STATISTICS */
403
404 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
405 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
406 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
407 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
408 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
409
410 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
411 }
412
413 return VINF_SUCCESS;
414}
415
416
417/**
418 * Applies relocations to data and code managed by this
419 * component. This function will be called at init and
420 * whenever the VMM need to relocate it self inside the GC.
421 *
422 * @param pVM Pointer to the VM.
423 */
424VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM)
425{
426 LogFlow(("EMR3Relocate\n"));
427 for (VMCPUID i = 0; i < pVM->cCpus; i++)
428 {
429 PVMCPU pVCpu = &pVM->aCpus[i];
430 if (pVCpu->em.s.pStatsR3)
431 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
432 }
433}
434
435
436/**
437 * Reset the EM state for a CPU.
438 *
439 * Called by EMR3Reset and hot plugging.
440 *
441 * @param pVCpu Pointer to the VMCPU.
442 */
443VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
444{
445 pVCpu->em.s.fForceRAW = false;
446
447 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
448 out of the HALTED state here so that enmPrevState doesn't end up as
449 HALTED when EMR3Execute returns. */
450 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
451 {
452 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
453 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
454 }
455}
456
457
458/**
459 * Reset notification.
460 *
461 * @param pVM Pointer to the VM.
462 */
463VMMR3_INT_DECL(void) EMR3Reset(PVM pVM)
464{
465 Log(("EMR3Reset: \n"));
466 for (VMCPUID i = 0; i < pVM->cCpus; i++)
467 EMR3ResetCpu(&pVM->aCpus[i]);
468}
469
470
471/**
472 * Terminates the EM.
473 *
474 * Termination means cleaning up and freeing all resources,
475 * the VM it self is at this point powered off or suspended.
476 *
477 * @returns VBox status code.
478 * @param pVM Pointer to the VM.
479 */
480VMMR3_INT_DECL(int) EMR3Term(PVM pVM)
481{
482 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
483
484#ifdef VBOX_WITH_REM
485 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
486#endif
487 return VINF_SUCCESS;
488}
489
490
491/**
492 * Execute state save operation.
493 *
494 * @returns VBox status code.
495 * @param pVM Pointer to the VM.
496 * @param pSSM SSM operation handle.
497 */
498static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
499{
500 for (VMCPUID i = 0; i < pVM->cCpus; i++)
501 {
502 PVMCPU pVCpu = &pVM->aCpus[i];
503
504 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
505 AssertRCReturn(rc, rc);
506
507 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
508 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
509 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
510 AssertRCReturn(rc, rc);
511
512 /* Save mwait state. */
513 rc = SSMR3PutU32(pSSM, pVCpu->em.s.MWait.fWait);
514 AssertRCReturn(rc, rc);
515 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRAX);
516 AssertRCReturn(rc, rc);
517 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRCX);
518 AssertRCReturn(rc, rc);
519 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRAX);
520 AssertRCReturn(rc, rc);
521 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRCX);
522 AssertRCReturn(rc, rc);
523 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRDX);
524 AssertRCReturn(rc, rc);
525 }
526 return VINF_SUCCESS;
527}
528
529
530/**
531 * Execute state load operation.
532 *
533 * @returns VBox status code.
534 * @param pVM Pointer to the VM.
535 * @param pSSM SSM operation handle.
536 * @param uVersion Data layout version.
537 * @param uPass The data pass.
538 */
539static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
540{
541 /*
542 * Validate version.
543 */
544 if ( uVersion != EM_SAVED_STATE_VERSION
545 && uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
546 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
547 {
548 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
549 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
550 }
551 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
552
553 /*
554 * Load the saved state.
555 */
556 for (VMCPUID i = 0; i < pVM->cCpus; i++)
557 {
558 PVMCPU pVCpu = &pVM->aCpus[i];
559
560 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
561 if (RT_FAILURE(rc))
562 pVCpu->em.s.fForceRAW = false;
563 AssertRCReturn(rc, rc);
564
565 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
566 {
567 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
568 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
569 AssertRCReturn(rc, rc);
570 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
571
572 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
573 }
574 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
575 {
576 /* Load mwait state. */
577 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.MWait.fWait);
578 AssertRCReturn(rc, rc);
579 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRAX);
580 AssertRCReturn(rc, rc);
581 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRCX);
582 AssertRCReturn(rc, rc);
583 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRAX);
584 AssertRCReturn(rc, rc);
585 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRCX);
586 AssertRCReturn(rc, rc);
587 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRDX);
588 AssertRCReturn(rc, rc);
589 }
590
591 Assert(!pVCpu->em.s.pCliStatTree);
592 }
593 return VINF_SUCCESS;
594}
595
596
597/**
598 * Argument packet for emR3SetExecutionPolicy.
599 */
600struct EMR3SETEXECPOLICYARGS
601{
602 EMEXECPOLICY enmPolicy;
603 bool fEnforce;
604};
605
606
607/**
608 * @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
609 */
610static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
611{
612 /*
613 * Only the first CPU changes the variables.
614 */
615 if (pVCpu->idCpu == 0)
616 {
617 struct EMR3SETEXECPOLICYARGS *pArgs = (struct EMR3SETEXECPOLICYARGS *)pvUser;
618 switch (pArgs->enmPolicy)
619 {
620 case EMEXECPOLICY_RECOMPILE_RING0:
621 pVM->fRecompileSupervisor = pArgs->fEnforce;
622 break;
623 case EMEXECPOLICY_RECOMPILE_RING3:
624 pVM->fRecompileUser = pArgs->fEnforce;
625 break;
626 default:
627 AssertFailedReturn(VERR_INVALID_PARAMETER);
628 }
629 Log(("emR3SetExecutionPolicy: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n",
630 pVM->fRecompileUser, pVM->fRecompileSupervisor));
631 }
632
633 /*
634 * Force rescheduling if in RAW, HM or REM.
635 */
636 return pVCpu->em.s.enmState == EMSTATE_RAW
637 || pVCpu->em.s.enmState == EMSTATE_HM
638 || pVCpu->em.s.enmState == EMSTATE_REM
639 ? VINF_EM_RESCHEDULE
640 : VINF_SUCCESS;
641}
642
643
644/**
645 * Changes a the execution scheduling policy.
646 *
647 * This is used to enable or disable raw-mode / hardware-virtualization
648 * execution of user and supervisor code.
649 *
650 * @returns VINF_SUCCESS on success.
651 * @returns VINF_RESCHEDULE if a rescheduling might be required.
652 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
653 *
654 * @param pUVM The user mode VM handle.
655 * @param enmPolicy The scheduling policy to change.
656 * @param fEnforce Whether to enforce the policy or not.
657 */
658VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce)
659{
660 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
661 VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
662 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
663
664 struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
665 return VMMR3EmtRendezvous(pUVM->pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
666}
667
668
669/**
670 * Checks if raw ring-3 execute mode is enabled.
671 *
672 * @returns true if enabled, false if disabled.
673 * @param pUVM The user mode VM handle.
674 */
675VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM)
676{
677 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
678 PVM pVM = pUVM->pVM;
679 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
680 return EMIsRawRing3Enabled(pVM);
681}
682
683
684/**
685 * Checks if raw ring-0 execute mode is enabled.
686 *
687 * @returns true if enabled, false if disabled.
688 * @param pUVM The user mode VM handle.
689 */
690VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM)
691{
692 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
693 PVM pVM = pUVM->pVM;
694 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
695 return EMIsRawRing0Enabled(pVM);
696}
697
698
699/**
700 * Raise a fatal error.
701 *
702 * Safely terminate the VM with full state report and stuff. This function
703 * will naturally never return.
704 *
705 * @param pVCpu Pointer to the VMCPU.
706 * @param rc VBox status code.
707 */
708VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
709{
710 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
711 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
712 AssertReleaseMsgFailed(("longjmp returned!\n"));
713}
714
715
716#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
717/**
718 * Gets the EM state name.
719 *
720 * @returns pointer to read only state name,
721 * @param enmState The state.
722 */
723static const char *emR3GetStateName(EMSTATE enmState)
724{
725 switch (enmState)
726 {
727 case EMSTATE_NONE: return "EMSTATE_NONE";
728 case EMSTATE_RAW: return "EMSTATE_RAW";
729 case EMSTATE_HM: return "EMSTATE_HM";
730 case EMSTATE_REM: return "EMSTATE_REM";
731 case EMSTATE_HALTED: return "EMSTATE_HALTED";
732 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
733 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
734 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
735 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
736 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
737 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
738 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
739 default: return "Unknown!";
740 }
741}
742#endif /* LOG_ENABLED || VBOX_STRICT */
743
744
745/**
746 * Debug loop.
747 *
748 * @returns VBox status code for EM.
749 * @param pVM Pointer to the VM.
750 * @param pVCpu Pointer to the VMCPU.
751 * @param rc Current EM VBox status code.
752 */
753static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
754{
755 for (;;)
756 {
757 Log(("emR3Debug: rc=%Rrc\n", rc));
758 const int rcLast = rc;
759
760 /*
761 * Debug related RC.
762 */
763 switch (rc)
764 {
765 /*
766 * Single step an instruction.
767 */
768 case VINF_EM_DBG_STEP:
769#ifdef VBOX_WITH_RAW_MODE
770 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
771 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
772 || pVCpu->em.s.fForceRAW /* paranoia */)
773 rc = emR3RawStep(pVM, pVCpu);
774 else
775 {
776 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
777 rc = emR3RemStep(pVM, pVCpu);
778 }
779#else
780 AssertLogRelMsgFailed(("%Rrc\n", rc));
781 rc = VERR_EM_INTERNAL_ERROR;
782#endif
783 break;
784
785 /*
786 * Simple events: stepped, breakpoint, stop/assertion.
787 */
788 case VINF_EM_DBG_STEPPED:
789 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
790 break;
791
792 case VINF_EM_DBG_BREAKPOINT:
793 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
794 break;
795
796 case VINF_EM_DBG_STOP:
797 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
798 break;
799
800 case VINF_EM_DBG_HYPER_STEPPED:
801 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
802 break;
803
804 case VINF_EM_DBG_HYPER_BREAKPOINT:
805 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
806 break;
807
808 case VINF_EM_DBG_HYPER_ASSERTION:
809 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
810 RTLogFlush(NULL);
811 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
812 break;
813
814 /*
815 * Guru meditation.
816 */
817 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
818 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
819 break;
820 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
821 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
822 break;
823
824 default: /** @todo don't use default for guru, but make special errors code! */
825 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
826 break;
827 }
828
829 /*
830 * Process the result.
831 */
832 do
833 {
834 switch (rc)
835 {
836 /*
837 * Continue the debugging loop.
838 */
839 case VINF_EM_DBG_STEP:
840 case VINF_EM_DBG_STOP:
841 case VINF_EM_DBG_STEPPED:
842 case VINF_EM_DBG_BREAKPOINT:
843 case VINF_EM_DBG_HYPER_STEPPED:
844 case VINF_EM_DBG_HYPER_BREAKPOINT:
845 case VINF_EM_DBG_HYPER_ASSERTION:
846 break;
847
848 /*
849 * Resuming execution (in some form) has to be done here if we got
850 * a hypervisor debug event.
851 */
852 case VINF_SUCCESS:
853 case VINF_EM_RESUME:
854 case VINF_EM_SUSPEND:
855 case VINF_EM_RESCHEDULE:
856 case VINF_EM_RESCHEDULE_RAW:
857 case VINF_EM_RESCHEDULE_REM:
858 case VINF_EM_HALT:
859 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
860 {
861#ifdef VBOX_WITH_RAW_MODE
862 rc = emR3RawResumeHyper(pVM, pVCpu);
863 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
864 continue;
865#else
866 AssertLogRelMsgFailedReturn(("Not implemented\n", rc), VERR_EM_INTERNAL_ERROR);
867#endif
868 }
869 if (rc == VINF_SUCCESS)
870 rc = VINF_EM_RESCHEDULE;
871 return rc;
872
873 /*
874 * The debugger isn't attached.
875 * We'll simply turn the thing off since that's the easiest thing to do.
876 */
877 case VERR_DBGF_NOT_ATTACHED:
878 switch (rcLast)
879 {
880 case VINF_EM_DBG_HYPER_STEPPED:
881 case VINF_EM_DBG_HYPER_BREAKPOINT:
882 case VINF_EM_DBG_HYPER_ASSERTION:
883 case VERR_TRPM_PANIC:
884 case VERR_TRPM_DONT_PANIC:
885 case VERR_VMM_RING0_ASSERTION:
886 case VERR_VMM_HYPER_CR3_MISMATCH:
887 case VERR_VMM_RING3_CALL_DISABLED:
888 return rcLast;
889 }
890 return VINF_EM_OFF;
891
892 /*
893 * Status codes terminating the VM in one or another sense.
894 */
895 case VINF_EM_TERMINATE:
896 case VINF_EM_OFF:
897 case VINF_EM_RESET:
898 case VINF_EM_NO_MEMORY:
899 case VINF_EM_RAW_STALE_SELECTOR:
900 case VINF_EM_RAW_IRET_TRAP:
901 case VERR_TRPM_PANIC:
902 case VERR_TRPM_DONT_PANIC:
903 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
904 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
905 case VERR_VMM_RING0_ASSERTION:
906 case VERR_VMM_HYPER_CR3_MISMATCH:
907 case VERR_VMM_RING3_CALL_DISABLED:
908 case VERR_INTERNAL_ERROR:
909 case VERR_INTERNAL_ERROR_2:
910 case VERR_INTERNAL_ERROR_3:
911 case VERR_INTERNAL_ERROR_4:
912 case VERR_INTERNAL_ERROR_5:
913 case VERR_IPE_UNEXPECTED_STATUS:
914 case VERR_IPE_UNEXPECTED_INFO_STATUS:
915 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
916 return rc;
917
918 /*
919 * The rest is unexpected, and will keep us here.
920 */
921 default:
922 AssertMsgFailed(("Unexpected rc %Rrc!\n", rc));
923 break;
924 }
925 } while (false);
926 } /* debug for ever */
927}
928
929/**
930 * Steps recompiled code.
931 *
932 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
933 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
934 *
935 * @param pVM Pointer to the VM.
936 * @param pVCpu Pointer to the VMCPU.
937 */
938static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
939{
940 LogFlow(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
941
942#ifdef VBOX_WITH_REM
943 EMRemLock(pVM);
944
945 /*
946 * Switch to REM, step instruction, switch back.
947 */
948 int rc = REMR3State(pVM, pVCpu);
949 if (RT_SUCCESS(rc))
950 {
951 rc = REMR3Step(pVM, pVCpu);
952 REMR3StateBack(pVM, pVCpu);
953 }
954 EMRemUnlock(pVM);
955
956#else
957 int rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
958#endif
959
960 LogFlow(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
961 return rc;
962}
963
964
965/**
966 * emR3RemExecute helper that syncs the state back from REM and leave the REM
967 * critical section.
968 *
969 * @returns false - new fInREMState value.
970 * @param pVM Pointer to the VM.
971 * @param pVCpu Pointer to the VMCPU.
972 */
973DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
974{
975#ifdef VBOX_WITH_REM
976 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
977 REMR3StateBack(pVM, pVCpu);
978 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
979
980 EMRemUnlock(pVM);
981#endif
982 return false;
983}
984
985
986/**
987 * Executes recompiled code.
988 *
989 * This function contains the recompiler version of the inner
990 * execution loop (the outer loop being in EMR3ExecuteVM()).
991 *
992 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
993 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
994 *
995 * @param pVM Pointer to the VM.
996 * @param pVCpu Pointer to the VMCPU.
997 * @param pfFFDone Where to store an indicator telling whether or not
998 * FFs were done before returning.
999 *
1000 */
1001static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1002{
1003#ifdef LOG_ENABLED
1004 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1005 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
1006
1007 if (pCtx->eflags.Bits.u1VM)
1008 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF));
1009 else
1010 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
1011#endif
1012 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
1013
1014#if defined(VBOX_STRICT) && defined(DEBUG_bird)
1015 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1016 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */
1017 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1018#endif
1019
1020 /*
1021 * Spin till we get a forced action which returns anything but VINF_SUCCESS
1022 * or the REM suggests raw-mode execution.
1023 */
1024 *pfFFDone = false;
1025#ifdef VBOX_WITH_REM
1026 bool fInREMState = false;
1027#endif
1028 int rc = VINF_SUCCESS;
1029 for (;;)
1030 {
1031#ifdef VBOX_WITH_REM
1032 /*
1033 * Lock REM and update the state if not already in sync.
1034 *
1035 * Note! Big lock, but you are not supposed to own any lock when
1036 * coming in here.
1037 */
1038 if (!fInREMState)
1039 {
1040 EMRemLock(pVM);
1041 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
1042
1043 /* Flush the recompiler translation blocks if the VCPU has changed,
1044 also force a full CPU state resync. */
1045 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1046 {
1047 REMFlushTBs(pVM);
1048 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1049 }
1050 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1051
1052 rc = REMR3State(pVM, pVCpu);
1053
1054 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
1055 if (RT_FAILURE(rc))
1056 break;
1057 fInREMState = true;
1058
1059 /*
1060 * We might have missed the raising of VMREQ, TIMER and some other
1061 * important FFs while we were busy switching the state. So, check again.
1062 */
1063 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
1064 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
1065 {
1066 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1067 goto l_REMDoForcedActions;
1068 }
1069 }
1070#endif
1071
1072 /*
1073 * Execute REM.
1074 */
1075 if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1076 {
1077 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1078#ifdef VBOX_WITH_REM
1079 rc = REMR3Run(pVM, pVCpu);
1080#else
1081 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
1082#endif
1083 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1084 }
1085 else
1086 {
1087 /* Give up this time slice; virtual time continues */
1088 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1089 RTThreadSleep(5);
1090 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1091 rc = VINF_SUCCESS;
1092 }
1093
1094 /*
1095 * Deal with high priority post execution FFs before doing anything
1096 * else. Sync back the state and leave the lock to be on the safe side.
1097 */
1098 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1099 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1100 {
1101#ifdef VBOX_WITH_REM
1102 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1103#endif
1104 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1105 }
1106
1107 /*
1108 * Process the returned status code.
1109 */
1110 if (rc != VINF_SUCCESS)
1111 {
1112 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1113 break;
1114 if (rc != VINF_REM_INTERRUPED_FF)
1115 {
1116 /*
1117 * Anything which is not known to us means an internal error
1118 * and the termination of the VM!
1119 */
1120 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1121 break;
1122 }
1123 }
1124
1125
1126 /*
1127 * Check and execute forced actions.
1128 *
1129 * Sync back the VM state and leave the lock before calling any of
1130 * these, you never know what's going to happen here.
1131 */
1132#ifdef VBOX_HIGH_RES_TIMERS_HACK
1133 TMTimerPollVoid(pVM, pVCpu);
1134#endif
1135 AssertCompile((VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
1136 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1137 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
1138 {
1139l_REMDoForcedActions:
1140#ifdef VBOX_WITH_REM
1141 if (fInREMState)
1142 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1143#endif
1144 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1145 rc = emR3ForcedActions(pVM, pVCpu, rc);
1146 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1147 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1148 if ( rc != VINF_SUCCESS
1149 && rc != VINF_EM_RESCHEDULE_REM)
1150 {
1151 *pfFFDone = true;
1152 break;
1153 }
1154 }
1155
1156 } /* The Inner Loop, recompiled execution mode version. */
1157
1158
1159#ifdef VBOX_WITH_REM
1160 /*
1161 * Returning. Sync back the VM state if required.
1162 */
1163 if (fInREMState)
1164 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1165#endif
1166
1167 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1168 return rc;
1169}
1170
1171
1172#ifdef DEBUG
1173
1174int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1175{
1176 EMSTATE enmOldState = pVCpu->em.s.enmState;
1177
1178 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1179
1180 Log(("Single step BEGIN:\n"));
1181 for (uint32_t i = 0; i < cIterations; i++)
1182 {
1183 DBGFR3PrgStep(pVCpu);
1184 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS: ");
1185 emR3RemStep(pVM, pVCpu);
1186 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1187 break;
1188 }
1189 Log(("Single step END:\n"));
1190 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1191 pVCpu->em.s.enmState = enmOldState;
1192 return VINF_EM_RESCHEDULE;
1193}
1194
1195#endif /* DEBUG */
1196
1197
1198/**
1199 * Decides whether to execute RAW, HWACC or REM.
1200 *
1201 * @returns new EM state
1202 * @param pVM Pointer to the VM.
1203 * @param pVCpu Pointer to the VMCPU.
1204 * @param pCtx Pointer to the guest CPU context.
1205 */
1206EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1207{
1208#ifdef IEM_VERIFICATION_MODE
1209 return EMSTATE_REM;
1210#else
1211
1212 /*
1213 * When forcing raw-mode execution, things are simple.
1214 */
1215 if (pVCpu->em.s.fForceRAW)
1216 return EMSTATE_RAW;
1217
1218 /*
1219 * We stay in the wait for SIPI state unless explicitly told otherwise.
1220 */
1221 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1222 return EMSTATE_WAIT_SIPI;
1223
1224 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1225 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1226 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1227
1228 X86EFLAGS EFlags = pCtx->eflags;
1229 if (HMIsEnabled(pVM))
1230 {
1231 /*
1232 * Hardware accelerated raw-mode:
1233 *
1234 * Typically only 32-bits protected mode, with paging enabled, code is
1235 * allowed here.
1236 */
1237 if ( EMIsHwVirtExecutionEnabled(pVM)
1238 && HMR3CanExecuteGuest(pVM, pCtx))
1239 return EMSTATE_HM;
1240
1241 /*
1242 * Note! Raw mode and hw accelerated mode are incompatible. The latter
1243 * turns off monitoring features essential for raw mode!
1244 */
1245 return EMSTATE_REM;
1246 }
1247
1248 /*
1249 * Standard raw-mode:
1250 *
1251 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1252 * or 32 bits protected mode ring 0 code
1253 *
1254 * The tests are ordered by the likelihood of being true during normal execution.
1255 */
1256 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1257 {
1258 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1259 return EMSTATE_REM;
1260 }
1261
1262# ifndef VBOX_RAW_V86
1263 if (EFlags.u32 & X86_EFL_VM) {
1264 Log2(("raw mode refused: VM_MASK\n"));
1265 return EMSTATE_REM;
1266 }
1267# endif
1268
1269 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1270 uint32_t u32CR0 = pCtx->cr0;
1271 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1272 {
1273 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1274 return EMSTATE_REM;
1275 }
1276
1277 if (pCtx->cr4 & X86_CR4_PAE)
1278 {
1279 uint32_t u32Dummy, u32Features;
1280
1281 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1282 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1283 return EMSTATE_REM;
1284 }
1285
1286 unsigned uSS = pCtx->ss.Sel;
1287 if ( pCtx->eflags.Bits.u1VM
1288 || (uSS & X86_SEL_RPL) == 3)
1289 {
1290 if (!EMIsRawRing3Enabled(pVM))
1291 return EMSTATE_REM;
1292
1293 if (!(EFlags.u32 & X86_EFL_IF))
1294 {
1295 Log2(("raw mode refused: IF (RawR3)\n"));
1296 return EMSTATE_REM;
1297 }
1298
1299 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1300 {
1301 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1302 return EMSTATE_REM;
1303 }
1304 }
1305 else
1306 {
1307 if (!EMIsRawRing0Enabled(pVM))
1308 return EMSTATE_REM;
1309
1310 /* Only ring 0 supervisor code. */
1311 if ((uSS & X86_SEL_RPL) != 0)
1312 {
1313 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1314 return EMSTATE_REM;
1315 }
1316
1317 // Let's start with pure 32 bits ring 0 code first
1318 /** @todo What's pure 32-bit mode? flat? */
1319 if ( !(pCtx->ss.Attr.n.u1DefBig)
1320 || !(pCtx->cs.Attr.n.u1DefBig))
1321 {
1322 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1323 return EMSTATE_REM;
1324 }
1325
1326 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1327 if (!(u32CR0 & X86_CR0_WP))
1328 {
1329 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1330 return EMSTATE_REM;
1331 }
1332
1333 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1334 {
1335 Log2(("raw r0 mode forced: patch code\n"));
1336 return EMSTATE_RAW;
1337 }
1338
1339# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1340 if (!(EFlags.u32 & X86_EFL_IF))
1341 {
1342 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1343 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1344 return EMSTATE_REM;
1345 }
1346# endif
1347
1348 /** @todo still necessary??? */
1349 if (EFlags.Bits.u2IOPL != 0)
1350 {
1351 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1352 return EMSTATE_REM;
1353 }
1354 }
1355
1356 /*
1357 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1358 */
1359 if (pCtx->cs.fFlags & CPUMSELREG_FLAGS_STALE)
1360 {
1361 Log2(("raw mode refused: stale CS\n"));
1362 return EMSTATE_REM;
1363 }
1364 if (pCtx->ss.fFlags & CPUMSELREG_FLAGS_STALE)
1365 {
1366 Log2(("raw mode refused: stale SS\n"));
1367 return EMSTATE_REM;
1368 }
1369 if (pCtx->ds.fFlags & CPUMSELREG_FLAGS_STALE)
1370 {
1371 Log2(("raw mode refused: stale DS\n"));
1372 return EMSTATE_REM;
1373 }
1374 if (pCtx->es.fFlags & CPUMSELREG_FLAGS_STALE)
1375 {
1376 Log2(("raw mode refused: stale ES\n"));
1377 return EMSTATE_REM;
1378 }
1379 if (pCtx->fs.fFlags & CPUMSELREG_FLAGS_STALE)
1380 {
1381 Log2(("raw mode refused: stale FS\n"));
1382 return EMSTATE_REM;
1383 }
1384 if (pCtx->gs.fFlags & CPUMSELREG_FLAGS_STALE)
1385 {
1386 Log2(("raw mode refused: stale GS\n"));
1387 return EMSTATE_REM;
1388 }
1389
1390 /*Assert(PGMPhysIsA20Enabled(pVCpu));*/
1391 return EMSTATE_RAW;
1392#endif /* !IEM_VERIFICATION_MODE */
1393
1394}
1395
1396
1397/**
1398 * Executes all high priority post execution force actions.
1399 *
1400 * @returns rc or a fatal status code.
1401 *
1402 * @param pVM Pointer to the VM.
1403 * @param pVCpu Pointer to the VMCPU.
1404 * @param rc The current rc.
1405 */
1406int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1407{
1408 VBOXVMM_EM_FF_HIGH(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1409
1410 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1411 PDMCritSectBothFF(pVCpu);
1412
1413 /* Update CR3 (Nested Paging case for HM). */
1414 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
1415 {
1416 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
1417 if (RT_FAILURE(rc2))
1418 return rc2;
1419 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
1420 }
1421
1422 /* Update PAE PDPEs. This must be done *after* PGMUpdateCR3() and used only by the Nested Paging case for HM. */
1423 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
1424 {
1425 if (CPUMIsGuestInPAEMode(pVCpu))
1426 {
1427 PX86PDPE pPdpes = HMGetPaePdpes(pVCpu);
1428 AssertPtr(pPdpes);
1429
1430 int rc2 = PGMGstUpdatePaePdpes(pVCpu, pPdpes);
1431 if (RT_FAILURE(rc2))
1432 return rc2;
1433 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
1434 }
1435 else
1436 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1437 }
1438
1439 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1440 CSAMR3DoPendingAction(pVM, pVCpu);
1441
1442 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1443 {
1444 if ( rc > VINF_EM_NO_MEMORY
1445 && rc <= VINF_EM_LAST)
1446 rc = VINF_EM_NO_MEMORY;
1447 }
1448
1449 return rc;
1450}
1451
1452
1453/**
1454 * Executes all pending forced actions.
1455 *
1456 * Forced actions can cause execution delays and execution
1457 * rescheduling. The first we deal with using action priority, so
1458 * that for instance pending timers aren't scheduled and ran until
1459 * right before execution. The rescheduling we deal with using
1460 * return codes. The same goes for VM termination, only in that case
1461 * we exit everything.
1462 *
1463 * @returns VBox status code of equal or greater importance/severity than rc.
1464 * The most important ones are: VINF_EM_RESCHEDULE,
1465 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1466 *
1467 * @param pVM Pointer to the VM.
1468 * @param pVCpu Pointer to the VMCPU.
1469 * @param rc The current rc.
1470 *
1471 */
1472int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1473{
1474 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1475#ifdef VBOX_STRICT
1476 int rcIrq = VINF_SUCCESS;
1477#endif
1478 int rc2;
1479#define UPDATE_RC() \
1480 do { \
1481 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1482 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1483 break; \
1484 if (!rc || rc2 < rc) \
1485 rc = rc2; \
1486 } while (0)
1487 VBOXVMM_EM_FF_ALL(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1488
1489 /*
1490 * Post execution chunk first.
1491 */
1492 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1493 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1494 {
1495 /*
1496 * EMT Rendezvous (must be serviced before termination).
1497 */
1498 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1499 {
1500 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1501 UPDATE_RC();
1502 /** @todo HACK ALERT! The following test is to make sure EM+TM
1503 * thinks the VM is stopped/reset before the next VM state change
1504 * is made. We need a better solution for this, or at least make it
1505 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1506 * VINF_EM_SUSPEND). */
1507 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1508 {
1509 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1510 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1511 return rc;
1512 }
1513 }
1514
1515 /*
1516 * State change request (cleared by vmR3SetStateLocked).
1517 */
1518 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1519 {
1520 VMSTATE enmState = VMR3GetState(pVM);
1521 switch (enmState)
1522 {
1523 case VMSTATE_FATAL_ERROR:
1524 case VMSTATE_FATAL_ERROR_LS:
1525 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1526 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1527 return VINF_EM_SUSPEND;
1528
1529 case VMSTATE_DESTROYING:
1530 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1531 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1532 return VINF_EM_TERMINATE;
1533
1534 default:
1535 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1536 }
1537 }
1538
1539 /*
1540 * Debugger Facility polling.
1541 */
1542 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1543 {
1544 rc2 = DBGFR3VMMForcedAction(pVM);
1545 UPDATE_RC();
1546 }
1547
1548 /*
1549 * Postponed reset request.
1550 */
1551 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1552 {
1553 rc2 = VMR3Reset(pVM->pUVM);
1554 UPDATE_RC();
1555 }
1556
1557 /*
1558 * CSAM page scanning.
1559 */
1560 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1561 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1562 {
1563 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1564
1565 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1566 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1567
1568 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1569 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1570 }
1571
1572 /*
1573 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1574 */
1575 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1576 {
1577 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1578 UPDATE_RC();
1579 if (rc == VINF_EM_NO_MEMORY)
1580 return rc;
1581 }
1582
1583 /* check that we got them all */
1584 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1585 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1586 }
1587
1588 /*
1589 * Normal priority then.
1590 * (Executed in no particular order.)
1591 */
1592 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1593 {
1594 /*
1595 * PDM Queues are pending.
1596 */
1597 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1598 PDMR3QueueFlushAll(pVM);
1599
1600 /*
1601 * PDM DMA transfers are pending.
1602 */
1603 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1604 PDMR3DmaRun(pVM);
1605
1606 /*
1607 * EMT Rendezvous (make sure they are handled before the requests).
1608 */
1609 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1610 {
1611 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1612 UPDATE_RC();
1613 /** @todo HACK ALERT! The following test is to make sure EM+TM
1614 * thinks the VM is stopped/reset before the next VM state change
1615 * is made. We need a better solution for this, or at least make it
1616 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1617 * VINF_EM_SUSPEND). */
1618 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1619 {
1620 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1621 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1622 return rc;
1623 }
1624 }
1625
1626 /*
1627 * Requests from other threads.
1628 */
1629 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1630 {
1631 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
1632 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1633 {
1634 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1635 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1636 return rc2;
1637 }
1638 UPDATE_RC();
1639 /** @todo HACK ALERT! The following test is to make sure EM+TM
1640 * thinks the VM is stopped/reset before the next VM state change
1641 * is made. We need a better solution for this, or at least make it
1642 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1643 * VINF_EM_SUSPEND). */
1644 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1645 {
1646 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1647 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1648 return rc;
1649 }
1650 }
1651
1652#ifdef VBOX_WITH_REM
1653 /* Replay the handler notification changes. */
1654 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1655 {
1656 /* Try not to cause deadlocks. */
1657 if ( pVM->cCpus == 1
1658 || ( !PGMIsLockOwner(pVM)
1659 && !IOMIsLockOwner(pVM))
1660 )
1661 {
1662 EMRemLock(pVM);
1663 REMR3ReplayHandlerNotifications(pVM);
1664 EMRemUnlock(pVM);
1665 }
1666 }
1667#endif
1668
1669 /* check that we got them all */
1670 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1671 }
1672
1673 /*
1674 * Normal priority then. (per-VCPU)
1675 * (Executed in no particular order.)
1676 */
1677 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1678 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1679 {
1680 /*
1681 * Requests from other threads.
1682 */
1683 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1684 {
1685 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
1686 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1687 {
1688 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1689 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1690 return rc2;
1691 }
1692 UPDATE_RC();
1693 /** @todo HACK ALERT! The following test is to make sure EM+TM
1694 * thinks the VM is stopped/reset before the next VM state change
1695 * is made. We need a better solution for this, or at least make it
1696 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1697 * VINF_EM_SUSPEND). */
1698 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1699 {
1700 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1701 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1702 return rc;
1703 }
1704 }
1705
1706 /* check that we got them all */
1707 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1708 }
1709
1710 /*
1711 * High priority pre execution chunk last.
1712 * (Executed in ascending priority order.)
1713 */
1714 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1715 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1716 {
1717 /*
1718 * Timers before interrupts.
1719 */
1720 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1721 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1722 TMR3TimerQueuesDo(pVM);
1723
1724 /*
1725 * The instruction following an emulated STI should *always* be executed!
1726 *
1727 * Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1728 * the eip is the same as the inhibited instr address. Before we
1729 * are able to execute this instruction in raw mode (iret to
1730 * guest code) an external interrupt might force a world switch
1731 * again. Possibly allowing a guest interrupt to be dispatched
1732 * in the process. This could break the guest. Sounds very
1733 * unlikely, but such timing sensitive problem are not as rare as
1734 * you might think.
1735 */
1736 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1737 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1738 {
1739 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1740 {
1741 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1742 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1743 }
1744 else
1745 Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1746 }
1747
1748 /*
1749 * Interrupts.
1750 */
1751 bool fWakeupPending = false;
1752 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1753 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1754 && (!rc || rc >= VINF_EM_RESCHEDULE_HM)
1755 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1756 && PATMAreInterruptsEnabled(pVM)
1757 && !HMR3IsEventPending(pVCpu))
1758 {
1759 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1760 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1761 {
1762 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1763 /** @todo this really isn't nice, should properly handle this */
1764 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1765#ifdef VBOX_STRICT
1766 rcIrq = rc2;
1767#endif
1768 UPDATE_RC();
1769 /* Reschedule required: We must not miss the wakeup below! */
1770 fWakeupPending = true;
1771 }
1772#ifdef VBOX_WITH_REM
1773 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1774 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1775 {
1776 rc2 = VINF_EM_RESCHEDULE_REM;
1777 UPDATE_RC();
1778 }
1779#endif
1780 }
1781
1782 /*
1783 * Allocate handy pages.
1784 */
1785 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1786 {
1787 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1788 UPDATE_RC();
1789 }
1790
1791 /*
1792 * Debugger Facility request.
1793 */
1794 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1795 {
1796 rc2 = DBGFR3VMMForcedAction(pVM);
1797 UPDATE_RC();
1798 }
1799
1800 /*
1801 * EMT Rendezvous (must be serviced before termination).
1802 */
1803 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1804 && VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1805 {
1806 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1807 UPDATE_RC();
1808 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1809 * stopped/reset before the next VM state change is made. We need a better
1810 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1811 * && rc >= VINF_EM_SUSPEND). */
1812 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1813 {
1814 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1815 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1816 return rc;
1817 }
1818 }
1819
1820 /*
1821 * State change request (cleared by vmR3SetStateLocked).
1822 */
1823 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1824 && VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1825 {
1826 VMSTATE enmState = VMR3GetState(pVM);
1827 switch (enmState)
1828 {
1829 case VMSTATE_FATAL_ERROR:
1830 case VMSTATE_FATAL_ERROR_LS:
1831 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1832 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1833 return VINF_EM_SUSPEND;
1834
1835 case VMSTATE_DESTROYING:
1836 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1837 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1838 return VINF_EM_TERMINATE;
1839
1840 default:
1841 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1842 }
1843 }
1844
1845 /*
1846 * Out of memory? Since most of our fellow high priority actions may cause us
1847 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1848 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1849 * than us since we can terminate without allocating more memory.
1850 */
1851 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1852 {
1853 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1854 UPDATE_RC();
1855 if (rc == VINF_EM_NO_MEMORY)
1856 return rc;
1857 }
1858
1859 /*
1860 * If the virtual sync clock is still stopped, make TM restart it.
1861 */
1862 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1863 TMR3VirtualSyncFF(pVM, pVCpu);
1864
1865#ifdef DEBUG
1866 /*
1867 * Debug, pause the VM.
1868 */
1869 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1870 {
1871 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1872 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1873 return VINF_EM_SUSPEND;
1874 }
1875#endif
1876
1877 /* check that we got them all */
1878 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1879 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
1880 }
1881
1882#undef UPDATE_RC
1883 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1884 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1885 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1886 return rc;
1887}
1888
1889
1890/**
1891 * Check if the preset execution time cap restricts guest execution scheduling.
1892 *
1893 * @returns true if allowed, false otherwise
1894 * @param pVM Pointer to the VM.
1895 * @param pVCpu Pointer to the VMCPU.
1896 *
1897 */
1898VMMR3_INT_DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1899{
1900 uint64_t u64UserTime, u64KernelTime;
1901
1902 if ( pVM->uCpuExecutionCap != 100
1903 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1904 {
1905 uint64_t u64TimeNow = RTTimeMilliTS();
1906 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1907 {
1908 /* New time slice. */
1909 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1910 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1911 pVCpu->em.s.u64TimeSliceExec = 0;
1912 }
1913 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1914
1915 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1916 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1917 return false;
1918 }
1919 return true;
1920}
1921
1922
1923/**
1924 * Execute VM.
1925 *
1926 * This function is the main loop of the VM. The emulation thread
1927 * calls this function when the VM has been successfully constructed
1928 * and we're ready for executing the VM.
1929 *
1930 * Returning from this function means that the VM is turned off or
1931 * suspended (state already saved) and deconstruction is next in line.
1932 *
1933 * All interaction from other thread are done using forced actions
1934 * and signaling of the wait object.
1935 *
1936 * @returns VBox status code, informational status codes may indicate failure.
1937 * @param pVM Pointer to the VM.
1938 * @param pVCpu Pointer to the VMCPU.
1939 */
1940VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1941{
1942 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1943 pVM,
1944 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1945 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1946 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1947 pVCpu->em.s.fForceRAW));
1948 VM_ASSERT_EMT(pVM);
1949 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1950 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1951 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1952 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
1953
1954 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1955 if (rc == 0)
1956 {
1957 /*
1958 * Start the virtual time.
1959 */
1960 TMR3NotifyResume(pVM, pVCpu);
1961
1962 /*
1963 * The Outer Main Loop.
1964 */
1965 bool fFFDone = false;
1966
1967 /* Reschedule right away to start in the right state. */
1968 rc = VINF_SUCCESS;
1969
1970 /* If resuming after a pause or a state load, restore the previous
1971 state or else we'll start executing code. Else, just reschedule. */
1972 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
1973 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
1974 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
1975 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
1976 else
1977 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
1978
1979 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
1980 for (;;)
1981 {
1982 /*
1983 * Before we can schedule anything (we're here because
1984 * scheduling is required) we must service any pending
1985 * forced actions to avoid any pending action causing
1986 * immediate rescheduling upon entering an inner loop
1987 *
1988 * Do forced actions.
1989 */
1990 if ( !fFFDone
1991 && rc != VINF_EM_TERMINATE
1992 && rc != VINF_EM_OFF
1993 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1994 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
1995 {
1996 rc = emR3ForcedActions(pVM, pVCpu, rc);
1997 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1998 if ( ( rc == VINF_EM_RESCHEDULE_REM
1999 || rc == VINF_EM_RESCHEDULE_HM)
2000 && pVCpu->em.s.fForceRAW)
2001 rc = VINF_EM_RESCHEDULE_RAW;
2002 }
2003 else if (fFFDone)
2004 fFFDone = false;
2005
2006 /*
2007 * Now what to do?
2008 */
2009 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
2010 EMSTATE const enmOldState = pVCpu->em.s.enmState;
2011 switch (rc)
2012 {
2013 /*
2014 * Keep doing what we're currently doing.
2015 */
2016 case VINF_SUCCESS:
2017 break;
2018
2019 /*
2020 * Reschedule - to raw-mode execution.
2021 */
2022 case VINF_EM_RESCHEDULE_RAW:
2023 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", enmOldState, EMSTATE_RAW));
2024 pVCpu->em.s.enmState = EMSTATE_RAW;
2025 break;
2026
2027 /*
2028 * Reschedule - to hardware accelerated raw-mode execution.
2029 */
2030 case VINF_EM_RESCHEDULE_HM:
2031 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HM: %d -> %d (EMSTATE_HM)\n", enmOldState, EMSTATE_HM));
2032 Assert(!pVCpu->em.s.fForceRAW);
2033 pVCpu->em.s.enmState = EMSTATE_HM;
2034 break;
2035
2036 /*
2037 * Reschedule - to recompiled execution.
2038 */
2039 case VINF_EM_RESCHEDULE_REM:
2040 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
2041 pVCpu->em.s.enmState = EMSTATE_REM;
2042 break;
2043
2044 /*
2045 * Resume.
2046 */
2047 case VINF_EM_RESUME:
2048 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", enmOldState));
2049 /* Don't reschedule in the halted or wait for SIPI case. */
2050 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2051 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
2052 {
2053 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2054 break;
2055 }
2056 /* fall through and get scheduled. */
2057
2058 /*
2059 * Reschedule.
2060 */
2061 case VINF_EM_RESCHEDULE:
2062 {
2063 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2064 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2065 pVCpu->em.s.enmState = enmState;
2066 break;
2067 }
2068
2069 /*
2070 * Halted.
2071 */
2072 case VINF_EM_HALT:
2073 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", enmOldState, EMSTATE_HALTED));
2074 pVCpu->em.s.enmState = EMSTATE_HALTED;
2075 break;
2076
2077 /*
2078 * Switch to the wait for SIPI state (application processor only)
2079 */
2080 case VINF_EM_WAIT_SIPI:
2081 Assert(pVCpu->idCpu != 0);
2082 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", enmOldState, EMSTATE_WAIT_SIPI));
2083 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2084 break;
2085
2086
2087 /*
2088 * Suspend.
2089 */
2090 case VINF_EM_SUSPEND:
2091 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2092 Assert(enmOldState != EMSTATE_SUSPENDED);
2093 pVCpu->em.s.enmPrevState = enmOldState;
2094 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2095 break;
2096
2097 /*
2098 * Reset.
2099 * We might end up doing a double reset for now, we'll have to clean up the mess later.
2100 */
2101 case VINF_EM_RESET:
2102 {
2103 if (pVCpu->idCpu == 0)
2104 {
2105 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2106 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2107 pVCpu->em.s.enmState = enmState;
2108 }
2109 else
2110 {
2111 /* All other VCPUs go into the wait for SIPI state. */
2112 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2113 }
2114 break;
2115 }
2116
2117 /*
2118 * Power Off.
2119 */
2120 case VINF_EM_OFF:
2121 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2122 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2123 TMR3NotifySuspend(pVM, pVCpu);
2124 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2125 return rc;
2126
2127 /*
2128 * Terminate the VM.
2129 */
2130 case VINF_EM_TERMINATE:
2131 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2132 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2133 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
2134 TMR3NotifySuspend(pVM, pVCpu);
2135 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2136 return rc;
2137
2138
2139 /*
2140 * Out of memory, suspend the VM and stuff.
2141 */
2142 case VINF_EM_NO_MEMORY:
2143 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2144 Assert(enmOldState != EMSTATE_SUSPENDED);
2145 pVCpu->em.s.enmPrevState = enmOldState;
2146 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2147 TMR3NotifySuspend(pVM, pVCpu);
2148 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2149
2150 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2151 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2152 if (rc != VINF_EM_SUSPEND)
2153 {
2154 if (RT_SUCCESS_NP(rc))
2155 {
2156 AssertLogRelMsgFailed(("%Rrc\n", rc));
2157 rc = VERR_EM_INTERNAL_ERROR;
2158 }
2159 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2160 }
2161 return rc;
2162
2163 /*
2164 * Guest debug events.
2165 */
2166 case VINF_EM_DBG_STEPPED:
2167 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
2168 case VINF_EM_DBG_STOP:
2169 case VINF_EM_DBG_BREAKPOINT:
2170 case VINF_EM_DBG_STEP:
2171 if (enmOldState == EMSTATE_RAW)
2172 {
2173 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_RAW));
2174 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2175 }
2176 else
2177 {
2178 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_REM));
2179 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2180 }
2181 break;
2182
2183 /*
2184 * Hypervisor debug events.
2185 */
2186 case VINF_EM_DBG_HYPER_STEPPED:
2187 case VINF_EM_DBG_HYPER_BREAKPOINT:
2188 case VINF_EM_DBG_HYPER_ASSERTION:
2189 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_HYPER));
2190 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2191 break;
2192
2193 /*
2194 * Guru mediations.
2195 */
2196 case VERR_VMM_RING0_ASSERTION:
2197 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2198 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2199 break;
2200
2201 /*
2202 * Any error code showing up here other than the ones we
2203 * know and process above are considered to be FATAL.
2204 *
2205 * Unknown warnings and informational status codes are also
2206 * included in this.
2207 */
2208 default:
2209 if (RT_SUCCESS_NP(rc))
2210 {
2211 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2212 rc = VERR_EM_INTERNAL_ERROR;
2213 }
2214 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2215 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2216 break;
2217 }
2218
2219 /*
2220 * Act on state transition.
2221 */
2222 EMSTATE const enmNewState = pVCpu->em.s.enmState;
2223 if (enmOldState != enmNewState)
2224 {
2225 VBOXVMM_EM_STATE_CHANGED(pVCpu, enmOldState, enmNewState, rc);
2226
2227 /* Clear MWait flags. */
2228 if ( enmOldState == EMSTATE_HALTED
2229 && (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2230 && ( enmNewState == EMSTATE_RAW
2231 || enmNewState == EMSTATE_HM
2232 || enmNewState == EMSTATE_REM
2233 || enmNewState == EMSTATE_DEBUG_GUEST_RAW
2234 || enmNewState == EMSTATE_DEBUG_GUEST_HM
2235 || enmNewState == EMSTATE_DEBUG_GUEST_REM) )
2236 {
2237 LogFlow(("EMR3ExecuteVM: Clearing MWAIT\n"));
2238 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2239 }
2240 }
2241 else
2242 VBOXVMM_EM_STATE_UNCHANGED(pVCpu, enmNewState, rc);
2243
2244 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2245 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2246
2247 /*
2248 * Act on the new state.
2249 */
2250 switch (enmNewState)
2251 {
2252 /*
2253 * Execute raw.
2254 */
2255 case EMSTATE_RAW:
2256#ifndef IEM_VERIFICATION_MODE /* remove later */
2257# ifdef VBOX_WITH_RAW_MODE
2258 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2259# else
2260 AssertLogRelMsgFailed(("%Rrc\n", rc));
2261 rc = VERR_EM_INTERNAL_ERROR;
2262# endif
2263 break;
2264#endif
2265
2266 /*
2267 * Execute hardware accelerated raw.
2268 */
2269 case EMSTATE_HM:
2270#ifndef IEM_VERIFICATION_MODE /* remove later */
2271 rc = emR3HmExecute(pVM, pVCpu, &fFFDone);
2272 break;
2273#endif
2274
2275 /*
2276 * Execute recompiled.
2277 */
2278 case EMSTATE_REM:
2279#ifdef IEM_VERIFICATION_MODE
2280# if 1
2281 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); fFFDone = false;
2282# else
2283 rc = VBOXSTRICTRC_TODO(REMR3EmulateInstruction(pVM, pVCpu)); fFFDone = false;
2284 if (rc == VINF_EM_RESCHEDULE)
2285 rc = VINF_SUCCESS;
2286# endif
2287#else
2288 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2289#endif
2290 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2291 break;
2292
2293 /*
2294 * Application processor execution halted until SIPI.
2295 */
2296 case EMSTATE_WAIT_SIPI:
2297 /* no break */
2298 /*
2299 * hlt - execution halted until interrupt.
2300 */
2301 case EMSTATE_HALTED:
2302 {
2303 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2304 /* MWAIT has a special extension where it's woken up when
2305 an interrupt is pending even when IF=0. */
2306 if ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2307 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2308 {
2309 rc = VMR3WaitHalted(pVM, pVCpu, false /*fIgnoreInterrupts*/);
2310 if ( rc == VINF_SUCCESS
2311 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2312 {
2313 Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
2314 rc = VINF_EM_RESCHEDULE;
2315 }
2316 }
2317 else
2318 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2319
2320 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2321 break;
2322 }
2323
2324 /*
2325 * Suspended - return to VM.cpp.
2326 */
2327 case EMSTATE_SUSPENDED:
2328 TMR3NotifySuspend(pVM, pVCpu);
2329 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2330 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2331 return VINF_EM_SUSPEND;
2332
2333 /*
2334 * Debugging in the guest.
2335 */
2336 case EMSTATE_DEBUG_GUEST_REM:
2337 case EMSTATE_DEBUG_GUEST_RAW:
2338 TMR3NotifySuspend(pVM, pVCpu);
2339 rc = emR3Debug(pVM, pVCpu, rc);
2340 TMR3NotifyResume(pVM, pVCpu);
2341 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2342 break;
2343
2344 /*
2345 * Debugging in the hypervisor.
2346 */
2347 case EMSTATE_DEBUG_HYPER:
2348 {
2349 TMR3NotifySuspend(pVM, pVCpu);
2350 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2351
2352 rc = emR3Debug(pVM, pVCpu, rc);
2353 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2354 if (rc != VINF_SUCCESS)
2355 {
2356 /* switch to guru meditation mode */
2357 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2358 VMMR3FatalDump(pVM, pVCpu, rc);
2359 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2360 return rc;
2361 }
2362
2363 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2364 TMR3NotifyResume(pVM, pVCpu);
2365 break;
2366 }
2367
2368 /*
2369 * Guru meditation takes place in the debugger.
2370 */
2371 case EMSTATE_GURU_MEDITATION:
2372 {
2373 TMR3NotifySuspend(pVM, pVCpu);
2374 VMMR3FatalDump(pVM, pVCpu, rc);
2375 emR3Debug(pVM, pVCpu, rc);
2376 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2377 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2378 return rc;
2379 }
2380
2381 /*
2382 * The states we don't expect here.
2383 */
2384 case EMSTATE_NONE:
2385 case EMSTATE_TERMINATING:
2386 default:
2387 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2388 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2389 TMR3NotifySuspend(pVM, pVCpu);
2390 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2391 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2392 return VERR_EM_INTERNAL_ERROR;
2393 }
2394 } /* The Outer Main Loop */
2395 }
2396 else
2397 {
2398 /*
2399 * Fatal error.
2400 */
2401 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2402 TMR3NotifySuspend(pVM, pVCpu);
2403 VMMR3FatalDump(pVM, pVCpu, rc);
2404 emR3Debug(pVM, pVCpu, rc);
2405 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2406 /** @todo change the VM state! */
2407 return rc;
2408 }
2409
2410 /* (won't ever get here). */
2411 AssertFailed();
2412}
2413
2414/**
2415 * Notify EM of a state change (used by FTM)
2416 *
2417 * @param pVM Pointer to the VM.
2418 */
2419VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM)
2420{
2421 PVMCPU pVCpu = VMMGetCpu(pVM);
2422
2423 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2424 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2425 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2426 return VINF_SUCCESS;
2427}
2428
2429/**
2430 * Notify EM of a state change (used by FTM)
2431 *
2432 * @param pVM Pointer to the VM.
2433 */
2434VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM)
2435{
2436 PVMCPU pVCpu = VMMGetCpu(pVM);
2437 EMSTATE enmCurState = pVCpu->em.s.enmState;
2438
2439 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2440 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2441 pVCpu->em.s.enmPrevState = enmCurState;
2442 return VINF_SUCCESS;
2443}
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