VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 45388

Last change on this file since 45388 was 45301, checked in by vboxsync, 12 years ago

IOM: Preparing to use read/write critsect.
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1/* $Id: EM.cpp 45301 2013-04-03 09:51:13Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HmExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/vmm.h>
40#include <VBox/vmm/patm.h>
41#include <VBox/vmm/csam.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iom.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/pgm.h>
47#ifdef VBOX_WITH_REM
48# include <VBox/vmm/rem.h>
49#else
50# include <VBox/vmm/iem.h>
51#endif
52#include <VBox/vmm/tm.h>
53#include <VBox/vmm/mm.h>
54#include <VBox/vmm/ssm.h>
55#include <VBox/vmm/pdmapi.h>
56#include <VBox/vmm/pdmcritsect.h>
57#include <VBox/vmm/pdmqueue.h>
58#include <VBox/vmm/hm.h>
59#include <VBox/vmm/patm.h>
60#ifdef IEM_VERIFICATION_MODE
61# include <VBox/vmm/iem.h>
62#endif
63#include "EMInternal.h"
64#include <VBox/vmm/vm.h>
65#include <VBox/vmm/uvm.h>
66#include <VBox/vmm/cpumdis.h>
67#include <VBox/dis.h>
68#include <VBox/disopcode.h>
69#include <VBox/vmm/dbgf.h>
70#include "VMMTracing.h"
71
72#include <iprt/asm.h>
73#include <iprt/string.h>
74#include <iprt/stream.h>
75#include <iprt/thread.h>
76
77
78/*******************************************************************************
79* Defined Constants And Macros *
80*******************************************************************************/
81#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
82#define EM_NOTIFY_HM
83#endif
84
85
86/*******************************************************************************
87* Internal Functions *
88*******************************************************************************/
89static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
90static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
91#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
92static const char *emR3GetStateName(EMSTATE enmState);
93#endif
94static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
95static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
96static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
97int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
98
99
100/**
101 * Initializes the EM.
102 *
103 * @returns VBox status code.
104 * @param pVM Pointer to the VM.
105 */
106VMMR3_INT_DECL(int) EMR3Init(PVM pVM)
107{
108 LogFlow(("EMR3Init\n"));
109 /*
110 * Assert alignment and sizes.
111 */
112 AssertCompileMemberAlignment(VM, em.s, 32);
113 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
114 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
115
116 /*
117 * Init the structure.
118 */
119 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
120 bool fEnabled;
121 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &fEnabled);
122 pVM->fRecompileUser = RT_SUCCESS(rc) ? !fEnabled : false;
123 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &fEnabled);
124 pVM->fRecompileSupervisor = RT_SUCCESS(rc) ? !fEnabled : false;
125 Log(("EMR3Init: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n", pVM->fRecompileUser, pVM->fRecompileSupervisor));
126
127#ifdef VBOX_WITH_RAW_RING1
128 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR1Enabled", &fEnabled);
129 pVM->fRawRing1Enabled = RT_SUCCESS(rc) ? fEnabled : false;
130 Log(("EMR3Init: fRawRing1Enabled=%RTbool\n", pVM->fRawRing1Enabled));
131#else
132 pVM->fRawRing1Enabled = false; /* disabled by default. */
133#endif
134
135#ifdef VBOX_WITH_REM
136 /*
137 * Initialize the REM critical section.
138 */
139 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
140 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
141 AssertRCReturn(rc, rc);
142#endif
143
144 /*
145 * Saved state.
146 */
147 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
148 NULL, NULL, NULL,
149 NULL, emR3Save, NULL,
150 NULL, emR3Load, NULL);
151 if (RT_FAILURE(rc))
152 return rc;
153
154 for (VMCPUID i = 0; i < pVM->cCpus; i++)
155 {
156 PVMCPU pVCpu = &pVM->aCpus[i];
157
158 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
159
160 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
161 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
162 pVCpu->em.s.fForceRAW = false;
163
164 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
165 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
166 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
167
168 /* Force reset of the time slice. */
169 pVCpu->em.s.u64TimeSliceStart = 0;
170
171# define EM_REG_COUNTER(a, b, c) \
172 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
173 AssertRC(rc);
174
175# define EM_REG_COUNTER_USED(a, b, c) \
176 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
177 AssertRC(rc);
178
179# define EM_REG_PROFILE(a, b, c) \
180 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
181 AssertRC(rc);
182
183# define EM_REG_PROFILE_ADV(a, b, c) \
184 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
185 AssertRC(rc);
186
187 /*
188 * Statistics.
189 */
190#ifdef VBOX_WITH_STATISTICS
191 PEMSTATS pStats;
192 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
193 if (RT_FAILURE(rc))
194 return rc;
195
196 pVCpu->em.s.pStatsR3 = pStats;
197 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
198 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
199
200 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
201 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
202
203 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
204 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
205
206 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
207 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
208 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
261 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
262 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
263 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
264 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatRZSmsw, "/EM/CPU%d/RZ/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatR3Smsw, "/EM/CPU%d/R3/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
280
281 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
282 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
283
284 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
285 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
286 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
315 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
316 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
317 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatRZFailedSmsw, "/EM/CPU%d/RZ/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatR3FailedSmsw, "/EM/CPU%d/R3/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
336
337 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
338 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
339 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
341 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
343 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
344 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
345 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
346 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
347 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
348 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
349 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
350 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
351 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
352 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
353 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
354 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
355 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
356 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
357 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
358 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
359 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
360 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
361 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
362 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
363 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
364 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
365
366 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
367 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
368 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
369 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
370
371 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
372 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
373 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
375 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
376 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
377 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
378 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
379 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 write instructions.");
380 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 write instructions.");
381 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 write instructions.");
382 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 write instructions.");
383 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 write instructions.");
384 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 read instructions.");
385 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 read instructions.");
386 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 read instructions.");
387 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 read instructions.");
388 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 read instructions.");
389 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
390 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
391 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
392 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
393 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
394 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
395 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
396 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
397 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
398
399 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
400 pVCpu->em.s.pCliStatTree = 0;
401
402 /* these should be considered for release statistics. */
403 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
404 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
405 EM_REG_PROFILE(&pVCpu->em.s.StatHmEntry, "/PROF/CPU%d/EM/HmEnter", "Profiling Hardware Accelerated Mode entry overhead.");
406 EM_REG_PROFILE(&pVCpu->em.s.StatHmExec, "/PROF/CPU%d/EM/HmExec", "Profiling Hardware Accelerated Mode execution.");
407 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
408 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
409 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
410 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
411 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
412 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
413
414#endif /* VBOX_WITH_STATISTICS */
415
416 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
417 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
418 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
419 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
420 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
421
422 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
423 }
424
425 return VINF_SUCCESS;
426}
427
428
429/**
430 * Applies relocations to data and code managed by this
431 * component. This function will be called at init and
432 * whenever the VMM need to relocate it self inside the GC.
433 *
434 * @param pVM Pointer to the VM.
435 */
436VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM)
437{
438 LogFlow(("EMR3Relocate\n"));
439 for (VMCPUID i = 0; i < pVM->cCpus; i++)
440 {
441 PVMCPU pVCpu = &pVM->aCpus[i];
442 if (pVCpu->em.s.pStatsR3)
443 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
444 }
445}
446
447
448/**
449 * Reset the EM state for a CPU.
450 *
451 * Called by EMR3Reset and hot plugging.
452 *
453 * @param pVCpu Pointer to the VMCPU.
454 */
455VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
456{
457 pVCpu->em.s.fForceRAW = false;
458
459 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
460 out of the HALTED state here so that enmPrevState doesn't end up as
461 HALTED when EMR3Execute returns. */
462 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
463 {
464 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
465 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
466 }
467}
468
469
470/**
471 * Reset notification.
472 *
473 * @param pVM Pointer to the VM.
474 */
475VMMR3_INT_DECL(void) EMR3Reset(PVM pVM)
476{
477 Log(("EMR3Reset: \n"));
478 for (VMCPUID i = 0; i < pVM->cCpus; i++)
479 EMR3ResetCpu(&pVM->aCpus[i]);
480}
481
482
483/**
484 * Terminates the EM.
485 *
486 * Termination means cleaning up and freeing all resources,
487 * the VM it self is at this point powered off or suspended.
488 *
489 * @returns VBox status code.
490 * @param pVM Pointer to the VM.
491 */
492VMMR3_INT_DECL(int) EMR3Term(PVM pVM)
493{
494 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
495
496#ifdef VBOX_WITH_REM
497 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
498#endif
499 return VINF_SUCCESS;
500}
501
502
503/**
504 * Execute state save operation.
505 *
506 * @returns VBox status code.
507 * @param pVM Pointer to the VM.
508 * @param pSSM SSM operation handle.
509 */
510static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
511{
512 for (VMCPUID i = 0; i < pVM->cCpus; i++)
513 {
514 PVMCPU pVCpu = &pVM->aCpus[i];
515
516 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
517 AssertRCReturn(rc, rc);
518
519 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
520 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
521 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
522 AssertRCReturn(rc, rc);
523
524 /* Save mwait state. */
525 rc = SSMR3PutU32(pSSM, pVCpu->em.s.MWait.fWait);
526 AssertRCReturn(rc, rc);
527 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRAX);
528 AssertRCReturn(rc, rc);
529 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRCX);
530 AssertRCReturn(rc, rc);
531 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRAX);
532 AssertRCReturn(rc, rc);
533 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRCX);
534 AssertRCReturn(rc, rc);
535 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRDX);
536 AssertRCReturn(rc, rc);
537 }
538 return VINF_SUCCESS;
539}
540
541
542/**
543 * Execute state load operation.
544 *
545 * @returns VBox status code.
546 * @param pVM Pointer to the VM.
547 * @param pSSM SSM operation handle.
548 * @param uVersion Data layout version.
549 * @param uPass The data pass.
550 */
551static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
552{
553 /*
554 * Validate version.
555 */
556 if ( uVersion != EM_SAVED_STATE_VERSION
557 && uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
558 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
559 {
560 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
561 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
562 }
563 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
564
565 /*
566 * Load the saved state.
567 */
568 for (VMCPUID i = 0; i < pVM->cCpus; i++)
569 {
570 PVMCPU pVCpu = &pVM->aCpus[i];
571
572 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
573 if (RT_FAILURE(rc))
574 pVCpu->em.s.fForceRAW = false;
575 AssertRCReturn(rc, rc);
576
577 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
578 {
579 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
580 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
581 AssertRCReturn(rc, rc);
582 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
583
584 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
585 }
586 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
587 {
588 /* Load mwait state. */
589 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.MWait.fWait);
590 AssertRCReturn(rc, rc);
591 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRAX);
592 AssertRCReturn(rc, rc);
593 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRCX);
594 AssertRCReturn(rc, rc);
595 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRAX);
596 AssertRCReturn(rc, rc);
597 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRCX);
598 AssertRCReturn(rc, rc);
599 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRDX);
600 AssertRCReturn(rc, rc);
601 }
602
603 Assert(!pVCpu->em.s.pCliStatTree);
604 }
605 return VINF_SUCCESS;
606}
607
608
609/**
610 * Argument packet for emR3SetExecutionPolicy.
611 */
612struct EMR3SETEXECPOLICYARGS
613{
614 EMEXECPOLICY enmPolicy;
615 bool fEnforce;
616};
617
618
619/**
620 * @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
621 */
622static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
623{
624 /*
625 * Only the first CPU changes the variables.
626 */
627 if (pVCpu->idCpu == 0)
628 {
629 struct EMR3SETEXECPOLICYARGS *pArgs = (struct EMR3SETEXECPOLICYARGS *)pvUser;
630 switch (pArgs->enmPolicy)
631 {
632 case EMEXECPOLICY_RECOMPILE_RING0:
633 pVM->fRecompileSupervisor = pArgs->fEnforce;
634 break;
635 case EMEXECPOLICY_RECOMPILE_RING3:
636 pVM->fRecompileUser = pArgs->fEnforce;
637 break;
638 default:
639 AssertFailedReturn(VERR_INVALID_PARAMETER);
640 }
641 Log(("emR3SetExecutionPolicy: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n",
642 pVM->fRecompileUser, pVM->fRecompileSupervisor));
643 }
644
645 /*
646 * Force rescheduling if in RAW, HM or REM.
647 */
648 return pVCpu->em.s.enmState == EMSTATE_RAW
649 || pVCpu->em.s.enmState == EMSTATE_HM
650 || pVCpu->em.s.enmState == EMSTATE_REM
651 ? VINF_EM_RESCHEDULE
652 : VINF_SUCCESS;
653}
654
655
656/**
657 * Changes a the execution scheduling policy.
658 *
659 * This is used to enable or disable raw-mode / hardware-virtualization
660 * execution of user and supervisor code.
661 *
662 * @returns VINF_SUCCESS on success.
663 * @returns VINF_RESCHEDULE if a rescheduling might be required.
664 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
665 *
666 * @param pUVM The user mode VM handle.
667 * @param enmPolicy The scheduling policy to change.
668 * @param fEnforce Whether to enforce the policy or not.
669 */
670VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce)
671{
672 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
673 VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
674 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
675
676 struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
677 return VMMR3EmtRendezvous(pUVM->pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
678}
679
680
681/**
682 * Checks if raw ring-3 execute mode is enabled.
683 *
684 * @returns true if enabled, false if disabled.
685 * @param pUVM The user mode VM handle.
686 */
687VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM)
688{
689 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
690 PVM pVM = pUVM->pVM;
691 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
692 return EMIsRawRing3Enabled(pVM);
693}
694
695
696/**
697 * Checks if raw ring-0 execute mode is enabled.
698 *
699 * @returns true if enabled, false if disabled.
700 * @param pUVM The user mode VM handle.
701 */
702VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM)
703{
704 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
705 PVM pVM = pUVM->pVM;
706 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
707 return EMIsRawRing0Enabled(pVM);
708}
709
710
711/**
712 * Raise a fatal error.
713 *
714 * Safely terminate the VM with full state report and stuff. This function
715 * will naturally never return.
716 *
717 * @param pVCpu Pointer to the VMCPU.
718 * @param rc VBox status code.
719 */
720VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
721{
722 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
723 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
724 AssertReleaseMsgFailed(("longjmp returned!\n"));
725}
726
727
728#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
729/**
730 * Gets the EM state name.
731 *
732 * @returns pointer to read only state name,
733 * @param enmState The state.
734 */
735static const char *emR3GetStateName(EMSTATE enmState)
736{
737 switch (enmState)
738 {
739 case EMSTATE_NONE: return "EMSTATE_NONE";
740 case EMSTATE_RAW: return "EMSTATE_RAW";
741 case EMSTATE_HM: return "EMSTATE_HM";
742 case EMSTATE_REM: return "EMSTATE_REM";
743 case EMSTATE_HALTED: return "EMSTATE_HALTED";
744 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
745 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
746 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
747 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
748 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
749 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
750 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
751 default: return "Unknown!";
752 }
753}
754#endif /* LOG_ENABLED || VBOX_STRICT */
755
756
757/**
758 * Debug loop.
759 *
760 * @returns VBox status code for EM.
761 * @param pVM Pointer to the VM.
762 * @param pVCpu Pointer to the VMCPU.
763 * @param rc Current EM VBox status code.
764 */
765static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
766{
767 for (;;)
768 {
769 Log(("emR3Debug: rc=%Rrc\n", rc));
770 const int rcLast = rc;
771
772 /*
773 * Debug related RC.
774 */
775 switch (rc)
776 {
777 /*
778 * Single step an instruction.
779 */
780 case VINF_EM_DBG_STEP:
781#ifdef VBOX_WITH_RAW_MODE
782 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
783 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
784 || pVCpu->em.s.fForceRAW /* paranoia */)
785 rc = emR3RawStep(pVM, pVCpu);
786 else
787 {
788 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
789 rc = emR3RemStep(pVM, pVCpu);
790 }
791#else
792 AssertLogRelMsgFailed(("%Rrc\n", rc));
793 rc = VERR_EM_INTERNAL_ERROR;
794#endif
795 break;
796
797 /*
798 * Simple events: stepped, breakpoint, stop/assertion.
799 */
800 case VINF_EM_DBG_STEPPED:
801 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
802 break;
803
804 case VINF_EM_DBG_BREAKPOINT:
805 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
806 break;
807
808 case VINF_EM_DBG_STOP:
809 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
810 break;
811
812 case VINF_EM_DBG_HYPER_STEPPED:
813 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
814 break;
815
816 case VINF_EM_DBG_HYPER_BREAKPOINT:
817 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
818 break;
819
820 case VINF_EM_DBG_HYPER_ASSERTION:
821 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
822 RTLogFlush(NULL);
823 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
824 break;
825
826 /*
827 * Guru meditation.
828 */
829 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
830 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
831 break;
832 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
833 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
834 break;
835
836 default: /** @todo don't use default for guru, but make special errors code! */
837 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
838 break;
839 }
840
841 /*
842 * Process the result.
843 */
844 do
845 {
846 switch (rc)
847 {
848 /*
849 * Continue the debugging loop.
850 */
851 case VINF_EM_DBG_STEP:
852 case VINF_EM_DBG_STOP:
853 case VINF_EM_DBG_STEPPED:
854 case VINF_EM_DBG_BREAKPOINT:
855 case VINF_EM_DBG_HYPER_STEPPED:
856 case VINF_EM_DBG_HYPER_BREAKPOINT:
857 case VINF_EM_DBG_HYPER_ASSERTION:
858 break;
859
860 /*
861 * Resuming execution (in some form) has to be done here if we got
862 * a hypervisor debug event.
863 */
864 case VINF_SUCCESS:
865 case VINF_EM_RESUME:
866 case VINF_EM_SUSPEND:
867 case VINF_EM_RESCHEDULE:
868 case VINF_EM_RESCHEDULE_RAW:
869 case VINF_EM_RESCHEDULE_REM:
870 case VINF_EM_HALT:
871 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
872 {
873#ifdef VBOX_WITH_RAW_MODE
874 rc = emR3RawResumeHyper(pVM, pVCpu);
875 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
876 continue;
877#else
878 AssertLogRelMsgFailedReturn(("Not implemented\n", rc), VERR_EM_INTERNAL_ERROR);
879#endif
880 }
881 if (rc == VINF_SUCCESS)
882 rc = VINF_EM_RESCHEDULE;
883 return rc;
884
885 /*
886 * The debugger isn't attached.
887 * We'll simply turn the thing off since that's the easiest thing to do.
888 */
889 case VERR_DBGF_NOT_ATTACHED:
890 switch (rcLast)
891 {
892 case VINF_EM_DBG_HYPER_STEPPED:
893 case VINF_EM_DBG_HYPER_BREAKPOINT:
894 case VINF_EM_DBG_HYPER_ASSERTION:
895 case VERR_TRPM_PANIC:
896 case VERR_TRPM_DONT_PANIC:
897 case VERR_VMM_RING0_ASSERTION:
898 case VERR_VMM_HYPER_CR3_MISMATCH:
899 case VERR_VMM_RING3_CALL_DISABLED:
900 return rcLast;
901 }
902 return VINF_EM_OFF;
903
904 /*
905 * Status codes terminating the VM in one or another sense.
906 */
907 case VINF_EM_TERMINATE:
908 case VINF_EM_OFF:
909 case VINF_EM_RESET:
910 case VINF_EM_NO_MEMORY:
911 case VINF_EM_RAW_STALE_SELECTOR:
912 case VINF_EM_RAW_IRET_TRAP:
913 case VERR_TRPM_PANIC:
914 case VERR_TRPM_DONT_PANIC:
915 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
916 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
917 case VERR_VMM_RING0_ASSERTION:
918 case VERR_VMM_HYPER_CR3_MISMATCH:
919 case VERR_VMM_RING3_CALL_DISABLED:
920 case VERR_INTERNAL_ERROR:
921 case VERR_INTERNAL_ERROR_2:
922 case VERR_INTERNAL_ERROR_3:
923 case VERR_INTERNAL_ERROR_4:
924 case VERR_INTERNAL_ERROR_5:
925 case VERR_IPE_UNEXPECTED_STATUS:
926 case VERR_IPE_UNEXPECTED_INFO_STATUS:
927 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
928 return rc;
929
930 /*
931 * The rest is unexpected, and will keep us here.
932 */
933 default:
934 AssertMsgFailed(("Unexpected rc %Rrc!\n", rc));
935 break;
936 }
937 } while (false);
938 } /* debug for ever */
939}
940
941/**
942 * Steps recompiled code.
943 *
944 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
945 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
946 *
947 * @param pVM Pointer to the VM.
948 * @param pVCpu Pointer to the VMCPU.
949 */
950static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
951{
952 Log3(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
953
954#ifdef VBOX_WITH_REM
955 EMRemLock(pVM);
956
957 /*
958 * Switch to REM, step instruction, switch back.
959 */
960 int rc = REMR3State(pVM, pVCpu);
961 if (RT_SUCCESS(rc))
962 {
963 rc = REMR3Step(pVM, pVCpu);
964 REMR3StateBack(pVM, pVCpu);
965 }
966 EMRemUnlock(pVM);
967
968#else
969 int rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
970#endif
971
972 Log3(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
973 return rc;
974}
975
976
977/**
978 * emR3RemExecute helper that syncs the state back from REM and leave the REM
979 * critical section.
980 *
981 * @returns false - new fInREMState value.
982 * @param pVM Pointer to the VM.
983 * @param pVCpu Pointer to the VMCPU.
984 */
985DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
986{
987#ifdef VBOX_WITH_REM
988 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
989 REMR3StateBack(pVM, pVCpu);
990 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
991
992 EMRemUnlock(pVM);
993#endif
994 return false;
995}
996
997
998/**
999 * Executes recompiled code.
1000 *
1001 * This function contains the recompiler version of the inner
1002 * execution loop (the outer loop being in EMR3ExecuteVM()).
1003 *
1004 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1005 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1006 *
1007 * @param pVM Pointer to the VM.
1008 * @param pVCpu Pointer to the VMCPU.
1009 * @param pfFFDone Where to store an indicator telling whether or not
1010 * FFs were done before returning.
1011 *
1012 */
1013static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1014{
1015#ifdef LOG_ENABLED
1016 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1017 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
1018
1019 if (pCtx->eflags.Bits.u1VM)
1020 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF));
1021 else
1022 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
1023#endif
1024 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
1025
1026#if defined(VBOX_STRICT) && defined(DEBUG_bird)
1027 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1028 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */
1029 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1030#endif
1031
1032 /*
1033 * Spin till we get a forced action which returns anything but VINF_SUCCESS
1034 * or the REM suggests raw-mode execution.
1035 */
1036 *pfFFDone = false;
1037#ifdef VBOX_WITH_REM
1038 bool fInREMState = false;
1039#endif
1040 int rc = VINF_SUCCESS;
1041 for (;;)
1042 {
1043#ifdef VBOX_WITH_REM
1044 /*
1045 * Lock REM and update the state if not already in sync.
1046 *
1047 * Note! Big lock, but you are not supposed to own any lock when
1048 * coming in here.
1049 */
1050 if (!fInREMState)
1051 {
1052 EMRemLock(pVM);
1053 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
1054
1055 /* Flush the recompiler translation blocks if the VCPU has changed,
1056 also force a full CPU state resync. */
1057 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1058 {
1059 REMFlushTBs(pVM);
1060 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1061 }
1062 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1063
1064 rc = REMR3State(pVM, pVCpu);
1065
1066 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
1067 if (RT_FAILURE(rc))
1068 break;
1069 fInREMState = true;
1070
1071 /*
1072 * We might have missed the raising of VMREQ, TIMER and some other
1073 * important FFs while we were busy switching the state. So, check again.
1074 */
1075 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
1076 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
1077 {
1078 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1079 goto l_REMDoForcedActions;
1080 }
1081 }
1082#endif
1083
1084 /*
1085 * Execute REM.
1086 */
1087 if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1088 {
1089 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1090#ifdef VBOX_WITH_REM
1091 rc = REMR3Run(pVM, pVCpu);
1092#else
1093 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
1094#endif
1095 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1096 }
1097 else
1098 {
1099 /* Give up this time slice; virtual time continues */
1100 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1101 RTThreadSleep(5);
1102 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1103 rc = VINF_SUCCESS;
1104 }
1105
1106 /*
1107 * Deal with high priority post execution FFs before doing anything
1108 * else. Sync back the state and leave the lock to be on the safe side.
1109 */
1110 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1111 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1112 {
1113#ifdef VBOX_WITH_REM
1114 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1115#endif
1116 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1117 }
1118
1119 /*
1120 * Process the returned status code.
1121 */
1122 if (rc != VINF_SUCCESS)
1123 {
1124 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1125 break;
1126 if (rc != VINF_REM_INTERRUPED_FF)
1127 {
1128 /*
1129 * Anything which is not known to us means an internal error
1130 * and the termination of the VM!
1131 */
1132 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1133 break;
1134 }
1135 }
1136
1137
1138 /*
1139 * Check and execute forced actions.
1140 *
1141 * Sync back the VM state and leave the lock before calling any of
1142 * these, you never know what's going to happen here.
1143 */
1144#ifdef VBOX_HIGH_RES_TIMERS_HACK
1145 TMTimerPollVoid(pVM, pVCpu);
1146#endif
1147 AssertCompile((VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)) & VMCPU_FF_TIMER);
1148 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1149 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK & ~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE)))
1150 {
1151l_REMDoForcedActions:
1152#ifdef VBOX_WITH_REM
1153 if (fInREMState)
1154 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1155#endif
1156 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1157 rc = emR3ForcedActions(pVM, pVCpu, rc);
1158 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1159 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1160 if ( rc != VINF_SUCCESS
1161 && rc != VINF_EM_RESCHEDULE_REM)
1162 {
1163 *pfFFDone = true;
1164 break;
1165 }
1166 }
1167
1168 } /* The Inner Loop, recompiled execution mode version. */
1169
1170
1171#ifdef VBOX_WITH_REM
1172 /*
1173 * Returning. Sync back the VM state if required.
1174 */
1175 if (fInREMState)
1176 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1177#endif
1178
1179 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1180 return rc;
1181}
1182
1183
1184#ifdef DEBUG
1185
1186int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1187{
1188 EMSTATE enmOldState = pVCpu->em.s.enmState;
1189
1190 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1191
1192 Log(("Single step BEGIN:\n"));
1193 for (uint32_t i = 0; i < cIterations; i++)
1194 {
1195 DBGFR3PrgStep(pVCpu);
1196 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
1197 emR3RemStep(pVM, pVCpu);
1198 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1199 break;
1200 }
1201 Log(("Single step END:\n"));
1202 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1203 pVCpu->em.s.enmState = enmOldState;
1204 return VINF_EM_RESCHEDULE;
1205}
1206
1207#endif /* DEBUG */
1208
1209
1210/**
1211 * Decides whether to execute RAW, HWACC or REM.
1212 *
1213 * @returns new EM state
1214 * @param pVM Pointer to the VM.
1215 * @param pVCpu Pointer to the VMCPU.
1216 * @param pCtx Pointer to the guest CPU context.
1217 */
1218EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1219{
1220#ifdef IEM_VERIFICATION_MODE
1221 return EMSTATE_REM;
1222#else
1223
1224 /*
1225 * When forcing raw-mode execution, things are simple.
1226 */
1227 if (pVCpu->em.s.fForceRAW)
1228 return EMSTATE_RAW;
1229
1230 /*
1231 * We stay in the wait for SIPI state unless explicitly told otherwise.
1232 */
1233 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1234 return EMSTATE_WAIT_SIPI;
1235
1236 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1237 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1238 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1239
1240 X86EFLAGS EFlags = pCtx->eflags;
1241 if (HMIsEnabled(pVM))
1242 {
1243 /*
1244 * Hardware accelerated raw-mode:
1245 *
1246 * Typically only 32-bits protected mode, with paging enabled, code is
1247 * allowed here.
1248 */
1249 if ( EMIsHwVirtExecutionEnabled(pVM)
1250 && HMR3CanExecuteGuest(pVM, pCtx))
1251 return EMSTATE_HM;
1252
1253 /*
1254 * Note! Raw mode and hw accelerated mode are incompatible. The latter
1255 * turns off monitoring features essential for raw mode!
1256 */
1257 return EMSTATE_REM;
1258 }
1259
1260 /*
1261 * Standard raw-mode:
1262 *
1263 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1264 * or 32 bits protected mode ring 0 code
1265 *
1266 * The tests are ordered by the likelihood of being true during normal execution.
1267 */
1268 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1269 {
1270 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1271 return EMSTATE_REM;
1272 }
1273
1274# ifndef VBOX_RAW_V86
1275 if (EFlags.u32 & X86_EFL_VM) {
1276 Log2(("raw mode refused: VM_MASK\n"));
1277 return EMSTATE_REM;
1278 }
1279# endif
1280
1281 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1282 uint32_t u32CR0 = pCtx->cr0;
1283 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1284 {
1285 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1286 return EMSTATE_REM;
1287 }
1288
1289 if (pCtx->cr4 & X86_CR4_PAE)
1290 {
1291 uint32_t u32Dummy, u32Features;
1292
1293 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1294 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1295 return EMSTATE_REM;
1296 }
1297
1298 unsigned uSS = pCtx->ss.Sel;
1299 if ( pCtx->eflags.Bits.u1VM
1300 || (uSS & X86_SEL_RPL) == 3)
1301 {
1302 if (!EMIsRawRing3Enabled(pVM))
1303 return EMSTATE_REM;
1304
1305 if (!(EFlags.u32 & X86_EFL_IF))
1306 {
1307 Log2(("raw mode refused: IF (RawR3)\n"));
1308 return EMSTATE_REM;
1309 }
1310
1311 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1312 {
1313 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1314 return EMSTATE_REM;
1315 }
1316 }
1317 else
1318 {
1319 if (!EMIsRawRing0Enabled(pVM))
1320 return EMSTATE_REM;
1321
1322# ifdef VBOX_WITH_RAW_RING1
1323 /* Only ring 0 and 1 supervisor code. */
1324 if (EMIsRawRing1Enabled(pVM))
1325 {
1326 if ((uSS & X86_SEL_RPL) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
1327 {
1328 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1329 return EMSTATE_REM;
1330 }
1331 }
1332 else
1333# endif
1334 /* Only ring 0 supervisor code. */
1335 if ((uSS & X86_SEL_RPL) != 0)
1336 {
1337 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1338 return EMSTATE_REM;
1339 }
1340
1341 // Let's start with pure 32 bits ring 0 code first
1342 /** @todo What's pure 32-bit mode? flat? */
1343 if ( !(pCtx->ss.Attr.n.u1DefBig)
1344 || !(pCtx->cs.Attr.n.u1DefBig))
1345 {
1346 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1347 return EMSTATE_REM;
1348 }
1349
1350 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1351 if (!(u32CR0 & X86_CR0_WP))
1352 {
1353 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1354 return EMSTATE_REM;
1355 }
1356
1357 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1358 {
1359 Log2(("raw r0 mode forced: patch code\n"));
1360# ifdef VBOX_WITH_SAFE_STR
1361 Assert(pCtx->tr.Sel);
1362# endif
1363 return EMSTATE_RAW;
1364 }
1365
1366# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1367 if (!(EFlags.u32 & X86_EFL_IF))
1368 {
1369 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1370 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1371 return EMSTATE_REM;
1372 }
1373# endif
1374
1375# ifndef VBOX_WITH_RAW_RING1
1376 /** @todo still necessary??? */
1377 if (EFlags.Bits.u2IOPL != 0)
1378 {
1379 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1380 return EMSTATE_REM;
1381 }
1382# endif
1383 }
1384
1385 /*
1386 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1387 */
1388 if (pCtx->cs.fFlags & CPUMSELREG_FLAGS_STALE)
1389 {
1390 Log2(("raw mode refused: stale CS\n"));
1391 return EMSTATE_REM;
1392 }
1393 if (pCtx->ss.fFlags & CPUMSELREG_FLAGS_STALE)
1394 {
1395 Log2(("raw mode refused: stale SS\n"));
1396 return EMSTATE_REM;
1397 }
1398 if (pCtx->ds.fFlags & CPUMSELREG_FLAGS_STALE)
1399 {
1400 Log2(("raw mode refused: stale DS\n"));
1401 return EMSTATE_REM;
1402 }
1403 if (pCtx->es.fFlags & CPUMSELREG_FLAGS_STALE)
1404 {
1405 Log2(("raw mode refused: stale ES\n"));
1406 return EMSTATE_REM;
1407 }
1408 if (pCtx->fs.fFlags & CPUMSELREG_FLAGS_STALE)
1409 {
1410 Log2(("raw mode refused: stale FS\n"));
1411 return EMSTATE_REM;
1412 }
1413 if (pCtx->gs.fFlags & CPUMSELREG_FLAGS_STALE)
1414 {
1415 Log2(("raw mode refused: stale GS\n"));
1416 return EMSTATE_REM;
1417 }
1418
1419# ifdef VBOX_WITH_SAFE_STR
1420 if (pCtx->tr.Sel == 0)
1421 {
1422 Log(("Raw mode refused -> TR=0\n"));
1423 return EMSTATE_REM;
1424 }
1425# endif
1426
1427 /*Assert(PGMPhysIsA20Enabled(pVCpu));*/
1428 return EMSTATE_RAW;
1429#endif /* !IEM_VERIFICATION_MODE */
1430
1431}
1432
1433
1434/**
1435 * Executes all high priority post execution force actions.
1436 *
1437 * @returns rc or a fatal status code.
1438 *
1439 * @param pVM Pointer to the VM.
1440 * @param pVCpu Pointer to the VMCPU.
1441 * @param rc The current rc.
1442 */
1443int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1444{
1445 VBOXVMM_EM_FF_HIGH(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1446
1447 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1448 PDMCritSectBothFF(pVCpu);
1449
1450 /* Update CR3 (Nested Paging case for HM). */
1451 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
1452 {
1453 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
1454 if (RT_FAILURE(rc2))
1455 return rc2;
1456 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
1457 }
1458
1459 /* Update PAE PDPEs. This must be done *after* PGMUpdateCR3() and used only by the Nested Paging case for HM. */
1460 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
1461 {
1462 if (CPUMIsGuestInPAEMode(pVCpu))
1463 {
1464 PX86PDPE pPdpes = HMGetPaePdpes(pVCpu);
1465 AssertPtr(pPdpes);
1466
1467 int rc2 = PGMGstUpdatePaePdpes(pVCpu, pPdpes);
1468 if (RT_FAILURE(rc2))
1469 return rc2;
1470 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
1471 }
1472 else
1473 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1474 }
1475
1476 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1477 CSAMR3DoPendingAction(pVM, pVCpu);
1478
1479 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1480 {
1481 if ( rc > VINF_EM_NO_MEMORY
1482 && rc <= VINF_EM_LAST)
1483 rc = VINF_EM_NO_MEMORY;
1484 }
1485
1486 return rc;
1487}
1488
1489
1490/**
1491 * Executes all pending forced actions.
1492 *
1493 * Forced actions can cause execution delays and execution
1494 * rescheduling. The first we deal with using action priority, so
1495 * that for instance pending timers aren't scheduled and ran until
1496 * right before execution. The rescheduling we deal with using
1497 * return codes. The same goes for VM termination, only in that case
1498 * we exit everything.
1499 *
1500 * @returns VBox status code of equal or greater importance/severity than rc.
1501 * The most important ones are: VINF_EM_RESCHEDULE,
1502 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1503 *
1504 * @param pVM Pointer to the VM.
1505 * @param pVCpu Pointer to the VMCPU.
1506 * @param rc The current rc.
1507 *
1508 */
1509int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1510{
1511 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1512#ifdef VBOX_STRICT
1513 int rcIrq = VINF_SUCCESS;
1514#endif
1515 int rc2;
1516#define UPDATE_RC() \
1517 do { \
1518 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1519 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1520 break; \
1521 if (!rc || rc2 < rc) \
1522 rc = rc2; \
1523 } while (0)
1524 VBOXVMM_EM_FF_ALL(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1525
1526 /*
1527 * Post execution chunk first.
1528 */
1529 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1530 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK))
1531 {
1532 /*
1533 * EMT Rendezvous (must be serviced before termination).
1534 */
1535 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1536 {
1537 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1538 UPDATE_RC();
1539 /** @todo HACK ALERT! The following test is to make sure EM+TM
1540 * thinks the VM is stopped/reset before the next VM state change
1541 * is made. We need a better solution for this, or at least make it
1542 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1543 * VINF_EM_SUSPEND). */
1544 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1545 {
1546 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1547 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1548 return rc;
1549 }
1550 }
1551
1552 /*
1553 * State change request (cleared by vmR3SetStateLocked).
1554 */
1555 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1556 {
1557 VMSTATE enmState = VMR3GetState(pVM);
1558 switch (enmState)
1559 {
1560 case VMSTATE_FATAL_ERROR:
1561 case VMSTATE_FATAL_ERROR_LS:
1562 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1563 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1564 return VINF_EM_SUSPEND;
1565
1566 case VMSTATE_DESTROYING:
1567 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1568 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1569 return VINF_EM_TERMINATE;
1570
1571 default:
1572 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1573 }
1574 }
1575
1576 /*
1577 * Debugger Facility polling.
1578 */
1579 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1580 {
1581 rc2 = DBGFR3VMMForcedAction(pVM);
1582 UPDATE_RC();
1583 }
1584
1585 /*
1586 * Postponed reset request.
1587 */
1588 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1589 {
1590 rc2 = VMR3Reset(pVM->pUVM);
1591 UPDATE_RC();
1592 }
1593
1594 /*
1595 * CSAM page scanning.
1596 */
1597 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1598 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1599 {
1600 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1601
1602 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1603 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1604
1605 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1606 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1607 }
1608
1609 /*
1610 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1611 */
1612 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1613 {
1614 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1615 UPDATE_RC();
1616 if (rc == VINF_EM_NO_MEMORY)
1617 return rc;
1618 }
1619
1620 /* check that we got them all */
1621 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1622 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VMCPU_FF_CSAM_SCAN_PAGE);
1623 }
1624
1625 /*
1626 * Normal priority then.
1627 * (Executed in no particular order.)
1628 */
1629 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1630 {
1631 /*
1632 * PDM Queues are pending.
1633 */
1634 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1635 PDMR3QueueFlushAll(pVM);
1636
1637 /*
1638 * PDM DMA transfers are pending.
1639 */
1640 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1641 PDMR3DmaRun(pVM);
1642
1643 /*
1644 * EMT Rendezvous (make sure they are handled before the requests).
1645 */
1646 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1647 {
1648 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1649 UPDATE_RC();
1650 /** @todo HACK ALERT! The following test is to make sure EM+TM
1651 * thinks the VM is stopped/reset before the next VM state change
1652 * is made. We need a better solution for this, or at least make it
1653 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1654 * VINF_EM_SUSPEND). */
1655 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1656 {
1657 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1658 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1659 return rc;
1660 }
1661 }
1662
1663 /*
1664 * Requests from other threads.
1665 */
1666 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1667 {
1668 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
1669 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1670 {
1671 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1672 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1673 return rc2;
1674 }
1675 UPDATE_RC();
1676 /** @todo HACK ALERT! The following test is to make sure EM+TM
1677 * thinks the VM is stopped/reset before the next VM state change
1678 * is made. We need a better solution for this, or at least make it
1679 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1680 * VINF_EM_SUSPEND). */
1681 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1682 {
1683 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1684 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1685 return rc;
1686 }
1687 }
1688
1689#ifdef VBOX_WITH_REM
1690 /* Replay the handler notification changes. */
1691 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1692 {
1693 /* Try not to cause deadlocks. */
1694 if ( pVM->cCpus == 1
1695 || ( !PGMIsLockOwner(pVM)
1696 && !IOMIsLockWriteOwner(pVM))
1697 )
1698 {
1699 EMRemLock(pVM);
1700 REMR3ReplayHandlerNotifications(pVM);
1701 EMRemUnlock(pVM);
1702 }
1703 }
1704#endif
1705
1706 /* check that we got them all */
1707 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1708 }
1709
1710 /*
1711 * Normal priority then. (per-VCPU)
1712 * (Executed in no particular order.)
1713 */
1714 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1715 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1716 {
1717 /*
1718 * Requests from other threads.
1719 */
1720 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1721 {
1722 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
1723 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1724 {
1725 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1726 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1727 return rc2;
1728 }
1729 UPDATE_RC();
1730 /** @todo HACK ALERT! The following test is to make sure EM+TM
1731 * thinks the VM is stopped/reset before the next VM state change
1732 * is made. We need a better solution for this, or at least make it
1733 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1734 * VINF_EM_SUSPEND). */
1735 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1736 {
1737 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1738 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1739 return rc;
1740 }
1741 }
1742
1743 /* check that we got them all */
1744 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1745 }
1746
1747 /*
1748 * High priority pre execution chunk last.
1749 * (Executed in ascending priority order.)
1750 */
1751 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1752 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1753 {
1754 /*
1755 * Timers before interrupts.
1756 */
1757 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1758 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1759 TMR3TimerQueuesDo(pVM);
1760
1761 /*
1762 * The instruction following an emulated STI should *always* be executed!
1763 *
1764 * Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1765 * the eip is the same as the inhibited instr address. Before we
1766 * are able to execute this instruction in raw mode (iret to
1767 * guest code) an external interrupt might force a world switch
1768 * again. Possibly allowing a guest interrupt to be dispatched
1769 * in the process. This could break the guest. Sounds very
1770 * unlikely, but such timing sensitive problem are not as rare as
1771 * you might think.
1772 */
1773 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1774 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1775 {
1776 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1777 {
1778 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1779 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1780 }
1781 else
1782 Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1783 }
1784
1785 /*
1786 * Interrupts.
1787 */
1788 bool fWakeupPending = false;
1789 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1790 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1791 && (!rc || rc >= VINF_EM_RESCHEDULE_HM)
1792 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1793 && PATMAreInterruptsEnabled(pVM)
1794 && !HMR3IsEventPending(pVCpu))
1795 {
1796 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1797 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1798 {
1799 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1800 /** @todo this really isn't nice, should properly handle this */
1801 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1802#ifdef VBOX_STRICT
1803 rcIrq = rc2;
1804#endif
1805 UPDATE_RC();
1806 /* Reschedule required: We must not miss the wakeup below! */
1807 fWakeupPending = true;
1808 }
1809#ifdef VBOX_WITH_REM
1810 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1811 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1812 {
1813 rc2 = VINF_EM_RESCHEDULE_REM;
1814 UPDATE_RC();
1815 }
1816#endif
1817 }
1818
1819 /*
1820 * Allocate handy pages.
1821 */
1822 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1823 {
1824 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1825 UPDATE_RC();
1826 }
1827
1828 /*
1829 * Debugger Facility request.
1830 */
1831 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1832 {
1833 rc2 = DBGFR3VMMForcedAction(pVM);
1834 UPDATE_RC();
1835 }
1836
1837 /*
1838 * EMT Rendezvous (must be serviced before termination).
1839 */
1840 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1841 && VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1842 {
1843 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1844 UPDATE_RC();
1845 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1846 * stopped/reset before the next VM state change is made. We need a better
1847 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1848 * && rc >= VINF_EM_SUSPEND). */
1849 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1850 {
1851 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1852 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1853 return rc;
1854 }
1855 }
1856
1857 /*
1858 * State change request (cleared by vmR3SetStateLocked).
1859 */
1860 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1861 && VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1862 {
1863 VMSTATE enmState = VMR3GetState(pVM);
1864 switch (enmState)
1865 {
1866 case VMSTATE_FATAL_ERROR:
1867 case VMSTATE_FATAL_ERROR_LS:
1868 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1869 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1870 return VINF_EM_SUSPEND;
1871
1872 case VMSTATE_DESTROYING:
1873 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1874 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1875 return VINF_EM_TERMINATE;
1876
1877 default:
1878 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1879 }
1880 }
1881
1882 /*
1883 * Out of memory? Since most of our fellow high priority actions may cause us
1884 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1885 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1886 * than us since we can terminate without allocating more memory.
1887 */
1888 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1889 {
1890 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1891 UPDATE_RC();
1892 if (rc == VINF_EM_NO_MEMORY)
1893 return rc;
1894 }
1895
1896 /*
1897 * If the virtual sync clock is still stopped, make TM restart it.
1898 */
1899 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1900 TMR3VirtualSyncFF(pVM, pVCpu);
1901
1902#ifdef DEBUG
1903 /*
1904 * Debug, pause the VM.
1905 */
1906 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1907 {
1908 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1909 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1910 return VINF_EM_SUSPEND;
1911 }
1912#endif
1913
1914 /* check that we got them all */
1915 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1916 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT | VMCPU_FF_INHIBIT_INTERRUPTS));
1917 }
1918
1919#undef UPDATE_RC
1920 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1921 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1922 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1923 return rc;
1924}
1925
1926
1927/**
1928 * Check if the preset execution time cap restricts guest execution scheduling.
1929 *
1930 * @returns true if allowed, false otherwise
1931 * @param pVM Pointer to the VM.
1932 * @param pVCpu Pointer to the VMCPU.
1933 *
1934 */
1935VMMR3_INT_DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1936{
1937 uint64_t u64UserTime, u64KernelTime;
1938
1939 if ( pVM->uCpuExecutionCap != 100
1940 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1941 {
1942 uint64_t u64TimeNow = RTTimeMilliTS();
1943 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1944 {
1945 /* New time slice. */
1946 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1947 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1948 pVCpu->em.s.u64TimeSliceExec = 0;
1949 }
1950 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1951
1952 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1953 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1954 return false;
1955 }
1956 return true;
1957}
1958
1959
1960/**
1961 * Execute VM.
1962 *
1963 * This function is the main loop of the VM. The emulation thread
1964 * calls this function when the VM has been successfully constructed
1965 * and we're ready for executing the VM.
1966 *
1967 * Returning from this function means that the VM is turned off or
1968 * suspended (state already saved) and deconstruction is next in line.
1969 *
1970 * All interaction from other thread are done using forced actions
1971 * and signaling of the wait object.
1972 *
1973 * @returns VBox status code, informational status codes may indicate failure.
1974 * @param pVM Pointer to the VM.
1975 * @param pVCpu Pointer to the VMCPU.
1976 */
1977VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1978{
1979 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1980 pVM,
1981 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1982 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1983 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1984 pVCpu->em.s.fForceRAW));
1985 VM_ASSERT_EMT(pVM);
1986 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1987 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1988 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
1989 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
1990
1991 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
1992 if (rc == 0)
1993 {
1994 /*
1995 * Start the virtual time.
1996 */
1997 TMR3NotifyResume(pVM, pVCpu);
1998
1999 /*
2000 * The Outer Main Loop.
2001 */
2002 bool fFFDone = false;
2003
2004 /* Reschedule right away to start in the right state. */
2005 rc = VINF_SUCCESS;
2006
2007 /* If resuming after a pause or a state load, restore the previous
2008 state or else we'll start executing code. Else, just reschedule. */
2009 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
2010 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2011 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
2012 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2013 else
2014 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2015
2016 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2017 for (;;)
2018 {
2019 /*
2020 * Before we can schedule anything (we're here because
2021 * scheduling is required) we must service any pending
2022 * forced actions to avoid any pending action causing
2023 * immediate rescheduling upon entering an inner loop
2024 *
2025 * Do forced actions.
2026 */
2027 if ( !fFFDone
2028 && rc != VINF_EM_TERMINATE
2029 && rc != VINF_EM_OFF
2030 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
2031 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
2032 {
2033 rc = emR3ForcedActions(pVM, pVCpu, rc);
2034 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
2035 if ( ( rc == VINF_EM_RESCHEDULE_REM
2036 || rc == VINF_EM_RESCHEDULE_HM)
2037 && pVCpu->em.s.fForceRAW)
2038 rc = VINF_EM_RESCHEDULE_RAW;
2039 }
2040 else if (fFFDone)
2041 fFFDone = false;
2042
2043 /*
2044 * Now what to do?
2045 */
2046 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
2047 EMSTATE const enmOldState = pVCpu->em.s.enmState;
2048 switch (rc)
2049 {
2050 /*
2051 * Keep doing what we're currently doing.
2052 */
2053 case VINF_SUCCESS:
2054 break;
2055
2056 /*
2057 * Reschedule - to raw-mode execution.
2058 */
2059 case VINF_EM_RESCHEDULE_RAW:
2060 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", enmOldState, EMSTATE_RAW));
2061 pVCpu->em.s.enmState = EMSTATE_RAW;
2062 break;
2063
2064 /*
2065 * Reschedule - to hardware accelerated raw-mode execution.
2066 */
2067 case VINF_EM_RESCHEDULE_HM:
2068 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HM: %d -> %d (EMSTATE_HM)\n", enmOldState, EMSTATE_HM));
2069 Assert(!pVCpu->em.s.fForceRAW);
2070 pVCpu->em.s.enmState = EMSTATE_HM;
2071 break;
2072
2073 /*
2074 * Reschedule - to recompiled execution.
2075 */
2076 case VINF_EM_RESCHEDULE_REM:
2077 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
2078 pVCpu->em.s.enmState = EMSTATE_REM;
2079 break;
2080
2081 /*
2082 * Resume.
2083 */
2084 case VINF_EM_RESUME:
2085 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", enmOldState));
2086 /* Don't reschedule in the halted or wait for SIPI case. */
2087 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2088 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
2089 {
2090 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2091 break;
2092 }
2093 /* fall through and get scheduled. */
2094
2095 /*
2096 * Reschedule.
2097 */
2098 case VINF_EM_RESCHEDULE:
2099 {
2100 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2101 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2102 pVCpu->em.s.enmState = enmState;
2103 break;
2104 }
2105
2106 /*
2107 * Halted.
2108 */
2109 case VINF_EM_HALT:
2110 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", enmOldState, EMSTATE_HALTED));
2111 pVCpu->em.s.enmState = EMSTATE_HALTED;
2112 break;
2113
2114 /*
2115 * Switch to the wait for SIPI state (application processor only)
2116 */
2117 case VINF_EM_WAIT_SIPI:
2118 Assert(pVCpu->idCpu != 0);
2119 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", enmOldState, EMSTATE_WAIT_SIPI));
2120 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2121 break;
2122
2123
2124 /*
2125 * Suspend.
2126 */
2127 case VINF_EM_SUSPEND:
2128 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2129 Assert(enmOldState != EMSTATE_SUSPENDED);
2130 pVCpu->em.s.enmPrevState = enmOldState;
2131 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2132 break;
2133
2134 /*
2135 * Reset.
2136 * We might end up doing a double reset for now, we'll have to clean up the mess later.
2137 */
2138 case VINF_EM_RESET:
2139 {
2140 if (pVCpu->idCpu == 0)
2141 {
2142 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2143 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2144 pVCpu->em.s.enmState = enmState;
2145 }
2146 else
2147 {
2148 /* All other VCPUs go into the wait for SIPI state. */
2149 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2150 }
2151 break;
2152 }
2153
2154 /*
2155 * Power Off.
2156 */
2157 case VINF_EM_OFF:
2158 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2159 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2160 TMR3NotifySuspend(pVM, pVCpu);
2161 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2162 return rc;
2163
2164 /*
2165 * Terminate the VM.
2166 */
2167 case VINF_EM_TERMINATE:
2168 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2169 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2170 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
2171 TMR3NotifySuspend(pVM, pVCpu);
2172 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2173 return rc;
2174
2175
2176 /*
2177 * Out of memory, suspend the VM and stuff.
2178 */
2179 case VINF_EM_NO_MEMORY:
2180 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2181 Assert(enmOldState != EMSTATE_SUSPENDED);
2182 pVCpu->em.s.enmPrevState = enmOldState;
2183 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2184 TMR3NotifySuspend(pVM, pVCpu);
2185 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2186
2187 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2188 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2189 if (rc != VINF_EM_SUSPEND)
2190 {
2191 if (RT_SUCCESS_NP(rc))
2192 {
2193 AssertLogRelMsgFailed(("%Rrc\n", rc));
2194 rc = VERR_EM_INTERNAL_ERROR;
2195 }
2196 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2197 }
2198 return rc;
2199
2200 /*
2201 * Guest debug events.
2202 */
2203 case VINF_EM_DBG_STEPPED:
2204 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
2205 case VINF_EM_DBG_STOP:
2206 case VINF_EM_DBG_BREAKPOINT:
2207 case VINF_EM_DBG_STEP:
2208 if (enmOldState == EMSTATE_RAW)
2209 {
2210 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_RAW));
2211 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2212 }
2213 else
2214 {
2215 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_REM));
2216 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2217 }
2218 break;
2219
2220 /*
2221 * Hypervisor debug events.
2222 */
2223 case VINF_EM_DBG_HYPER_STEPPED:
2224 case VINF_EM_DBG_HYPER_BREAKPOINT:
2225 case VINF_EM_DBG_HYPER_ASSERTION:
2226 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_HYPER));
2227 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2228 break;
2229
2230 /*
2231 * Guru mediations.
2232 */
2233 case VERR_VMM_RING0_ASSERTION:
2234 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2235 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2236 break;
2237
2238 /*
2239 * Any error code showing up here other than the ones we
2240 * know and process above are considered to be FATAL.
2241 *
2242 * Unknown warnings and informational status codes are also
2243 * included in this.
2244 */
2245 default:
2246 if (RT_SUCCESS_NP(rc))
2247 {
2248 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2249 rc = VERR_EM_INTERNAL_ERROR;
2250 }
2251 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2252 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2253 break;
2254 }
2255
2256 /*
2257 * Act on state transition.
2258 */
2259 EMSTATE const enmNewState = pVCpu->em.s.enmState;
2260 if (enmOldState != enmNewState)
2261 {
2262 VBOXVMM_EM_STATE_CHANGED(pVCpu, enmOldState, enmNewState, rc);
2263
2264 /* Clear MWait flags. */
2265 if ( enmOldState == EMSTATE_HALTED
2266 && (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2267 && ( enmNewState == EMSTATE_RAW
2268 || enmNewState == EMSTATE_HM
2269 || enmNewState == EMSTATE_REM
2270 || enmNewState == EMSTATE_DEBUG_GUEST_RAW
2271 || enmNewState == EMSTATE_DEBUG_GUEST_HM
2272 || enmNewState == EMSTATE_DEBUG_GUEST_REM) )
2273 {
2274 LogFlow(("EMR3ExecuteVM: Clearing MWAIT\n"));
2275 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2276 }
2277 }
2278 else
2279 VBOXVMM_EM_STATE_UNCHANGED(pVCpu, enmNewState, rc);
2280
2281 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2282 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2283
2284 /*
2285 * Act on the new state.
2286 */
2287 switch (enmNewState)
2288 {
2289 /*
2290 * Execute raw.
2291 */
2292 case EMSTATE_RAW:
2293#ifndef IEM_VERIFICATION_MODE /* remove later */
2294# ifdef VBOX_WITH_RAW_MODE
2295 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2296# else
2297 AssertLogRelMsgFailed(("%Rrc\n", rc));
2298 rc = VERR_EM_INTERNAL_ERROR;
2299# endif
2300 break;
2301#endif
2302
2303 /*
2304 * Execute hardware accelerated raw.
2305 */
2306 case EMSTATE_HM:
2307#ifndef IEM_VERIFICATION_MODE /* remove later */
2308 rc = emR3HmExecute(pVM, pVCpu, &fFFDone);
2309 break;
2310#endif
2311
2312 /*
2313 * Execute recompiled.
2314 */
2315 case EMSTATE_REM:
2316#ifdef IEM_VERIFICATION_MODE
2317# if 1
2318 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); fFFDone = false;
2319# else
2320 rc = VBOXSTRICTRC_TODO(REMR3EmulateInstruction(pVM, pVCpu)); fFFDone = false;
2321 if (rc == VINF_EM_RESCHEDULE)
2322 rc = VINF_SUCCESS;
2323# endif
2324#else
2325 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2326#endif
2327 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2328 break;
2329
2330 /*
2331 * Application processor execution halted until SIPI.
2332 */
2333 case EMSTATE_WAIT_SIPI:
2334 /* no break */
2335 /*
2336 * hlt - execution halted until interrupt.
2337 */
2338 case EMSTATE_HALTED:
2339 {
2340 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2341 /* MWAIT has a special extension where it's woken up when
2342 an interrupt is pending even when IF=0. */
2343 if ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2344 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2345 {
2346 rc = VMR3WaitHalted(pVM, pVCpu, false /*fIgnoreInterrupts*/);
2347 if ( rc == VINF_SUCCESS
2348 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2349 {
2350 Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
2351 rc = VINF_EM_RESCHEDULE;
2352 }
2353 }
2354 else
2355 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2356
2357 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2358 break;
2359 }
2360
2361 /*
2362 * Suspended - return to VM.cpp.
2363 */
2364 case EMSTATE_SUSPENDED:
2365 TMR3NotifySuspend(pVM, pVCpu);
2366 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2367 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2368 return VINF_EM_SUSPEND;
2369
2370 /*
2371 * Debugging in the guest.
2372 */
2373 case EMSTATE_DEBUG_GUEST_REM:
2374 case EMSTATE_DEBUG_GUEST_RAW:
2375 TMR3NotifySuspend(pVM, pVCpu);
2376 rc = emR3Debug(pVM, pVCpu, rc);
2377 TMR3NotifyResume(pVM, pVCpu);
2378 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2379 break;
2380
2381 /*
2382 * Debugging in the hypervisor.
2383 */
2384 case EMSTATE_DEBUG_HYPER:
2385 {
2386 TMR3NotifySuspend(pVM, pVCpu);
2387 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2388
2389 rc = emR3Debug(pVM, pVCpu, rc);
2390 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2391 if (rc != VINF_SUCCESS)
2392 {
2393 /* switch to guru meditation mode */
2394 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2395 VMMR3FatalDump(pVM, pVCpu, rc);
2396 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2397 return rc;
2398 }
2399
2400 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2401 TMR3NotifyResume(pVM, pVCpu);
2402 break;
2403 }
2404
2405 /*
2406 * Guru meditation takes place in the debugger.
2407 */
2408 case EMSTATE_GURU_MEDITATION:
2409 {
2410 TMR3NotifySuspend(pVM, pVCpu);
2411 VMMR3FatalDump(pVM, pVCpu, rc);
2412 emR3Debug(pVM, pVCpu, rc);
2413 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2414 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2415 return rc;
2416 }
2417
2418 /*
2419 * The states we don't expect here.
2420 */
2421 case EMSTATE_NONE:
2422 case EMSTATE_TERMINATING:
2423 default:
2424 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2425 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2426 TMR3NotifySuspend(pVM, pVCpu);
2427 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2428 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2429 return VERR_EM_INTERNAL_ERROR;
2430 }
2431 } /* The Outer Main Loop */
2432 }
2433 else
2434 {
2435 /*
2436 * Fatal error.
2437 */
2438 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2439 TMR3NotifySuspend(pVM, pVCpu);
2440 VMMR3FatalDump(pVM, pVCpu, rc);
2441 emR3Debug(pVM, pVCpu, rc);
2442 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2443 /** @todo change the VM state! */
2444 return rc;
2445 }
2446
2447 /* (won't ever get here). */
2448 AssertFailed();
2449}
2450
2451/**
2452 * Notify EM of a state change (used by FTM)
2453 *
2454 * @param pVM Pointer to the VM.
2455 */
2456VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM)
2457{
2458 PVMCPU pVCpu = VMMGetCpu(pVM);
2459
2460 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2461 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2462 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2463 return VINF_SUCCESS;
2464}
2465
2466/**
2467 * Notify EM of a state change (used by FTM)
2468 *
2469 * @param pVM Pointer to the VM.
2470 */
2471VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM)
2472{
2473 PVMCPU pVCpu = VMMGetCpu(pVM);
2474 EMSTATE enmCurState = pVCpu->em.s.enmState;
2475
2476 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2477 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2478 pVCpu->em.s.enmPrevState = enmCurState;
2479 return VINF_SUCCESS;
2480}
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