VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 45536

Last change on this file since 45536 was 45533, checked in by vboxsync, 12 years ago

#ifdef the raw-mode force flags to find more code to #ifdef out.

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1/* $Id: EM.cpp 45533 2013-04-13 16:13:22Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HmExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/vmm.h>
40#include <VBox/vmm/patm.h>
41#include <VBox/vmm/csam.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iom.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/pgm.h>
47#ifdef VBOX_WITH_REM
48# include <VBox/vmm/rem.h>
49#else
50# include <VBox/vmm/iem.h>
51#endif
52#include <VBox/vmm/tm.h>
53#include <VBox/vmm/mm.h>
54#include <VBox/vmm/ssm.h>
55#include <VBox/vmm/pdmapi.h>
56#include <VBox/vmm/pdmcritsect.h>
57#include <VBox/vmm/pdmqueue.h>
58#include <VBox/vmm/hm.h>
59#include <VBox/vmm/patm.h>
60#ifdef IEM_VERIFICATION_MODE
61# include <VBox/vmm/iem.h>
62#endif
63#include "EMInternal.h"
64#include <VBox/vmm/vm.h>
65#include <VBox/vmm/uvm.h>
66#include <VBox/vmm/cpumdis.h>
67#include <VBox/dis.h>
68#include <VBox/disopcode.h>
69#include <VBox/vmm/dbgf.h>
70#include "VMMTracing.h"
71
72#include <iprt/asm.h>
73#include <iprt/string.h>
74#include <iprt/stream.h>
75#include <iprt/thread.h>
76
77
78/*******************************************************************************
79* Defined Constants And Macros *
80*******************************************************************************/
81#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
82#define EM_NOTIFY_HM
83#endif
84
85
86/*******************************************************************************
87* Internal Functions *
88*******************************************************************************/
89static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
90static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
91#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
92static const char *emR3GetStateName(EMSTATE enmState);
93#endif
94static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
95static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
96static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
97int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
98
99
100/**
101 * Initializes the EM.
102 *
103 * @returns VBox status code.
104 * @param pVM Pointer to the VM.
105 */
106VMMR3_INT_DECL(int) EMR3Init(PVM pVM)
107{
108 LogFlow(("EMR3Init\n"));
109 /*
110 * Assert alignment and sizes.
111 */
112 AssertCompileMemberAlignment(VM, em.s, 32);
113 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
114 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
115
116 /*
117 * Init the structure.
118 */
119 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
120 bool fEnabled;
121 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &fEnabled);
122 pVM->fRecompileUser = RT_SUCCESS(rc) ? !fEnabled : false;
123 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &fEnabled);
124 pVM->fRecompileSupervisor = RT_SUCCESS(rc) ? !fEnabled : false;
125 Log(("EMR3Init: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n", pVM->fRecompileUser, pVM->fRecompileSupervisor));
126
127#ifdef VBOX_WITH_RAW_RING1
128 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR1Enabled", &fEnabled);
129 pVM->fRawRing1Enabled = RT_SUCCESS(rc) ? fEnabled : false;
130 Log(("EMR3Init: fRawRing1Enabled=%RTbool\n", pVM->fRawRing1Enabled));
131#else
132 pVM->fRawRing1Enabled = false; /* disabled by default. */
133#endif
134
135#ifdef VBOX_WITH_REM
136 /*
137 * Initialize the REM critical section.
138 */
139 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
140 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
141 AssertRCReturn(rc, rc);
142#endif
143
144 /*
145 * Saved state.
146 */
147 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
148 NULL, NULL, NULL,
149 NULL, emR3Save, NULL,
150 NULL, emR3Load, NULL);
151 if (RT_FAILURE(rc))
152 return rc;
153
154 for (VMCPUID i = 0; i < pVM->cCpus; i++)
155 {
156 PVMCPU pVCpu = &pVM->aCpus[i];
157
158 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
159
160 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
161 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
162 pVCpu->em.s.fForceRAW = false;
163
164 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
165#ifdef VBOX_WITH_RAW_MODE
166 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
167 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
168#endif
169
170 /* Force reset of the time slice. */
171 pVCpu->em.s.u64TimeSliceStart = 0;
172
173# define EM_REG_COUNTER(a, b, c) \
174 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
175 AssertRC(rc);
176
177# define EM_REG_COUNTER_USED(a, b, c) \
178 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
179 AssertRC(rc);
180
181# define EM_REG_PROFILE(a, b, c) \
182 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
183 AssertRC(rc);
184
185# define EM_REG_PROFILE_ADV(a, b, c) \
186 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
187 AssertRC(rc);
188
189 /*
190 * Statistics.
191 */
192#ifdef VBOX_WITH_STATISTICS
193 PEMSTATS pStats;
194 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
195 if (RT_FAILURE(rc))
196 return rc;
197
198 pVCpu->em.s.pStatsR3 = pStats;
199 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
200 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
201
202 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
203 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
204
205 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
206 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
207
208 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
209 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
210 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
211 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
261 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
262 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
263 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
264 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatRZSmsw, "/EM/CPU%d/RZ/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatR3Smsw, "/EM/CPU%d/R3/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
282
283 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
284 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
285
286 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
287 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
288 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
289 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
315 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
316 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
317 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatRZFailedSmsw, "/EM/CPU%d/RZ/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatR3FailedSmsw, "/EM/CPU%d/R3/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
338
339 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
340 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
341 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
342 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
343 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
344 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
345 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
346 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
347 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
348 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
349 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
350 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
351 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
352 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
353 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
354 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
355 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
356 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
357 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
358 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
359 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
360 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
361 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
362 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
363 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
364 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
365 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
366 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
367
368 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
369 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
370 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
371 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
372
373 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
374 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
375 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
376 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
377 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
378 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
379 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
380 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
381 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 write instructions.");
382 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 write instructions.");
383 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 write instructions.");
384 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 write instructions.");
385 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 write instructions.");
386 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 read instructions.");
387 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 read instructions.");
388 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 read instructions.");
389 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 read instructions.");
390 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 read instructions.");
391 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
392 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
393 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
394 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
395 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
396 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
397 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
398 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
399 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
400
401 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
402 pVCpu->em.s.pCliStatTree = 0;
403
404 /* these should be considered for release statistics. */
405 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
406 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
407 EM_REG_PROFILE(&pVCpu->em.s.StatHmEntry, "/PROF/CPU%d/EM/HmEnter", "Profiling Hardware Accelerated Mode entry overhead.");
408 EM_REG_PROFILE(&pVCpu->em.s.StatHmExec, "/PROF/CPU%d/EM/HmExec", "Profiling Hardware Accelerated Mode execution.");
409 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
410 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
411 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
412 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
413 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
414 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
415
416#endif /* VBOX_WITH_STATISTICS */
417
418 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
419 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
420 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
421 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
422 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
423
424 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
425 }
426
427 return VINF_SUCCESS;
428}
429
430
431/**
432 * Applies relocations to data and code managed by this
433 * component. This function will be called at init and
434 * whenever the VMM need to relocate it self inside the GC.
435 *
436 * @param pVM Pointer to the VM.
437 */
438VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM)
439{
440 LogFlow(("EMR3Relocate\n"));
441 for (VMCPUID i = 0; i < pVM->cCpus; i++)
442 {
443 PVMCPU pVCpu = &pVM->aCpus[i];
444 if (pVCpu->em.s.pStatsR3)
445 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
446 }
447}
448
449
450/**
451 * Reset the EM state for a CPU.
452 *
453 * Called by EMR3Reset and hot plugging.
454 *
455 * @param pVCpu Pointer to the VMCPU.
456 */
457VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
458{
459 pVCpu->em.s.fForceRAW = false;
460
461 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
462 out of the HALTED state here so that enmPrevState doesn't end up as
463 HALTED when EMR3Execute returns. */
464 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
465 {
466 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
467 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
468 }
469}
470
471
472/**
473 * Reset notification.
474 *
475 * @param pVM Pointer to the VM.
476 */
477VMMR3_INT_DECL(void) EMR3Reset(PVM pVM)
478{
479 Log(("EMR3Reset: \n"));
480 for (VMCPUID i = 0; i < pVM->cCpus; i++)
481 EMR3ResetCpu(&pVM->aCpus[i]);
482}
483
484
485/**
486 * Terminates the EM.
487 *
488 * Termination means cleaning up and freeing all resources,
489 * the VM it self is at this point powered off or suspended.
490 *
491 * @returns VBox status code.
492 * @param pVM Pointer to the VM.
493 */
494VMMR3_INT_DECL(int) EMR3Term(PVM pVM)
495{
496 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
497
498#ifdef VBOX_WITH_REM
499 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
500#endif
501 return VINF_SUCCESS;
502}
503
504
505/**
506 * Execute state save operation.
507 *
508 * @returns VBox status code.
509 * @param pVM Pointer to the VM.
510 * @param pSSM SSM operation handle.
511 */
512static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
513{
514 for (VMCPUID i = 0; i < pVM->cCpus; i++)
515 {
516 PVMCPU pVCpu = &pVM->aCpus[i];
517
518 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
519 AssertRCReturn(rc, rc);
520
521 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
522 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
523 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
524 AssertRCReturn(rc, rc);
525
526 /* Save mwait state. */
527 rc = SSMR3PutU32(pSSM, pVCpu->em.s.MWait.fWait);
528 AssertRCReturn(rc, rc);
529 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRAX);
530 AssertRCReturn(rc, rc);
531 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRCX);
532 AssertRCReturn(rc, rc);
533 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRAX);
534 AssertRCReturn(rc, rc);
535 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRCX);
536 AssertRCReturn(rc, rc);
537 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRDX);
538 AssertRCReturn(rc, rc);
539 }
540 return VINF_SUCCESS;
541}
542
543
544/**
545 * Execute state load operation.
546 *
547 * @returns VBox status code.
548 * @param pVM Pointer to the VM.
549 * @param pSSM SSM operation handle.
550 * @param uVersion Data layout version.
551 * @param uPass The data pass.
552 */
553static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
554{
555 /*
556 * Validate version.
557 */
558 if ( uVersion != EM_SAVED_STATE_VERSION
559 && uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
560 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
561 {
562 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
563 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
564 }
565 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
566
567 /*
568 * Load the saved state.
569 */
570 for (VMCPUID i = 0; i < pVM->cCpus; i++)
571 {
572 PVMCPU pVCpu = &pVM->aCpus[i];
573
574 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
575 if (RT_FAILURE(rc))
576 pVCpu->em.s.fForceRAW = false;
577 AssertRCReturn(rc, rc);
578
579 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
580 {
581 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
582 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
583 AssertRCReturn(rc, rc);
584 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
585
586 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
587 }
588 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
589 {
590 /* Load mwait state. */
591 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.MWait.fWait);
592 AssertRCReturn(rc, rc);
593 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRAX);
594 AssertRCReturn(rc, rc);
595 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRCX);
596 AssertRCReturn(rc, rc);
597 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRAX);
598 AssertRCReturn(rc, rc);
599 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRCX);
600 AssertRCReturn(rc, rc);
601 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRDX);
602 AssertRCReturn(rc, rc);
603 }
604
605 Assert(!pVCpu->em.s.pCliStatTree);
606 }
607 return VINF_SUCCESS;
608}
609
610
611/**
612 * Argument packet for emR3SetExecutionPolicy.
613 */
614struct EMR3SETEXECPOLICYARGS
615{
616 EMEXECPOLICY enmPolicy;
617 bool fEnforce;
618};
619
620
621/**
622 * @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
623 */
624static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
625{
626 /*
627 * Only the first CPU changes the variables.
628 */
629 if (pVCpu->idCpu == 0)
630 {
631 struct EMR3SETEXECPOLICYARGS *pArgs = (struct EMR3SETEXECPOLICYARGS *)pvUser;
632 switch (pArgs->enmPolicy)
633 {
634 case EMEXECPOLICY_RECOMPILE_RING0:
635 pVM->fRecompileSupervisor = pArgs->fEnforce;
636 break;
637 case EMEXECPOLICY_RECOMPILE_RING3:
638 pVM->fRecompileUser = pArgs->fEnforce;
639 break;
640 default:
641 AssertFailedReturn(VERR_INVALID_PARAMETER);
642 }
643 Log(("emR3SetExecutionPolicy: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n",
644 pVM->fRecompileUser, pVM->fRecompileSupervisor));
645 }
646
647 /*
648 * Force rescheduling if in RAW, HM or REM.
649 */
650 return pVCpu->em.s.enmState == EMSTATE_RAW
651 || pVCpu->em.s.enmState == EMSTATE_HM
652 || pVCpu->em.s.enmState == EMSTATE_REM
653 ? VINF_EM_RESCHEDULE
654 : VINF_SUCCESS;
655}
656
657
658/**
659 * Changes a the execution scheduling policy.
660 *
661 * This is used to enable or disable raw-mode / hardware-virtualization
662 * execution of user and supervisor code.
663 *
664 * @returns VINF_SUCCESS on success.
665 * @returns VINF_RESCHEDULE if a rescheduling might be required.
666 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
667 *
668 * @param pUVM The user mode VM handle.
669 * @param enmPolicy The scheduling policy to change.
670 * @param fEnforce Whether to enforce the policy or not.
671 */
672VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce)
673{
674 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
675 VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
676 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
677
678 struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
679 return VMMR3EmtRendezvous(pUVM->pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
680}
681
682
683/**
684 * Checks if raw ring-3 execute mode is enabled.
685 *
686 * @returns true if enabled, false if disabled.
687 * @param pUVM The user mode VM handle.
688 */
689VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM)
690{
691 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
692 PVM pVM = pUVM->pVM;
693 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
694 return EMIsRawRing3Enabled(pVM);
695}
696
697
698/**
699 * Checks if raw ring-0 execute mode is enabled.
700 *
701 * @returns true if enabled, false if disabled.
702 * @param pUVM The user mode VM handle.
703 */
704VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM)
705{
706 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
707 PVM pVM = pUVM->pVM;
708 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
709 return EMIsRawRing0Enabled(pVM);
710}
711
712
713/**
714 * Raise a fatal error.
715 *
716 * Safely terminate the VM with full state report and stuff. This function
717 * will naturally never return.
718 *
719 * @param pVCpu Pointer to the VMCPU.
720 * @param rc VBox status code.
721 */
722VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
723{
724 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
725 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
726 AssertReleaseMsgFailed(("longjmp returned!\n"));
727}
728
729
730#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
731/**
732 * Gets the EM state name.
733 *
734 * @returns pointer to read only state name,
735 * @param enmState The state.
736 */
737static const char *emR3GetStateName(EMSTATE enmState)
738{
739 switch (enmState)
740 {
741 case EMSTATE_NONE: return "EMSTATE_NONE";
742 case EMSTATE_RAW: return "EMSTATE_RAW";
743 case EMSTATE_HM: return "EMSTATE_HM";
744 case EMSTATE_REM: return "EMSTATE_REM";
745 case EMSTATE_HALTED: return "EMSTATE_HALTED";
746 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
747 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
748 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
749 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
750 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
751 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
752 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
753 default: return "Unknown!";
754 }
755}
756#endif /* LOG_ENABLED || VBOX_STRICT */
757
758
759/**
760 * Debug loop.
761 *
762 * @returns VBox status code for EM.
763 * @param pVM Pointer to the VM.
764 * @param pVCpu Pointer to the VMCPU.
765 * @param rc Current EM VBox status code.
766 */
767static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
768{
769 for (;;)
770 {
771 Log(("emR3Debug: rc=%Rrc\n", rc));
772 const int rcLast = rc;
773
774 /*
775 * Debug related RC.
776 */
777 switch (rc)
778 {
779 /*
780 * Single step an instruction.
781 */
782 case VINF_EM_DBG_STEP:
783#ifdef VBOX_WITH_RAW_MODE
784 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
785 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
786 || pVCpu->em.s.fForceRAW /* paranoia */)
787 rc = emR3RawStep(pVM, pVCpu);
788 else
789 {
790 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
791 rc = emR3RemStep(pVM, pVCpu);
792 }
793#else
794 AssertLogRelMsgFailed(("%Rrc\n", rc));
795 rc = VERR_EM_INTERNAL_ERROR;
796#endif
797 break;
798
799 /*
800 * Simple events: stepped, breakpoint, stop/assertion.
801 */
802 case VINF_EM_DBG_STEPPED:
803 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
804 break;
805
806 case VINF_EM_DBG_BREAKPOINT:
807 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
808 break;
809
810 case VINF_EM_DBG_STOP:
811 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
812 break;
813
814 case VINF_EM_DBG_HYPER_STEPPED:
815 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
816 break;
817
818 case VINF_EM_DBG_HYPER_BREAKPOINT:
819 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
820 break;
821
822 case VINF_EM_DBG_HYPER_ASSERTION:
823 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
824 RTLogFlush(NULL);
825 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
826 break;
827
828 /*
829 * Guru meditation.
830 */
831 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
832 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
833 break;
834 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
835 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
836 break;
837
838 default: /** @todo don't use default for guru, but make special errors code! */
839 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
840 break;
841 }
842
843 /*
844 * Process the result.
845 */
846 do
847 {
848 switch (rc)
849 {
850 /*
851 * Continue the debugging loop.
852 */
853 case VINF_EM_DBG_STEP:
854 case VINF_EM_DBG_STOP:
855 case VINF_EM_DBG_STEPPED:
856 case VINF_EM_DBG_BREAKPOINT:
857 case VINF_EM_DBG_HYPER_STEPPED:
858 case VINF_EM_DBG_HYPER_BREAKPOINT:
859 case VINF_EM_DBG_HYPER_ASSERTION:
860 break;
861
862 /*
863 * Resuming execution (in some form) has to be done here if we got
864 * a hypervisor debug event.
865 */
866 case VINF_SUCCESS:
867 case VINF_EM_RESUME:
868 case VINF_EM_SUSPEND:
869 case VINF_EM_RESCHEDULE:
870 case VINF_EM_RESCHEDULE_RAW:
871 case VINF_EM_RESCHEDULE_REM:
872 case VINF_EM_HALT:
873 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
874 {
875#ifdef VBOX_WITH_RAW_MODE
876 rc = emR3RawResumeHyper(pVM, pVCpu);
877 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
878 continue;
879#else
880 AssertLogRelMsgFailedReturn(("Not implemented\n", rc), VERR_EM_INTERNAL_ERROR);
881#endif
882 }
883 if (rc == VINF_SUCCESS)
884 rc = VINF_EM_RESCHEDULE;
885 return rc;
886
887 /*
888 * The debugger isn't attached.
889 * We'll simply turn the thing off since that's the easiest thing to do.
890 */
891 case VERR_DBGF_NOT_ATTACHED:
892 switch (rcLast)
893 {
894 case VINF_EM_DBG_HYPER_STEPPED:
895 case VINF_EM_DBG_HYPER_BREAKPOINT:
896 case VINF_EM_DBG_HYPER_ASSERTION:
897 case VERR_TRPM_PANIC:
898 case VERR_TRPM_DONT_PANIC:
899 case VERR_VMM_RING0_ASSERTION:
900 case VERR_VMM_HYPER_CR3_MISMATCH:
901 case VERR_VMM_RING3_CALL_DISABLED:
902 return rcLast;
903 }
904 return VINF_EM_OFF;
905
906 /*
907 * Status codes terminating the VM in one or another sense.
908 */
909 case VINF_EM_TERMINATE:
910 case VINF_EM_OFF:
911 case VINF_EM_RESET:
912 case VINF_EM_NO_MEMORY:
913 case VINF_EM_RAW_STALE_SELECTOR:
914 case VINF_EM_RAW_IRET_TRAP:
915 case VERR_TRPM_PANIC:
916 case VERR_TRPM_DONT_PANIC:
917 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
918 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
919 case VERR_VMM_RING0_ASSERTION:
920 case VERR_VMM_HYPER_CR3_MISMATCH:
921 case VERR_VMM_RING3_CALL_DISABLED:
922 case VERR_INTERNAL_ERROR:
923 case VERR_INTERNAL_ERROR_2:
924 case VERR_INTERNAL_ERROR_3:
925 case VERR_INTERNAL_ERROR_4:
926 case VERR_INTERNAL_ERROR_5:
927 case VERR_IPE_UNEXPECTED_STATUS:
928 case VERR_IPE_UNEXPECTED_INFO_STATUS:
929 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
930 return rc;
931
932 /*
933 * The rest is unexpected, and will keep us here.
934 */
935 default:
936 AssertMsgFailed(("Unexpected rc %Rrc!\n", rc));
937 break;
938 }
939 } while (false);
940 } /* debug for ever */
941}
942
943/**
944 * Steps recompiled code.
945 *
946 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
947 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
948 *
949 * @param pVM Pointer to the VM.
950 * @param pVCpu Pointer to the VMCPU.
951 */
952static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
953{
954 Log3(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
955
956#ifdef VBOX_WITH_REM
957 EMRemLock(pVM);
958
959 /*
960 * Switch to REM, step instruction, switch back.
961 */
962 int rc = REMR3State(pVM, pVCpu);
963 if (RT_SUCCESS(rc))
964 {
965 rc = REMR3Step(pVM, pVCpu);
966 REMR3StateBack(pVM, pVCpu);
967 }
968 EMRemUnlock(pVM);
969
970#else
971 int rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
972#endif
973
974 Log3(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
975 return rc;
976}
977
978
979/**
980 * emR3RemExecute helper that syncs the state back from REM and leave the REM
981 * critical section.
982 *
983 * @returns false - new fInREMState value.
984 * @param pVM Pointer to the VM.
985 * @param pVCpu Pointer to the VMCPU.
986 */
987DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
988{
989#ifdef VBOX_WITH_REM
990 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
991 REMR3StateBack(pVM, pVCpu);
992 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
993
994 EMRemUnlock(pVM);
995#endif
996 return false;
997}
998
999
1000/**
1001 * Executes recompiled code.
1002 *
1003 * This function contains the recompiler version of the inner
1004 * execution loop (the outer loop being in EMR3ExecuteVM()).
1005 *
1006 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1007 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1008 *
1009 * @param pVM Pointer to the VM.
1010 * @param pVCpu Pointer to the VMCPU.
1011 * @param pfFFDone Where to store an indicator telling whether or not
1012 * FFs were done before returning.
1013 *
1014 */
1015static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1016{
1017#ifdef LOG_ENABLED
1018 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1019 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
1020
1021 if (pCtx->eflags.Bits.u1VM)
1022 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF));
1023 else
1024 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
1025#endif
1026 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
1027
1028#if defined(VBOX_STRICT) && defined(DEBUG_bird)
1029 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1030 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */
1031 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1032#endif
1033
1034 /*
1035 * Spin till we get a forced action which returns anything but VINF_SUCCESS
1036 * or the REM suggests raw-mode execution.
1037 */
1038 *pfFFDone = false;
1039#ifdef VBOX_WITH_REM
1040 bool fInREMState = false;
1041#endif
1042 int rc = VINF_SUCCESS;
1043 for (;;)
1044 {
1045#ifdef VBOX_WITH_REM
1046 /*
1047 * Lock REM and update the state if not already in sync.
1048 *
1049 * Note! Big lock, but you are not supposed to own any lock when
1050 * coming in here.
1051 */
1052 if (!fInREMState)
1053 {
1054 EMRemLock(pVM);
1055 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
1056
1057 /* Flush the recompiler translation blocks if the VCPU has changed,
1058 also force a full CPU state resync. */
1059 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1060 {
1061 REMFlushTBs(pVM);
1062 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1063 }
1064 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1065
1066 rc = REMR3State(pVM, pVCpu);
1067
1068 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
1069 if (RT_FAILURE(rc))
1070 break;
1071 fInREMState = true;
1072
1073 /*
1074 * We might have missed the raising of VMREQ, TIMER and some other
1075 * important FFs while we were busy switching the state. So, check again.
1076 */
1077 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
1078 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
1079 {
1080 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1081 goto l_REMDoForcedActions;
1082 }
1083 }
1084#endif
1085
1086 /*
1087 * Execute REM.
1088 */
1089 if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1090 {
1091 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1092#ifdef VBOX_WITH_REM
1093 rc = REMR3Run(pVM, pVCpu);
1094#else
1095 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
1096#endif
1097 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1098 }
1099 else
1100 {
1101 /* Give up this time slice; virtual time continues */
1102 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1103 RTThreadSleep(5);
1104 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1105 rc = VINF_SUCCESS;
1106 }
1107
1108 /*
1109 * Deal with high priority post execution FFs before doing anything
1110 * else. Sync back the state and leave the lock to be on the safe side.
1111 */
1112 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1113 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1114 {
1115#ifdef VBOX_WITH_REM
1116 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1117#endif
1118 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1119 }
1120
1121 /*
1122 * Process the returned status code.
1123 */
1124 if (rc != VINF_SUCCESS)
1125 {
1126 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1127 break;
1128 if (rc != VINF_REM_INTERRUPED_FF)
1129 {
1130 /*
1131 * Anything which is not known to us means an internal error
1132 * and the termination of the VM!
1133 */
1134 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1135 break;
1136 }
1137 }
1138
1139
1140 /*
1141 * Check and execute forced actions.
1142 *
1143 * Sync back the VM state and leave the lock before calling any of
1144 * these, you never know what's going to happen here.
1145 */
1146#ifdef VBOX_HIGH_RES_TIMERS_HACK
1147 TMTimerPollVoid(pVM, pVCpu);
1148#endif
1149 AssertCompile(VMCPU_FF_ALL_REM_MASK & VMCPU_FF_TIMER);
1150 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1151 || VMCPU_FF_ISPENDING(pVCpu,
1152 VMCPU_FF_ALL_REM_MASK
1153 & VM_WHEN_RAW_MODE(~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE), UINT32_MAX)) )
1154 {
1155l_REMDoForcedActions:
1156#ifdef VBOX_WITH_REM
1157 if (fInREMState)
1158 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1159#endif
1160 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1161 rc = emR3ForcedActions(pVM, pVCpu, rc);
1162 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1163 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1164 if ( rc != VINF_SUCCESS
1165 && rc != VINF_EM_RESCHEDULE_REM)
1166 {
1167 *pfFFDone = true;
1168 break;
1169 }
1170 }
1171
1172 } /* The Inner Loop, recompiled execution mode version. */
1173
1174
1175#ifdef VBOX_WITH_REM
1176 /*
1177 * Returning. Sync back the VM state if required.
1178 */
1179 if (fInREMState)
1180 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1181#endif
1182
1183 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1184 return rc;
1185}
1186
1187
1188#ifdef DEBUG
1189
1190int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1191{
1192 EMSTATE enmOldState = pVCpu->em.s.enmState;
1193
1194 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1195
1196 Log(("Single step BEGIN:\n"));
1197 for (uint32_t i = 0; i < cIterations; i++)
1198 {
1199 DBGFR3PrgStep(pVCpu);
1200 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
1201 emR3RemStep(pVM, pVCpu);
1202 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1203 break;
1204 }
1205 Log(("Single step END:\n"));
1206 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1207 pVCpu->em.s.enmState = enmOldState;
1208 return VINF_EM_RESCHEDULE;
1209}
1210
1211#endif /* DEBUG */
1212
1213
1214/**
1215 * Decides whether to execute RAW, HWACC or REM.
1216 *
1217 * @returns new EM state
1218 * @param pVM Pointer to the VM.
1219 * @param pVCpu Pointer to the VMCPU.
1220 * @param pCtx Pointer to the guest CPU context.
1221 */
1222EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1223{
1224#ifdef IEM_VERIFICATION_MODE
1225 return EMSTATE_REM;
1226#else
1227
1228 /*
1229 * When forcing raw-mode execution, things are simple.
1230 */
1231 if (pVCpu->em.s.fForceRAW)
1232 return EMSTATE_RAW;
1233
1234 /*
1235 * We stay in the wait for SIPI state unless explicitly told otherwise.
1236 */
1237 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1238 return EMSTATE_WAIT_SIPI;
1239
1240 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1241 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1242 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1243
1244 X86EFLAGS EFlags = pCtx->eflags;
1245 if (HMIsEnabled(pVM))
1246 {
1247 /*
1248 * Hardware accelerated raw-mode:
1249 *
1250 * Typically only 32-bits protected mode, with paging enabled, code is
1251 * allowed here.
1252 */
1253 if ( EMIsHwVirtExecutionEnabled(pVM)
1254 && HMR3CanExecuteGuest(pVM, pCtx))
1255 return EMSTATE_HM;
1256
1257 /*
1258 * Note! Raw mode and hw accelerated mode are incompatible. The latter
1259 * turns off monitoring features essential for raw mode!
1260 */
1261 return EMSTATE_REM;
1262 }
1263
1264 /*
1265 * Standard raw-mode:
1266 *
1267 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1268 * or 32 bits protected mode ring 0 code
1269 *
1270 * The tests are ordered by the likelihood of being true during normal execution.
1271 */
1272 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1273 {
1274 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1275 return EMSTATE_REM;
1276 }
1277
1278# ifndef VBOX_RAW_V86
1279 if (EFlags.u32 & X86_EFL_VM) {
1280 Log2(("raw mode refused: VM_MASK\n"));
1281 return EMSTATE_REM;
1282 }
1283# endif
1284
1285 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1286 uint32_t u32CR0 = pCtx->cr0;
1287 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1288 {
1289 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1290 return EMSTATE_REM;
1291 }
1292
1293 if (pCtx->cr4 & X86_CR4_PAE)
1294 {
1295 uint32_t u32Dummy, u32Features;
1296
1297 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1298 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1299 return EMSTATE_REM;
1300 }
1301
1302 unsigned uSS = pCtx->ss.Sel;
1303 if ( pCtx->eflags.Bits.u1VM
1304 || (uSS & X86_SEL_RPL) == 3)
1305 {
1306 if (!EMIsRawRing3Enabled(pVM))
1307 return EMSTATE_REM;
1308
1309 if (!(EFlags.u32 & X86_EFL_IF))
1310 {
1311 Log2(("raw mode refused: IF (RawR3)\n"));
1312 return EMSTATE_REM;
1313 }
1314
1315 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1316 {
1317 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1318 return EMSTATE_REM;
1319 }
1320 }
1321 else
1322 {
1323 if (!EMIsRawRing0Enabled(pVM))
1324 return EMSTATE_REM;
1325
1326 if (EMIsRawRing1Enabled(pVM))
1327 {
1328 /* Only ring 0 and 1 supervisor code. */
1329 if ((uSS & X86_SEL_RPL) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
1330 {
1331 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1332 return EMSTATE_REM;
1333 }
1334 }
1335 /* Only ring 0 supervisor code. */
1336 else if ((uSS & X86_SEL_RPL) != 0)
1337 {
1338 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1339 return EMSTATE_REM;
1340 }
1341
1342 // Let's start with pure 32 bits ring 0 code first
1343 /** @todo What's pure 32-bit mode? flat? */
1344 if ( !(pCtx->ss.Attr.n.u1DefBig)
1345 || !(pCtx->cs.Attr.n.u1DefBig))
1346 {
1347 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1348 return EMSTATE_REM;
1349 }
1350
1351 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1352 if (!(u32CR0 & X86_CR0_WP))
1353 {
1354 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1355 return EMSTATE_REM;
1356 }
1357
1358# ifdef VBOX_WITH_RAW_MODE
1359 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1360 {
1361 Log2(("raw r0 mode forced: patch code\n"));
1362# ifdef VBOX_WITH_SAFE_STR
1363 Assert(pCtx->tr.Sel);
1364# endif
1365 return EMSTATE_RAW;
1366 }
1367# endif /* VBOX_WITH_RAW_MODE */
1368
1369# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1370 if (!(EFlags.u32 & X86_EFL_IF))
1371 {
1372 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1373 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1374 return EMSTATE_REM;
1375 }
1376# endif
1377
1378# ifndef VBOX_WITH_RAW_RING1
1379 /** @todo still necessary??? */
1380 if (EFlags.Bits.u2IOPL != 0)
1381 {
1382 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1383 return EMSTATE_REM;
1384 }
1385# endif
1386 }
1387
1388 /*
1389 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1390 */
1391 if (pCtx->cs.fFlags & CPUMSELREG_FLAGS_STALE)
1392 {
1393 Log2(("raw mode refused: stale CS\n"));
1394 return EMSTATE_REM;
1395 }
1396 if (pCtx->ss.fFlags & CPUMSELREG_FLAGS_STALE)
1397 {
1398 Log2(("raw mode refused: stale SS\n"));
1399 return EMSTATE_REM;
1400 }
1401 if (pCtx->ds.fFlags & CPUMSELREG_FLAGS_STALE)
1402 {
1403 Log2(("raw mode refused: stale DS\n"));
1404 return EMSTATE_REM;
1405 }
1406 if (pCtx->es.fFlags & CPUMSELREG_FLAGS_STALE)
1407 {
1408 Log2(("raw mode refused: stale ES\n"));
1409 return EMSTATE_REM;
1410 }
1411 if (pCtx->fs.fFlags & CPUMSELREG_FLAGS_STALE)
1412 {
1413 Log2(("raw mode refused: stale FS\n"));
1414 return EMSTATE_REM;
1415 }
1416 if (pCtx->gs.fFlags & CPUMSELREG_FLAGS_STALE)
1417 {
1418 Log2(("raw mode refused: stale GS\n"));
1419 return EMSTATE_REM;
1420 }
1421
1422# ifdef VBOX_WITH_SAFE_STR
1423 if (pCtx->tr.Sel == 0)
1424 {
1425 Log(("Raw mode refused -> TR=0\n"));
1426 return EMSTATE_REM;
1427 }
1428# endif
1429
1430 /*Assert(PGMPhysIsA20Enabled(pVCpu));*/
1431 return EMSTATE_RAW;
1432#endif /* !IEM_VERIFICATION_MODE */
1433
1434}
1435
1436
1437/**
1438 * Executes all high priority post execution force actions.
1439 *
1440 * @returns rc or a fatal status code.
1441 *
1442 * @param pVM Pointer to the VM.
1443 * @param pVCpu Pointer to the VMCPU.
1444 * @param rc The current rc.
1445 */
1446int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1447{
1448 VBOXVMM_EM_FF_HIGH(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1449
1450 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1451 PDMCritSectBothFF(pVCpu);
1452
1453 /* Update CR3 (Nested Paging case for HM). */
1454 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
1455 {
1456 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
1457 if (RT_FAILURE(rc2))
1458 return rc2;
1459 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
1460 }
1461
1462 /* Update PAE PDPEs. This must be done *after* PGMUpdateCR3() and used only by the Nested Paging case for HM. */
1463 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
1464 {
1465 if (CPUMIsGuestInPAEMode(pVCpu))
1466 {
1467 PX86PDPE pPdpes = HMGetPaePdpes(pVCpu);
1468 AssertPtr(pPdpes);
1469
1470 int rc2 = PGMGstUpdatePaePdpes(pVCpu, pPdpes);
1471 if (RT_FAILURE(rc2))
1472 return rc2;
1473 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
1474 }
1475 else
1476 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1477 }
1478
1479#ifdef VBOX_WITH_RAW_MODE
1480 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1481 CSAMR3DoPendingAction(pVM, pVCpu);
1482#endif
1483
1484 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1485 {
1486 if ( rc > VINF_EM_NO_MEMORY
1487 && rc <= VINF_EM_LAST)
1488 rc = VINF_EM_NO_MEMORY;
1489 }
1490
1491 return rc;
1492}
1493
1494
1495/**
1496 * Executes all pending forced actions.
1497 *
1498 * Forced actions can cause execution delays and execution
1499 * rescheduling. The first we deal with using action priority, so
1500 * that for instance pending timers aren't scheduled and ran until
1501 * right before execution. The rescheduling we deal with using
1502 * return codes. The same goes for VM termination, only in that case
1503 * we exit everything.
1504 *
1505 * @returns VBox status code of equal or greater importance/severity than rc.
1506 * The most important ones are: VINF_EM_RESCHEDULE,
1507 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1508 *
1509 * @param pVM Pointer to the VM.
1510 * @param pVCpu Pointer to the VMCPU.
1511 * @param rc The current rc.
1512 *
1513 */
1514int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1515{
1516 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1517#ifdef VBOX_STRICT
1518 int rcIrq = VINF_SUCCESS;
1519#endif
1520 int rc2;
1521#define UPDATE_RC() \
1522 do { \
1523 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1524 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1525 break; \
1526 if (!rc || rc2 < rc) \
1527 rc = rc2; \
1528 } while (0)
1529 VBOXVMM_EM_FF_ALL(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1530
1531 /*
1532 * Post execution chunk first.
1533 */
1534 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1535 || (VMCPU_FF_NORMAL_PRIORITY_POST_MASK && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK)) )
1536 {
1537 /*
1538 * EMT Rendezvous (must be serviced before termination).
1539 */
1540 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1541 {
1542 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1543 UPDATE_RC();
1544 /** @todo HACK ALERT! The following test is to make sure EM+TM
1545 * thinks the VM is stopped/reset before the next VM state change
1546 * is made. We need a better solution for this, or at least make it
1547 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1548 * VINF_EM_SUSPEND). */
1549 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1550 {
1551 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1552 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1553 return rc;
1554 }
1555 }
1556
1557 /*
1558 * State change request (cleared by vmR3SetStateLocked).
1559 */
1560 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1561 {
1562 VMSTATE enmState = VMR3GetState(pVM);
1563 switch (enmState)
1564 {
1565 case VMSTATE_FATAL_ERROR:
1566 case VMSTATE_FATAL_ERROR_LS:
1567 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1568 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1569 return VINF_EM_SUSPEND;
1570
1571 case VMSTATE_DESTROYING:
1572 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1573 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1574 return VINF_EM_TERMINATE;
1575
1576 default:
1577 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1578 }
1579 }
1580
1581 /*
1582 * Debugger Facility polling.
1583 */
1584 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1585 {
1586 rc2 = DBGFR3VMMForcedAction(pVM);
1587 UPDATE_RC();
1588 }
1589
1590 /*
1591 * Postponed reset request.
1592 */
1593 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1594 {
1595 rc2 = VMR3Reset(pVM->pUVM);
1596 UPDATE_RC();
1597 }
1598
1599#ifdef VBOX_WITH_RAW_MODE
1600 /*
1601 * CSAM page scanning.
1602 */
1603 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1604 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1605 {
1606 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1607
1608 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1609 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1610
1611 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1612 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1613 }
1614#endif
1615
1616 /*
1617 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1618 */
1619 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1620 {
1621 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1622 UPDATE_RC();
1623 if (rc == VINF_EM_NO_MEMORY)
1624 return rc;
1625 }
1626
1627 /* check that we got them all */
1628 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1629 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0));
1630 }
1631
1632 /*
1633 * Normal priority then.
1634 * (Executed in no particular order.)
1635 */
1636 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1637 {
1638 /*
1639 * PDM Queues are pending.
1640 */
1641 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1642 PDMR3QueueFlushAll(pVM);
1643
1644 /*
1645 * PDM DMA transfers are pending.
1646 */
1647 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1648 PDMR3DmaRun(pVM);
1649
1650 /*
1651 * EMT Rendezvous (make sure they are handled before the requests).
1652 */
1653 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1654 {
1655 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1656 UPDATE_RC();
1657 /** @todo HACK ALERT! The following test is to make sure EM+TM
1658 * thinks the VM is stopped/reset before the next VM state change
1659 * is made. We need a better solution for this, or at least make it
1660 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1661 * VINF_EM_SUSPEND). */
1662 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1663 {
1664 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1665 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1666 return rc;
1667 }
1668 }
1669
1670 /*
1671 * Requests from other threads.
1672 */
1673 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1674 {
1675 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
1676 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1677 {
1678 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1679 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1680 return rc2;
1681 }
1682 UPDATE_RC();
1683 /** @todo HACK ALERT! The following test is to make sure EM+TM
1684 * thinks the VM is stopped/reset before the next VM state change
1685 * is made. We need a better solution for this, or at least make it
1686 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1687 * VINF_EM_SUSPEND). */
1688 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1689 {
1690 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1691 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1692 return rc;
1693 }
1694 }
1695
1696#ifdef VBOX_WITH_REM
1697 /* Replay the handler notification changes. */
1698 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1699 {
1700 /* Try not to cause deadlocks. */
1701 if ( pVM->cCpus == 1
1702 || ( !PGMIsLockOwner(pVM)
1703 && !IOMIsLockWriteOwner(pVM))
1704 )
1705 {
1706 EMRemLock(pVM);
1707 REMR3ReplayHandlerNotifications(pVM);
1708 EMRemUnlock(pVM);
1709 }
1710 }
1711#endif
1712
1713 /* check that we got them all */
1714 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1715 }
1716
1717 /*
1718 * Normal priority then. (per-VCPU)
1719 * (Executed in no particular order.)
1720 */
1721 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1722 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1723 {
1724 /*
1725 * Requests from other threads.
1726 */
1727 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1728 {
1729 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
1730 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1731 {
1732 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1733 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1734 return rc2;
1735 }
1736 UPDATE_RC();
1737 /** @todo HACK ALERT! The following test is to make sure EM+TM
1738 * thinks the VM is stopped/reset before the next VM state change
1739 * is made. We need a better solution for this, or at least make it
1740 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1741 * VINF_EM_SUSPEND). */
1742 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1743 {
1744 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1745 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1746 return rc;
1747 }
1748 }
1749
1750 /* check that we got them all */
1751 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1752 }
1753
1754 /*
1755 * High priority pre execution chunk last.
1756 * (Executed in ascending priority order.)
1757 */
1758 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1759 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1760 {
1761 /*
1762 * Timers before interrupts.
1763 */
1764 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1765 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1766 TMR3TimerQueuesDo(pVM);
1767
1768 /*
1769 * The instruction following an emulated STI should *always* be executed!
1770 *
1771 * Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1772 * the eip is the same as the inhibited instr address. Before we
1773 * are able to execute this instruction in raw mode (iret to
1774 * guest code) an external interrupt might force a world switch
1775 * again. Possibly allowing a guest interrupt to be dispatched
1776 * in the process. This could break the guest. Sounds very
1777 * unlikely, but such timing sensitive problem are not as rare as
1778 * you might think.
1779 */
1780 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1781 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1782 {
1783 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1784 {
1785 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1786 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1787 }
1788 else
1789 Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1790 }
1791
1792 /*
1793 * Interrupts.
1794 */
1795 bool fWakeupPending = false;
1796 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1797 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1798 && (!rc || rc >= VINF_EM_RESCHEDULE_HM)
1799 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1800#ifdef VBOX_WITH_RAW_MODE
1801 && PATMAreInterruptsEnabled(pVM)
1802#else
1803 && (pVCpu->em.s.pCtx->eflags.u32 & X86_EFL_IF)
1804#endif
1805 && !HMR3IsEventPending(pVCpu))
1806 {
1807 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1808 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1809 {
1810 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1811 /** @todo this really isn't nice, should properly handle this */
1812 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1813#ifdef VBOX_STRICT
1814 rcIrq = rc2;
1815#endif
1816 UPDATE_RC();
1817 /* Reschedule required: We must not miss the wakeup below! */
1818 fWakeupPending = true;
1819 }
1820#ifdef VBOX_WITH_REM
1821 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1822 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1823 {
1824 rc2 = VINF_EM_RESCHEDULE_REM;
1825 UPDATE_RC();
1826 }
1827#endif
1828 }
1829
1830 /*
1831 * Allocate handy pages.
1832 */
1833 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1834 {
1835 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1836 UPDATE_RC();
1837 }
1838
1839 /*
1840 * Debugger Facility request.
1841 */
1842 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1843 {
1844 rc2 = DBGFR3VMMForcedAction(pVM);
1845 UPDATE_RC();
1846 }
1847
1848 /*
1849 * EMT Rendezvous (must be serviced before termination).
1850 */
1851 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1852 && VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1853 {
1854 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1855 UPDATE_RC();
1856 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1857 * stopped/reset before the next VM state change is made. We need a better
1858 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1859 * && rc >= VINF_EM_SUSPEND). */
1860 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1861 {
1862 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1863 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1864 return rc;
1865 }
1866 }
1867
1868 /*
1869 * State change request (cleared by vmR3SetStateLocked).
1870 */
1871 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1872 && VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1873 {
1874 VMSTATE enmState = VMR3GetState(pVM);
1875 switch (enmState)
1876 {
1877 case VMSTATE_FATAL_ERROR:
1878 case VMSTATE_FATAL_ERROR_LS:
1879 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1880 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1881 return VINF_EM_SUSPEND;
1882
1883 case VMSTATE_DESTROYING:
1884 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1885 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1886 return VINF_EM_TERMINATE;
1887
1888 default:
1889 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1890 }
1891 }
1892
1893 /*
1894 * Out of memory? Since most of our fellow high priority actions may cause us
1895 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1896 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1897 * than us since we can terminate without allocating more memory.
1898 */
1899 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1900 {
1901 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1902 UPDATE_RC();
1903 if (rc == VINF_EM_NO_MEMORY)
1904 return rc;
1905 }
1906
1907 /*
1908 * If the virtual sync clock is still stopped, make TM restart it.
1909 */
1910 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1911 TMR3VirtualSyncFF(pVM, pVCpu);
1912
1913#ifdef DEBUG
1914 /*
1915 * Debug, pause the VM.
1916 */
1917 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1918 {
1919 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1920 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1921 return VINF_EM_SUSPEND;
1922 }
1923#endif
1924
1925 /* check that we got them all */
1926 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1927 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_INHIBIT_INTERRUPTS | VM_WHEN_RAW_MODE(VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0)));
1928 }
1929
1930#undef UPDATE_RC
1931 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1932 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1933 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1934 return rc;
1935}
1936
1937
1938/**
1939 * Check if the preset execution time cap restricts guest execution scheduling.
1940 *
1941 * @returns true if allowed, false otherwise
1942 * @param pVM Pointer to the VM.
1943 * @param pVCpu Pointer to the VMCPU.
1944 *
1945 */
1946VMMR3_INT_DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1947{
1948 uint64_t u64UserTime, u64KernelTime;
1949
1950 if ( pVM->uCpuExecutionCap != 100
1951 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1952 {
1953 uint64_t u64TimeNow = RTTimeMilliTS();
1954 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1955 {
1956 /* New time slice. */
1957 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1958 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1959 pVCpu->em.s.u64TimeSliceExec = 0;
1960 }
1961 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1962
1963 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1964 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1965 return false;
1966 }
1967 return true;
1968}
1969
1970
1971/**
1972 * Execute VM.
1973 *
1974 * This function is the main loop of the VM. The emulation thread
1975 * calls this function when the VM has been successfully constructed
1976 * and we're ready for executing the VM.
1977 *
1978 * Returning from this function means that the VM is turned off or
1979 * suspended (state already saved) and deconstruction is next in line.
1980 *
1981 * All interaction from other thread are done using forced actions
1982 * and signaling of the wait object.
1983 *
1984 * @returns VBox status code, informational status codes may indicate failure.
1985 * @param pVM Pointer to the VM.
1986 * @param pVCpu Pointer to the VMCPU.
1987 */
1988VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1989{
1990 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1991 pVM,
1992 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1993 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1994 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1995 pVCpu->em.s.fForceRAW));
1996 VM_ASSERT_EMT(pVM);
1997 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
1998 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
1999 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
2000 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
2001
2002 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
2003 if (rc == 0)
2004 {
2005 /*
2006 * Start the virtual time.
2007 */
2008 TMR3NotifyResume(pVM, pVCpu);
2009
2010 /*
2011 * The Outer Main Loop.
2012 */
2013 bool fFFDone = false;
2014
2015 /* Reschedule right away to start in the right state. */
2016 rc = VINF_SUCCESS;
2017
2018 /* If resuming after a pause or a state load, restore the previous
2019 state or else we'll start executing code. Else, just reschedule. */
2020 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
2021 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2022 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
2023 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2024 else
2025 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2026
2027 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2028 for (;;)
2029 {
2030 /*
2031 * Before we can schedule anything (we're here because
2032 * scheduling is required) we must service any pending
2033 * forced actions to avoid any pending action causing
2034 * immediate rescheduling upon entering an inner loop
2035 *
2036 * Do forced actions.
2037 */
2038 if ( !fFFDone
2039 && rc != VINF_EM_TERMINATE
2040 && rc != VINF_EM_OFF
2041 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
2042 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
2043 {
2044 rc = emR3ForcedActions(pVM, pVCpu, rc);
2045 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
2046 if ( ( rc == VINF_EM_RESCHEDULE_REM
2047 || rc == VINF_EM_RESCHEDULE_HM)
2048 && pVCpu->em.s.fForceRAW)
2049 rc = VINF_EM_RESCHEDULE_RAW;
2050 }
2051 else if (fFFDone)
2052 fFFDone = false;
2053
2054 /*
2055 * Now what to do?
2056 */
2057 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
2058 EMSTATE const enmOldState = pVCpu->em.s.enmState;
2059 switch (rc)
2060 {
2061 /*
2062 * Keep doing what we're currently doing.
2063 */
2064 case VINF_SUCCESS:
2065 break;
2066
2067 /*
2068 * Reschedule - to raw-mode execution.
2069 */
2070 case VINF_EM_RESCHEDULE_RAW:
2071 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", enmOldState, EMSTATE_RAW));
2072 pVCpu->em.s.enmState = EMSTATE_RAW;
2073 break;
2074
2075 /*
2076 * Reschedule - to hardware accelerated raw-mode execution.
2077 */
2078 case VINF_EM_RESCHEDULE_HM:
2079 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HM: %d -> %d (EMSTATE_HM)\n", enmOldState, EMSTATE_HM));
2080 Assert(!pVCpu->em.s.fForceRAW);
2081 pVCpu->em.s.enmState = EMSTATE_HM;
2082 break;
2083
2084 /*
2085 * Reschedule - to recompiled execution.
2086 */
2087 case VINF_EM_RESCHEDULE_REM:
2088 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
2089 pVCpu->em.s.enmState = EMSTATE_REM;
2090 break;
2091
2092 /*
2093 * Resume.
2094 */
2095 case VINF_EM_RESUME:
2096 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", enmOldState));
2097 /* Don't reschedule in the halted or wait for SIPI case. */
2098 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2099 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
2100 {
2101 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2102 break;
2103 }
2104 /* fall through and get scheduled. */
2105
2106 /*
2107 * Reschedule.
2108 */
2109 case VINF_EM_RESCHEDULE:
2110 {
2111 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2112 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2113 pVCpu->em.s.enmState = enmState;
2114 break;
2115 }
2116
2117 /*
2118 * Halted.
2119 */
2120 case VINF_EM_HALT:
2121 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", enmOldState, EMSTATE_HALTED));
2122 pVCpu->em.s.enmState = EMSTATE_HALTED;
2123 break;
2124
2125 /*
2126 * Switch to the wait for SIPI state (application processor only)
2127 */
2128 case VINF_EM_WAIT_SIPI:
2129 Assert(pVCpu->idCpu != 0);
2130 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", enmOldState, EMSTATE_WAIT_SIPI));
2131 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2132 break;
2133
2134
2135 /*
2136 * Suspend.
2137 */
2138 case VINF_EM_SUSPEND:
2139 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2140 Assert(enmOldState != EMSTATE_SUSPENDED);
2141 pVCpu->em.s.enmPrevState = enmOldState;
2142 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2143 break;
2144
2145 /*
2146 * Reset.
2147 * We might end up doing a double reset for now, we'll have to clean up the mess later.
2148 */
2149 case VINF_EM_RESET:
2150 {
2151 if (pVCpu->idCpu == 0)
2152 {
2153 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2154 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2155 pVCpu->em.s.enmState = enmState;
2156 }
2157 else
2158 {
2159 /* All other VCPUs go into the wait for SIPI state. */
2160 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2161 }
2162 break;
2163 }
2164
2165 /*
2166 * Power Off.
2167 */
2168 case VINF_EM_OFF:
2169 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2170 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2171 TMR3NotifySuspend(pVM, pVCpu);
2172 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2173 return rc;
2174
2175 /*
2176 * Terminate the VM.
2177 */
2178 case VINF_EM_TERMINATE:
2179 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2180 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2181 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
2182 TMR3NotifySuspend(pVM, pVCpu);
2183 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2184 return rc;
2185
2186
2187 /*
2188 * Out of memory, suspend the VM and stuff.
2189 */
2190 case VINF_EM_NO_MEMORY:
2191 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2192 Assert(enmOldState != EMSTATE_SUSPENDED);
2193 pVCpu->em.s.enmPrevState = enmOldState;
2194 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2195 TMR3NotifySuspend(pVM, pVCpu);
2196 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2197
2198 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2199 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2200 if (rc != VINF_EM_SUSPEND)
2201 {
2202 if (RT_SUCCESS_NP(rc))
2203 {
2204 AssertLogRelMsgFailed(("%Rrc\n", rc));
2205 rc = VERR_EM_INTERNAL_ERROR;
2206 }
2207 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2208 }
2209 return rc;
2210
2211 /*
2212 * Guest debug events.
2213 */
2214 case VINF_EM_DBG_STEPPED:
2215 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
2216 case VINF_EM_DBG_STOP:
2217 case VINF_EM_DBG_BREAKPOINT:
2218 case VINF_EM_DBG_STEP:
2219 if (enmOldState == EMSTATE_RAW)
2220 {
2221 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_RAW));
2222 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2223 }
2224 else
2225 {
2226 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_REM));
2227 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2228 }
2229 break;
2230
2231 /*
2232 * Hypervisor debug events.
2233 */
2234 case VINF_EM_DBG_HYPER_STEPPED:
2235 case VINF_EM_DBG_HYPER_BREAKPOINT:
2236 case VINF_EM_DBG_HYPER_ASSERTION:
2237 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_HYPER));
2238 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2239 break;
2240
2241 /*
2242 * Guru mediations.
2243 */
2244 case VERR_VMM_RING0_ASSERTION:
2245 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2246 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2247 break;
2248
2249 /*
2250 * Any error code showing up here other than the ones we
2251 * know and process above are considered to be FATAL.
2252 *
2253 * Unknown warnings and informational status codes are also
2254 * included in this.
2255 */
2256 default:
2257 if (RT_SUCCESS_NP(rc))
2258 {
2259 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2260 rc = VERR_EM_INTERNAL_ERROR;
2261 }
2262 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2263 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2264 break;
2265 }
2266
2267 /*
2268 * Act on state transition.
2269 */
2270 EMSTATE const enmNewState = pVCpu->em.s.enmState;
2271 if (enmOldState != enmNewState)
2272 {
2273 VBOXVMM_EM_STATE_CHANGED(pVCpu, enmOldState, enmNewState, rc);
2274
2275 /* Clear MWait flags. */
2276 if ( enmOldState == EMSTATE_HALTED
2277 && (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2278 && ( enmNewState == EMSTATE_RAW
2279 || enmNewState == EMSTATE_HM
2280 || enmNewState == EMSTATE_REM
2281 || enmNewState == EMSTATE_DEBUG_GUEST_RAW
2282 || enmNewState == EMSTATE_DEBUG_GUEST_HM
2283 || enmNewState == EMSTATE_DEBUG_GUEST_REM) )
2284 {
2285 LogFlow(("EMR3ExecuteVM: Clearing MWAIT\n"));
2286 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2287 }
2288 }
2289 else
2290 VBOXVMM_EM_STATE_UNCHANGED(pVCpu, enmNewState, rc);
2291
2292 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2293 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2294
2295 /*
2296 * Act on the new state.
2297 */
2298 switch (enmNewState)
2299 {
2300 /*
2301 * Execute raw.
2302 */
2303 case EMSTATE_RAW:
2304#ifndef IEM_VERIFICATION_MODE /* remove later */
2305# ifdef VBOX_WITH_RAW_MODE
2306 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2307# else
2308 AssertLogRelMsgFailed(("%Rrc\n", rc));
2309 rc = VERR_EM_INTERNAL_ERROR;
2310# endif
2311 break;
2312#endif
2313
2314 /*
2315 * Execute hardware accelerated raw.
2316 */
2317 case EMSTATE_HM:
2318#ifndef IEM_VERIFICATION_MODE /* remove later */
2319 rc = emR3HmExecute(pVM, pVCpu, &fFFDone);
2320 break;
2321#endif
2322
2323 /*
2324 * Execute recompiled.
2325 */
2326 case EMSTATE_REM:
2327#ifdef IEM_VERIFICATION_MODE
2328# if 1
2329 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); fFFDone = false;
2330# else
2331 rc = VBOXSTRICTRC_TODO(REMR3EmulateInstruction(pVM, pVCpu)); fFFDone = false;
2332 if (rc == VINF_EM_RESCHEDULE)
2333 rc = VINF_SUCCESS;
2334# endif
2335#else
2336 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2337#endif
2338 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2339 break;
2340
2341 /*
2342 * Application processor execution halted until SIPI.
2343 */
2344 case EMSTATE_WAIT_SIPI:
2345 /* no break */
2346 /*
2347 * hlt - execution halted until interrupt.
2348 */
2349 case EMSTATE_HALTED:
2350 {
2351 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2352 /* MWAIT has a special extension where it's woken up when
2353 an interrupt is pending even when IF=0. */
2354 if ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2355 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2356 {
2357 rc = VMR3WaitHalted(pVM, pVCpu, false /*fIgnoreInterrupts*/);
2358 if ( rc == VINF_SUCCESS
2359 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2360 {
2361 Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
2362 rc = VINF_EM_RESCHEDULE;
2363 }
2364 }
2365 else
2366 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2367
2368 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2369 break;
2370 }
2371
2372 /*
2373 * Suspended - return to VM.cpp.
2374 */
2375 case EMSTATE_SUSPENDED:
2376 TMR3NotifySuspend(pVM, pVCpu);
2377 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2378 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2379 return VINF_EM_SUSPEND;
2380
2381 /*
2382 * Debugging in the guest.
2383 */
2384 case EMSTATE_DEBUG_GUEST_REM:
2385 case EMSTATE_DEBUG_GUEST_RAW:
2386 TMR3NotifySuspend(pVM, pVCpu);
2387 rc = emR3Debug(pVM, pVCpu, rc);
2388 TMR3NotifyResume(pVM, pVCpu);
2389 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2390 break;
2391
2392 /*
2393 * Debugging in the hypervisor.
2394 */
2395 case EMSTATE_DEBUG_HYPER:
2396 {
2397 TMR3NotifySuspend(pVM, pVCpu);
2398 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2399
2400 rc = emR3Debug(pVM, pVCpu, rc);
2401 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2402 if (rc != VINF_SUCCESS)
2403 {
2404 /* switch to guru meditation mode */
2405 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2406 VMMR3FatalDump(pVM, pVCpu, rc);
2407 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2408 return rc;
2409 }
2410
2411 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2412 TMR3NotifyResume(pVM, pVCpu);
2413 break;
2414 }
2415
2416 /*
2417 * Guru meditation takes place in the debugger.
2418 */
2419 case EMSTATE_GURU_MEDITATION:
2420 {
2421 TMR3NotifySuspend(pVM, pVCpu);
2422 VMMR3FatalDump(pVM, pVCpu, rc);
2423 emR3Debug(pVM, pVCpu, rc);
2424 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2425 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2426 return rc;
2427 }
2428
2429 /*
2430 * The states we don't expect here.
2431 */
2432 case EMSTATE_NONE:
2433 case EMSTATE_TERMINATING:
2434 default:
2435 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2436 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2437 TMR3NotifySuspend(pVM, pVCpu);
2438 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2439 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2440 return VERR_EM_INTERNAL_ERROR;
2441 }
2442 } /* The Outer Main Loop */
2443 }
2444 else
2445 {
2446 /*
2447 * Fatal error.
2448 */
2449 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2450 TMR3NotifySuspend(pVM, pVCpu);
2451 VMMR3FatalDump(pVM, pVCpu, rc);
2452 emR3Debug(pVM, pVCpu, rc);
2453 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2454 /** @todo change the VM state! */
2455 return rc;
2456 }
2457
2458 /* (won't ever get here). */
2459 AssertFailed();
2460}
2461
2462/**
2463 * Notify EM of a state change (used by FTM)
2464 *
2465 * @param pVM Pointer to the VM.
2466 */
2467VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM)
2468{
2469 PVMCPU pVCpu = VMMGetCpu(pVM);
2470
2471 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2472 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2473 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2474 return VINF_SUCCESS;
2475}
2476
2477/**
2478 * Notify EM of a state change (used by FTM)
2479 *
2480 * @param pVM Pointer to the VM.
2481 */
2482VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM)
2483{
2484 PVMCPU pVCpu = VMMGetCpu(pVM);
2485 EMSTATE enmCurState = pVCpu->em.s.enmState;
2486
2487 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2488 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2489 pVCpu->em.s.enmPrevState = enmCurState;
2490 return VINF_SUCCESS;
2491}
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