VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/EM.cpp@ 45841

Last change on this file since 45841 was 45808, checked in by vboxsync, 12 years ago

VMM,DevVGA: Don't resolve RC symbols when HM is enabled (part 1).
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1/* $Id: EM.cpp 45808 2013-04-29 12:41:07Z vboxsync $ */
2/** @file
3 * EM - Execution Monitor / Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_em EM - The Execution Monitor / Manager
19 *
20 * The Execution Monitor/Manager is responsible for running the VM, scheduling
21 * the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
22 * Interpreted), and keeping the CPU states in sync. The function
23 * EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
24 * modes has different inner loops (emR3RawExecute, emR3HmExecute, and
25 * emR3RemExecute).
26 *
27 * The interpreted execution is only used to avoid switching between
28 * raw-mode/hm and the recompiler when fielding virtualization traps/faults.
29 * The interpretation is thus implemented as part of EM.
30 *
31 * @see grp_em
32 */
33
34/*******************************************************************************
35* Header Files *
36*******************************************************************************/
37#define LOG_GROUP LOG_GROUP_EM
38#include <VBox/vmm/em.h>
39#include <VBox/vmm/vmm.h>
40#include <VBox/vmm/patm.h>
41#include <VBox/vmm/csam.h>
42#include <VBox/vmm/selm.h>
43#include <VBox/vmm/trpm.h>
44#include <VBox/vmm/iom.h>
45#include <VBox/vmm/dbgf.h>
46#include <VBox/vmm/pgm.h>
47#ifdef VBOX_WITH_REM
48# include <VBox/vmm/rem.h>
49#else
50# include <VBox/vmm/iem.h>
51#endif
52#include <VBox/vmm/tm.h>
53#include <VBox/vmm/mm.h>
54#include <VBox/vmm/ssm.h>
55#include <VBox/vmm/pdmapi.h>
56#include <VBox/vmm/pdmcritsect.h>
57#include <VBox/vmm/pdmqueue.h>
58#include <VBox/vmm/hm.h>
59#include <VBox/vmm/patm.h>
60#ifdef IEM_VERIFICATION_MODE
61# include <VBox/vmm/iem.h>
62#endif
63#include "EMInternal.h"
64#include <VBox/vmm/vm.h>
65#include <VBox/vmm/uvm.h>
66#include <VBox/vmm/cpumdis.h>
67#include <VBox/dis.h>
68#include <VBox/disopcode.h>
69#include <VBox/vmm/dbgf.h>
70#include "VMMTracing.h"
71
72#include <iprt/asm.h>
73#include <iprt/string.h>
74#include <iprt/stream.h>
75#include <iprt/thread.h>
76
77
78/*******************************************************************************
79* Defined Constants And Macros *
80*******************************************************************************/
81#if 0 /* Disabled till after 2.1.0 when we've time to test it. */
82#define EM_NOTIFY_HM
83#endif
84
85
86/*******************************************************************************
87* Internal Functions *
88*******************************************************************************/
89static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM);
90static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
91#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
92static const char *emR3GetStateName(EMSTATE enmState);
93#endif
94static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc);
95static int emR3RemStep(PVM pVM, PVMCPU pVCpu);
96static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone);
97int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc);
98
99
100/**
101 * Initializes the EM.
102 *
103 * @returns VBox status code.
104 * @param pVM Pointer to the VM.
105 */
106VMMR3_INT_DECL(int) EMR3Init(PVM pVM)
107{
108 LogFlow(("EMR3Init\n"));
109 /*
110 * Assert alignment and sizes.
111 */
112 AssertCompileMemberAlignment(VM, em.s, 32);
113 AssertCompile(sizeof(pVM->em.s) <= sizeof(pVM->em.padding));
114 AssertCompile(sizeof(pVM->aCpus[0].em.s.u.FatalLongJump) <= sizeof(pVM->aCpus[0].em.s.u.achPaddingFatalLongJump));
115
116 /*
117 * Init the structure.
118 */
119 pVM->em.s.offVM = RT_OFFSETOF(VM, em.s);
120 bool fEnabled;
121 int rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR3Enabled", &fEnabled);
122 pVM->fRecompileUser = RT_SUCCESS(rc) ? !fEnabled : false;
123 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR0Enabled", &fEnabled);
124 pVM->fRecompileSupervisor = RT_SUCCESS(rc) ? !fEnabled : false;
125 Log(("EMR3Init: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n", pVM->fRecompileUser, pVM->fRecompileSupervisor));
126
127#ifdef VBOX_WITH_RAW_RING1
128 rc = CFGMR3QueryBool(CFGMR3GetRoot(pVM), "RawR1Enabled", &fEnabled);
129 pVM->fRawRing1Enabled = RT_SUCCESS(rc) ? fEnabled : false;
130 Log(("EMR3Init: fRawRing1Enabled=%RTbool\n", pVM->fRawRing1Enabled));
131#else
132 pVM->fRawRing1Enabled = false; /* disabled by default. */
133#endif
134
135#ifdef VBOX_WITH_REM
136 /*
137 * Initialize the REM critical section.
138 */
139 AssertCompileMemberAlignment(EM, CritSectREM, sizeof(uintptr_t));
140 rc = PDMR3CritSectInit(pVM, &pVM->em.s.CritSectREM, RT_SRC_POS, "EM-REM");
141 AssertRCReturn(rc, rc);
142#endif
143
144 /*
145 * Saved state.
146 */
147 rc = SSMR3RegisterInternal(pVM, "em", 0, EM_SAVED_STATE_VERSION, 16,
148 NULL, NULL, NULL,
149 NULL, emR3Save, NULL,
150 NULL, emR3Load, NULL);
151 if (RT_FAILURE(rc))
152 return rc;
153
154 for (VMCPUID i = 0; i < pVM->cCpus; i++)
155 {
156 PVMCPU pVCpu = &pVM->aCpus[i];
157
158 pVCpu->em.s.offVMCPU = RT_OFFSETOF(VMCPU, em.s);
159
160 pVCpu->em.s.enmState = (i == 0) ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
161 pVCpu->em.s.enmPrevState = EMSTATE_NONE;
162 pVCpu->em.s.fForceRAW = false;
163
164 pVCpu->em.s.pCtx = CPUMQueryGuestCtxPtr(pVCpu);
165#ifdef VBOX_WITH_RAW_MODE
166 if (!HMIsEnabled(pVM))
167 {
168 pVCpu->em.s.pPatmGCState = PATMR3QueryGCStateHC(pVM);
169 AssertMsg(pVCpu->em.s.pPatmGCState, ("PATMR3QueryGCStateHC failed!\n"));
170 }
171#endif
172
173 /* Force reset of the time slice. */
174 pVCpu->em.s.u64TimeSliceStart = 0;
175
176# define EM_REG_COUNTER(a, b, c) \
177 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, c, b, i); \
178 AssertRC(rc);
179
180# define EM_REG_COUNTER_USED(a, b, c) \
181 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, c, b, i); \
182 AssertRC(rc);
183
184# define EM_REG_PROFILE(a, b, c) \
185 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
186 AssertRC(rc);
187
188# define EM_REG_PROFILE_ADV(a, b, c) \
189 rc = STAMR3RegisterF(pVM, a, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, c, b, i); \
190 AssertRC(rc);
191
192 /*
193 * Statistics.
194 */
195#ifdef VBOX_WITH_STATISTICS
196 PEMSTATS pStats;
197 rc = MMHyperAlloc(pVM, sizeof(*pStats), 0, MM_TAG_EM, (void **)&pStats);
198 if (RT_FAILURE(rc))
199 return rc;
200
201 pVCpu->em.s.pStatsR3 = pStats;
202 pVCpu->em.s.pStatsR0 = MMHyperR3ToR0(pVM, pStats);
203 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pStats);
204
205 EM_REG_PROFILE(&pStats->StatRZEmulate, "/EM/CPU%d/RZ/Interpret", "Profiling of EMInterpretInstruction.");
206 EM_REG_PROFILE(&pStats->StatR3Emulate, "/EM/CPU%d/R3/Interpret", "Profiling of EMInterpretInstruction.");
207
208 EM_REG_PROFILE(&pStats->StatRZInterpretSucceeded, "/EM/CPU%d/RZ/Interpret/Success", "The number of times an instruction was successfully interpreted.");
209 EM_REG_PROFILE(&pStats->StatR3InterpretSucceeded, "/EM/CPU%d/R3/Interpret/Success", "The number of times an instruction was successfully interpreted.");
210
211 EM_REG_COUNTER_USED(&pStats->StatRZAnd, "/EM/CPU%d/RZ/Interpret/Success/And", "The number of times AND was successfully interpreted.");
212 EM_REG_COUNTER_USED(&pStats->StatR3And, "/EM/CPU%d/R3/Interpret/Success/And", "The number of times AND was successfully interpreted.");
213 EM_REG_COUNTER_USED(&pStats->StatRZAdd, "/EM/CPU%d/RZ/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
214 EM_REG_COUNTER_USED(&pStats->StatR3Add, "/EM/CPU%d/R3/Interpret/Success/Add", "The number of times ADD was successfully interpreted.");
215 EM_REG_COUNTER_USED(&pStats->StatRZAdc, "/EM/CPU%d/RZ/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
216 EM_REG_COUNTER_USED(&pStats->StatR3Adc, "/EM/CPU%d/R3/Interpret/Success/Adc", "The number of times ADC was successfully interpreted.");
217 EM_REG_COUNTER_USED(&pStats->StatRZSub, "/EM/CPU%d/RZ/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
218 EM_REG_COUNTER_USED(&pStats->StatR3Sub, "/EM/CPU%d/R3/Interpret/Success/Sub", "The number of times SUB was successfully interpreted.");
219 EM_REG_COUNTER_USED(&pStats->StatRZCpuId, "/EM/CPU%d/RZ/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
220 EM_REG_COUNTER_USED(&pStats->StatR3CpuId, "/EM/CPU%d/R3/Interpret/Success/CpuId", "The number of times CPUID was successfully interpreted.");
221 EM_REG_COUNTER_USED(&pStats->StatRZDec, "/EM/CPU%d/RZ/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
222 EM_REG_COUNTER_USED(&pStats->StatR3Dec, "/EM/CPU%d/R3/Interpret/Success/Dec", "The number of times DEC was successfully interpreted.");
223 EM_REG_COUNTER_USED(&pStats->StatRZHlt, "/EM/CPU%d/RZ/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
224 EM_REG_COUNTER_USED(&pStats->StatR3Hlt, "/EM/CPU%d/R3/Interpret/Success/Hlt", "The number of times HLT was successfully interpreted.");
225 EM_REG_COUNTER_USED(&pStats->StatRZInc, "/EM/CPU%d/RZ/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
226 EM_REG_COUNTER_USED(&pStats->StatR3Inc, "/EM/CPU%d/R3/Interpret/Success/Inc", "The number of times INC was successfully interpreted.");
227 EM_REG_COUNTER_USED(&pStats->StatRZInvlPg, "/EM/CPU%d/RZ/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
228 EM_REG_COUNTER_USED(&pStats->StatR3InvlPg, "/EM/CPU%d/R3/Interpret/Success/Invlpg", "The number of times INVLPG was successfully interpreted.");
229 EM_REG_COUNTER_USED(&pStats->StatRZIret, "/EM/CPU%d/RZ/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
230 EM_REG_COUNTER_USED(&pStats->StatR3Iret, "/EM/CPU%d/R3/Interpret/Success/Iret", "The number of times IRET was successfully interpreted.");
231 EM_REG_COUNTER_USED(&pStats->StatRZLLdt, "/EM/CPU%d/RZ/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
232 EM_REG_COUNTER_USED(&pStats->StatR3LLdt, "/EM/CPU%d/R3/Interpret/Success/LLdt", "The number of times LLDT was successfully interpreted.");
233 EM_REG_COUNTER_USED(&pStats->StatRZLIdt, "/EM/CPU%d/RZ/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
234 EM_REG_COUNTER_USED(&pStats->StatR3LIdt, "/EM/CPU%d/R3/Interpret/Success/LIdt", "The number of times LIDT was successfully interpreted.");
235 EM_REG_COUNTER_USED(&pStats->StatRZLGdt, "/EM/CPU%d/RZ/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
236 EM_REG_COUNTER_USED(&pStats->StatR3LGdt, "/EM/CPU%d/R3/Interpret/Success/LGdt", "The number of times LGDT was successfully interpreted.");
237 EM_REG_COUNTER_USED(&pStats->StatRZMov, "/EM/CPU%d/RZ/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
238 EM_REG_COUNTER_USED(&pStats->StatR3Mov, "/EM/CPU%d/R3/Interpret/Success/Mov", "The number of times MOV was successfully interpreted.");
239 EM_REG_COUNTER_USED(&pStats->StatRZMovCRx, "/EM/CPU%d/RZ/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
240 EM_REG_COUNTER_USED(&pStats->StatR3MovCRx, "/EM/CPU%d/R3/Interpret/Success/MovCRx", "The number of times MOV CRx was successfully interpreted.");
241 EM_REG_COUNTER_USED(&pStats->StatRZMovDRx, "/EM/CPU%d/RZ/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
242 EM_REG_COUNTER_USED(&pStats->StatR3MovDRx, "/EM/CPU%d/R3/Interpret/Success/MovDRx", "The number of times MOV DRx was successfully interpreted.");
243 EM_REG_COUNTER_USED(&pStats->StatRZOr, "/EM/CPU%d/RZ/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
244 EM_REG_COUNTER_USED(&pStats->StatR3Or, "/EM/CPU%d/R3/Interpret/Success/Or", "The number of times OR was successfully interpreted.");
245 EM_REG_COUNTER_USED(&pStats->StatRZPop, "/EM/CPU%d/RZ/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
246 EM_REG_COUNTER_USED(&pStats->StatR3Pop, "/EM/CPU%d/R3/Interpret/Success/Pop", "The number of times POP was successfully interpreted.");
247 EM_REG_COUNTER_USED(&pStats->StatRZRdtsc, "/EM/CPU%d/RZ/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
248 EM_REG_COUNTER_USED(&pStats->StatR3Rdtsc, "/EM/CPU%d/R3/Interpret/Success/Rdtsc", "The number of times RDTSC was successfully interpreted.");
249 EM_REG_COUNTER_USED(&pStats->StatRZRdpmc, "/EM/CPU%d/RZ/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
250 EM_REG_COUNTER_USED(&pStats->StatR3Rdpmc, "/EM/CPU%d/R3/Interpret/Success/Rdpmc", "The number of times RDPMC was successfully interpreted.");
251 EM_REG_COUNTER_USED(&pStats->StatRZSti, "/EM/CPU%d/RZ/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
252 EM_REG_COUNTER_USED(&pStats->StatR3Sti, "/EM/CPU%d/R3/Interpret/Success/Sti", "The number of times STI was successfully interpreted.");
253 EM_REG_COUNTER_USED(&pStats->StatRZXchg, "/EM/CPU%d/RZ/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
254 EM_REG_COUNTER_USED(&pStats->StatR3Xchg, "/EM/CPU%d/R3/Interpret/Success/Xchg", "The number of times XCHG was successfully interpreted.");
255 EM_REG_COUNTER_USED(&pStats->StatRZXor, "/EM/CPU%d/RZ/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
256 EM_REG_COUNTER_USED(&pStats->StatR3Xor, "/EM/CPU%d/R3/Interpret/Success/Xor", "The number of times XOR was successfully interpreted.");
257 EM_REG_COUNTER_USED(&pStats->StatRZMonitor, "/EM/CPU%d/RZ/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
258 EM_REG_COUNTER_USED(&pStats->StatR3Monitor, "/EM/CPU%d/R3/Interpret/Success/Monitor", "The number of times MONITOR was successfully interpreted.");
259 EM_REG_COUNTER_USED(&pStats->StatRZMWait, "/EM/CPU%d/RZ/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
260 EM_REG_COUNTER_USED(&pStats->StatR3MWait, "/EM/CPU%d/R3/Interpret/Success/MWait", "The number of times MWAIT was successfully interpreted.");
261 EM_REG_COUNTER_USED(&pStats->StatRZBtr, "/EM/CPU%d/RZ/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
262 EM_REG_COUNTER_USED(&pStats->StatR3Btr, "/EM/CPU%d/R3/Interpret/Success/Btr", "The number of times BTR was successfully interpreted.");
263 EM_REG_COUNTER_USED(&pStats->StatRZBts, "/EM/CPU%d/RZ/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
264 EM_REG_COUNTER_USED(&pStats->StatR3Bts, "/EM/CPU%d/R3/Interpret/Success/Bts", "The number of times BTS was successfully interpreted.");
265 EM_REG_COUNTER_USED(&pStats->StatRZBtc, "/EM/CPU%d/RZ/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
266 EM_REG_COUNTER_USED(&pStats->StatR3Btc, "/EM/CPU%d/R3/Interpret/Success/Btc", "The number of times BTC was successfully interpreted.");
267 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
268 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg, "/EM/CPU%d/R3/Interpret/Success/CmpXchg", "The number of times CMPXCHG was successfully interpreted.");
269 EM_REG_COUNTER_USED(&pStats->StatRZCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
270 EM_REG_COUNTER_USED(&pStats->StatR3CmpXchg8b, "/EM/CPU%d/R3/Interpret/Success/CmpXchg8b", "The number of times CMPXCHG8B was successfully interpreted.");
271 EM_REG_COUNTER_USED(&pStats->StatRZXAdd, "/EM/CPU%d/RZ/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
272 EM_REG_COUNTER_USED(&pStats->StatR3XAdd, "/EM/CPU%d/R3/Interpret/Success/XAdd", "The number of times XADD was successfully interpreted.");
273 EM_REG_COUNTER_USED(&pStats->StatR3Rdmsr, "/EM/CPU%d/R3/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
274 EM_REG_COUNTER_USED(&pStats->StatRZRdmsr, "/EM/CPU%d/RZ/Interpret/Success/Rdmsr", "The number of times RDMSR was successfully interpreted.");
275 EM_REG_COUNTER_USED(&pStats->StatR3Wrmsr, "/EM/CPU%d/R3/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
276 EM_REG_COUNTER_USED(&pStats->StatRZWrmsr, "/EM/CPU%d/RZ/Interpret/Success/Wrmsr", "The number of times WRMSR was successfully interpreted.");
277 EM_REG_COUNTER_USED(&pStats->StatR3StosWD, "/EM/CPU%d/R3/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
278 EM_REG_COUNTER_USED(&pStats->StatRZStosWD, "/EM/CPU%d/RZ/Interpret/Success/Stoswd", "The number of times STOSWD was successfully interpreted.");
279 EM_REG_COUNTER_USED(&pStats->StatRZWbInvd, "/EM/CPU%d/RZ/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
280 EM_REG_COUNTER_USED(&pStats->StatR3WbInvd, "/EM/CPU%d/R3/Interpret/Success/WbInvd", "The number of times WBINVD was successfully interpreted.");
281 EM_REG_COUNTER_USED(&pStats->StatRZLmsw, "/EM/CPU%d/RZ/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
282 EM_REG_COUNTER_USED(&pStats->StatR3Lmsw, "/EM/CPU%d/R3/Interpret/Success/Lmsw", "The number of times LMSW was successfully interpreted.");
283 EM_REG_COUNTER_USED(&pStats->StatRZSmsw, "/EM/CPU%d/RZ/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
284 EM_REG_COUNTER_USED(&pStats->StatR3Smsw, "/EM/CPU%d/R3/Interpret/Success/Smsw", "The number of times SMSW was successfully interpreted.");
285
286 EM_REG_COUNTER(&pStats->StatRZInterpretFailed, "/EM/CPU%d/RZ/Interpret/Failed", "The number of times an instruction was not interpreted.");
287 EM_REG_COUNTER(&pStats->StatR3InterpretFailed, "/EM/CPU%d/R3/Interpret/Failed", "The number of times an instruction was not interpreted.");
288
289 EM_REG_COUNTER_USED(&pStats->StatRZFailedAnd, "/EM/CPU%d/RZ/Interpret/Failed/And", "The number of times AND was not interpreted.");
290 EM_REG_COUNTER_USED(&pStats->StatR3FailedAnd, "/EM/CPU%d/R3/Interpret/Failed/And", "The number of times AND was not interpreted.");
291 EM_REG_COUNTER_USED(&pStats->StatRZFailedCpuId, "/EM/CPU%d/RZ/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
292 EM_REG_COUNTER_USED(&pStats->StatR3FailedCpuId, "/EM/CPU%d/R3/Interpret/Failed/CpuId", "The number of times CPUID was not interpreted.");
293 EM_REG_COUNTER_USED(&pStats->StatRZFailedDec, "/EM/CPU%d/RZ/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
294 EM_REG_COUNTER_USED(&pStats->StatR3FailedDec, "/EM/CPU%d/R3/Interpret/Failed/Dec", "The number of times DEC was not interpreted.");
295 EM_REG_COUNTER_USED(&pStats->StatRZFailedHlt, "/EM/CPU%d/RZ/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
296 EM_REG_COUNTER_USED(&pStats->StatR3FailedHlt, "/EM/CPU%d/R3/Interpret/Failed/Hlt", "The number of times HLT was not interpreted.");
297 EM_REG_COUNTER_USED(&pStats->StatRZFailedInc, "/EM/CPU%d/RZ/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
298 EM_REG_COUNTER_USED(&pStats->StatR3FailedInc, "/EM/CPU%d/R3/Interpret/Failed/Inc", "The number of times INC was not interpreted.");
299 EM_REG_COUNTER_USED(&pStats->StatRZFailedInvlPg, "/EM/CPU%d/RZ/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
300 EM_REG_COUNTER_USED(&pStats->StatR3FailedInvlPg, "/EM/CPU%d/R3/Interpret/Failed/InvlPg", "The number of times INVLPG was not interpreted.");
301 EM_REG_COUNTER_USED(&pStats->StatRZFailedIret, "/EM/CPU%d/RZ/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
302 EM_REG_COUNTER_USED(&pStats->StatR3FailedIret, "/EM/CPU%d/R3/Interpret/Failed/Iret", "The number of times IRET was not interpreted.");
303 EM_REG_COUNTER_USED(&pStats->StatRZFailedLLdt, "/EM/CPU%d/RZ/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
304 EM_REG_COUNTER_USED(&pStats->StatR3FailedLLdt, "/EM/CPU%d/R3/Interpret/Failed/LLdt", "The number of times LLDT was not interpreted.");
305 EM_REG_COUNTER_USED(&pStats->StatRZFailedLIdt, "/EM/CPU%d/RZ/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
306 EM_REG_COUNTER_USED(&pStats->StatR3FailedLIdt, "/EM/CPU%d/R3/Interpret/Failed/LIdt", "The number of times LIDT was not interpreted.");
307 EM_REG_COUNTER_USED(&pStats->StatRZFailedLGdt, "/EM/CPU%d/RZ/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
308 EM_REG_COUNTER_USED(&pStats->StatR3FailedLGdt, "/EM/CPU%d/R3/Interpret/Failed/LGdt", "The number of times LGDT was not interpreted.");
309 EM_REG_COUNTER_USED(&pStats->StatRZFailedMov, "/EM/CPU%d/RZ/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
310 EM_REG_COUNTER_USED(&pStats->StatR3FailedMov, "/EM/CPU%d/R3/Interpret/Failed/Mov", "The number of times MOV was not interpreted.");
311 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovCRx, "/EM/CPU%d/RZ/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
312 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovCRx, "/EM/CPU%d/R3/Interpret/Failed/MovCRx", "The number of times MOV CRx was not interpreted.");
313 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovDRx, "/EM/CPU%d/RZ/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
314 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovDRx, "/EM/CPU%d/R3/Interpret/Failed/MovDRx", "The number of times MOV DRx was not interpreted.");
315 EM_REG_COUNTER_USED(&pStats->StatRZFailedOr, "/EM/CPU%d/RZ/Interpret/Failed/Or", "The number of times OR was not interpreted.");
316 EM_REG_COUNTER_USED(&pStats->StatR3FailedOr, "/EM/CPU%d/R3/Interpret/Failed/Or", "The number of times OR was not interpreted.");
317 EM_REG_COUNTER_USED(&pStats->StatRZFailedPop, "/EM/CPU%d/RZ/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
318 EM_REG_COUNTER_USED(&pStats->StatR3FailedPop, "/EM/CPU%d/R3/Interpret/Failed/Pop", "The number of times POP was not interpreted.");
319 EM_REG_COUNTER_USED(&pStats->StatRZFailedSti, "/EM/CPU%d/RZ/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
320 EM_REG_COUNTER_USED(&pStats->StatR3FailedSti, "/EM/CPU%d/R3/Interpret/Failed/Sti", "The number of times STI was not interpreted.");
321 EM_REG_COUNTER_USED(&pStats->StatRZFailedXchg, "/EM/CPU%d/RZ/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
322 EM_REG_COUNTER_USED(&pStats->StatR3FailedXchg, "/EM/CPU%d/R3/Interpret/Failed/Xchg", "The number of times XCHG was not interpreted.");
323 EM_REG_COUNTER_USED(&pStats->StatRZFailedXor, "/EM/CPU%d/RZ/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
324 EM_REG_COUNTER_USED(&pStats->StatR3FailedXor, "/EM/CPU%d/R3/Interpret/Failed/Xor", "The number of times XOR was not interpreted.");
325 EM_REG_COUNTER_USED(&pStats->StatRZFailedMonitor, "/EM/CPU%d/RZ/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
326 EM_REG_COUNTER_USED(&pStats->StatR3FailedMonitor, "/EM/CPU%d/R3/Interpret/Failed/Monitor", "The number of times MONITOR was not interpreted.");
327 EM_REG_COUNTER_USED(&pStats->StatRZFailedMWait, "/EM/CPU%d/RZ/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
328 EM_REG_COUNTER_USED(&pStats->StatR3FailedMWait, "/EM/CPU%d/R3/Interpret/Failed/MWait", "The number of times MWAIT was not interpreted.");
329 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdtsc, "/EM/CPU%d/RZ/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
330 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdtsc, "/EM/CPU%d/R3/Interpret/Failed/Rdtsc", "The number of times RDTSC was not interpreted.");
331 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdpmc, "/EM/CPU%d/RZ/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
332 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdpmc, "/EM/CPU%d/R3/Interpret/Failed/Rdpmc", "The number of times RDPMC was not interpreted.");
333 EM_REG_COUNTER_USED(&pStats->StatRZFailedRdmsr, "/EM/CPU%d/RZ/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
334 EM_REG_COUNTER_USED(&pStats->StatR3FailedRdmsr, "/EM/CPU%d/R3/Interpret/Failed/Rdmsr", "The number of times RDMSR was not interpreted.");
335 EM_REG_COUNTER_USED(&pStats->StatRZFailedWrmsr, "/EM/CPU%d/RZ/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
336 EM_REG_COUNTER_USED(&pStats->StatR3FailedWrmsr, "/EM/CPU%d/R3/Interpret/Failed/Wrmsr", "The number of times WRMSR was not interpreted.");
337 EM_REG_COUNTER_USED(&pStats->StatRZFailedLmsw, "/EM/CPU%d/RZ/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
338 EM_REG_COUNTER_USED(&pStats->StatR3FailedLmsw, "/EM/CPU%d/R3/Interpret/Failed/Lmsw", "The number of times LMSW was not interpreted.");
339 EM_REG_COUNTER_USED(&pStats->StatRZFailedSmsw, "/EM/CPU%d/RZ/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
340 EM_REG_COUNTER_USED(&pStats->StatR3FailedSmsw, "/EM/CPU%d/R3/Interpret/Failed/Smsw", "The number of times SMSW was not interpreted.");
341
342 EM_REG_COUNTER_USED(&pStats->StatRZFailedMisc, "/EM/CPU%d/RZ/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
343 EM_REG_COUNTER_USED(&pStats->StatR3FailedMisc, "/EM/CPU%d/R3/Interpret/Failed/Misc", "The number of times some misc instruction was encountered.");
344 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdd, "/EM/CPU%d/RZ/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
345 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdd, "/EM/CPU%d/R3/Interpret/Failed/Add", "The number of times ADD was not interpreted.");
346 EM_REG_COUNTER_USED(&pStats->StatRZFailedAdc, "/EM/CPU%d/RZ/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
347 EM_REG_COUNTER_USED(&pStats->StatR3FailedAdc, "/EM/CPU%d/R3/Interpret/Failed/Adc", "The number of times ADC was not interpreted.");
348 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtr, "/EM/CPU%d/RZ/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
349 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtr, "/EM/CPU%d/R3/Interpret/Failed/Btr", "The number of times BTR was not interpreted.");
350 EM_REG_COUNTER_USED(&pStats->StatRZFailedBts, "/EM/CPU%d/RZ/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
351 EM_REG_COUNTER_USED(&pStats->StatR3FailedBts, "/EM/CPU%d/R3/Interpret/Failed/Bts", "The number of times BTS was not interpreted.");
352 EM_REG_COUNTER_USED(&pStats->StatRZFailedBtc, "/EM/CPU%d/RZ/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
353 EM_REG_COUNTER_USED(&pStats->StatR3FailedBtc, "/EM/CPU%d/R3/Interpret/Failed/Btc", "The number of times BTC was not interpreted.");
354 EM_REG_COUNTER_USED(&pStats->StatRZFailedCli, "/EM/CPU%d/RZ/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
355 EM_REG_COUNTER_USED(&pStats->StatR3FailedCli, "/EM/CPU%d/R3/Interpret/Failed/Cli", "The number of times CLI was not interpreted.");
356 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
357 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg", "The number of times CMPXCHG was not interpreted.");
358 EM_REG_COUNTER_USED(&pStats->StatRZFailedCmpXchg8b, "/EM/CPU%d/RZ/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
359 EM_REG_COUNTER_USED(&pStats->StatR3FailedCmpXchg8b, "/EM/CPU%d/R3/Interpret/Failed/CmpXchg8b", "The number of times CMPXCHG8B was not interpreted.");
360 EM_REG_COUNTER_USED(&pStats->StatRZFailedXAdd, "/EM/CPU%d/RZ/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
361 EM_REG_COUNTER_USED(&pStats->StatR3FailedXAdd, "/EM/CPU%d/R3/Interpret/Failed/XAdd", "The number of times XADD was not interpreted.");
362 EM_REG_COUNTER_USED(&pStats->StatRZFailedMovNTPS, "/EM/CPU%d/RZ/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
363 EM_REG_COUNTER_USED(&pStats->StatR3FailedMovNTPS, "/EM/CPU%d/R3/Interpret/Failed/MovNTPS", "The number of times MOVNTPS was not interpreted.");
364 EM_REG_COUNTER_USED(&pStats->StatRZFailedStosWD, "/EM/CPU%d/RZ/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
365 EM_REG_COUNTER_USED(&pStats->StatR3FailedStosWD, "/EM/CPU%d/R3/Interpret/Failed/StosWD", "The number of times STOSWD was not interpreted.");
366 EM_REG_COUNTER_USED(&pStats->StatRZFailedSub, "/EM/CPU%d/RZ/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
367 EM_REG_COUNTER_USED(&pStats->StatR3FailedSub, "/EM/CPU%d/R3/Interpret/Failed/Sub", "The number of times SUB was not interpreted.");
368 EM_REG_COUNTER_USED(&pStats->StatRZFailedWbInvd, "/EM/CPU%d/RZ/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
369 EM_REG_COUNTER_USED(&pStats->StatR3FailedWbInvd, "/EM/CPU%d/R3/Interpret/Failed/WbInvd", "The number of times WBINVD was not interpreted.");
370
371 EM_REG_COUNTER_USED(&pStats->StatRZFailedUserMode, "/EM/CPU%d/RZ/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
372 EM_REG_COUNTER_USED(&pStats->StatR3FailedUserMode, "/EM/CPU%d/R3/Interpret/Failed/UserMode", "The number of rejections because of CPL.");
373 EM_REG_COUNTER_USED(&pStats->StatRZFailedPrefix, "/EM/CPU%d/RZ/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
374 EM_REG_COUNTER_USED(&pStats->StatR3FailedPrefix, "/EM/CPU%d/R3/Interpret/Failed/Prefix", "The number of rejections because of prefix .");
375
376 EM_REG_COUNTER_USED(&pStats->StatCli, "/EM/CPU%d/R3/PrivInst/Cli", "Number of cli instructions.");
377 EM_REG_COUNTER_USED(&pStats->StatSti, "/EM/CPU%d/R3/PrivInst/Sti", "Number of sli instructions.");
378 EM_REG_COUNTER_USED(&pStats->StatIn, "/EM/CPU%d/R3/PrivInst/In", "Number of in instructions.");
379 EM_REG_COUNTER_USED(&pStats->StatOut, "/EM/CPU%d/R3/PrivInst/Out", "Number of out instructions.");
380 EM_REG_COUNTER_USED(&pStats->StatIoRestarted, "/EM/CPU%d/R3/PrivInst/IoRestarted", "Number of restarted i/o instructions.");
381 EM_REG_COUNTER_USED(&pStats->StatHlt, "/EM/CPU%d/R3/PrivInst/Hlt", "Number of hlt instructions not handled in GC because of PATM.");
382 EM_REG_COUNTER_USED(&pStats->StatInvlpg, "/EM/CPU%d/R3/PrivInst/Invlpg", "Number of invlpg instructions.");
383 EM_REG_COUNTER_USED(&pStats->StatMisc, "/EM/CPU%d/R3/PrivInst/Misc", "Number of misc. instructions.");
384 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[0], "/EM/CPU%d/R3/PrivInst/Mov CR0, X", "Number of mov CR0 write instructions.");
385 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[1], "/EM/CPU%d/R3/PrivInst/Mov CR1, X", "Number of mov CR1 write instructions.");
386 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[2], "/EM/CPU%d/R3/PrivInst/Mov CR2, X", "Number of mov CR2 write instructions.");
387 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[3], "/EM/CPU%d/R3/PrivInst/Mov CR3, X", "Number of mov CR3 write instructions.");
388 EM_REG_COUNTER_USED(&pStats->StatMovWriteCR[4], "/EM/CPU%d/R3/PrivInst/Mov CR4, X", "Number of mov CR4 write instructions.");
389 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[0], "/EM/CPU%d/R3/PrivInst/Mov X, CR0", "Number of mov CR0 read instructions.");
390 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[1], "/EM/CPU%d/R3/PrivInst/Mov X, CR1", "Number of mov CR1 read instructions.");
391 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[2], "/EM/CPU%d/R3/PrivInst/Mov X, CR2", "Number of mov CR2 read instructions.");
392 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[3], "/EM/CPU%d/R3/PrivInst/Mov X, CR3", "Number of mov CR3 read instructions.");
393 EM_REG_COUNTER_USED(&pStats->StatMovReadCR[4], "/EM/CPU%d/R3/PrivInst/Mov X, CR4", "Number of mov CR4 read instructions.");
394 EM_REG_COUNTER_USED(&pStats->StatMovDRx, "/EM/CPU%d/R3/PrivInst/MovDRx", "Number of mov DRx instructions.");
395 EM_REG_COUNTER_USED(&pStats->StatIret, "/EM/CPU%d/R3/PrivInst/Iret", "Number of iret instructions.");
396 EM_REG_COUNTER_USED(&pStats->StatMovLgdt, "/EM/CPU%d/R3/PrivInst/Lgdt", "Number of lgdt instructions.");
397 EM_REG_COUNTER_USED(&pStats->StatMovLidt, "/EM/CPU%d/R3/PrivInst/Lidt", "Number of lidt instructions.");
398 EM_REG_COUNTER_USED(&pStats->StatMovLldt, "/EM/CPU%d/R3/PrivInst/Lldt", "Number of lldt instructions.");
399 EM_REG_COUNTER_USED(&pStats->StatSysEnter, "/EM/CPU%d/R3/PrivInst/Sysenter", "Number of sysenter instructions.");
400 EM_REG_COUNTER_USED(&pStats->StatSysExit, "/EM/CPU%d/R3/PrivInst/Sysexit", "Number of sysexit instructions.");
401 EM_REG_COUNTER_USED(&pStats->StatSysCall, "/EM/CPU%d/R3/PrivInst/Syscall", "Number of syscall instructions.");
402 EM_REG_COUNTER_USED(&pStats->StatSysRet, "/EM/CPU%d/R3/PrivInst/Sysret", "Number of sysret instructions.");
403
404 EM_REG_COUNTER(&pVCpu->em.s.StatTotalClis, "/EM/CPU%d/Cli/Total", "Total number of cli instructions executed.");
405 pVCpu->em.s.pCliStatTree = 0;
406
407 /* these should be considered for release statistics. */
408 EM_REG_COUNTER(&pVCpu->em.s.StatIOEmu, "/PROF/CPU%d/EM/Emulation/IO", "Profiling of emR3RawExecuteIOInstruction.");
409 EM_REG_COUNTER(&pVCpu->em.s.StatPrivEmu, "/PROF/CPU%d/EM/Emulation/Priv", "Profiling of emR3RawPrivileged.");
410 EM_REG_PROFILE(&pVCpu->em.s.StatHmEntry, "/PROF/CPU%d/EM/HmEnter", "Profiling Hardware Accelerated Mode entry overhead.");
411 EM_REG_PROFILE(&pVCpu->em.s.StatHmExec, "/PROF/CPU%d/EM/HmExec", "Profiling Hardware Accelerated Mode execution.");
412 EM_REG_PROFILE(&pVCpu->em.s.StatREMEmu, "/PROF/CPU%d/EM/REMEmuSingle", "Profiling single instruction REM execution.");
413 EM_REG_PROFILE(&pVCpu->em.s.StatREMExec, "/PROF/CPU%d/EM/REMExec", "Profiling REM execution.");
414 EM_REG_PROFILE(&pVCpu->em.s.StatREMSync, "/PROF/CPU%d/EM/REMSync", "Profiling REM context syncing.");
415 EM_REG_PROFILE(&pVCpu->em.s.StatRAWEntry, "/PROF/CPU%d/EM/RAWEnter", "Profiling Raw Mode entry overhead.");
416 EM_REG_PROFILE(&pVCpu->em.s.StatRAWExec, "/PROF/CPU%d/EM/RAWExec", "Profiling Raw Mode execution.");
417 EM_REG_PROFILE(&pVCpu->em.s.StatRAWTail, "/PROF/CPU%d/EM/RAWTail", "Profiling Raw Mode tail overhead.");
418
419#endif /* VBOX_WITH_STATISTICS */
420
421 EM_REG_COUNTER(&pVCpu->em.s.StatForcedActions, "/PROF/CPU%d/EM/ForcedActions", "Profiling forced action execution.");
422 EM_REG_COUNTER(&pVCpu->em.s.StatHalted, "/PROF/CPU%d/EM/Halted", "Profiling halted state (VMR3WaitHalted).");
423 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatCapped, "/PROF/CPU%d/EM/Capped", "Profiling capped state (sleep).");
424 EM_REG_COUNTER(&pVCpu->em.s.StatREMTotal, "/PROF/CPU%d/EM/REMTotal", "Profiling emR3RemExecute (excluding FFs).");
425 EM_REG_COUNTER(&pVCpu->em.s.StatRAWTotal, "/PROF/CPU%d/EM/RAWTotal", "Profiling emR3RawExecute (excluding FFs).");
426
427 EM_REG_PROFILE_ADV(&pVCpu->em.s.StatTotal, "/PROF/CPU%d/EM/Total", "Profiling EMR3ExecuteVM.");
428 }
429
430 return VINF_SUCCESS;
431}
432
433
434/**
435 * Applies relocations to data and code managed by this
436 * component. This function will be called at init and
437 * whenever the VMM need to relocate it self inside the GC.
438 *
439 * @param pVM Pointer to the VM.
440 */
441VMMR3_INT_DECL(void) EMR3Relocate(PVM pVM)
442{
443 LogFlow(("EMR3Relocate\n"));
444 for (VMCPUID i = 0; i < pVM->cCpus; i++)
445 {
446 PVMCPU pVCpu = &pVM->aCpus[i];
447 if (pVCpu->em.s.pStatsR3)
448 pVCpu->em.s.pStatsRC = MMHyperR3ToRC(pVM, pVCpu->em.s.pStatsR3);
449 }
450}
451
452
453/**
454 * Reset the EM state for a CPU.
455 *
456 * Called by EMR3Reset and hot plugging.
457 *
458 * @param pVCpu Pointer to the VMCPU.
459 */
460VMMR3_INT_DECL(void) EMR3ResetCpu(PVMCPU pVCpu)
461{
462 pVCpu->em.s.fForceRAW = false;
463
464 /* VMR3Reset may return VINF_EM_RESET or VINF_EM_SUSPEND, so transition
465 out of the HALTED state here so that enmPrevState doesn't end up as
466 HALTED when EMR3Execute returns. */
467 if (pVCpu->em.s.enmState == EMSTATE_HALTED)
468 {
469 Log(("EMR3ResetCpu: Cpu#%u %s -> %s\n", pVCpu->idCpu, emR3GetStateName(pVCpu->em.s.enmState), pVCpu->idCpu == 0 ? "EMSTATE_NONE" : "EMSTATE_WAIT_SIPI"));
470 pVCpu->em.s.enmState = pVCpu->idCpu == 0 ? EMSTATE_NONE : EMSTATE_WAIT_SIPI;
471 }
472}
473
474
475/**
476 * Reset notification.
477 *
478 * @param pVM Pointer to the VM.
479 */
480VMMR3_INT_DECL(void) EMR3Reset(PVM pVM)
481{
482 Log(("EMR3Reset: \n"));
483 for (VMCPUID i = 0; i < pVM->cCpus; i++)
484 EMR3ResetCpu(&pVM->aCpus[i]);
485}
486
487
488/**
489 * Terminates the EM.
490 *
491 * Termination means cleaning up and freeing all resources,
492 * the VM it self is at this point powered off or suspended.
493 *
494 * @returns VBox status code.
495 * @param pVM Pointer to the VM.
496 */
497VMMR3_INT_DECL(int) EMR3Term(PVM pVM)
498{
499 AssertMsg(pVM->em.s.offVM, ("bad init order!\n"));
500
501#ifdef VBOX_WITH_REM
502 PDMR3CritSectDelete(&pVM->em.s.CritSectREM);
503#endif
504 return VINF_SUCCESS;
505}
506
507
508/**
509 * Execute state save operation.
510 *
511 * @returns VBox status code.
512 * @param pVM Pointer to the VM.
513 * @param pSSM SSM operation handle.
514 */
515static DECLCALLBACK(int) emR3Save(PVM pVM, PSSMHANDLE pSSM)
516{
517 for (VMCPUID i = 0; i < pVM->cCpus; i++)
518 {
519 PVMCPU pVCpu = &pVM->aCpus[i];
520
521 int rc = SSMR3PutBool(pSSM, pVCpu->em.s.fForceRAW);
522 AssertRCReturn(rc, rc);
523
524 Assert(pVCpu->em.s.enmState == EMSTATE_SUSPENDED);
525 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
526 rc = SSMR3PutU32(pSSM, pVCpu->em.s.enmPrevState);
527 AssertRCReturn(rc, rc);
528
529 /* Save mwait state. */
530 rc = SSMR3PutU32(pSSM, pVCpu->em.s.MWait.fWait);
531 AssertRCReturn(rc, rc);
532 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRAX);
533 AssertRCReturn(rc, rc);
534 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMWaitRCX);
535 AssertRCReturn(rc, rc);
536 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRAX);
537 AssertRCReturn(rc, rc);
538 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRCX);
539 AssertRCReturn(rc, rc);
540 rc = SSMR3PutGCPtr(pSSM, pVCpu->em.s.MWait.uMonitorRDX);
541 AssertRCReturn(rc, rc);
542 }
543 return VINF_SUCCESS;
544}
545
546
547/**
548 * Execute state load operation.
549 *
550 * @returns VBox status code.
551 * @param pVM Pointer to the VM.
552 * @param pSSM SSM operation handle.
553 * @param uVersion Data layout version.
554 * @param uPass The data pass.
555 */
556static DECLCALLBACK(int) emR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
557{
558 /*
559 * Validate version.
560 */
561 if ( uVersion != EM_SAVED_STATE_VERSION
562 && uVersion != EM_SAVED_STATE_VERSION_PRE_MWAIT
563 && uVersion != EM_SAVED_STATE_VERSION_PRE_SMP)
564 {
565 AssertMsgFailed(("emR3Load: Invalid version uVersion=%d (current %d)!\n", uVersion, EM_SAVED_STATE_VERSION));
566 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
567 }
568 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
569
570 /*
571 * Load the saved state.
572 */
573 for (VMCPUID i = 0; i < pVM->cCpus; i++)
574 {
575 PVMCPU pVCpu = &pVM->aCpus[i];
576
577 int rc = SSMR3GetBool(pSSM, &pVCpu->em.s.fForceRAW);
578 if (RT_FAILURE(rc))
579 pVCpu->em.s.fForceRAW = false;
580 AssertRCReturn(rc, rc);
581
582 if (uVersion > EM_SAVED_STATE_VERSION_PRE_SMP)
583 {
584 AssertCompile(sizeof(pVCpu->em.s.enmPrevState) == sizeof(uint32_t));
585 rc = SSMR3GetU32(pSSM, (uint32_t *)&pVCpu->em.s.enmPrevState);
586 AssertRCReturn(rc, rc);
587 Assert(pVCpu->em.s.enmPrevState != EMSTATE_SUSPENDED);
588
589 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
590 }
591 if (uVersion > EM_SAVED_STATE_VERSION_PRE_MWAIT)
592 {
593 /* Load mwait state. */
594 rc = SSMR3GetU32(pSSM, &pVCpu->em.s.MWait.fWait);
595 AssertRCReturn(rc, rc);
596 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRAX);
597 AssertRCReturn(rc, rc);
598 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMWaitRCX);
599 AssertRCReturn(rc, rc);
600 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRAX);
601 AssertRCReturn(rc, rc);
602 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRCX);
603 AssertRCReturn(rc, rc);
604 rc = SSMR3GetGCPtr(pSSM, &pVCpu->em.s.MWait.uMonitorRDX);
605 AssertRCReturn(rc, rc);
606 }
607
608 Assert(!pVCpu->em.s.pCliStatTree);
609 }
610 return VINF_SUCCESS;
611}
612
613
614/**
615 * Argument packet for emR3SetExecutionPolicy.
616 */
617struct EMR3SETEXECPOLICYARGS
618{
619 EMEXECPOLICY enmPolicy;
620 bool fEnforce;
621};
622
623
624/**
625 * @callback_method_impl{FNVMMEMTRENDEZVOUS, Rendezvous callback for EMR3SetExecutionPolicy.}
626 */
627static DECLCALLBACK(VBOXSTRICTRC) emR3SetExecutionPolicy(PVM pVM, PVMCPU pVCpu, void *pvUser)
628{
629 /*
630 * Only the first CPU changes the variables.
631 */
632 if (pVCpu->idCpu == 0)
633 {
634 struct EMR3SETEXECPOLICYARGS *pArgs = (struct EMR3SETEXECPOLICYARGS *)pvUser;
635 switch (pArgs->enmPolicy)
636 {
637 case EMEXECPOLICY_RECOMPILE_RING0:
638 pVM->fRecompileSupervisor = pArgs->fEnforce;
639 break;
640 case EMEXECPOLICY_RECOMPILE_RING3:
641 pVM->fRecompileUser = pArgs->fEnforce;
642 break;
643 default:
644 AssertFailedReturn(VERR_INVALID_PARAMETER);
645 }
646 Log(("emR3SetExecutionPolicy: fRecompileUser=%RTbool fRecompileSupervisor=%RTbool\n",
647 pVM->fRecompileUser, pVM->fRecompileSupervisor));
648 }
649
650 /*
651 * Force rescheduling if in RAW, HM or REM.
652 */
653 return pVCpu->em.s.enmState == EMSTATE_RAW
654 || pVCpu->em.s.enmState == EMSTATE_HM
655 || pVCpu->em.s.enmState == EMSTATE_REM
656 ? VINF_EM_RESCHEDULE
657 : VINF_SUCCESS;
658}
659
660
661/**
662 * Changes a the execution scheduling policy.
663 *
664 * This is used to enable or disable raw-mode / hardware-virtualization
665 * execution of user and supervisor code.
666 *
667 * @returns VINF_SUCCESS on success.
668 * @returns VINF_RESCHEDULE if a rescheduling might be required.
669 * @returns VERR_INVALID_PARAMETER on an invalid enmMode value.
670 *
671 * @param pUVM The user mode VM handle.
672 * @param enmPolicy The scheduling policy to change.
673 * @param fEnforce Whether to enforce the policy or not.
674 */
675VMMR3DECL(int) EMR3SetExecutionPolicy(PUVM pUVM, EMEXECPOLICY enmPolicy, bool fEnforce)
676{
677 UVM_ASSERT_VALID_EXT_RETURN(pUVM, VERR_INVALID_VM_HANDLE);
678 VM_ASSERT_VALID_EXT_RETURN(pUVM->pVM, VERR_INVALID_VM_HANDLE);
679 AssertReturn(enmPolicy > EMEXECPOLICY_INVALID && enmPolicy < EMEXECPOLICY_END, VERR_INVALID_PARAMETER);
680
681 struct EMR3SETEXECPOLICYARGS Args = { enmPolicy, fEnforce };
682 return VMMR3EmtRendezvous(pUVM->pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_DESCENDING, emR3SetExecutionPolicy, &Args);
683}
684
685
686/**
687 * Checks if raw ring-3 execute mode is enabled.
688 *
689 * @returns true if enabled, false if disabled.
690 * @param pUVM The user mode VM handle.
691 */
692VMMR3DECL(bool) EMR3IsRawRing3Enabled(PUVM pUVM)
693{
694 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
695 PVM pVM = pUVM->pVM;
696 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
697 return EMIsRawRing3Enabled(pVM);
698}
699
700
701/**
702 * Checks if raw ring-0 execute mode is enabled.
703 *
704 * @returns true if enabled, false if disabled.
705 * @param pUVM The user mode VM handle.
706 */
707VMMR3DECL(bool) EMR3IsRawRing0Enabled(PUVM pUVM)
708{
709 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
710 PVM pVM = pUVM->pVM;
711 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
712 return EMIsRawRing0Enabled(pVM);
713}
714
715
716/**
717 * Raise a fatal error.
718 *
719 * Safely terminate the VM with full state report and stuff. This function
720 * will naturally never return.
721 *
722 * @param pVCpu Pointer to the VMCPU.
723 * @param rc VBox status code.
724 */
725VMMR3DECL(void) EMR3FatalError(PVMCPU pVCpu, int rc)
726{
727 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
728 longjmp(pVCpu->em.s.u.FatalLongJump, rc);
729 AssertReleaseMsgFailed(("longjmp returned!\n"));
730}
731
732
733#if defined(LOG_ENABLED) || defined(VBOX_STRICT)
734/**
735 * Gets the EM state name.
736 *
737 * @returns pointer to read only state name,
738 * @param enmState The state.
739 */
740static const char *emR3GetStateName(EMSTATE enmState)
741{
742 switch (enmState)
743 {
744 case EMSTATE_NONE: return "EMSTATE_NONE";
745 case EMSTATE_RAW: return "EMSTATE_RAW";
746 case EMSTATE_HM: return "EMSTATE_HM";
747 case EMSTATE_REM: return "EMSTATE_REM";
748 case EMSTATE_HALTED: return "EMSTATE_HALTED";
749 case EMSTATE_WAIT_SIPI: return "EMSTATE_WAIT_SIPI";
750 case EMSTATE_SUSPENDED: return "EMSTATE_SUSPENDED";
751 case EMSTATE_TERMINATING: return "EMSTATE_TERMINATING";
752 case EMSTATE_DEBUG_GUEST_RAW: return "EMSTATE_DEBUG_GUEST_RAW";
753 case EMSTATE_DEBUG_GUEST_REM: return "EMSTATE_DEBUG_GUEST_REM";
754 case EMSTATE_DEBUG_HYPER: return "EMSTATE_DEBUG_HYPER";
755 case EMSTATE_GURU_MEDITATION: return "EMSTATE_GURU_MEDITATION";
756 default: return "Unknown!";
757 }
758}
759#endif /* LOG_ENABLED || VBOX_STRICT */
760
761
762/**
763 * Debug loop.
764 *
765 * @returns VBox status code for EM.
766 * @param pVM Pointer to the VM.
767 * @param pVCpu Pointer to the VMCPU.
768 * @param rc Current EM VBox status code.
769 */
770static int emR3Debug(PVM pVM, PVMCPU pVCpu, int rc)
771{
772 for (;;)
773 {
774 Log(("emR3Debug: rc=%Rrc\n", rc));
775 const int rcLast = rc;
776
777 /*
778 * Debug related RC.
779 */
780 switch (rc)
781 {
782 /*
783 * Single step an instruction.
784 */
785 case VINF_EM_DBG_STEP:
786#ifdef VBOX_WITH_RAW_MODE
787 if ( pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
788 || pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
789 || pVCpu->em.s.fForceRAW /* paranoia */)
790 rc = emR3RawStep(pVM, pVCpu);
791 else
792 {
793 Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
794 rc = emR3RemStep(pVM, pVCpu);
795 }
796#else
797 AssertLogRelMsgFailed(("%Rrc\n", rc));
798 rc = VERR_EM_INTERNAL_ERROR;
799#endif
800 break;
801
802 /*
803 * Simple events: stepped, breakpoint, stop/assertion.
804 */
805 case VINF_EM_DBG_STEPPED:
806 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED);
807 break;
808
809 case VINF_EM_DBG_BREAKPOINT:
810 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT);
811 break;
812
813 case VINF_EM_DBG_STOP:
814 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, NULL, 0, NULL, NULL);
815 break;
816
817 case VINF_EM_DBG_HYPER_STEPPED:
818 rc = DBGFR3Event(pVM, DBGFEVENT_STEPPED_HYPER);
819 break;
820
821 case VINF_EM_DBG_HYPER_BREAKPOINT:
822 rc = DBGFR3EventBreakpoint(pVM, DBGFEVENT_BREAKPOINT_HYPER);
823 break;
824
825 case VINF_EM_DBG_HYPER_ASSERTION:
826 RTPrintf("\nVINF_EM_DBG_HYPER_ASSERTION:\n%s%s\n", VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
827 RTLogFlush(NULL);
828 rc = DBGFR3EventAssertion(pVM, DBGFEVENT_ASSERTION_HYPER, VMMR3GetRZAssertMsg1(pVM), VMMR3GetRZAssertMsg2(pVM));
829 break;
830
831 /*
832 * Guru meditation.
833 */
834 case VERR_VMM_RING0_ASSERTION: /** @todo Make a guru meditation event! */
835 rc = DBGFR3EventSrc(pVM, DBGFEVENT_FATAL_ERROR, "VERR_VMM_RING0_ASSERTION", 0, NULL, NULL);
836 break;
837 case VERR_REM_TOO_MANY_TRAPS: /** @todo Make a guru meditation event! */
838 rc = DBGFR3EventSrc(pVM, DBGFEVENT_DEV_STOP, "VERR_REM_TOO_MANY_TRAPS", 0, NULL, NULL);
839 break;
840
841 default: /** @todo don't use default for guru, but make special errors code! */
842 rc = DBGFR3Event(pVM, DBGFEVENT_FATAL_ERROR);
843 break;
844 }
845
846 /*
847 * Process the result.
848 */
849 do
850 {
851 switch (rc)
852 {
853 /*
854 * Continue the debugging loop.
855 */
856 case VINF_EM_DBG_STEP:
857 case VINF_EM_DBG_STOP:
858 case VINF_EM_DBG_STEPPED:
859 case VINF_EM_DBG_BREAKPOINT:
860 case VINF_EM_DBG_HYPER_STEPPED:
861 case VINF_EM_DBG_HYPER_BREAKPOINT:
862 case VINF_EM_DBG_HYPER_ASSERTION:
863 break;
864
865 /*
866 * Resuming execution (in some form) has to be done here if we got
867 * a hypervisor debug event.
868 */
869 case VINF_SUCCESS:
870 case VINF_EM_RESUME:
871 case VINF_EM_SUSPEND:
872 case VINF_EM_RESCHEDULE:
873 case VINF_EM_RESCHEDULE_RAW:
874 case VINF_EM_RESCHEDULE_REM:
875 case VINF_EM_HALT:
876 if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
877 {
878#ifdef VBOX_WITH_RAW_MODE
879 rc = emR3RawResumeHyper(pVM, pVCpu);
880 if (rc != VINF_SUCCESS && RT_SUCCESS(rc))
881 continue;
882#else
883 AssertLogRelMsgFailedReturn(("Not implemented\n", rc), VERR_EM_INTERNAL_ERROR);
884#endif
885 }
886 if (rc == VINF_SUCCESS)
887 rc = VINF_EM_RESCHEDULE;
888 return rc;
889
890 /*
891 * The debugger isn't attached.
892 * We'll simply turn the thing off since that's the easiest thing to do.
893 */
894 case VERR_DBGF_NOT_ATTACHED:
895 switch (rcLast)
896 {
897 case VINF_EM_DBG_HYPER_STEPPED:
898 case VINF_EM_DBG_HYPER_BREAKPOINT:
899 case VINF_EM_DBG_HYPER_ASSERTION:
900 case VERR_TRPM_PANIC:
901 case VERR_TRPM_DONT_PANIC:
902 case VERR_VMM_RING0_ASSERTION:
903 case VERR_VMM_HYPER_CR3_MISMATCH:
904 case VERR_VMM_RING3_CALL_DISABLED:
905 return rcLast;
906 }
907 return VINF_EM_OFF;
908
909 /*
910 * Status codes terminating the VM in one or another sense.
911 */
912 case VINF_EM_TERMINATE:
913 case VINF_EM_OFF:
914 case VINF_EM_RESET:
915 case VINF_EM_NO_MEMORY:
916 case VINF_EM_RAW_STALE_SELECTOR:
917 case VINF_EM_RAW_IRET_TRAP:
918 case VERR_TRPM_PANIC:
919 case VERR_TRPM_DONT_PANIC:
920 case VERR_IEM_INSTR_NOT_IMPLEMENTED:
921 case VERR_IEM_ASPECT_NOT_IMPLEMENTED:
922 case VERR_VMM_RING0_ASSERTION:
923 case VERR_VMM_HYPER_CR3_MISMATCH:
924 case VERR_VMM_RING3_CALL_DISABLED:
925 case VERR_INTERNAL_ERROR:
926 case VERR_INTERNAL_ERROR_2:
927 case VERR_INTERNAL_ERROR_3:
928 case VERR_INTERNAL_ERROR_4:
929 case VERR_INTERNAL_ERROR_5:
930 case VERR_IPE_UNEXPECTED_STATUS:
931 case VERR_IPE_UNEXPECTED_INFO_STATUS:
932 case VERR_IPE_UNEXPECTED_ERROR_STATUS:
933 return rc;
934
935 /*
936 * The rest is unexpected, and will keep us here.
937 */
938 default:
939 AssertMsgFailed(("Unexpected rc %Rrc!\n", rc));
940 break;
941 }
942 } while (false);
943 } /* debug for ever */
944}
945
946/**
947 * Steps recompiled code.
948 *
949 * @returns VBox status code. The most important ones are: VINF_EM_STEP_EVENT,
950 * VINF_EM_RESCHEDULE, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
951 *
952 * @param pVM Pointer to the VM.
953 * @param pVCpu Pointer to the VMCPU.
954 */
955static int emR3RemStep(PVM pVM, PVMCPU pVCpu)
956{
957 Log3(("emR3RemStep: cs:eip=%04x:%08x\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
958
959#ifdef VBOX_WITH_REM
960 EMRemLock(pVM);
961
962 /*
963 * Switch to REM, step instruction, switch back.
964 */
965 int rc = REMR3State(pVM, pVCpu);
966 if (RT_SUCCESS(rc))
967 {
968 rc = REMR3Step(pVM, pVCpu);
969 REMR3StateBack(pVM, pVCpu);
970 }
971 EMRemUnlock(pVM);
972
973#else
974 int rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); NOREF(pVM);
975#endif
976
977 Log3(("emR3RemStep: returns %Rrc cs:eip=%04x:%08x\n", rc, CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
978 return rc;
979}
980
981
982/**
983 * emR3RemExecute helper that syncs the state back from REM and leave the REM
984 * critical section.
985 *
986 * @returns false - new fInREMState value.
987 * @param pVM Pointer to the VM.
988 * @param pVCpu Pointer to the VMCPU.
989 */
990DECLINLINE(bool) emR3RemExecuteSyncBack(PVM pVM, PVMCPU pVCpu)
991{
992#ifdef VBOX_WITH_REM
993 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, a);
994 REMR3StateBack(pVM, pVCpu);
995 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, a);
996
997 EMRemUnlock(pVM);
998#endif
999 return false;
1000}
1001
1002
1003/**
1004 * Executes recompiled code.
1005 *
1006 * This function contains the recompiler version of the inner
1007 * execution loop (the outer loop being in EMR3ExecuteVM()).
1008 *
1009 * @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1010 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1011 *
1012 * @param pVM Pointer to the VM.
1013 * @param pVCpu Pointer to the VMCPU.
1014 * @param pfFFDone Where to store an indicator telling whether or not
1015 * FFs were done before returning.
1016 *
1017 */
1018static int emR3RemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1019{
1020#ifdef LOG_ENABLED
1021 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1022 uint32_t cpl = CPUMGetGuestCPL(pVCpu);
1023
1024 if (pCtx->eflags.Bits.u1VM)
1025 Log(("EMV86: %04X:%08X IF=%d\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF));
1026 else
1027 Log(("EMR%d: %04X:%08X ESP=%08X IF=%d CR0=%x eflags=%x\n", cpl, pCtx->cs.Sel, pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, (uint32_t)pCtx->cr0, pCtx->eflags.u));
1028#endif
1029 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatREMTotal, a);
1030
1031#if defined(VBOX_STRICT) && defined(DEBUG_bird)
1032 AssertMsg( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1033 || !MMHyperIsInsideArea(pVM, CPUMGetGuestEIP(pVCpu)), /** @todo @bugref{1419} - get flat address. */
1034 ("cs:eip=%RX16:%RX32\n", CPUMGetGuestCS(pVCpu), CPUMGetGuestEIP(pVCpu)));
1035#endif
1036
1037 /*
1038 * Spin till we get a forced action which returns anything but VINF_SUCCESS
1039 * or the REM suggests raw-mode execution.
1040 */
1041 *pfFFDone = false;
1042#ifdef VBOX_WITH_REM
1043 bool fInREMState = false;
1044#endif
1045 int rc = VINF_SUCCESS;
1046 for (;;)
1047 {
1048#ifdef VBOX_WITH_REM
1049 /*
1050 * Lock REM and update the state if not already in sync.
1051 *
1052 * Note! Big lock, but you are not supposed to own any lock when
1053 * coming in here.
1054 */
1055 if (!fInREMState)
1056 {
1057 EMRemLock(pVM);
1058 STAM_PROFILE_START(&pVCpu->em.s.StatREMSync, b);
1059
1060 /* Flush the recompiler translation blocks if the VCPU has changed,
1061 also force a full CPU state resync. */
1062 if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
1063 {
1064 REMFlushTBs(pVM);
1065 CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
1066 }
1067 pVM->em.s.idLastRemCpu = pVCpu->idCpu;
1068
1069 rc = REMR3State(pVM, pVCpu);
1070
1071 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMSync, b);
1072 if (RT_FAILURE(rc))
1073 break;
1074 fInREMState = true;
1075
1076 /*
1077 * We might have missed the raising of VMREQ, TIMER and some other
1078 * important FFs while we were busy switching the state. So, check again.
1079 */
1080 if ( VM_FF_ISPENDING(pVM, VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_RESET)
1081 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER | VMCPU_FF_REQUEST))
1082 {
1083 LogFlow(("emR3RemExecute: Skipping run, because FF is set. %#x\n", pVM->fGlobalForcedActions));
1084 goto l_REMDoForcedActions;
1085 }
1086 }
1087#endif
1088
1089 /*
1090 * Execute REM.
1091 */
1092 if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1093 {
1094 STAM_PROFILE_START(&pVCpu->em.s.StatREMExec, c);
1095#ifdef VBOX_WITH_REM
1096 rc = REMR3Run(pVM, pVCpu);
1097#else
1098 rc = VBOXSTRICTRC_TODO(IEMExecLots(pVCpu));
1099#endif
1100 STAM_PROFILE_STOP(&pVCpu->em.s.StatREMExec, c);
1101 }
1102 else
1103 {
1104 /* Give up this time slice; virtual time continues */
1105 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1106 RTThreadSleep(5);
1107 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1108 rc = VINF_SUCCESS;
1109 }
1110
1111 /*
1112 * Deal with high priority post execution FFs before doing anything
1113 * else. Sync back the state and leave the lock to be on the safe side.
1114 */
1115 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1116 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1117 {
1118#ifdef VBOX_WITH_REM
1119 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1120#endif
1121 rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1122 }
1123
1124 /*
1125 * Process the returned status code.
1126 */
1127 if (rc != VINF_SUCCESS)
1128 {
1129 if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1130 break;
1131 if (rc != VINF_REM_INTERRUPED_FF)
1132 {
1133 /*
1134 * Anything which is not known to us means an internal error
1135 * and the termination of the VM!
1136 */
1137 AssertMsg(rc == VERR_REM_TOO_MANY_TRAPS, ("Unknown GC return code: %Rra\n", rc));
1138 break;
1139 }
1140 }
1141
1142
1143 /*
1144 * Check and execute forced actions.
1145 *
1146 * Sync back the VM state and leave the lock before calling any of
1147 * these, you never know what's going to happen here.
1148 */
1149#ifdef VBOX_HIGH_RES_TIMERS_HACK
1150 TMTimerPollVoid(pVM, pVCpu);
1151#endif
1152 AssertCompile(VMCPU_FF_ALL_REM_MASK & VMCPU_FF_TIMER);
1153 if ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
1154 || VMCPU_FF_ISPENDING(pVCpu,
1155 VMCPU_FF_ALL_REM_MASK
1156 & VM_WHEN_RAW_MODE(~(VMCPU_FF_CSAM_PENDING_ACTION | VMCPU_FF_CSAM_SCAN_PAGE), UINT32_MAX)) )
1157 {
1158l_REMDoForcedActions:
1159#ifdef VBOX_WITH_REM
1160 if (fInREMState)
1161 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1162#endif
1163 STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatREMTotal, a);
1164 rc = emR3ForcedActions(pVM, pVCpu, rc);
1165 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1166 STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatREMTotal, a);
1167 if ( rc != VINF_SUCCESS
1168 && rc != VINF_EM_RESCHEDULE_REM)
1169 {
1170 *pfFFDone = true;
1171 break;
1172 }
1173 }
1174
1175 } /* The Inner Loop, recompiled execution mode version. */
1176
1177
1178#ifdef VBOX_WITH_REM
1179 /*
1180 * Returning. Sync back the VM state if required.
1181 */
1182 if (fInREMState)
1183 fInREMState = emR3RemExecuteSyncBack(pVM, pVCpu);
1184#endif
1185
1186 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatREMTotal, a);
1187 return rc;
1188}
1189
1190
1191#ifdef DEBUG
1192
1193int emR3SingleStepExecRem(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
1194{
1195 EMSTATE enmOldState = pVCpu->em.s.enmState;
1196
1197 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
1198
1199 Log(("Single step BEGIN:\n"));
1200 for (uint32_t i = 0; i < cIterations; i++)
1201 {
1202 DBGFR3PrgStep(pVCpu);
1203 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
1204 emR3RemStep(pVM, pVCpu);
1205 if (emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx) != EMSTATE_REM)
1206 break;
1207 }
1208 Log(("Single step END:\n"));
1209 CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
1210 pVCpu->em.s.enmState = enmOldState;
1211 return VINF_EM_RESCHEDULE;
1212}
1213
1214#endif /* DEBUG */
1215
1216
1217/**
1218 * Decides whether to execute RAW, HWACC or REM.
1219 *
1220 * @returns new EM state
1221 * @param pVM Pointer to the VM.
1222 * @param pVCpu Pointer to the VMCPU.
1223 * @param pCtx Pointer to the guest CPU context.
1224 */
1225EMSTATE emR3Reschedule(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1226{
1227#ifdef IEM_VERIFICATION_MODE
1228 return EMSTATE_REM;
1229#else
1230
1231 /*
1232 * When forcing raw-mode execution, things are simple.
1233 */
1234 if (pVCpu->em.s.fForceRAW)
1235 return EMSTATE_RAW;
1236
1237 /*
1238 * We stay in the wait for SIPI state unless explicitly told otherwise.
1239 */
1240 if (pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI)
1241 return EMSTATE_WAIT_SIPI;
1242
1243 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1244 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1245 /* !!! THIS MUST BE IN SYNC WITH remR3CanExecuteRaw !!! */
1246
1247 X86EFLAGS EFlags = pCtx->eflags;
1248 if (HMIsEnabled(pVM))
1249 {
1250 /*
1251 * Hardware accelerated raw-mode:
1252 *
1253 * Typically only 32-bits protected mode, with paging enabled, code is
1254 * allowed here.
1255 */
1256 if ( EMIsHwVirtExecutionEnabled(pVM)
1257 && HMR3CanExecuteGuest(pVM, pCtx))
1258 return EMSTATE_HM;
1259
1260 /*
1261 * Note! Raw mode and hw accelerated mode are incompatible. The latter
1262 * turns off monitoring features essential for raw mode!
1263 */
1264 return EMSTATE_REM;
1265 }
1266
1267 /*
1268 * Standard raw-mode:
1269 *
1270 * Here we only support 16 & 32 bits protected mode ring 3 code that has no IO privileges
1271 * or 32 bits protected mode ring 0 code
1272 *
1273 * The tests are ordered by the likelihood of being true during normal execution.
1274 */
1275 if (EFlags.u32 & (X86_EFL_TF /* | HF_INHIBIT_IRQ_MASK*/))
1276 {
1277 Log2(("raw mode refused: EFlags=%#x\n", EFlags.u32));
1278 return EMSTATE_REM;
1279 }
1280
1281# ifndef VBOX_RAW_V86
1282 if (EFlags.u32 & X86_EFL_VM) {
1283 Log2(("raw mode refused: VM_MASK\n"));
1284 return EMSTATE_REM;
1285 }
1286# endif
1287
1288 /** @todo check up the X86_CR0_AM flag in respect to raw mode!!! We're probably not emulating it right! */
1289 uint32_t u32CR0 = pCtx->cr0;
1290 if ((u32CR0 & (X86_CR0_PG | X86_CR0_PE)) != (X86_CR0_PG | X86_CR0_PE))
1291 {
1292 //Log2(("raw mode refused: %s%s%s\n", (u32CR0 & X86_CR0_PG) ? "" : " !PG", (u32CR0 & X86_CR0_PE) ? "" : " !PE", (u32CR0 & X86_CR0_AM) ? "" : " !AM"));
1293 return EMSTATE_REM;
1294 }
1295
1296 if (pCtx->cr4 & X86_CR4_PAE)
1297 {
1298 uint32_t u32Dummy, u32Features;
1299
1300 CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32Dummy, &u32Features);
1301 if (!(u32Features & X86_CPUID_FEATURE_EDX_PAE))
1302 return EMSTATE_REM;
1303 }
1304
1305 unsigned uSS = pCtx->ss.Sel;
1306 if ( pCtx->eflags.Bits.u1VM
1307 || (uSS & X86_SEL_RPL) == 3)
1308 {
1309 if (!EMIsRawRing3Enabled(pVM))
1310 return EMSTATE_REM;
1311
1312 if (!(EFlags.u32 & X86_EFL_IF))
1313 {
1314 Log2(("raw mode refused: IF (RawR3)\n"));
1315 return EMSTATE_REM;
1316 }
1317
1318 if (!(u32CR0 & X86_CR0_WP) && EMIsRawRing0Enabled(pVM))
1319 {
1320 Log2(("raw mode refused: CR0.WP + RawR0\n"));
1321 return EMSTATE_REM;
1322 }
1323 }
1324 else
1325 {
1326 if (!EMIsRawRing0Enabled(pVM))
1327 return EMSTATE_REM;
1328
1329 if (EMIsRawRing1Enabled(pVM))
1330 {
1331 /* Only ring 0 and 1 supervisor code. */
1332 if ((uSS & X86_SEL_RPL) == 2) /* ring 1 code is moved into ring 2, so we can't support ring-2 in that case. */
1333 {
1334 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1335 return EMSTATE_REM;
1336 }
1337 }
1338 /* Only ring 0 supervisor code. */
1339 else if ((uSS & X86_SEL_RPL) != 0)
1340 {
1341 Log2(("raw r0 mode refused: CPL %d\n", uSS & X86_SEL_RPL));
1342 return EMSTATE_REM;
1343 }
1344
1345 // Let's start with pure 32 bits ring 0 code first
1346 /** @todo What's pure 32-bit mode? flat? */
1347 if ( !(pCtx->ss.Attr.n.u1DefBig)
1348 || !(pCtx->cs.Attr.n.u1DefBig))
1349 {
1350 Log2(("raw r0 mode refused: SS/CS not 32bit\n"));
1351 return EMSTATE_REM;
1352 }
1353
1354 /* Write protection must be turned on, or else the guest can overwrite our hypervisor code and data. */
1355 if (!(u32CR0 & X86_CR0_WP))
1356 {
1357 Log2(("raw r0 mode refused: CR0.WP=0!\n"));
1358 return EMSTATE_REM;
1359 }
1360
1361# ifdef VBOX_WITH_RAW_MODE
1362 if (PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip))
1363 {
1364 Log2(("raw r0 mode forced: patch code\n"));
1365# ifdef VBOX_WITH_SAFE_STR
1366 Assert(pCtx->tr.Sel);
1367# endif
1368 return EMSTATE_RAW;
1369 }
1370# endif /* VBOX_WITH_RAW_MODE */
1371
1372# if !defined(VBOX_ALLOW_IF0) && !defined(VBOX_RUN_INTERRUPT_GATE_HANDLERS)
1373 if (!(EFlags.u32 & X86_EFL_IF))
1374 {
1375 ////Log2(("R0: IF=0 VIF=%d %08X\n", eip, pVMeflags));
1376 //Log2(("RR0: Interrupts turned off; fall back to emulation\n"));
1377 return EMSTATE_REM;
1378 }
1379# endif
1380
1381# ifndef VBOX_WITH_RAW_RING1
1382 /** @todo still necessary??? */
1383 if (EFlags.Bits.u2IOPL != 0)
1384 {
1385 Log2(("raw r0 mode refused: IOPL %d\n", EFlags.Bits.u2IOPL));
1386 return EMSTATE_REM;
1387 }
1388# endif
1389 }
1390
1391 /*
1392 * Stale hidden selectors means raw-mode is unsafe (being very careful).
1393 */
1394 if (pCtx->cs.fFlags & CPUMSELREG_FLAGS_STALE)
1395 {
1396 Log2(("raw mode refused: stale CS\n"));
1397 return EMSTATE_REM;
1398 }
1399 if (pCtx->ss.fFlags & CPUMSELREG_FLAGS_STALE)
1400 {
1401 Log2(("raw mode refused: stale SS\n"));
1402 return EMSTATE_REM;
1403 }
1404 if (pCtx->ds.fFlags & CPUMSELREG_FLAGS_STALE)
1405 {
1406 Log2(("raw mode refused: stale DS\n"));
1407 return EMSTATE_REM;
1408 }
1409 if (pCtx->es.fFlags & CPUMSELREG_FLAGS_STALE)
1410 {
1411 Log2(("raw mode refused: stale ES\n"));
1412 return EMSTATE_REM;
1413 }
1414 if (pCtx->fs.fFlags & CPUMSELREG_FLAGS_STALE)
1415 {
1416 Log2(("raw mode refused: stale FS\n"));
1417 return EMSTATE_REM;
1418 }
1419 if (pCtx->gs.fFlags & CPUMSELREG_FLAGS_STALE)
1420 {
1421 Log2(("raw mode refused: stale GS\n"));
1422 return EMSTATE_REM;
1423 }
1424
1425# ifdef VBOX_WITH_SAFE_STR
1426 if (pCtx->tr.Sel == 0)
1427 {
1428 Log(("Raw mode refused -> TR=0\n"));
1429 return EMSTATE_REM;
1430 }
1431# endif
1432
1433 /*Assert(PGMPhysIsA20Enabled(pVCpu));*/
1434 return EMSTATE_RAW;
1435#endif /* !IEM_VERIFICATION_MODE */
1436
1437}
1438
1439
1440/**
1441 * Executes all high priority post execution force actions.
1442 *
1443 * @returns rc or a fatal status code.
1444 *
1445 * @param pVM Pointer to the VM.
1446 * @param pVCpu Pointer to the VMCPU.
1447 * @param rc The current rc.
1448 */
1449int emR3HighPriorityPostForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1450{
1451 VBOXVMM_EM_FF_HIGH(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1452
1453 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PDM_CRITSECT))
1454 PDMCritSectBothFF(pVCpu);
1455
1456 /* Update CR3 (Nested Paging case for HM). */
1457 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3))
1458 {
1459 int rc2 = PGMUpdateCR3(pVCpu, CPUMGetGuestCR3(pVCpu));
1460 if (RT_FAILURE(rc2))
1461 return rc2;
1462 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_CR3));
1463 }
1464
1465 /* Update PAE PDPEs. This must be done *after* PGMUpdateCR3() and used only by the Nested Paging case for HM. */
1466 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES))
1467 {
1468 if (CPUMIsGuestInPAEMode(pVCpu))
1469 {
1470 PX86PDPE pPdpes = HMGetPaePdpes(pVCpu);
1471 AssertPtr(pPdpes);
1472
1473 int rc2 = PGMGstUpdatePaePdpes(pVCpu, pPdpes);
1474 if (RT_FAILURE(rc2))
1475 return rc2;
1476 Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES));
1477 }
1478 else
1479 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_HM_UPDATE_PAE_PDPES);
1480 }
1481
1482#ifdef VBOX_WITH_RAW_MODE
1483 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_PENDING_ACTION))
1484 CSAMR3DoPendingAction(pVM, pVCpu);
1485#endif
1486
1487 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1488 {
1489 if ( rc > VINF_EM_NO_MEMORY
1490 && rc <= VINF_EM_LAST)
1491 rc = VINF_EM_NO_MEMORY;
1492 }
1493
1494 return rc;
1495}
1496
1497
1498/**
1499 * Executes all pending forced actions.
1500 *
1501 * Forced actions can cause execution delays and execution
1502 * rescheduling. The first we deal with using action priority, so
1503 * that for instance pending timers aren't scheduled and ran until
1504 * right before execution. The rescheduling we deal with using
1505 * return codes. The same goes for VM termination, only in that case
1506 * we exit everything.
1507 *
1508 * @returns VBox status code of equal or greater importance/severity than rc.
1509 * The most important ones are: VINF_EM_RESCHEDULE,
1510 * VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1511 *
1512 * @param pVM Pointer to the VM.
1513 * @param pVCpu Pointer to the VMCPU.
1514 * @param rc The current rc.
1515 *
1516 */
1517int emR3ForcedActions(PVM pVM, PVMCPU pVCpu, int rc)
1518{
1519 STAM_REL_PROFILE_START(&pVCpu->em.s.StatForcedActions, a);
1520#ifdef VBOX_STRICT
1521 int rcIrq = VINF_SUCCESS;
1522#endif
1523 int rc2;
1524#define UPDATE_RC() \
1525 do { \
1526 AssertMsg(rc2 <= 0 || (rc2 >= VINF_EM_FIRST && rc2 <= VINF_EM_LAST), ("Invalid FF return code: %Rra\n", rc2)); \
1527 if (rc2 == VINF_SUCCESS || rc < VINF_SUCCESS) \
1528 break; \
1529 if (!rc || rc2 < rc) \
1530 rc = rc2; \
1531 } while (0)
1532 VBOXVMM_EM_FF_ALL(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions, rc);
1533
1534 /*
1535 * Post execution chunk first.
1536 */
1537 if ( VM_FF_ISPENDING(pVM, VM_FF_NORMAL_PRIORITY_POST_MASK)
1538 || (VMCPU_FF_NORMAL_PRIORITY_POST_MASK && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_POST_MASK)) )
1539 {
1540 /*
1541 * EMT Rendezvous (must be serviced before termination).
1542 */
1543 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1544 {
1545 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1546 UPDATE_RC();
1547 /** @todo HACK ALERT! The following test is to make sure EM+TM
1548 * thinks the VM is stopped/reset before the next VM state change
1549 * is made. We need a better solution for this, or at least make it
1550 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1551 * VINF_EM_SUSPEND). */
1552 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1553 {
1554 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1555 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1556 return rc;
1557 }
1558 }
1559
1560 /*
1561 * State change request (cleared by vmR3SetStateLocked).
1562 */
1563 if (VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1564 {
1565 VMSTATE enmState = VMR3GetState(pVM);
1566 switch (enmState)
1567 {
1568 case VMSTATE_FATAL_ERROR:
1569 case VMSTATE_FATAL_ERROR_LS:
1570 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1571 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1572 return VINF_EM_SUSPEND;
1573
1574 case VMSTATE_DESTROYING:
1575 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1576 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1577 return VINF_EM_TERMINATE;
1578
1579 default:
1580 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1581 }
1582 }
1583
1584 /*
1585 * Debugger Facility polling.
1586 */
1587 if (VM_FF_ISPENDING(pVM, VM_FF_DBGF))
1588 {
1589 rc2 = DBGFR3VMMForcedAction(pVM);
1590 UPDATE_RC();
1591 }
1592
1593 /*
1594 * Postponed reset request.
1595 */
1596 if (VM_FF_TESTANDCLEAR(pVM, VM_FF_RESET))
1597 {
1598 rc2 = VMR3Reset(pVM->pUVM);
1599 UPDATE_RC();
1600 }
1601
1602#ifdef VBOX_WITH_RAW_MODE
1603 /*
1604 * CSAM page scanning.
1605 */
1606 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1607 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE))
1608 {
1609 PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1610
1611 /** @todo: check for 16 or 32 bits code! (D bit in the code selector) */
1612 Log(("Forced action VMCPU_FF_CSAM_SCAN_PAGE\n"));
1613
1614 CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1615 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_CSAM_SCAN_PAGE);
1616 }
1617#endif
1618
1619 /*
1620 * Out of memory? Putting this after CSAM as it may in theory cause us to run out of memory.
1621 */
1622 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1623 {
1624 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1625 UPDATE_RC();
1626 if (rc == VINF_EM_NO_MEMORY)
1627 return rc;
1628 }
1629
1630 /* check that we got them all */
1631 AssertCompile(VM_FF_NORMAL_PRIORITY_POST_MASK == (VM_FF_CHECK_VM_STATE | VM_FF_DBGF | VM_FF_RESET | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1632 AssertCompile(VMCPU_FF_NORMAL_PRIORITY_POST_MASK == VM_WHEN_RAW_MODE(VMCPU_FF_CSAM_SCAN_PAGE, 0));
1633 }
1634
1635 /*
1636 * Normal priority then.
1637 * (Executed in no particular order.)
1638 */
1639 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_NORMAL_PRIORITY_MASK, VM_FF_PGM_NO_MEMORY))
1640 {
1641 /*
1642 * PDM Queues are pending.
1643 */
1644 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_QUEUES, VM_FF_PGM_NO_MEMORY))
1645 PDMR3QueueFlushAll(pVM);
1646
1647 /*
1648 * PDM DMA transfers are pending.
1649 */
1650 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PDM_DMA, VM_FF_PGM_NO_MEMORY))
1651 PDMR3DmaRun(pVM);
1652
1653 /*
1654 * EMT Rendezvous (make sure they are handled before the requests).
1655 */
1656 if (VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1657 {
1658 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1659 UPDATE_RC();
1660 /** @todo HACK ALERT! The following test is to make sure EM+TM
1661 * thinks the VM is stopped/reset before the next VM state change
1662 * is made. We need a better solution for this, or at least make it
1663 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1664 * VINF_EM_SUSPEND). */
1665 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1666 {
1667 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1668 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1669 return rc;
1670 }
1671 }
1672
1673 /*
1674 * Requests from other threads.
1675 */
1676 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REQUEST, VM_FF_PGM_NO_MEMORY))
1677 {
1678 rc2 = VMR3ReqProcessU(pVM->pUVM, VMCPUID_ANY, false /*fPriorityOnly*/);
1679 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE) /** @todo this shouldn't be necessary */
1680 {
1681 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1682 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1683 return rc2;
1684 }
1685 UPDATE_RC();
1686 /** @todo HACK ALERT! The following test is to make sure EM+TM
1687 * thinks the VM is stopped/reset before the next VM state change
1688 * is made. We need a better solution for this, or at least make it
1689 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1690 * VINF_EM_SUSPEND). */
1691 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1692 {
1693 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1694 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1695 return rc;
1696 }
1697 }
1698
1699#ifdef VBOX_WITH_REM
1700 /* Replay the handler notification changes. */
1701 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_REM_HANDLER_NOTIFY, VM_FF_PGM_NO_MEMORY))
1702 {
1703 /* Try not to cause deadlocks. */
1704 if ( pVM->cCpus == 1
1705 || ( !PGMIsLockOwner(pVM)
1706 && !IOMIsLockWriteOwner(pVM))
1707 )
1708 {
1709 EMRemLock(pVM);
1710 REMR3ReplayHandlerNotifications(pVM);
1711 EMRemUnlock(pVM);
1712 }
1713 }
1714#endif
1715
1716 /* check that we got them all */
1717 AssertCompile(VM_FF_NORMAL_PRIORITY_MASK == (VM_FF_REQUEST | VM_FF_PDM_QUEUES | VM_FF_PDM_DMA | VM_FF_REM_HANDLER_NOTIFY | VM_FF_EMT_RENDEZVOUS));
1718 }
1719
1720 /*
1721 * Normal priority then. (per-VCPU)
1722 * (Executed in no particular order.)
1723 */
1724 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1725 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_NORMAL_PRIORITY_MASK))
1726 {
1727 /*
1728 * Requests from other threads.
1729 */
1730 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_REQUEST))
1731 {
1732 rc2 = VMR3ReqProcessU(pVM->pUVM, pVCpu->idCpu, false /*fPriorityOnly*/);
1733 if (rc2 == VINF_EM_OFF || rc2 == VINF_EM_TERMINATE || rc2 == VINF_EM_RESET)
1734 {
1735 Log2(("emR3ForcedActions: returns %Rrc\n", rc2));
1736 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1737 return rc2;
1738 }
1739 UPDATE_RC();
1740 /** @todo HACK ALERT! The following test is to make sure EM+TM
1741 * thinks the VM is stopped/reset before the next VM state change
1742 * is made. We need a better solution for this, or at least make it
1743 * possible to do: (rc >= VINF_EM_FIRST && rc <=
1744 * VINF_EM_SUSPEND). */
1745 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1746 {
1747 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1748 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1749 return rc;
1750 }
1751 }
1752
1753 /* check that we got them all */
1754 Assert(!(VMCPU_FF_NORMAL_PRIORITY_MASK & ~(VMCPU_FF_REQUEST)));
1755 }
1756
1757 /*
1758 * High priority pre execution chunk last.
1759 * (Executed in ascending priority order.)
1760 */
1761 if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_MASK)
1762 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_MASK))
1763 {
1764 /*
1765 * Timers before interrupts.
1766 */
1767 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TIMER)
1768 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1769 TMR3TimerQueuesDo(pVM);
1770
1771 /*
1772 * The instruction following an emulated STI should *always* be executed!
1773 *
1774 * Note! We intentionally don't clear VM_FF_INHIBIT_INTERRUPTS here if
1775 * the eip is the same as the inhibited instr address. Before we
1776 * are able to execute this instruction in raw mode (iret to
1777 * guest code) an external interrupt might force a world switch
1778 * again. Possibly allowing a guest interrupt to be dispatched
1779 * in the process. This could break the guest. Sounds very
1780 * unlikely, but such timing sensitive problem are not as rare as
1781 * you might think.
1782 */
1783 if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1784 && !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1785 {
1786 if (CPUMGetGuestRIP(pVCpu) != EMGetInhibitInterruptsPC(pVCpu))
1787 {
1788 Log(("Clearing VMCPU_FF_INHIBIT_INTERRUPTS at %RGv - successor %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu), EMGetInhibitInterruptsPC(pVCpu)));
1789 VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS);
1790 }
1791 else
1792 Log(("Leaving VMCPU_FF_INHIBIT_INTERRUPTS set at %RGv\n", (RTGCPTR)CPUMGetGuestRIP(pVCpu)));
1793 }
1794
1795 /*
1796 * Interrupts.
1797 */
1798 bool fWakeupPending = false;
1799 if ( !VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY)
1800 && !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INHIBIT_INTERRUPTS)
1801 && (!rc || rc >= VINF_EM_RESCHEDULE_HM)
1802 && !TRPMHasTrap(pVCpu) /* an interrupt could already be scheduled for dispatching in the recompiler. */
1803#ifdef VBOX_WITH_RAW_MODE
1804 && PATMAreInterruptsEnabled(pVM)
1805#else
1806 && (pVCpu->em.s.pCtx->eflags.u32 & X86_EFL_IF)
1807#endif
1808 && !HMR3IsEventPending(pVCpu))
1809 {
1810 Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1811 if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
1812 {
1813 /* Note: it's important to make sure the return code from TRPMR3InjectEvent isn't ignored! */
1814 /** @todo this really isn't nice, should properly handle this */
1815 rc2 = TRPMR3InjectEvent(pVM, pVCpu, TRPM_HARDWARE_INT);
1816#ifdef VBOX_STRICT
1817 rcIrq = rc2;
1818#endif
1819 UPDATE_RC();
1820 /* Reschedule required: We must not miss the wakeup below! */
1821 fWakeupPending = true;
1822 }
1823#ifdef VBOX_WITH_REM
1824 /** @todo really ugly; if we entered the hlt state when exiting the recompiler and an interrupt was pending, we previously got stuck in the halted state. */
1825 else if (REMR3QueryPendingInterrupt(pVM, pVCpu) != REM_NO_PENDING_IRQ)
1826 {
1827 rc2 = VINF_EM_RESCHEDULE_REM;
1828 UPDATE_RC();
1829 }
1830#endif
1831 }
1832
1833 /*
1834 * Allocate handy pages.
1835 */
1836 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1837 {
1838 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1839 UPDATE_RC();
1840 }
1841
1842 /*
1843 * Debugger Facility request.
1844 */
1845 if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_DBGF, VM_FF_PGM_NO_MEMORY))
1846 {
1847 rc2 = DBGFR3VMMForcedAction(pVM);
1848 UPDATE_RC();
1849 }
1850
1851 /*
1852 * EMT Rendezvous (must be serviced before termination).
1853 */
1854 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1855 && VM_FF_ISPENDING(pVM, VM_FF_EMT_RENDEZVOUS))
1856 {
1857 rc2 = VMMR3EmtRendezvousFF(pVM, pVCpu);
1858 UPDATE_RC();
1859 /** @todo HACK ALERT! The following test is to make sure EM+TM thinks the VM is
1860 * stopped/reset before the next VM state change is made. We need a better
1861 * solution for this, or at least make it possible to do: (rc >= VINF_EM_FIRST
1862 * && rc >= VINF_EM_SUSPEND). */
1863 if (RT_UNLIKELY(rc == VINF_EM_SUSPEND || rc == VINF_EM_RESET || rc == VINF_EM_OFF))
1864 {
1865 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1866 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1867 return rc;
1868 }
1869 }
1870
1871 /*
1872 * State change request (cleared by vmR3SetStateLocked).
1873 */
1874 if ( !fWakeupPending /* don't miss the wakeup from EMSTATE_HALTED! */
1875 && VM_FF_ISPENDING(pVM, VM_FF_CHECK_VM_STATE))
1876 {
1877 VMSTATE enmState = VMR3GetState(pVM);
1878 switch (enmState)
1879 {
1880 case VMSTATE_FATAL_ERROR:
1881 case VMSTATE_FATAL_ERROR_LS:
1882 Log2(("emR3ForcedActions: %s -> VINF_EM_SUSPEND\n", VMGetStateName(enmState) ));
1883 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1884 return VINF_EM_SUSPEND;
1885
1886 case VMSTATE_DESTROYING:
1887 Log2(("emR3ForcedActions: %s -> VINF_EM_TERMINATE\n", VMGetStateName(enmState) ));
1888 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1889 return VINF_EM_TERMINATE;
1890
1891 default:
1892 AssertMsgFailed(("%s\n", VMGetStateName(enmState)));
1893 }
1894 }
1895
1896 /*
1897 * Out of memory? Since most of our fellow high priority actions may cause us
1898 * to run out of memory, we're employing VM_FF_IS_PENDING_EXCEPT and putting this
1899 * at the end rather than the start. Also, VM_FF_TERMINATE has higher priority
1900 * than us since we can terminate without allocating more memory.
1901 */
1902 if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1903 {
1904 rc2 = PGMR3PhysAllocateHandyPages(pVM);
1905 UPDATE_RC();
1906 if (rc == VINF_EM_NO_MEMORY)
1907 return rc;
1908 }
1909
1910 /*
1911 * If the virtual sync clock is still stopped, make TM restart it.
1912 */
1913 if (VM_FF_ISPENDING(pVM, VM_FF_TM_VIRTUAL_SYNC))
1914 TMR3VirtualSyncFF(pVM, pVCpu);
1915
1916#ifdef DEBUG
1917 /*
1918 * Debug, pause the VM.
1919 */
1920 if (VM_FF_ISPENDING(pVM, VM_FF_DEBUG_SUSPEND))
1921 {
1922 VM_FF_CLEAR(pVM, VM_FF_DEBUG_SUSPEND);
1923 Log(("emR3ForcedActions: returns VINF_EM_SUSPEND\n"));
1924 return VINF_EM_SUSPEND;
1925 }
1926#endif
1927
1928 /* check that we got them all */
1929 AssertCompile(VM_FF_HIGH_PRIORITY_PRE_MASK == (VM_FF_TM_VIRTUAL_SYNC | VM_FF_DBGF | VM_FF_CHECK_VM_STATE | VM_FF_DEBUG_SUSPEND | VM_FF_PGM_NEED_HANDY_PAGES | VM_FF_PGM_NO_MEMORY | VM_FF_EMT_RENDEZVOUS));
1930 AssertCompile(VMCPU_FF_HIGH_PRIORITY_PRE_MASK == (VMCPU_FF_TIMER | VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC | VMCPU_FF_PGM_SYNC_CR3 | VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL | VMCPU_FF_INHIBIT_INTERRUPTS | VM_WHEN_RAW_MODE(VMCPU_FF_SELM_SYNC_TSS | VMCPU_FF_TRPM_SYNC_IDT | VMCPU_FF_SELM_SYNC_GDT | VMCPU_FF_SELM_SYNC_LDT, 0)));
1931 }
1932
1933#undef UPDATE_RC
1934 Log2(("emR3ForcedActions: returns %Rrc\n", rc));
1935 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatForcedActions, a);
1936 Assert(rcIrq == VINF_SUCCESS || rcIrq == rc);
1937 return rc;
1938}
1939
1940
1941/**
1942 * Check if the preset execution time cap restricts guest execution scheduling.
1943 *
1944 * @returns true if allowed, false otherwise
1945 * @param pVM Pointer to the VM.
1946 * @param pVCpu Pointer to the VMCPU.
1947 *
1948 */
1949VMMR3_INT_DECL(bool) EMR3IsExecutionAllowed(PVM pVM, PVMCPU pVCpu)
1950{
1951 uint64_t u64UserTime, u64KernelTime;
1952
1953 if ( pVM->uCpuExecutionCap != 100
1954 && RT_SUCCESS(RTThreadGetExecutionTimeMilli(&u64KernelTime, &u64UserTime)))
1955 {
1956 uint64_t u64TimeNow = RTTimeMilliTS();
1957 if (pVCpu->em.s.u64TimeSliceStart + EM_TIME_SLICE < u64TimeNow)
1958 {
1959 /* New time slice. */
1960 pVCpu->em.s.u64TimeSliceStart = u64TimeNow;
1961 pVCpu->em.s.u64TimeSliceStartExec = u64KernelTime + u64UserTime;
1962 pVCpu->em.s.u64TimeSliceExec = 0;
1963 }
1964 pVCpu->em.s.u64TimeSliceExec = u64KernelTime + u64UserTime - pVCpu->em.s.u64TimeSliceStartExec;
1965
1966 Log2(("emR3IsExecutionAllowed: start=%RX64 startexec=%RX64 exec=%RX64 (cap=%x)\n", pVCpu->em.s.u64TimeSliceStart, pVCpu->em.s.u64TimeSliceStartExec, pVCpu->em.s.u64TimeSliceExec, (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100));
1967 if (pVCpu->em.s.u64TimeSliceExec >= (EM_TIME_SLICE * pVM->uCpuExecutionCap) / 100)
1968 return false;
1969 }
1970 return true;
1971}
1972
1973
1974/**
1975 * Execute VM.
1976 *
1977 * This function is the main loop of the VM. The emulation thread
1978 * calls this function when the VM has been successfully constructed
1979 * and we're ready for executing the VM.
1980 *
1981 * Returning from this function means that the VM is turned off or
1982 * suspended (state already saved) and deconstruction is next in line.
1983 *
1984 * All interaction from other thread are done using forced actions
1985 * and signaling of the wait object.
1986 *
1987 * @returns VBox status code, informational status codes may indicate failure.
1988 * @param pVM Pointer to the VM.
1989 * @param pVCpu Pointer to the VMCPU.
1990 */
1991VMMR3_INT_DECL(int) EMR3ExecuteVM(PVM pVM, PVMCPU pVCpu)
1992{
1993 Log(("EMR3ExecuteVM: pVM=%p enmVMState=%d (%s) enmState=%d (%s) enmPrevState=%d (%s) fForceRAW=%RTbool\n",
1994 pVM,
1995 pVM->enmVMState, VMR3GetStateName(pVM->enmVMState),
1996 pVCpu->em.s.enmState, emR3GetStateName(pVCpu->em.s.enmState),
1997 pVCpu->em.s.enmPrevState, emR3GetStateName(pVCpu->em.s.enmPrevState),
1998 pVCpu->em.s.fForceRAW));
1999 VM_ASSERT_EMT(pVM);
2000 AssertMsg( pVCpu->em.s.enmState == EMSTATE_NONE
2001 || pVCpu->em.s.enmState == EMSTATE_WAIT_SIPI
2002 || pVCpu->em.s.enmState == EMSTATE_SUSPENDED,
2003 ("%s\n", emR3GetStateName(pVCpu->em.s.enmState)));
2004
2005 int rc = setjmp(pVCpu->em.s.u.FatalLongJump);
2006 if (rc == 0)
2007 {
2008 /*
2009 * Start the virtual time.
2010 */
2011 TMR3NotifyResume(pVM, pVCpu);
2012
2013 /*
2014 * The Outer Main Loop.
2015 */
2016 bool fFFDone = false;
2017
2018 /* Reschedule right away to start in the right state. */
2019 rc = VINF_SUCCESS;
2020
2021 /* If resuming after a pause or a state load, restore the previous
2022 state or else we'll start executing code. Else, just reschedule. */
2023 if ( pVCpu->em.s.enmState == EMSTATE_SUSPENDED
2024 && ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2025 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED))
2026 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2027 else
2028 pVCpu->em.s.enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2029
2030 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2031 for (;;)
2032 {
2033 /*
2034 * Before we can schedule anything (we're here because
2035 * scheduling is required) we must service any pending
2036 * forced actions to avoid any pending action causing
2037 * immediate rescheduling upon entering an inner loop
2038 *
2039 * Do forced actions.
2040 */
2041 if ( !fFFDone
2042 && RT_SUCCESS(rc)
2043 && rc != VINF_EM_TERMINATE
2044 && rc != VINF_EM_OFF
2045 && ( VM_FF_ISPENDING(pVM, VM_FF_ALL_REM_MASK)
2046 || VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_ALL_REM_MASK)))
2047 {
2048 rc = emR3ForcedActions(pVM, pVCpu, rc);
2049 VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
2050 if ( ( rc == VINF_EM_RESCHEDULE_REM
2051 || rc == VINF_EM_RESCHEDULE_HM)
2052 && pVCpu->em.s.fForceRAW)
2053 rc = VINF_EM_RESCHEDULE_RAW;
2054 }
2055 else if (fFFDone)
2056 fFFDone = false;
2057
2058 /*
2059 * Now what to do?
2060 */
2061 Log2(("EMR3ExecuteVM: rc=%Rrc\n", rc));
2062 EMSTATE const enmOldState = pVCpu->em.s.enmState;
2063 switch (rc)
2064 {
2065 /*
2066 * Keep doing what we're currently doing.
2067 */
2068 case VINF_SUCCESS:
2069 break;
2070
2071 /*
2072 * Reschedule - to raw-mode execution.
2073 */
2074 case VINF_EM_RESCHEDULE_RAW:
2075 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_RAW: %d -> %d (EMSTATE_RAW)\n", enmOldState, EMSTATE_RAW));
2076 pVCpu->em.s.enmState = EMSTATE_RAW;
2077 break;
2078
2079 /*
2080 * Reschedule - to hardware accelerated raw-mode execution.
2081 */
2082 case VINF_EM_RESCHEDULE_HM:
2083 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_HM: %d -> %d (EMSTATE_HM)\n", enmOldState, EMSTATE_HM));
2084 Assert(!pVCpu->em.s.fForceRAW);
2085 pVCpu->em.s.enmState = EMSTATE_HM;
2086 break;
2087
2088 /*
2089 * Reschedule - to recompiled execution.
2090 */
2091 case VINF_EM_RESCHEDULE_REM:
2092 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE_REM: %d -> %d (EMSTATE_REM)\n", enmOldState, EMSTATE_REM));
2093 pVCpu->em.s.enmState = EMSTATE_REM;
2094 break;
2095
2096 /*
2097 * Resume.
2098 */
2099 case VINF_EM_RESUME:
2100 Log2(("EMR3ExecuteVM: VINF_EM_RESUME: %d -> VINF_EM_RESCHEDULE\n", enmOldState));
2101 /* Don't reschedule in the halted or wait for SIPI case. */
2102 if ( pVCpu->em.s.enmPrevState == EMSTATE_WAIT_SIPI
2103 || pVCpu->em.s.enmPrevState == EMSTATE_HALTED)
2104 {
2105 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2106 break;
2107 }
2108 /* fall through and get scheduled. */
2109
2110 /*
2111 * Reschedule.
2112 */
2113 case VINF_EM_RESCHEDULE:
2114 {
2115 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2116 Log2(("EMR3ExecuteVM: VINF_EM_RESCHEDULE: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2117 pVCpu->em.s.enmState = enmState;
2118 break;
2119 }
2120
2121 /*
2122 * Halted.
2123 */
2124 case VINF_EM_HALT:
2125 Log2(("EMR3ExecuteVM: VINF_EM_HALT: %d -> %d\n", enmOldState, EMSTATE_HALTED));
2126 pVCpu->em.s.enmState = EMSTATE_HALTED;
2127 break;
2128
2129 /*
2130 * Switch to the wait for SIPI state (application processor only)
2131 */
2132 case VINF_EM_WAIT_SIPI:
2133 Assert(pVCpu->idCpu != 0);
2134 Log2(("EMR3ExecuteVM: VINF_EM_WAIT_SIPI: %d -> %d\n", enmOldState, EMSTATE_WAIT_SIPI));
2135 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2136 break;
2137
2138
2139 /*
2140 * Suspend.
2141 */
2142 case VINF_EM_SUSPEND:
2143 Log2(("EMR3ExecuteVM: VINF_EM_SUSPEND: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2144 Assert(enmOldState != EMSTATE_SUSPENDED);
2145 pVCpu->em.s.enmPrevState = enmOldState;
2146 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2147 break;
2148
2149 /*
2150 * Reset.
2151 * We might end up doing a double reset for now, we'll have to clean up the mess later.
2152 */
2153 case VINF_EM_RESET:
2154 {
2155 if (pVCpu->idCpu == 0)
2156 {
2157 EMSTATE enmState = emR3Reschedule(pVM, pVCpu, pVCpu->em.s.pCtx);
2158 Log2(("EMR3ExecuteVM: VINF_EM_RESET: %d -> %d (%s)\n", enmOldState, enmState, emR3GetStateName(enmState)));
2159 pVCpu->em.s.enmState = enmState;
2160 }
2161 else
2162 {
2163 /* All other VCPUs go into the wait for SIPI state. */
2164 pVCpu->em.s.enmState = EMSTATE_WAIT_SIPI;
2165 }
2166 break;
2167 }
2168
2169 /*
2170 * Power Off.
2171 */
2172 case VINF_EM_OFF:
2173 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2174 Log2(("EMR3ExecuteVM: returns VINF_EM_OFF (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2175 TMR3NotifySuspend(pVM, pVCpu);
2176 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2177 return rc;
2178
2179 /*
2180 * Terminate the VM.
2181 */
2182 case VINF_EM_TERMINATE:
2183 pVCpu->em.s.enmState = EMSTATE_TERMINATING;
2184 Log(("EMR3ExecuteVM returns VINF_EM_TERMINATE (%d -> %d)\n", enmOldState, EMSTATE_TERMINATING));
2185 if (pVM->enmVMState < VMSTATE_DESTROYING) /* ugly */
2186 TMR3NotifySuspend(pVM, pVCpu);
2187 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2188 return rc;
2189
2190
2191 /*
2192 * Out of memory, suspend the VM and stuff.
2193 */
2194 case VINF_EM_NO_MEMORY:
2195 Log2(("EMR3ExecuteVM: VINF_EM_NO_MEMORY: %d -> %d\n", enmOldState, EMSTATE_SUSPENDED));
2196 Assert(enmOldState != EMSTATE_SUSPENDED);
2197 pVCpu->em.s.enmPrevState = enmOldState;
2198 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2199 TMR3NotifySuspend(pVM, pVCpu);
2200 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2201
2202 rc = VMSetRuntimeError(pVM, VMSETRTERR_FLAGS_SUSPEND, "HostMemoryLow",
2203 N_("Unable to allocate and lock memory. The virtual machine will be paused. Please close applications to free up memory or close the VM"));
2204 if (rc != VINF_EM_SUSPEND)
2205 {
2206 if (RT_SUCCESS_NP(rc))
2207 {
2208 AssertLogRelMsgFailed(("%Rrc\n", rc));
2209 rc = VERR_EM_INTERNAL_ERROR;
2210 }
2211 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2212 }
2213 return rc;
2214
2215 /*
2216 * Guest debug events.
2217 */
2218 case VINF_EM_DBG_STEPPED:
2219 AssertMsgFailed(("VINF_EM_DBG_STEPPED cannot be here!"));
2220 case VINF_EM_DBG_STOP:
2221 case VINF_EM_DBG_BREAKPOINT:
2222 case VINF_EM_DBG_STEP:
2223 if (enmOldState == EMSTATE_RAW)
2224 {
2225 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_RAW));
2226 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
2227 }
2228 else
2229 {
2230 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_GUEST_REM));
2231 pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_REM;
2232 }
2233 break;
2234
2235 /*
2236 * Hypervisor debug events.
2237 */
2238 case VINF_EM_DBG_HYPER_STEPPED:
2239 case VINF_EM_DBG_HYPER_BREAKPOINT:
2240 case VINF_EM_DBG_HYPER_ASSERTION:
2241 Log2(("EMR3ExecuteVM: %Rrc: %d -> %d\n", rc, enmOldState, EMSTATE_DEBUG_HYPER));
2242 pVCpu->em.s.enmState = EMSTATE_DEBUG_HYPER;
2243 break;
2244
2245 /*
2246 * Guru mediations.
2247 */
2248 case VERR_VMM_RING0_ASSERTION:
2249 case VINF_EM_TRIPLE_FAULT:
2250 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2251 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2252 break;
2253
2254 /*
2255 * Any error code showing up here other than the ones we
2256 * know and process above are considered to be FATAL.
2257 *
2258 * Unknown warnings and informational status codes are also
2259 * included in this.
2260 */
2261 default:
2262 if (RT_SUCCESS_NP(rc))
2263 {
2264 AssertMsgFailed(("Unexpected warning or informational status code %Rra!\n", rc));
2265 rc = VERR_EM_INTERNAL_ERROR;
2266 }
2267 Log(("EMR3ExecuteVM: %Rrc: %d -> %d (EMSTATE_GURU_MEDITATION)\n", rc, enmOldState, EMSTATE_GURU_MEDITATION));
2268 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2269 break;
2270 }
2271
2272 /*
2273 * Act on state transition.
2274 */
2275 EMSTATE const enmNewState = pVCpu->em.s.enmState;
2276 if (enmOldState != enmNewState)
2277 {
2278 VBOXVMM_EM_STATE_CHANGED(pVCpu, enmOldState, enmNewState, rc);
2279
2280 /* Clear MWait flags. */
2281 if ( enmOldState == EMSTATE_HALTED
2282 && (pVCpu->em.s.MWait.fWait & EMMWAIT_FLAG_ACTIVE)
2283 && ( enmNewState == EMSTATE_RAW
2284 || enmNewState == EMSTATE_HM
2285 || enmNewState == EMSTATE_REM
2286 || enmNewState == EMSTATE_DEBUG_GUEST_RAW
2287 || enmNewState == EMSTATE_DEBUG_GUEST_HM
2288 || enmNewState == EMSTATE_DEBUG_GUEST_REM) )
2289 {
2290 LogFlow(("EMR3ExecuteVM: Clearing MWAIT\n"));
2291 pVCpu->em.s.MWait.fWait &= ~(EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0);
2292 }
2293 }
2294 else
2295 VBOXVMM_EM_STATE_UNCHANGED(pVCpu, enmNewState, rc);
2296
2297 STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x); /* (skip this in release) */
2298 STAM_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2299
2300 /*
2301 * Act on the new state.
2302 */
2303 switch (enmNewState)
2304 {
2305 /*
2306 * Execute raw.
2307 */
2308 case EMSTATE_RAW:
2309#ifndef IEM_VERIFICATION_MODE /* remove later */
2310# ifdef VBOX_WITH_RAW_MODE
2311 rc = emR3RawExecute(pVM, pVCpu, &fFFDone);
2312# else
2313 AssertLogRelMsgFailed(("%Rrc\n", rc));
2314 rc = VERR_EM_INTERNAL_ERROR;
2315# endif
2316 break;
2317#endif
2318
2319 /*
2320 * Execute hardware accelerated raw.
2321 */
2322 case EMSTATE_HM:
2323#ifndef IEM_VERIFICATION_MODE /* remove later */
2324 rc = emR3HmExecute(pVM, pVCpu, &fFFDone);
2325 break;
2326#endif
2327
2328 /*
2329 * Execute recompiled.
2330 */
2331 case EMSTATE_REM:
2332#ifdef IEM_VERIFICATION_MODE
2333# if 1
2334 rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu)); fFFDone = false;
2335# else
2336 rc = VBOXSTRICTRC_TODO(REMR3EmulateInstruction(pVM, pVCpu)); fFFDone = false;
2337 if (rc == VINF_EM_RESCHEDULE)
2338 rc = VINF_SUCCESS;
2339# endif
2340#else
2341 rc = emR3RemExecute(pVM, pVCpu, &fFFDone);
2342#endif
2343 Log2(("EMR3ExecuteVM: emR3RemExecute -> %Rrc\n", rc));
2344 break;
2345
2346 /*
2347 * Application processor execution halted until SIPI.
2348 */
2349 case EMSTATE_WAIT_SIPI:
2350 /* no break */
2351 /*
2352 * hlt - execution halted until interrupt.
2353 */
2354 case EMSTATE_HALTED:
2355 {
2356 STAM_REL_PROFILE_START(&pVCpu->em.s.StatHalted, y);
2357 /* MWAIT has a special extension where it's woken up when
2358 an interrupt is pending even when IF=0. */
2359 if ( (pVCpu->em.s.MWait.fWait & (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2360 == (EMMWAIT_FLAG_ACTIVE | EMMWAIT_FLAG_BREAKIRQIF0))
2361 {
2362 rc = VMR3WaitHalted(pVM, pVCpu, false /*fIgnoreInterrupts*/);
2363 if ( rc == VINF_SUCCESS
2364 && VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_INTERRUPT_APIC | VMCPU_FF_INTERRUPT_PIC))
2365 {
2366 Log(("EMR3ExecuteVM: Triggering reschedule on pending IRQ after MWAIT\n"));
2367 rc = VINF_EM_RESCHEDULE;
2368 }
2369 }
2370 else
2371 rc = VMR3WaitHalted(pVM, pVCpu, !(CPUMGetGuestEFlags(pVCpu) & X86_EFL_IF));
2372
2373 STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatHalted, y);
2374 break;
2375 }
2376
2377 /*
2378 * Suspended - return to VM.cpp.
2379 */
2380 case EMSTATE_SUSPENDED:
2381 TMR3NotifySuspend(pVM, pVCpu);
2382 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2383 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2384 return VINF_EM_SUSPEND;
2385
2386 /*
2387 * Debugging in the guest.
2388 */
2389 case EMSTATE_DEBUG_GUEST_REM:
2390 case EMSTATE_DEBUG_GUEST_RAW:
2391 TMR3NotifySuspend(pVM, pVCpu);
2392 rc = emR3Debug(pVM, pVCpu, rc);
2393 TMR3NotifyResume(pVM, pVCpu);
2394 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2395 break;
2396
2397 /*
2398 * Debugging in the hypervisor.
2399 */
2400 case EMSTATE_DEBUG_HYPER:
2401 {
2402 TMR3NotifySuspend(pVM, pVCpu);
2403 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2404
2405 rc = emR3Debug(pVM, pVCpu, rc);
2406 Log2(("EMR3ExecuteVM: enmr3Debug -> %Rrc (state %d)\n", rc, pVCpu->em.s.enmState));
2407 if (rc != VINF_SUCCESS)
2408 {
2409 /* switch to guru meditation mode */
2410 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2411 VMMR3FatalDump(pVM, pVCpu, rc);
2412 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2413 return rc;
2414 }
2415
2416 STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatTotal, x);
2417 TMR3NotifyResume(pVM, pVCpu);
2418 break;
2419 }
2420
2421 /*
2422 * Guru meditation takes place in the debugger.
2423 */
2424 case EMSTATE_GURU_MEDITATION:
2425 {
2426 TMR3NotifySuspend(pVM, pVCpu);
2427 VMMR3FatalDump(pVM, pVCpu, rc);
2428 emR3Debug(pVM, pVCpu, rc);
2429 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2430 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2431 return rc;
2432 }
2433
2434 /*
2435 * The states we don't expect here.
2436 */
2437 case EMSTATE_NONE:
2438 case EMSTATE_TERMINATING:
2439 default:
2440 AssertMsgFailed(("EMR3ExecuteVM: Invalid state %d!\n", pVCpu->em.s.enmState));
2441 pVCpu->em.s.enmState = EMSTATE_GURU_MEDITATION;
2442 TMR3NotifySuspend(pVM, pVCpu);
2443 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2444 Log(("EMR3ExecuteVM: actually returns %Rrc (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(enmOldState)));
2445 return VERR_EM_INTERNAL_ERROR;
2446 }
2447 } /* The Outer Main Loop */
2448 }
2449 else
2450 {
2451 /*
2452 * Fatal error.
2453 */
2454 Log(("EMR3ExecuteVM: returns %Rrc because of longjmp / fatal error; (state %s / %s)\n", rc, emR3GetStateName(pVCpu->em.s.enmState), emR3GetStateName(pVCpu->em.s.enmPrevState)));
2455 TMR3NotifySuspend(pVM, pVCpu);
2456 VMMR3FatalDump(pVM, pVCpu, rc);
2457 emR3Debug(pVM, pVCpu, rc);
2458 STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatTotal, x);
2459 /** @todo change the VM state! */
2460 return rc;
2461 }
2462
2463 /* (won't ever get here). */
2464 AssertFailed();
2465}
2466
2467/**
2468 * Notify EM of a state change (used by FTM)
2469 *
2470 * @param pVM Pointer to the VM.
2471 */
2472VMMR3_INT_DECL(int) EMR3NotifySuspend(PVM pVM)
2473{
2474 PVMCPU pVCpu = VMMGetCpu(pVM);
2475
2476 TMR3NotifySuspend(pVM, pVCpu); /* Stop the virtual time. */
2477 pVCpu->em.s.enmPrevState = pVCpu->em.s.enmState;
2478 pVCpu->em.s.enmState = EMSTATE_SUSPENDED;
2479 return VINF_SUCCESS;
2480}
2481
2482/**
2483 * Notify EM of a state change (used by FTM)
2484 *
2485 * @param pVM Pointer to the VM.
2486 */
2487VMMR3_INT_DECL(int) EMR3NotifyResume(PVM pVM)
2488{
2489 PVMCPU pVCpu = VMMGetCpu(pVM);
2490 EMSTATE enmCurState = pVCpu->em.s.enmState;
2491
2492 TMR3NotifyResume(pVM, pVCpu); /* Resume the virtual time. */
2493 pVCpu->em.s.enmState = pVCpu->em.s.enmPrevState;
2494 pVCpu->em.s.enmPrevState = enmCurState;
2495 return VINF_SUCCESS;
2496}
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