EMR3Nem.cpp@ 80239

Last change on this file since 80239 was 80191, checked in by vboxsync, 5 years ago
VMM/r3: Refactored VMCPU enumeration in preparation that aCpus will be replaced with a pointer array. Removed two raw-mode offset members from the CPUM and CPUMCPU sub-structures. bugref:9217 bugref:9517
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File size: 19.1 KB

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1	/* $Id: EMR3Nem.cpp 80191 2019-08-08 00:36:57Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - NEM interface.
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define VBOX_BUGREF_9217_PART_I
23	#define LOG_GROUP LOG_GROUP_EM
24	#define VMCPU_INCL_CPUM_GST_CTX
25	#include <VBox/vmm/em.h>
26	#include <VBox/vmm/vmm.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/nem.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/vmm/pgm.h>
34	#ifdef VBOX_WITH_REM
35	# include <VBox/vmm/rem.h>
36	#endif
37	#include <VBox/vmm/tm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/ssm.h>
40	#include <VBox/vmm/pdmapi.h>
41	#include <VBox/vmm/pdmcritsect.h>
42	#include <VBox/vmm/pdmqueue.h>
43	#include "EMInternal.h"
44	#include <VBox/vmm/vm.h>
45	#include <VBox/vmm/gim.h>
46	#include <VBox/vmm/cpumdis.h>
47	#include <VBox/dis.h>
48	#include <VBox/disopcode.h>
49	#include <VBox/err.h>
50	#include <VBox/vmm/dbgf.h>
51	#include "VMMTracing.h"
52
53	#include <iprt/asm.h>
54
55
56	/*********************************************************************************************************************************
57	* Internal Functions *
58	*********************************************************************************************************************************/
59	static int emR3NemHandleRC(PVM pVM, PVMCPU pVCpu, int rc);
60	DECLINLINE(int) emR3NemExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
61	static int emR3NemExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
62	static int emR3NemForcedActions(PVM pVM, PVMCPU pVCpu);
63
64	#define EMHANDLERC_WITH_NEM
65	#define emR3ExecuteInstruction emR3NemExecuteInstruction
66	#define emR3ExecuteIOInstruction emR3NemExecuteIOInstruction
67	#include "EMHandleRCTmpl.h"
68
69
70	/**
71	* Executes instruction in NEM mode if we can.
72	*
73	* This is somewhat comparable to REMR3EmulateInstruction.
74	*
75	* @returns VBox strict status code.
76	* @retval VINF_EM_DBG_STEPPED on success.
77	* @retval VERR_EM_CANNOT_EXEC_GUEST if we cannot execute guest instructions in
78	* HM right now.
79	*
80	* @param pVM The cross context VM structure.
81	* @param pVCpu The cross context virtual CPU structure for the calling EMT.
82	* @param fFlags Combinations of EM_ONE_INS_FLAGS_XXX.
83	* @thread EMT.
84	*/
85	VBOXSTRICTRC emR3NemSingleInstruction(PVM pVM, PVMCPU pVCpu, uint32_t fFlags)
86	{
87	Assert(!(fFlags & ~EM_ONE_INS_FLAGS_MASK));
88
89	if (!NEMR3CanExecuteGuest(pVM, pVCpu))
90	return VINF_EM_RESCHEDULE;
91
92	uint64_t const uOldRip = pVCpu->cpum.GstCtx.rip;
93	for (;;)
94	{
95	/*
96	* Service necessary FFs before going into HM.
97	*/
98	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
99	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
100	{
101	VBOXSTRICTRC rcStrict = emR3NemForcedActions(pVM, pVCpu);
102	if (rcStrict != VINF_SUCCESS)
103	{
104	Log(("emR3NemSingleInstruction: FFs before -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
105	return rcStrict;
106	}
107	}
108
109	/*
110	* Go execute it.
111	*/
112	bool fOld = NEMR3SetSingleInstruction(pVM, pVCpu, true);
113	VBOXSTRICTRC rcStrict = NEMR3RunGC(pVM, pVCpu);
114	NEMR3SetSingleInstruction(pVM, pVCpu, fOld);
115	LogFlow(("emR3NemSingleInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
116
117	/*
118	* Handle high priority FFs and informational status codes. We don't do
119	* normal FF processing the caller or the next call can deal with them.
120	*/
121	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
122	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
123	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
124	{
125	rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, rcStrict);
126	LogFlow(("emR3NemSingleInstruction: FFs after -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
127	}
128
129	if (rcStrict != VINF_SUCCESS && (rcStrict < VINF_EM_FIRST \|\| rcStrict > VINF_EM_LAST))
130	{
131	rcStrict = emR3NemHandleRC(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict));
132	Log(("emR3NemSingleInstruction: emR3NemHandleRC -> %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
133	}
134
135	/*
136	* Done?
137	*/
138	CPUM_ASSERT_NOT_EXTRN(pVCpu, CPUMCTX_EXTRN_RIP);
139	if ( (rcStrict != VINF_SUCCESS && rcStrict != VINF_EM_DBG_STEPPED)
140	\|\| !(fFlags & EM_ONE_INS_FLAGS_RIP_CHANGE)
141	\|\| pVCpu->cpum.GstCtx.rip != uOldRip)
142	{
143	if (rcStrict == VINF_SUCCESS && pVCpu->cpum.GstCtx.rip != uOldRip)
144	rcStrict = VINF_EM_DBG_STEPPED;
145	Log(("emR3NemSingleInstruction: returns %Rrc (rip %llx -> %llx)\n",
146	VBOXSTRICTRC_VAL(rcStrict), uOldRip, pVCpu->cpum.GstCtx.rip));
147	CPUM_IMPORT_EXTRN_RET(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK);
148	return rcStrict;
149	}
150	}
151	}
152
153
154	/**
155	* Executes one (or perhaps a few more) instruction(s).
156	*
157	* @returns VBox status code suitable for EM.
158	*
159	* @param pVM The cross context VM structure.
160	* @param pVCpu The cross context virtual CPU structure.
161	* @param rcRC Return code from RC.
162	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
163	* instruction and prefix the log output with this text.
164	*/
165	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
166	static int emR3NemExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC, const char *pszPrefix)
167	#else
168	static int emR3NemExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcRC)
169	#endif
170	{
171	NOREF(rcRC);
172
173	#ifdef LOG_ENABLED
174	/*
175	* Log it.
176	*/
177	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
178	if (pszPrefix)
179	{
180	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", pszPrefix);
181	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
182	}
183	#endif
184
185	/*
186	* Use IEM and fallback on REM if the functionality is missing.
187	* Once IEM gets mature enough, nothing should ever fall back.
188	*/
189	STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
190
191	VBOXSTRICTRC rcStrict;
192	uint32_t idxContinueExitRec = pVCpu->em.s.idxContinueExitRec;
193	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
194	if (idxContinueExitRec >= RT_ELEMENTS(pVCpu->em.s.aExitRecords))
195	{
196	CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
197	rcStrict = IEMExecOne(pVCpu);
198	}
199	else
200	{
201	RT_UNTRUSTED_VALIDATED_FENCE();
202	rcStrict = EMHistoryExec(pVCpu, &pVCpu->em.s.aExitRecords[idxContinueExitRec], 0);
203	LogFlow(("emR3NemExecuteInstruction: %Rrc (EMHistoryExec)\n", VBOXSTRICTRC_VAL(rcStrict)));
204	}
205
206	STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
207
208	if ( rcStrict == VERR_IEM_ASPECT_NOT_IMPLEMENTED
209	\|\| rcStrict == VERR_IEM_INSTR_NOT_IMPLEMENTED)
210	{
211	#ifdef VBOX_WITH_REM
212	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
213	CPUM_IMPORT_EXTRN_RET(pVCpu, ~CPUMCTX_EXTRN_KEEPER_MASK);
214	EMRemLock(pVM);
215	/* Flush the recompiler TLB if the VCPU has changed. */
216	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
217	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
218	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
219
220	rcStrict = REMR3EmulateInstruction(pVM, pVCpu);
221	EMRemUnlock(pVM);
222	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
223	#else /* !VBOX_WITH_REM */
224	NOREF(pVM);
225	#endif /* !VBOX_WITH_REM */
226	}
227	return VBOXSTRICTRC_TODO(rcStrict);
228	}
229
230
231	/**
232	* Executes one (or perhaps a few more) instruction(s).
233	* This is just a wrapper for discarding pszPrefix in non-logging builds.
234	*
235	* @returns VBox status code suitable for EM.
236	* @param pVM The cross context VM structure.
237	* @param pVCpu The cross context virtual CPU structure.
238	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
239	* instruction and prefix the log output with this text.
240	* @param rcGC GC return code
241	*/
242	DECLINLINE(int) emR3NemExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
243	{
244	#ifdef LOG_ENABLED
245	return emR3NemExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
246	#else
247	RT_NOREF_PV(pszPrefix);
248	return emR3NemExecuteInstructionWorker(pVM, pVCpu, rcGC);
249	#endif
250	}
251
252	/**
253	* Executes one (or perhaps a few more) IO instruction(s).
254	*
255	* @returns VBox status code suitable for EM.
256	* @param pVM The cross context VM structure.
257	* @param pVCpu The cross context virtual CPU structure.
258	*/
259	static int emR3NemExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
260	{
261	RT_NOREF_PV(pVM);
262	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
263
264	/*
265	* Hand it over to the interpreter.
266	*/
267	CPUM_IMPORT_EXTRN_RET(pVCpu, IEM_CPUMCTX_EXTRN_MUST_MASK);
268	VBOXSTRICTRC rcStrict;
269	uint32_t idxContinueExitRec = pVCpu->em.s.idxContinueExitRec;
270	RT_UNTRUSTED_NONVOLATILE_COPY_FENCE();
271	if (idxContinueExitRec >= RT_ELEMENTS(pVCpu->em.s.aExitRecords))
272	{
273	rcStrict = IEMExecOne(pVCpu);
274	LogFlow(("emR3NemExecuteIOInstruction: %Rrc (IEMExecOne)\n", VBOXSTRICTRC_VAL(rcStrict)));
275	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
276	}
277	else
278	{
279	RT_UNTRUSTED_VALIDATED_FENCE();
280	rcStrict = EMHistoryExec(pVCpu, &pVCpu->em.s.aExitRecords[idxContinueExitRec], 0);
281	LogFlow(("emR3NemExecuteIOInstruction: %Rrc (EMHistoryExec)\n", VBOXSTRICTRC_VAL(rcStrict)));
282	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoRestarted);
283	}
284
285	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
286	return VBOXSTRICTRC_TODO(rcStrict);
287	}
288
289
290	/**
291	* Process NEM specific forced actions.
292	*
293	* This function is called when any FFs in VM_FF_HIGH_PRIORITY_PRE_RAW_MASK
294	* or/and VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK are pending.
295	*
296	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
297	* EM statuses.
298	* @param pVM The cross context VM structure.
299	* @param pVCpu The cross context virtual CPU structure.
300	*/
301	static int emR3NemForcedActions(PVM pVM, PVMCPU pVCpu)
302	{
303	/*
304	* Sync page directory should not happen in NEM mode.
305	*/
306	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
307	{
308	Log(("NEM: TODO: Make VMCPU_FF_PGM_SYNC_CR3 / VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL quiet! (%#RX64)\n", (uint64_t)pVCpu->fLocalForcedActions));
309	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL);
310	}
311
312	/*
313	* Allocate handy pages (just in case the above actions have consumed some pages).
314	*/
315	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
316	{
317	int rc = PGMR3PhysAllocateHandyPages(pVM);
318	if (RT_FAILURE(rc))
319	return rc;
320	}
321
322	/*
323	* Check whether we're out of memory now.
324	*
325	* This may stem from some of the above actions or operations that has been executed
326	* since we ran FFs. The allocate handy pages must for instance always be followed by
327	* this check.
328	*/
329	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
330	return VINF_EM_NO_MEMORY;
331
332	return VINF_SUCCESS;
333	}
334
335
336	/**
337	* Executes hardware accelerated raw code. (Intel VT-x & AMD-V)
338	*
339	* This function contains the raw-mode version of the inner
340	* execution loop (the outer loop being in EMR3ExecuteVM()).
341	*
342	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE, VINF_EM_RESCHEDULE_RAW,
343	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
344	*
345	* @param pVM The cross context VM structure.
346	* @param pVCpu The cross context virtual CPU structure.
347	* @param pfFFDone Where to store an indicator telling whether or not
348	* FFs were done before returning.
349	*/
350	VBOXSTRICTRC emR3NemExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
351	{
352	VBOXSTRICTRC rcStrict = VERR_IPE_UNINITIALIZED_STATUS;
353
354	LogFlow(("emR3NemExecute%d: (cs:eip=%04x:%RGv)\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip));
355	*pfFFDone = false;
356
357	STAM_REL_COUNTER_INC(&pVCpu->em.s.StatNEMExecuteCalled);
358
359	/*
360	* Spin till we get a forced action which returns anything but VINF_SUCCESS.
361	*/
362	for (;;)
363	{
364	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatNEMEntry, a);
365
366	#if 0
367	/* Check if a forced reschedule is pending. */
368	if (NEMR3IsRescheduleRequired(pVCpu))
369	{
370	rcStrict = VINF_EM_RESCHEDULE;
371	break;
372	}
373	#endif
374
375	/*
376	* Process high priority pre-execution raw-mode FFs.
377	*/
378	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
379	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
380	{
381	rcStrict = emR3NemForcedActions(pVM, pVCpu);
382	if (rcStrict != VINF_SUCCESS)
383	break;
384	}
385
386	#ifdef LOG_ENABLED
387	/*
388	* Log important stuff before entering GC.
389	*/
390	if (TRPMHasTrap(pVCpu))
391	Log(("CPU%d: Pending hardware interrupt=0x%x cs:rip=%04X:%RGv\n", pVCpu->idCpu, TRPMGetTrapNo(pVCpu), pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip));
392
393	if (!(pVCpu->cpum.GstCtx.fExtrn & ( CPUMCTX_EXTRN_RIP \| CPUMCTX_EXTRN_CS \| CPUMCTX_EXTRN_RFLAGS \| CPUMCTX_EXTRN_SS
394	\| CPUMCTX_EXTRN_RSP \| CPUMCTX_EXTRN_CR0 \| CPUMCTX_EXTRN_CR4 \| CPUMCTX_EXTRN_EFER)))
395	{
396	uint32_t cpl = CPUMGetGuestCPL(pVCpu);
397	if (pVM->cCpus == 1)
398	{
399	if (pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
400	Log(("NEMV86: %08x IF=%d\n", pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF));
401	else if (CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx))
402	Log(("NEMR%d: %04x:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rsp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, (uint32_t)pVCpu->cpum.GstCtx.cr0, (uint32_t)pVCpu->cpum.GstCtx.cr4, (uint32_t)pVCpu->cpum.GstCtx.msrEFER));
403	else
404	Log(("NEMR%d: %04x:%08x ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, (uint32_t)pVCpu->cpum.GstCtx.cr0, (uint32_t)pVCpu->cpum.GstCtx.cr4, (uint32_t)pVCpu->cpum.GstCtx.msrEFER));
405	}
406	else
407	{
408	if (pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
409	Log(("NEMV86-CPU%d: %08x IF=%d\n", pVCpu->idCpu, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF));
410	else if (CPUMIsGuestIn64BitCodeEx(&pVCpu->cpum.GstCtx))
411	Log(("NEMR%d-CPU%d: %04x:%RGv ESP=%RGv IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, pVCpu->cpum.GstCtx.rsp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, (uint32_t)pVCpu->cpum.GstCtx.cr0, (uint32_t)pVCpu->cpum.GstCtx.cr4, (uint32_t)pVCpu->cpum.GstCtx.msrEFER));
412	else
413	Log(("NEMR%d-CPU%d: %04x:%08x ESP=%08X IF=%d IOPL=%d CR0=%x CR4=%x EFER=%x\n", cpl, pVCpu->idCpu, pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->cpum.GstCtx.eflags.Bits.u2IOPL, (uint32_t)pVCpu->cpum.GstCtx.cr0, (uint32_t)pVCpu->cpum.GstCtx.cr4, (uint32_t)pVCpu->cpum.GstCtx.msrEFER));
414	}
415	}
416	else if (pVM->cCpus == 1)
417	Log(("NEMRx: -> NEMR3RunGC\n"));
418	else
419	Log(("NEMRx-CPU%u: -> NEMR3RunGC\n", pVCpu->idCpu));
420	#endif /* LOG_ENABLED */
421
422	/*
423	* Execute the code.
424	*/
425	if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
426	{
427	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatNEMEntry, a);
428	STAM_REL_PROFILE_START(&pVCpu->em.s.StatNEMExec, x);
429	rcStrict = NEMR3RunGC(pVM, pVCpu);
430	STAM_REL_PROFILE_STOP(&pVCpu->em.s.StatNEMExec, x);
431	}
432	else
433	{
434	/* Give up this time slice; virtual time continues */
435	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatNEMEntry, a);
436	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
437	RTThreadSleep(5);
438	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
439	rcStrict = VINF_SUCCESS;
440	}
441
442
443	/*
444	* Deal with high priority post execution FFs before doing anything else.
445	*/
446	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
447	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
448	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
449	rcStrict = emR3HighPriorityPostForcedActions(pVM, pVCpu, rcStrict);
450
451	/*
452	* Process the returned status code.
453	*/
454	if (rcStrict >= VINF_EM_FIRST && rcStrict <= VINF_EM_LAST)
455	break;
456
457	rcStrict = emR3NemHandleRC(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict));
458	if (rcStrict != VINF_SUCCESS)
459	break;
460
461	/*
462	* Check and execute forced actions.
463	*/
464	#ifdef VBOX_HIGH_RES_TIMERS_HACK
465	TMTimerPollVoid(pVM, pVCpu);
466	#endif
467	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_ALL_MASK)
468	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_ALL_MASK))
469	{
470	rcStrict = emR3ForcedActions(pVM, pVCpu, VBOXSTRICTRC_TODO(rcStrict));
471	VBOXVMM_EM_FF_ALL_RET(pVCpu, VBOXSTRICTRC_VAL(rcStrict));
472	if ( rcStrict != VINF_SUCCESS
473	&& rcStrict != VINF_EM_RESCHEDULE_HM)
474	{
475	*pfFFDone = true;
476	break;
477	}
478	}
479	}
480
481	/*
482	* Return to outer loop, making sure the fetch all state as we leave.
483	*
484	* Note! Not using CPUM_IMPORT_EXTRN_RET here, to prioritize an rcStrict error
485	* status over import errors.
486	*/
487	if (pVCpu->cpum.GstCtx.fExtrn)
488	{
489	int rcImport = NEMImportStateOnDemand(pVCpu, pVCpu->cpum.GstCtx.fExtrn);
490	AssertReturn(RT_SUCCESS(rcImport) \|\| RT_FAILURE_NP(rcStrict), rcImport);
491	}
492	#if defined(LOG_ENABLED) && defined(DEBUG)
493	RTLogFlush(NULL);
494	#endif
495	return rcStrict;
496	}
497

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMR3Nem.cpp@ 80239

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