EMRaw.cpp@ 39057

Last change on this file since 39057 was 38324, checked in by vboxsync, 13 years ago
FE/Qt,FE/BFE,MachineDebugger,EM: Added execution scheduling options to the Qt GUI and reworked the main/VMM interface.
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1	/* $Id: EMRaw.cpp 38324 2011-08-05 14:02:53Z vboxsync $ */
2
3	/** @file
4	* EM - Execution Monitor / Manager - software virtualization
5	*/
6
7	/*
8	* Copyright (C) 2006-2009 Oracle Corporation
9	*
10	* This file is part of VirtualBox Open Source Edition (OSE), as
11	* available from http://www.virtualbox.org. This file is free software;
12	* you can redistribute it and/or modify it under the terms of the GNU
13	* General Public License (GPL) as published by the Free Software
14	* Foundation, in version 2 as it comes in the "COPYING" file of the
15	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
16	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
17	*/
18
19	/** @page pg_em EM - The Execution Monitor / Manager
20	*
21	* The Execution Monitor/Manager is responsible for running the VM, scheduling
22	* the right kind of execution (Raw-mode, Hardware Assisted, Recompiled or
23	* Interpreted), and keeping the CPU states in sync. The function
24	* EMR3ExecuteVM() is the 'main-loop' of the VM, while each of the execution
25	* modes has different inner loops (emR3RawExecute, emR3HwAccExecute, and
26	* emR3RemExecute).
27	*
28	* The interpreted execution is only used to avoid switching between
29	* raw-mode/hwaccm and the recompiler when fielding virtualization traps/faults.
30	* The interpretation is thus implemented as part of EM.
31	*
32	* @see grp_em
33	*/
34
35	/*******************************************************************************
36	* Header Files *
37	*******************************************************************************/
38	#define LOG_GROUP LOG_GROUP_EM
39	#include <VBox/vmm/em.h>
40	#include <VBox/vmm/vmm.h>
41	#include <VBox/vmm/patm.h>
42	#include <VBox/vmm/csam.h>
43	#include <VBox/vmm/selm.h>
44	#include <VBox/vmm/trpm.h>
45	#include <VBox/vmm/iom.h>
46	#include <VBox/vmm/dbgf.h>
47	#include <VBox/vmm/pgm.h>
48	#include <VBox/vmm/rem.h>
49	#include <VBox/vmm/tm.h>
50	#include <VBox/vmm/mm.h>
51	#include <VBox/vmm/ssm.h>
52	#include <VBox/vmm/pdmapi.h>
53	#include <VBox/vmm/pdmcritsect.h>
54	#include <VBox/vmm/pdmqueue.h>
55	#include <VBox/vmm/patm.h>
56	#include "EMInternal.h"
57	#include "internal/em.h"
58	#include <VBox/vmm/vm.h>
59	#include <VBox/vmm/cpumdis.h>
60	#include <VBox/dis.h>
61	#include <VBox/disopcode.h>
62	#include <VBox/vmm/dbgf.h>
63
64	#include <VBox/log.h>
65	#include <iprt/asm.h>
66	#include <iprt/string.h>
67	#include <iprt/stream.h>
68
69
70
71	/*******************************************************************************
72	* Internal Functions *
73	*******************************************************************************/
74	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
75	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
76	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
77	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
78	static int emR3SingleStepExecRem(PVM pVM, uint32_t cIterations);
79	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
80	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
81	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
82
83	#define EMHANDLERC_WITH_PATM
84	#include "EMHandleRCTmpl.h"
85
86
87
88	#ifdef VBOX_WITH_STATISTICS
89	/**
90	* Just a braindead function to keep track of cli addresses.
91	* @param pVM VM handle.
92	* @param pVMCPU VMCPU handle.
93	* @param GCPtrInstr The EIP of the cli instruction.
94	*/
95	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
96	{
97	PCLISTAT pRec;
98
99	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
100	if (!pRec)
101	{
102	/* New cli instruction; insert into the tree. */
103	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
104	Assert(pRec);
105	if (!pRec)
106	return;
107	pRec->Core.Key = GCPtrInstr;
108
109	char szCliStatName[32];
110	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
111	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
112
113	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
114	Assert(fRc); NOREF(fRc);
115	}
116	STAM_COUNTER_INC(&pRec->Counter);
117	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
118	}
119	#endif /* VBOX_WITH_STATISTICS */
120
121
122
123	/**
124	* Resumes executing hypervisor after a debug event.
125	*
126	* This is kind of special since our current guest state is
127	* potentially out of sync.
128	*
129	* @returns VBox status code.
130	* @param pVM The VM handle.
131	* @param pVCpu The VMCPU handle.
132	*/
133	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
134	{
135	int rc;
136	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
137	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
138	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
139
140	/*
141	* Resume execution.
142	*/
143	CPUMR3RawEnter(pVCpu, NULL);
144	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
145	rc = VMMR3ResumeHyper(pVM, pVCpu);
146	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
147	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
148	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
149
150	/*
151	* Deal with the return code.
152	*/
153	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
154	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
155	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
156	return rc;
157	}
158
159
160	/**
161	* Steps rawmode.
162	*
163	* @returns VBox status code.
164	* @param pVM The VM handle.
165	* @param pVCpu The VMCPU handle.
166	*/
167	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
168	{
169	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
170	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
171	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
172	int rc;
173	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
174	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
175	#ifndef DEBUG_sandervl
176	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
177	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
178	#endif
179	if (fGuest)
180	{
181	/*
182	* Check vital forced actions, but ignore pending interrupts and timers.
183	*/
184	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
185	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
186	{
187	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
188	if (rc != VINF_SUCCESS)
189	return rc;
190	}
191
192	/*
193	* Set flags for single stepping.
194	*/
195	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
196	}
197	else
198	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
199
200	/*
201	* Single step.
202	* We do not start time or anything, if anything we should just do a few nanoseconds.
203	*/
204	CPUMR3RawEnter(pVCpu, NULL);
205	do
206	{
207	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
208	rc = VMMR3ResumeHyper(pVM, pVCpu);
209	else
210	rc = VMMR3RawRunGC(pVM, pVCpu);
211	#ifndef DEBUG_sandervl
212	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
213	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
214	#endif
215	} while ( rc == VINF_SUCCESS
216	\|\| rc == VINF_EM_RAW_INTERRUPT);
217	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
218	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
219
220	/*
221	* Make sure the trap flag is cleared.
222	* (Too bad if the guest is trying to single step too.)
223	*/
224	if (fGuest)
225	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
226	else
227	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
228
229	/*
230	* Deal with the return codes.
231	*/
232	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
233	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
234	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
235	return rc;
236	}
237
238
239	#ifdef DEBUG
240
241
242	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
243	{
244	int rc = VINF_SUCCESS;
245	EMSTATE enmOldState = pVCpu->em.s.enmState;
246	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
247
248	Log(("Single step BEGIN:\n"));
249	for (uint32_t i = 0; i < cIterations; i++)
250	{
251	DBGFR3PrgStep(pVCpu);
252	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
253	rc = emR3RawStep(pVM, pVCpu);
254	if (rc != VINF_SUCCESS)
255	break;
256	}
257	Log(("Single step END: rc=%Rrc\n", rc));
258	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
259	pVCpu->em.s.enmState = enmOldState;
260	return rc;
261	}
262
263	#endif /* DEBUG */
264
265
266	/**
267	* Executes one (or perhaps a few more) instruction(s).
268	*
269	* @returns VBox status code suitable for EM.
270	*
271	* @param pVM VM handle.
272	* @param pVCpu VMCPU handle
273	* @param rcGC GC return code
274	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
275	* instruction and prefix the log output with this text.
276	*/
277	#ifdef LOG_ENABLED
278	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
279	#else
280	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
281	#endif
282	{
283	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
284	int rc;
285
286	/*
287	*
288	* The simple solution is to use the recompiler.
289	* The better solution is to disassemble the current instruction and
290	* try handle as many as possible without using REM.
291	*
292	*/
293
294	#ifdef LOG_ENABLED
295	/*
296	* Disassemble the instruction if requested.
297	*/
298	if (pszPrefix)
299	{
300	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
301	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
302	}
303	#endif /* LOG_ENABLED */
304
305	/*
306	* PATM is making life more interesting.
307	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
308	* tell PATM there is a trap in this code and have it take the appropriate actions
309	* to allow us execute the code in REM.
310	*/
311	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
312	{
313	Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
314
315	RTGCPTR pNewEip;
316	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
317	switch (rc)
318	{
319	/*
320	* It's not very useful to emulate a single instruction and then go back to raw
321	* mode; just execute the whole block until IF is set again.
322	*/
323	case VINF_SUCCESS:
324	Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
325	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
326	pCtx->eip = pNewEip;
327	Assert(pCtx->eip);
328
329	if (pCtx->eflags.Bits.u1IF)
330	{
331	/*
332	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
333	*/
334	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
335	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
336	}
337	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
338	{
339	/* special case: iret, that sets IF, detected a pending irq/event */
340	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
341	}
342	return VINF_EM_RESCHEDULE_REM;
343
344	/*
345	* One instruction.
346	*/
347	case VINF_PATCH_EMULATE_INSTR:
348	Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
349	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
350	pCtx->eip = pNewEip;
351	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
352
353	/*
354	* The patch was disabled, hand it to the REM.
355	*/
356	case VERR_PATCH_DISABLED:
357	Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
358	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
359	pCtx->eip = pNewEip;
360	if (pCtx->eflags.Bits.u1IF)
361	{
362	/*
363	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
364	*/
365	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
366	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
367	}
368	return VINF_EM_RESCHEDULE_REM;
369
370	/* Force continued patch exection; usually due to write monitored stack. */
371	case VINF_PATCH_CONTINUE:
372	return VINF_SUCCESS;
373
374	default:
375	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
376	return VERR_IPE_UNEXPECTED_STATUS;
377	}
378	}
379
380	#if 0
381	/* Try our own instruction emulator before falling back to the recompiler. */
382	DISCPUSTATE Cpu;
383	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
384	if (RT_SUCCESS(rc))
385	{
386	uint32_t size;
387
388	switch (Cpu.pCurInstr->opcode)
389	{
390	/* @todo we can do more now */
391	case OP_MOV:
392	case OP_AND:
393	case OP_OR:
394	case OP_XOR:
395	case OP_POP:
396	case OP_INC:
397	case OP_DEC:
398	case OP_XCHG:
399	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
400	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
401	if (RT_SUCCESS(rc))
402	{
403	pCtx->rip += Cpu.opsize;
404	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
405	return rc;
406	}
407	if (rc != VERR_EM_INTERPRETER)
408	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
409	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
410	break;
411	}
412	}
413	#endif /* 0 */
414	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
415	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
416	EMRemLock(pVM);
417	/* Flush the recompiler TLB if the VCPU has changed. */
418	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
419	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
420	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
421
422	rc = REMR3EmulateInstruction(pVM, pVCpu);
423	EMRemUnlock(pVM);
424	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
425
426	return rc;
427	}
428
429
430	/**
431	* Executes one (or perhaps a few more) instruction(s).
432	* This is just a wrapper for discarding pszPrefix in non-logging builds.
433	*
434	* @returns VBox status code suitable for EM.
435	* @param pVM VM handle.
436	* @param pVCpu VMCPU handle.
437	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
438	* instruction and prefix the log output with this text.
439	* @param rcGC GC return code
440	*/
441	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
442	{
443	#ifdef LOG_ENABLED
444	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
445	#else
446	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
447	#endif
448	}
449
450	/**
451	* Executes one (or perhaps a few more) IO instruction(s).
452	*
453	* @returns VBox status code suitable for EM.
454	* @param pVM VM handle.
455	* @param pVCpu VMCPU handle.
456	*/
457	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
458	{
459	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
460
461	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
462
463	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
464	* as io instructions tend to come in packages of more than one
465	*/
466	DISCPUSTATE Cpu;
467	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
468	if (RT_SUCCESS(rc))
469	{
470	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
471
472	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
473	{
474	switch (Cpu.pCurInstr->opcode)
475	{
476	case OP_IN:
477	{
478	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
479	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
480	break;
481	}
482
483	case OP_OUT:
484	{
485	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
486	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
487	break;
488	}
489	}
490	}
491	else if (Cpu.prefix & PREFIX_REP)
492	{
493	switch (Cpu.pCurInstr->opcode)
494	{
495	case OP_INSB:
496	case OP_INSWD:
497	{
498	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
499	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
500	break;
501	}
502
503	case OP_OUTSB:
504	case OP_OUTSWD:
505	{
506	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
507	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
508	break;
509	}
510	}
511	}
512
513	/*
514	* Handled the I/O return codes.
515	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
516	*/
517	if (IOM_SUCCESS(rcStrict))
518	{
519	pCtx->rip += Cpu.opsize;
520	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
521	return VBOXSTRICTRC_TODO(rcStrict);
522	}
523
524	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
525	{
526	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
527	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
528	return VBOXSTRICTRC_TODO(rcStrict);
529	}
530	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
531
532	if (RT_FAILURE(rcStrict))
533	{
534	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
535	return VBOXSTRICTRC_TODO(rcStrict);
536	}
537	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
538	}
539	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
540	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
541	}
542
543
544	/**
545	* Handle a guest context trap.
546	*
547	* @returns VBox status code suitable for EM.
548	* @param pVM VM handle.
549	* @param pVCpu VMCPU handle.
550	*/
551	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
552	{
553	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
554
555	/*
556	* Get the trap info.
557	*/
558	uint8_t u8TrapNo;
559	TRPMEVENT enmType;
560	RTGCUINT uErrorCode;
561	RTGCUINTPTR uCR2;
562	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
563	if (RT_FAILURE(rc))
564	{
565	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
566	return rc;
567	}
568
569
570	#if 1 /* Experimental: Review, disable if it causes trouble. */
571	/*
572	* Handle traps in patch code first.
573	*
574	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
575	* but several traps isn't handled specially by TRPM in RC and we end up here
576	* instead. One example is #DE.
577	*/
578	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
579	if ( uCpl == 0
580	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
581	{
582	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
583	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
584	}
585	#endif
586
587	/*
588	* If the guest gate is marked unpatched, then we will check again if we can patch it.
589	* (This assumes that we've already tried and failed to dispatch the trap in
590	* RC for the gates that already has been patched. Which is true for most high
591	* volume traps, because these are handled specially, but not for odd ones like #DE.)
592	*/
593	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
594	{
595	CSAMR3CheckGates(pVM, u8TrapNo, 1);
596	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
597
598	/* If it was successful, then we could go back to raw mode. */
599	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
600	{
601	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
602	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
603	AssertRCReturn(rc, rc);
604
605	TRPMERRORCODE enmError = uErrorCode != ~0U
606	? TRPM_TRAP_HAS_ERRORCODE
607	: TRPM_TRAP_NO_ERRORCODE;
608	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
609	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
610	{
611	TRPMResetTrap(pVCpu);
612	return VINF_EM_RESCHEDULE_RAW;
613	}
614	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
615	}
616	}
617
618	/*
619	* Scan kernel code that traps; we might not get another chance.
620	*/
621	/** @todo move this up before the dispatching? */
622	if ( (pCtx->ss & X86_SEL_RPL) <= 1
623	&& !pCtx->eflags.Bits.u1VM)
624	{
625	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
626	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
627	}
628
629	/*
630	* Trap specific handling.
631	*/
632	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
633	{
634	/*
635	* If MONITOR & MWAIT are supported, then interpret them here.
636	*/
637	DISCPUSTATE cpu;
638	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
639	if ( RT_SUCCESS(rc)
640	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
641	{
642	uint32_t u32Dummy, u32Features, u32ExtFeatures;
643	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
644	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
645	{
646	rc = TRPMResetTrap(pVCpu);
647	AssertRC(rc);
648
649	uint32_t opsize;
650	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &opsize));
651	if (RT_SUCCESS(rc))
652	{
653	pCtx->rip += cpu.opsize;
654	return rc;
655	}
656	return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
657	}
658	}
659	}
660	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
661	{
662	/*
663	* Handle I/O bitmap?
664	*/
665	/** @todo We're not supposed to be here with a false guest trap concerning
666	* I/O access. We can easily handle those in RC. */
667	DISCPUSTATE cpu;
668	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
669	if ( RT_SUCCESS(rc)
670	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
671	{
672	/*
673	* We should really check the TSS for the IO bitmap, but it's not like this
674	* lazy approach really makes things worse.
675	*/
676	rc = TRPMResetTrap(pVCpu);
677	AssertRC(rc);
678	return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
679	}
680	}
681
682	#ifdef LOG_ENABLED
683	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
684	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
685
686	/* Get guest page information. */
687	uint64_t fFlags = 0;
688	RTGCPHYS GCPhys = 0;
689	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
690	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
691	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
692	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
693	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
694	#endif
695
696	/*
697	* #PG has CR2.
698	* (Because of stuff like above we must set CR2 in a delayed fashion.)
699	*/
700	if (u8TrapNo == 14 /* #PG */)
701	pCtx->cr2 = uCR2;
702
703	return VINF_EM_RESCHEDULE_REM;
704	}
705
706
707	/**
708	* Handle a ring switch trap.
709	* Need to do statistics and to install patches. The result is going to REM.
710	*
711	* @returns VBox status code suitable for EM.
712	* @param pVM VM handle.
713	* @param pVCpu VMCPU handle.
714	*/
715	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
716	{
717	int rc;
718	DISCPUSTATE Cpu;
719	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
720
721	/*
722	* sysenter, syscall & callgate
723	*/
724	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
725	if (RT_SUCCESS(rc))
726	{
727	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
728	{
729	if (pCtx->SysEnter.cs != 0)
730	{
731	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
732	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
733	if (RT_SUCCESS(rc))
734	{
735	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
736	return VINF_EM_RESCHEDULE_RAW;
737	}
738	}
739	}
740
741	#ifdef VBOX_WITH_STATISTICS
742	switch (Cpu.pCurInstr->opcode)
743	{
744	case OP_SYSENTER:
745	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
746	break;
747	case OP_SYSEXIT:
748	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
749	break;
750	case OP_SYSCALL:
751	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
752	break;
753	case OP_SYSRET:
754	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
755	break;
756	}
757	#endif
758	}
759	else
760	AssertRC(rc);
761
762	/* go to the REM to emulate a single instruction */
763	return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
764	}
765
766
767	/**
768	* Handle a trap (\#PF or \#GP) in patch code
769	*
770	* @returns VBox status code suitable for EM.
771	* @param pVM VM handle.
772	* @param pVCpu VMCPU handle.
773	* @param pCtx CPU context
774	* @param gcret GC return code
775	*/
776	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
777	{
778	uint8_t u8TrapNo;
779	int rc;
780	TRPMEVENT enmType;
781	RTGCUINT uErrorCode;
782	RTGCUINTPTR uCR2;
783
784	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
785
786	if (gcret == VINF_PATM_PATCH_INT3)
787	{
788	u8TrapNo = 3;
789	uCR2 = 0;
790	uErrorCode = 0;
791	}
792	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
793	{
794	/* No active trap in this case. Kind of ugly. */
795	u8TrapNo = X86_XCPT_GP;
796	uCR2 = 0;
797	uErrorCode = 0;
798	}
799	else
800	{
801	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
802	if (RT_FAILURE(rc))
803	{
804	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
805	return rc;
806	}
807	/* Reset the trap as we'll execute the original instruction again. */
808	TRPMResetTrap(pVCpu);
809	}
810
811	/*
812	* Deal with traps inside patch code.
813	* (This code won't run outside GC.)
814	*/
815	if (u8TrapNo != 1)
816	{
817	#ifdef LOG_ENABLED
818	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
819	DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
820
821	DISCPUSTATE Cpu;
822	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
823	if ( RT_SUCCESS(rc)
824	&& Cpu.pCurInstr->opcode == OP_IRET)
825	{
826	uint32_t eip, selCS, uEFlags;
827
828	/* Iret crashes are bad as we have already changed the flags on the stack */
829	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
830	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
831	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
832	if (rc == VINF_SUCCESS)
833	{
834	if ( (uEFlags & X86_EFL_VM)
835	\|\| (selCS & X86_SEL_RPL) == 3)
836	{
837	uint32_t selSS, esp;
838
839	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
840	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
841
842	if (uEFlags & X86_EFL_VM)
843	{
844	uint32_t selDS, selES, selFS, selGS;
845	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
846	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
847	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
848	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
849	if (rc == VINF_SUCCESS)
850	{
851	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
852	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
853	}
854	}
855	else
856	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
857	}
858	else
859	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
860	}
861	}
862	#endif /* LOG_ENABLED */
863	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
864	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
865
866	RTGCPTR pNewEip;
867	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
868	switch (rc)
869	{
870	/*
871	* Execute the faulting instruction.
872	*/
873	case VINF_SUCCESS:
874	{
875	/** @todo execute a whole block */
876	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
877	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
878	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
879
880	pCtx->eip = pNewEip;
881	AssertRelease(pCtx->eip);
882
883	if (pCtx->eflags.Bits.u1IF)
884	{
885	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
886	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
887	*/
888	if ( u8TrapNo == X86_XCPT_GP
889	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
890	{
891	/** @todo move to PATMR3HandleTrap */
892	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
893	PATMR3RemovePatch(pVM, pCtx->eip);
894	}
895
896	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
897	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
898
899	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
900	/* Interrupts are enabled; just go back to the original instruction.
901	return VINF_SUCCESS; */
902	}
903	return VINF_EM_RESCHEDULE_REM;
904	}
905
906	/*
907	* One instruction.
908	*/
909	case VINF_PATCH_EMULATE_INSTR:
910	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
911	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
912	pCtx->eip = pNewEip;
913	AssertRelease(pCtx->eip);
914	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
915
916	/*
917	* The patch was disabled, hand it to the REM.
918	*/
919	case VERR_PATCH_DISABLED:
920	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
921	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
922	pCtx->eip = pNewEip;
923	AssertRelease(pCtx->eip);
924
925	if (pCtx->eflags.Bits.u1IF)
926	{
927	/*
928	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
929	*/
930	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
931	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
932	}
933	return VINF_EM_RESCHEDULE_REM;
934
935	/* Force continued patch exection; usually due to write monitored stack. */
936	case VINF_PATCH_CONTINUE:
937	return VINF_SUCCESS;
938
939	/*
940	* Anything else is fatal.
941	*/
942	default:
943	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
944	return VERR_IPE_UNEXPECTED_STATUS;
945	}
946	}
947	return VINF_SUCCESS;
948	}
949
950
951	/**
952	* Handle a privileged instruction.
953	*
954	* @returns VBox status code suitable for EM.
955	* @param pVM VM handle.
956	* @param pVCpu VMCPU handle;
957	*/
958	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
959	{
960	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
961
962	Assert(!pCtx->eflags.Bits.u1VM);
963
964	if (PATMIsEnabled(pVM))
965	{
966	/*
967	* Check if in patch code.
968	*/
969	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
970	{
971	#ifdef LOG_ENABLED
972	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
973	#endif
974	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
975	return VERR_EM_RAW_PATCH_CONFLICT;
976	}
977	if ( (pCtx->ss & X86_SEL_RPL) == 0
978	&& !pCtx->eflags.Bits.u1VM
979	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
980	{
981	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
982	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
983	if (RT_SUCCESS(rc))
984	{
985	#ifdef LOG_ENABLED
986	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
987	#endif
988	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
989	return VINF_SUCCESS;
990	}
991	}
992	}
993
994	#ifdef LOG_ENABLED
995	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
996	{
997	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
998	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
999	}
1000	#endif
1001
1002	/*
1003	* Instruction statistics and logging.
1004	*/
1005	DISCPUSTATE Cpu;
1006	int rc;
1007
1008	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
1009	if (RT_SUCCESS(rc))
1010	{
1011	#ifdef VBOX_WITH_STATISTICS
1012	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
1013	switch (Cpu.pCurInstr->opcode)
1014	{
1015	case OP_INVLPG:
1016	STAM_COUNTER_INC(&pStats->StatInvlpg);
1017	break;
1018	case OP_IRET:
1019	STAM_COUNTER_INC(&pStats->StatIret);
1020	break;
1021	case OP_CLI:
1022	STAM_COUNTER_INC(&pStats->StatCli);
1023	emR3RecordCli(pVM, pVCpu, pCtx->rip);
1024	break;
1025	case OP_STI:
1026	STAM_COUNTER_INC(&pStats->StatSti);
1027	break;
1028	case OP_INSB:
1029	case OP_INSWD:
1030	case OP_IN:
1031	case OP_OUTSB:
1032	case OP_OUTSWD:
1033	case OP_OUT:
1034	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1035	break;
1036
1037	case OP_MOV_CR:
1038	if (Cpu.param1.flags & USE_REG_GEN32)
1039	{
1040	//read
1041	Assert(Cpu.param2.flags & USE_REG_CR);
1042	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1043	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1044	}
1045	else
1046	{
1047	//write
1048	Assert(Cpu.param1.flags & USE_REG_CR);
1049	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1050	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1051	}
1052	break;
1053
1054	case OP_MOV_DR:
1055	STAM_COUNTER_INC(&pStats->StatMovDRx);
1056	break;
1057	case OP_LLDT:
1058	STAM_COUNTER_INC(&pStats->StatMovLldt);
1059	break;
1060	case OP_LIDT:
1061	STAM_COUNTER_INC(&pStats->StatMovLidt);
1062	break;
1063	case OP_LGDT:
1064	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1065	break;
1066	case OP_SYSENTER:
1067	STAM_COUNTER_INC(&pStats->StatSysEnter);
1068	break;
1069	case OP_SYSEXIT:
1070	STAM_COUNTER_INC(&pStats->StatSysExit);
1071	break;
1072	case OP_SYSCALL:
1073	STAM_COUNTER_INC(&pStats->StatSysCall);
1074	break;
1075	case OP_SYSRET:
1076	STAM_COUNTER_INC(&pStats->StatSysRet);
1077	break;
1078	case OP_HLT:
1079	STAM_COUNTER_INC(&pStats->StatHlt);
1080	break;
1081	default:
1082	STAM_COUNTER_INC(&pStats->StatMisc);
1083	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1084	break;
1085	}
1086	#endif /* VBOX_WITH_STATISTICS */
1087	if ( (pCtx->ss & X86_SEL_RPL) == 0
1088	&& !pCtx->eflags.Bits.u1VM
1089	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1090	{
1091	uint32_t size;
1092
1093	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1094	switch (Cpu.pCurInstr->opcode)
1095	{
1096	case OP_CLI:
1097	pCtx->eflags.u32 &= ~X86_EFL_IF;
1098	Assert(Cpu.opsize == 1);
1099	pCtx->rip += Cpu.opsize;
1100	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1101	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1102
1103	case OP_STI:
1104	pCtx->eflags.u32 \|= X86_EFL_IF;
1105	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
1106	Assert(Cpu.opsize == 1);
1107	pCtx->rip += Cpu.opsize;
1108	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1109	return VINF_SUCCESS;
1110
1111	case OP_HLT:
1112	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1113	{
1114	PATMTRANSSTATE enmState;
1115	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1116
1117	if (enmState == PATMTRANS_OVERWRITTEN)
1118	{
1119	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1120	Assert(rc == VERR_PATCH_DISABLED);
1121	/* Conflict detected, patch disabled */
1122	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1123
1124	enmState = PATMTRANS_SAFE;
1125	}
1126
1127	/* The translation had better be successful. Otherwise we can't recover. */
1128	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1129	if (enmState != PATMTRANS_OVERWRITTEN)
1130	pCtx->eip = pOrgInstrGC;
1131	}
1132	/* no break; we could just return VINF_EM_HALT here */
1133
1134	case OP_MOV_CR:
1135	case OP_MOV_DR:
1136	#ifdef LOG_ENABLED
1137	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1138	{
1139	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1140	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1141	}
1142	#endif
1143
1144	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &size));
1145	if (RT_SUCCESS(rc))
1146	{
1147	pCtx->rip += Cpu.opsize;
1148	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1149
1150	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1151	&& Cpu.param1.flags == USE_REG_CR /* write */
1152	)
1153	{
1154	/* Deal with CR0 updates inside patch code that force
1155	* us to go to the recompiler.
1156	*/
1157	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1158	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1159	{
1160	PATMTRANSSTATE enmState;
1161	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1162
1163	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1164	if (enmState == PATMTRANS_OVERWRITTEN)
1165	{
1166	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1167	Assert(rc == VERR_PATCH_DISABLED);
1168	/* Conflict detected, patch disabled */
1169	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1170	enmState = PATMTRANS_SAFE;
1171	}
1172	/* The translation had better be successful. Otherwise we can't recover. */
1173	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1174	if (enmState != PATMTRANS_OVERWRITTEN)
1175	pCtx->rip = pOrgInstrGC;
1176	}
1177
1178	/* Reschedule is necessary as the execution/paging mode might have changed. */
1179	return VINF_EM_RESCHEDULE;
1180	}
1181	return rc; /* can return VINF_EM_HALT as well. */
1182	}
1183	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1184	break; /* fall back to the recompiler */
1185	}
1186	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1187	}
1188	}
1189
1190	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1191	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1192
1193	return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1194	}
1195
1196
1197	/**
1198	* Update the forced rawmode execution modifier.
1199	*
1200	* This function is called when we're returning from the raw-mode loop(s). If we're
1201	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1202	* if not in patch code, the flag will be cleared.
1203	*
1204	* We should never interrupt patch code while it's being executed. Cli patches can
1205	* contain big code blocks, but they are always executed with IF=0. Other patches
1206	* replace single instructions and should be atomic.
1207	*
1208	* @returns Updated rc.
1209	*
1210	* @param pVM The VM handle.
1211	* @param pVCpu The VMCPU handle.
1212	* @param pCtx The guest CPU context.
1213	* @param rc The result code.
1214	*/
1215	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1216	{
1217	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1218	{
1219	/* ignore reschedule attempts. */
1220	switch (rc)
1221	{
1222	case VINF_EM_RESCHEDULE:
1223	case VINF_EM_RESCHEDULE_REM:
1224	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1225	rc = VINF_SUCCESS;
1226	break;
1227	}
1228	pVCpu->em.s.fForceRAW = true;
1229	}
1230	else
1231	pVCpu->em.s.fForceRAW = false;
1232	return rc;
1233	}
1234
1235
1236	/**
1237	* Check for pending raw actions
1238	*
1239	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1240	* EM statuses.
1241	* @param pVM The VM to operate on.
1242	* @param pVCpu The VMCPU handle.
1243	*/
1244	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1245	{
1246	return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1247	}
1248
1249
1250	/**
1251	* Process raw-mode specific forced actions.
1252	*
1253	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1254	*
1255	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1256	* EM statuses.
1257	* @param pVM The VM handle.
1258	* @param pVCpu The VMCPU handle.
1259	* @param pCtx The guest CPUM register context.
1260	*/
1261	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1262	{
1263	/*
1264	* Note that the order is vitally important!
1265	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1266	*/
1267
1268
1269	/*
1270	* Sync selector tables.
1271	*/
1272	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1273	{
1274	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
1275	if (RT_FAILURE(rc))
1276	return rc;
1277	}
1278
1279	/*
1280	* Sync IDT.
1281	*
1282	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1283	* and PGMShwModifyPage, so we're in for trouble if for instance a
1284	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1285	*/
1286	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1287	{
1288	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1289	&& EMIsRawRing0Enabled(pVM)
1290	&& CSAMIsEnabled(pVM))
1291	{
1292	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1293	if (RT_FAILURE(rc))
1294	return rc;
1295	}
1296
1297	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1298	if (RT_FAILURE(rc))
1299	return rc;
1300	}
1301
1302	/*
1303	* Sync TSS.
1304	*/
1305	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1306	{
1307	int rc = SELMR3SyncTSS(pVM, pVCpu);
1308	if (RT_FAILURE(rc))
1309	return rc;
1310	}
1311
1312	/*
1313	* Sync page directory.
1314	*/
1315	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1316	{
1317	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1318	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1319	if (RT_FAILURE(rc))
1320	return rc;
1321
1322	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1323
1324	/* Prefetch pages for EIP and ESP. */
1325	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1326	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1327	if (rc == VINF_SUCCESS)
1328	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1329	if (rc != VINF_SUCCESS)
1330	{
1331	if (rc != VINF_PGM_SYNC_CR3)
1332	{
1333	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1334	return rc;
1335	}
1336	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1337	if (RT_FAILURE(rc))
1338	return rc;
1339	}
1340	/** @todo maybe prefetch the supervisor stack page as well */
1341	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1342	}
1343
1344	/*
1345	* Allocate handy pages (just in case the above actions have consumed some pages).
1346	*/
1347	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1348	{
1349	int rc = PGMR3PhysAllocateHandyPages(pVM);
1350	if (RT_FAILURE(rc))
1351	return rc;
1352	}
1353
1354	/*
1355	* Check whether we're out of memory now.
1356	*
1357	* This may stem from some of the above actions or operations that has been executed
1358	* since we ran FFs. The allocate handy pages must for instance always be followed by
1359	* this check.
1360	*/
1361	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1362	return VINF_EM_NO_MEMORY;
1363
1364	return VINF_SUCCESS;
1365	}
1366
1367
1368	/**
1369	* Executes raw code.
1370	*
1371	* This function contains the raw-mode version of the inner
1372	* execution loop (the outer loop being in EMR3ExecuteVM()).
1373	*
1374	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1375	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1376	*
1377	* @param pVM VM handle.
1378	* @param pVCpu VMCPU handle.
1379	* @param pfFFDone Where to store an indicator telling whether or not
1380	* FFs were done before returning.
1381	*/
1382	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1383	{
1384	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1385
1386	int rc = VERR_INTERNAL_ERROR;
1387	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1388	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
1389	pVCpu->em.s.fForceRAW = false;
1390	*pfFFDone = false;
1391
1392
1393	/*
1394	*
1395	* Spin till we get a forced action or raw mode status code resulting in
1396	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1397	*
1398	*/
1399	for (;;)
1400	{
1401	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1402
1403	/*
1404	* Check various preconditions.
1405	*/
1406	#ifdef VBOX_STRICT
1407	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1408	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
1409	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1410	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1411	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1412	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1413	&& PGMMapHasConflicts(pVM))
1414	{
1415	PGMMapCheck(pVM);
1416	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1417	return VERR_INTERNAL_ERROR;
1418	}
1419	#endif /* VBOX_STRICT */
1420
1421	/*
1422	* Process high priority pre-execution raw-mode FFs.
1423	*/
1424	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1425	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1426	{
1427	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1428	if (rc != VINF_SUCCESS)
1429	break;
1430	}
1431
1432	/*
1433	* If we're going to execute ring-0 code, the guest state needs to
1434	* be modified a bit and some of the state components (IF, SS/CS RPL,
1435	* and perhaps EIP) needs to be stored with PATM.
1436	*/
1437	rc = CPUMR3RawEnter(pVCpu, NULL);
1438	if (rc != VINF_SUCCESS)
1439	{
1440	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1441	break;
1442	}
1443
1444	/*
1445	* Scan code before executing it. Don't bother with user mode or V86 code
1446	*/
1447	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1448	&& !pCtx->eflags.Bits.u1VM
1449	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1450	{
1451	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1452	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1453	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1454	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1455	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1456	{
1457	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1458	if (rc != VINF_SUCCESS)
1459	{
1460	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1461	break;
1462	}
1463	}
1464	}
1465
1466	#ifdef LOG_ENABLED
1467	/*
1468	* Log important stuff before entering GC.
1469	*/
1470	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1471	if (pCtx->eflags.Bits.u1VM)
1472	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1473	else if ((pCtx->ss & X86_SEL_RPL) == 1)
1474	{
1475	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
1476	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
1477	}
1478	else if ((pCtx->ss & X86_SEL_RPL) == 3)
1479	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1480	#endif /* LOG_ENABLED */
1481
1482
1483
1484	/*
1485	* Execute the code.
1486	*/
1487	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1488	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1489	{
1490	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1491	rc = VMMR3RawRunGC(pVM, pVCpu);
1492	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1493	}
1494	else
1495	{
1496	/* Give up this time slice; virtual time continues */
1497	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1498	RTThreadSleep(5);
1499	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1500	rc = VINF_SUCCESS;
1501	}
1502	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1503
1504	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
1505	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1506
1507
1508
1509	/*
1510	* Restore the real CPU state and deal with high priority post
1511	* execution FFs before doing anything else.
1512	*/
1513	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1514	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1515	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1516	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1517	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1518
1519	#ifdef VBOX_STRICT
1520	/*
1521	* Assert TSS consistency & rc vs patch code.
1522	*/
1523	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1524	&& EMIsRawRing0Enabled(pVM))
1525	SELMR3CheckTSS(pVM);
1526	switch (rc)
1527	{
1528	case VINF_SUCCESS:
1529	case VINF_EM_RAW_INTERRUPT:
1530	case VINF_PATM_PATCH_TRAP_PF:
1531	case VINF_PATM_PATCH_TRAP_GP:
1532	case VINF_PATM_PATCH_INT3:
1533	case VINF_PATM_CHECK_PATCH_PAGE:
1534	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1535	case VINF_EM_RAW_GUEST_TRAP:
1536	case VINF_EM_RESCHEDULE_RAW:
1537	break;
1538
1539	default:
1540	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1541	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1542	break;
1543	}
1544	/*
1545	* Let's go paranoid!
1546	*/
1547	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1548	&& PGMMapHasConflicts(pVM))
1549	{
1550	PGMMapCheck(pVM);
1551	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1552	return VERR_INTERNAL_ERROR;
1553	}
1554	#endif /* VBOX_STRICT */
1555
1556	/*
1557	* Process the returned status code.
1558	*/
1559	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1560	{
1561	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1562	break;
1563	}
1564	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1565	if (rc != VINF_SUCCESS)
1566	{
1567	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1568	if (rc != VINF_SUCCESS)
1569	{
1570	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1571	break;
1572	}
1573	}
1574
1575	/*
1576	* Check and execute forced actions.
1577	*/
1578	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1579	TMTimerPollVoid(pVM, pVCpu);
1580	#endif
1581	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1582	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1583	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1584	{
1585	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
1586
1587	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1588	rc = emR3ForcedActions(pVM, pVCpu, rc);
1589	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1590	if ( rc != VINF_SUCCESS
1591	&& rc != VINF_EM_RESCHEDULE_RAW)
1592	{
1593	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1594	if (rc != VINF_SUCCESS)
1595	{
1596	*pfFFDone = true;
1597	break;
1598	}
1599	}
1600	}
1601	}
1602
1603	/*
1604	* Return to outer loop.
1605	*/
1606	#if defined(LOG_ENABLED) && defined(DEBUG)
1607	RTLogFlush(NULL);
1608	#endif
1609	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1610	return rc;
1611	}
1612

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 39057

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