EMRaw.cpp@ 39685

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1	/* $Id: EMRaw.cpp 39685 2011-12-30 01:29:33Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iom.h>
30	#include <VBox/vmm/dbgf.h>
31	#include <VBox/vmm/pgm.h>
32	#include <VBox/vmm/rem.h>
33	#include <VBox/vmm/tm.h>
34	#include <VBox/vmm/mm.h>
35	#include <VBox/vmm/ssm.h>
36	#include <VBox/vmm/pdmapi.h>
37	#include <VBox/vmm/pdmcritsect.h>
38	#include <VBox/vmm/pdmqueue.h>
39	#include <VBox/vmm/patm.h>
40	#include "EMInternal.h"
41	#include "internal/em.h"
42	#include <VBox/vmm/vm.h>
43	#include <VBox/vmm/cpumdis.h>
44	#include <VBox/dis.h>
45	#include <VBox/disopcode.h>
46	#include <VBox/vmm/dbgf.h>
47
48	#include <VBox/log.h>
49	#include <iprt/asm.h>
50	#include <iprt/string.h>
51	#include <iprt/stream.h>
52
53
54
55	/*******************************************************************************
56	* Internal Functions *
57	*******************************************************************************/
58	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
59	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
60	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
61	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
62	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
63	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
64	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
65
66	#define EMHANDLERC_WITH_PATM
67	#include "EMHandleRCTmpl.h"
68
69
70
71	#ifdef VBOX_WITH_STATISTICS
72	/**
73	* Just a braindead function to keep track of cli addresses.
74	* @param pVM VM handle.
75	* @param pVMCPU VMCPU handle.
76	* @param GCPtrInstr The EIP of the cli instruction.
77	*/
78	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
79	{
80	PCLISTAT pRec;
81
82	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
83	if (!pRec)
84	{
85	/* New cli instruction; insert into the tree. */
86	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
87	Assert(pRec);
88	if (!pRec)
89	return;
90	pRec->Core.Key = GCPtrInstr;
91
92	char szCliStatName[32];
93	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
94	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
95
96	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
97	Assert(fRc); NOREF(fRc);
98	}
99	STAM_COUNTER_INC(&pRec->Counter);
100	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
101	}
102	#endif /* VBOX_WITH_STATISTICS */
103
104
105
106	/**
107	* Resumes executing hypervisor after a debug event.
108	*
109	* This is kind of special since our current guest state is
110	* potentially out of sync.
111	*
112	* @returns VBox status code.
113	* @param pVM The VM handle.
114	* @param pVCpu The VMCPU handle.
115	*/
116	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
117	{
118	int rc;
119	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
120	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
121	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
122
123	/*
124	* Resume execution.
125	*/
126	CPUMR3RawEnter(pVCpu, NULL);
127	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
128	rc = VMMR3ResumeHyper(pVM, pVCpu);
129	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
130	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
131	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
132
133	/*
134	* Deal with the return code.
135	*/
136	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
137	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
138	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
139	return rc;
140	}
141
142
143	/**
144	* Steps rawmode.
145	*
146	* @returns VBox status code.
147	* @param pVM The VM handle.
148	* @param pVCpu The VMCPU handle.
149	*/
150	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
151	{
152	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
153	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
154	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
155	int rc;
156	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
157	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
158	#ifndef DEBUG_sandervl
159	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
160	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
161	#endif
162	if (fGuest)
163	{
164	/*
165	* Check vital forced actions, but ignore pending interrupts and timers.
166	*/
167	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
168	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
169	{
170	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
171	if (rc != VINF_SUCCESS)
172	return rc;
173	}
174
175	/*
176	* Set flags for single stepping.
177	*/
178	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
179	}
180	else
181	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
182
183	/*
184	* Single step.
185	* We do not start time or anything, if anything we should just do a few nanoseconds.
186	*/
187	CPUMR3RawEnter(pVCpu, NULL);
188	do
189	{
190	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
191	rc = VMMR3ResumeHyper(pVM, pVCpu);
192	else
193	rc = VMMR3RawRunGC(pVM, pVCpu);
194	#ifndef DEBUG_sandervl
195	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
196	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
197	#endif
198	} while ( rc == VINF_SUCCESS
199	\|\| rc == VINF_EM_RAW_INTERRUPT);
200	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
201	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
202
203	/*
204	* Make sure the trap flag is cleared.
205	* (Too bad if the guest is trying to single step too.)
206	*/
207	if (fGuest)
208	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
209	else
210	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
211
212	/*
213	* Deal with the return codes.
214	*/
215	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
216	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
217	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
218	return rc;
219	}
220
221
222	#ifdef DEBUG
223
224
225	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
226	{
227	int rc = VINF_SUCCESS;
228	EMSTATE enmOldState = pVCpu->em.s.enmState;
229	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
230
231	Log(("Single step BEGIN:\n"));
232	for (uint32_t i = 0; i < cIterations; i++)
233	{
234	DBGFR3PrgStep(pVCpu);
235	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
236	rc = emR3RawStep(pVM, pVCpu);
237	if (rc != VINF_SUCCESS)
238	break;
239	}
240	Log(("Single step END: rc=%Rrc\n", rc));
241	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
242	pVCpu->em.s.enmState = enmOldState;
243	return rc;
244	}
245
246	#endif /* DEBUG */
247
248
249	/**
250	* Executes one (or perhaps a few more) instruction(s).
251	*
252	* @returns VBox status code suitable for EM.
253	*
254	* @param pVM VM handle.
255	* @param pVCpu VMCPU handle
256	* @param rcGC GC return code
257	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
258	* instruction and prefix the log output with this text.
259	*/
260	#ifdef LOG_ENABLED
261	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
262	#else
263	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
264	#endif
265	{
266	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
267	int rc;
268
269	/*
270	*
271	* The simple solution is to use the recompiler.
272	* The better solution is to disassemble the current instruction and
273	* try handle as many as possible without using REM.
274	*
275	*/
276
277	#ifdef LOG_ENABLED
278	/*
279	* Disassemble the instruction if requested.
280	*/
281	if (pszPrefix)
282	{
283	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
284	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
285	}
286	#endif /* LOG_ENABLED */
287
288	/*
289	* PATM is making life more interesting.
290	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
291	* tell PATM there is a trap in this code and have it take the appropriate actions
292	* to allow us execute the code in REM.
293	*/
294	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
295	{
296	Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
297
298	RTGCPTR pNewEip;
299	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
300	switch (rc)
301	{
302	/*
303	* It's not very useful to emulate a single instruction and then go back to raw
304	* mode; just execute the whole block until IF is set again.
305	*/
306	case VINF_SUCCESS:
307	Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
308	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
309	pCtx->eip = pNewEip;
310	Assert(pCtx->eip);
311
312	if (pCtx->eflags.Bits.u1IF)
313	{
314	/*
315	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
316	*/
317	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
318	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
319	}
320	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
321	{
322	/* special case: iret, that sets IF, detected a pending irq/event */
323	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
324	}
325	return VINF_EM_RESCHEDULE_REM;
326
327	/*
328	* One instruction.
329	*/
330	case VINF_PATCH_EMULATE_INSTR:
331	Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
332	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
333	pCtx->eip = pNewEip;
334	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
335
336	/*
337	* The patch was disabled, hand it to the REM.
338	*/
339	case VERR_PATCH_DISABLED:
340	Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
341	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
342	pCtx->eip = pNewEip;
343	if (pCtx->eflags.Bits.u1IF)
344	{
345	/*
346	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
347	*/
348	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
349	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
350	}
351	return VINF_EM_RESCHEDULE_REM;
352
353	/* Force continued patch exection; usually due to write monitored stack. */
354	case VINF_PATCH_CONTINUE:
355	return VINF_SUCCESS;
356
357	default:
358	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
359	return VERR_IPE_UNEXPECTED_STATUS;
360	}
361	}
362
363	#if 0
364	/* Try our own instruction emulator before falling back to the recompiler. */
365	DISCPUSTATE Cpu;
366	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "GEN EMU");
367	if (RT_SUCCESS(rc))
368	{
369	uint32_t size;
370
371	switch (Cpu.pCurInstr->opcode)
372	{
373	/* @todo we can do more now */
374	case OP_MOV:
375	case OP_AND:
376	case OP_OR:
377	case OP_XOR:
378	case OP_POP:
379	case OP_INC:
380	case OP_DEC:
381	case OP_XCHG:
382	STAM_PROFILE_START(&pVCpu->em.s.StatMiscEmu, a);
383	rc = EMInterpretInstructionCPU(pVM, &Cpu, CPUMCTX2CORE(pCtx), 0, &size);
384	if (RT_SUCCESS(rc))
385	{
386	pCtx->rip += Cpu.opsize;
387	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
388	return rc;
389	}
390	if (rc != VERR_EM_INTERPRETER)
391	AssertMsgFailedReturn(("rc=%Rrc\n", rc), rc);
392	STAM_PROFILE_STOP(&pVCpu->em.s.StatMiscEmu, a);
393	break;
394	}
395	}
396	#endif /* 0 */
397	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
398	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
399	EMRemLock(pVM);
400	/* Flush the recompiler TLB if the VCPU has changed. */
401	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
402	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
403	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
404
405	rc = REMR3EmulateInstruction(pVM, pVCpu);
406	EMRemUnlock(pVM);
407	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
408
409	return rc;
410	}
411
412
413	/**
414	* Executes one (or perhaps a few more) instruction(s).
415	* This is just a wrapper for discarding pszPrefix in non-logging builds.
416	*
417	* @returns VBox status code suitable for EM.
418	* @param pVM VM handle.
419	* @param pVCpu VMCPU handle.
420	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
421	* instruction and prefix the log output with this text.
422	* @param rcGC GC return code
423	*/
424	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
425	{
426	#ifdef LOG_ENABLED
427	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
428	#else
429	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
430	#endif
431	}
432
433	/**
434	* Executes one (or perhaps a few more) IO instruction(s).
435	*
436	* @returns VBox status code suitable for EM.
437	* @param pVM VM handle.
438	* @param pVCpu VMCPU handle.
439	*/
440	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
441	{
442	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
443
444	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
445
446	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
447	* as io instructions tend to come in packages of more than one
448	*/
449	DISCPUSTATE Cpu;
450	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
451	if (RT_SUCCESS(rc))
452	{
453	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
454
455	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
456	{
457	switch (Cpu.pCurInstr->opcode)
458	{
459	case OP_IN:
460	{
461	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
462	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
463	break;
464	}
465
466	case OP_OUT:
467	{
468	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
469	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
470	break;
471	}
472	}
473	}
474	else if (Cpu.prefix & PREFIX_REP)
475	{
476	switch (Cpu.pCurInstr->opcode)
477	{
478	case OP_INSB:
479	case OP_INSWD:
480	{
481	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
482	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
483	break;
484	}
485
486	case OP_OUTSB:
487	case OP_OUTSWD:
488	{
489	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
490	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
491	break;
492	}
493	}
494	}
495
496	/*
497	* Handled the I/O return codes.
498	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
499	*/
500	if (IOM_SUCCESS(rcStrict))
501	{
502	pCtx->rip += Cpu.opsize;
503	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
504	return VBOXSTRICTRC_TODO(rcStrict);
505	}
506
507	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
508	{
509	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
510	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
511	return VBOXSTRICTRC_TODO(rcStrict);
512	}
513	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
514
515	if (RT_FAILURE(rcStrict))
516	{
517	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
518	return VBOXSTRICTRC_TODO(rcStrict);
519	}
520	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
521	}
522	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
523	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
524	}
525
526
527	/**
528	* Handle a guest context trap.
529	*
530	* @returns VBox status code suitable for EM.
531	* @param pVM VM handle.
532	* @param pVCpu VMCPU handle.
533	*/
534	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
535	{
536	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
537
538	/*
539	* Get the trap info.
540	*/
541	uint8_t u8TrapNo;
542	TRPMEVENT enmType;
543	RTGCUINT uErrorCode;
544	RTGCUINTPTR uCR2;
545	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
546	if (RT_FAILURE(rc))
547	{
548	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
549	return rc;
550	}
551
552
553	#if 1 /* Experimental: Review, disable if it causes trouble. */
554	/*
555	* Handle traps in patch code first.
556	*
557	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
558	* but several traps isn't handled specially by TRPM in RC and we end up here
559	* instead. One example is #DE.
560	*/
561	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
562	if ( uCpl == 0
563	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
564	{
565	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
566	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
567	}
568	#endif
569
570	/*
571	* If the guest gate is marked unpatched, then we will check again if we can patch it.
572	* (This assumes that we've already tried and failed to dispatch the trap in
573	* RC for the gates that already has been patched. Which is true for most high
574	* volume traps, because these are handled specially, but not for odd ones like #DE.)
575	*/
576	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
577	{
578	CSAMR3CheckGates(pVM, u8TrapNo, 1);
579	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
580
581	/* If it was successful, then we could go back to raw mode. */
582	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
583	{
584	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
585	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
586	AssertRCReturn(rc, rc);
587
588	TRPMERRORCODE enmError = uErrorCode != ~0U
589	? TRPM_TRAP_HAS_ERRORCODE
590	: TRPM_TRAP_NO_ERRORCODE;
591	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
592	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
593	{
594	TRPMResetTrap(pVCpu);
595	return VINF_EM_RESCHEDULE_RAW;
596	}
597	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
598	}
599	}
600
601	/*
602	* Scan kernel code that traps; we might not get another chance.
603	*/
604	/** @todo move this up before the dispatching? */
605	if ( (pCtx->ss & X86_SEL_RPL) <= 1
606	&& !pCtx->eflags.Bits.u1VM)
607	{
608	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
609	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
610	}
611
612	/*
613	* Trap specific handling.
614	*/
615	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
616	{
617	/*
618	* If MONITOR & MWAIT are supported, then interpret them here.
619	*/
620	DISCPUSTATE cpu;
621	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
622	if ( RT_SUCCESS(rc)
623	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
624	{
625	uint32_t u32Dummy, u32Features, u32ExtFeatures;
626	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
627	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
628	{
629	rc = TRPMResetTrap(pVCpu);
630	AssertRC(rc);
631
632	uint32_t opsize;
633	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &opsize));
634	if (RT_SUCCESS(rc))
635	{
636	pCtx->rip += cpu.opsize;
637	return rc;
638	}
639	return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
640	}
641	}
642	}
643	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
644	{
645	/*
646	* Handle I/O bitmap?
647	*/
648	/** @todo We're not supposed to be here with a false guest trap concerning
649	* I/O access. We can easily handle those in RC. */
650	DISCPUSTATE cpu;
651	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
652	if ( RT_SUCCESS(rc)
653	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
654	{
655	/*
656	* We should really check the TSS for the IO bitmap, but it's not like this
657	* lazy approach really makes things worse.
658	*/
659	rc = TRPMResetTrap(pVCpu);
660	AssertRC(rc);
661	return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
662	}
663	}
664
665	#ifdef LOG_ENABLED
666	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
667	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
668
669	/* Get guest page information. */
670	uint64_t fFlags = 0;
671	RTGCPHYS GCPhys = 0;
672	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
673	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
674	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
675	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
676	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
677	#endif
678
679	/*
680	* #PG has CR2.
681	* (Because of stuff like above we must set CR2 in a delayed fashion.)
682	*/
683	if (u8TrapNo == 14 /* #PG */)
684	pCtx->cr2 = uCR2;
685
686	return VINF_EM_RESCHEDULE_REM;
687	}
688
689
690	/**
691	* Handle a ring switch trap.
692	* Need to do statistics and to install patches. The result is going to REM.
693	*
694	* @returns VBox status code suitable for EM.
695	* @param pVM VM handle.
696	* @param pVCpu VMCPU handle.
697	*/
698	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
699	{
700	int rc;
701	DISCPUSTATE Cpu;
702	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
703
704	/*
705	* sysenter, syscall & callgate
706	*/
707	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
708	if (RT_SUCCESS(rc))
709	{
710	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
711	{
712	if (pCtx->SysEnter.cs != 0)
713	{
714	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
715	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
716	if (RT_SUCCESS(rc))
717	{
718	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
719	return VINF_EM_RESCHEDULE_RAW;
720	}
721	}
722	}
723
724	#ifdef VBOX_WITH_STATISTICS
725	switch (Cpu.pCurInstr->opcode)
726	{
727	case OP_SYSENTER:
728	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
729	break;
730	case OP_SYSEXIT:
731	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
732	break;
733	case OP_SYSCALL:
734	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
735	break;
736	case OP_SYSRET:
737	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
738	break;
739	}
740	#endif
741	}
742	else
743	AssertRC(rc);
744
745	/* go to the REM to emulate a single instruction */
746	return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
747	}
748
749
750	/**
751	* Handle a trap (\#PF or \#GP) in patch code
752	*
753	* @returns VBox status code suitable for EM.
754	* @param pVM VM handle.
755	* @param pVCpu VMCPU handle.
756	* @param pCtx CPU context
757	* @param gcret GC return code
758	*/
759	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
760	{
761	uint8_t u8TrapNo;
762	int rc;
763	TRPMEVENT enmType;
764	RTGCUINT uErrorCode;
765	RTGCUINTPTR uCR2;
766
767	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
768
769	if (gcret == VINF_PATM_PATCH_INT3)
770	{
771	u8TrapNo = 3;
772	uCR2 = 0;
773	uErrorCode = 0;
774	}
775	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
776	{
777	/* No active trap in this case. Kind of ugly. */
778	u8TrapNo = X86_XCPT_GP;
779	uCR2 = 0;
780	uErrorCode = 0;
781	}
782	else
783	{
784	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
785	if (RT_FAILURE(rc))
786	{
787	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
788	return rc;
789	}
790	/* Reset the trap as we'll execute the original instruction again. */
791	TRPMResetTrap(pVCpu);
792	}
793
794	/*
795	* Deal with traps inside patch code.
796	* (This code won't run outside GC.)
797	*/
798	if (u8TrapNo != 1)
799	{
800	#ifdef LOG_ENABLED
801	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
802	DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
803
804	DISCPUSTATE Cpu;
805	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
806	if ( RT_SUCCESS(rc)
807	&& Cpu.pCurInstr->opcode == OP_IRET)
808	{
809	uint32_t eip, selCS, uEFlags;
810
811	/* Iret crashes are bad as we have already changed the flags on the stack */
812	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
813	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
814	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
815	if (rc == VINF_SUCCESS)
816	{
817	if ( (uEFlags & X86_EFL_VM)
818	\|\| (selCS & X86_SEL_RPL) == 3)
819	{
820	uint32_t selSS, esp;
821
822	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
823	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
824
825	if (uEFlags & X86_EFL_VM)
826	{
827	uint32_t selDS, selES, selFS, selGS;
828	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
829	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
830	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
831	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
832	if (rc == VINF_SUCCESS)
833	{
834	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
835	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
836	}
837	}
838	else
839	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
840	}
841	else
842	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
843	}
844	}
845	#endif /* LOG_ENABLED */
846	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
847	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
848
849	RTGCPTR pNewEip;
850	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
851	switch (rc)
852	{
853	/*
854	* Execute the faulting instruction.
855	*/
856	case VINF_SUCCESS:
857	{
858	/** @todo execute a whole block */
859	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
860	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
861	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
862
863	pCtx->eip = pNewEip;
864	AssertRelease(pCtx->eip);
865
866	if (pCtx->eflags.Bits.u1IF)
867	{
868	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
869	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
870	*/
871	if ( u8TrapNo == X86_XCPT_GP
872	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
873	{
874	/** @todo move to PATMR3HandleTrap */
875	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
876	PATMR3RemovePatch(pVM, pCtx->eip);
877	}
878
879	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
880	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
881
882	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
883	/* Interrupts are enabled; just go back to the original instruction.
884	return VINF_SUCCESS; */
885	}
886	return VINF_EM_RESCHEDULE_REM;
887	}
888
889	/*
890	* One instruction.
891	*/
892	case VINF_PATCH_EMULATE_INSTR:
893	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
894	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
895	pCtx->eip = pNewEip;
896	AssertRelease(pCtx->eip);
897	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
898
899	/*
900	* The patch was disabled, hand it to the REM.
901	*/
902	case VERR_PATCH_DISABLED:
903	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
904	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
905	pCtx->eip = pNewEip;
906	AssertRelease(pCtx->eip);
907
908	if (pCtx->eflags.Bits.u1IF)
909	{
910	/*
911	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
912	*/
913	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
914	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
915	}
916	return VINF_EM_RESCHEDULE_REM;
917
918	/* Force continued patch exection; usually due to write monitored stack. */
919	case VINF_PATCH_CONTINUE:
920	return VINF_SUCCESS;
921
922	/*
923	* Anything else is fatal.
924	*/
925	default:
926	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
927	return VERR_IPE_UNEXPECTED_STATUS;
928	}
929	}
930	return VINF_SUCCESS;
931	}
932
933
934	/**
935	* Handle a privileged instruction.
936	*
937	* @returns VBox status code suitable for EM.
938	* @param pVM VM handle.
939	* @param pVCpu VMCPU handle;
940	*/
941	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
942	{
943	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
944
945	Assert(!pCtx->eflags.Bits.u1VM);
946
947	if (PATMIsEnabled(pVM))
948	{
949	/*
950	* Check if in patch code.
951	*/
952	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
953	{
954	#ifdef LOG_ENABLED
955	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
956	#endif
957	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
958	return VERR_EM_RAW_PATCH_CONFLICT;
959	}
960	if ( (pCtx->ss & X86_SEL_RPL) == 0
961	&& !pCtx->eflags.Bits.u1VM
962	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
963	{
964	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
965	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
966	if (RT_SUCCESS(rc))
967	{
968	#ifdef LOG_ENABLED
969	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
970	#endif
971	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
972	return VINF_SUCCESS;
973	}
974	}
975	}
976
977	#ifdef LOG_ENABLED
978	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
979	{
980	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
981	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
982	}
983	#endif
984
985	/*
986	* Instruction statistics and logging.
987	*/
988	DISCPUSTATE Cpu;
989	int rc;
990
991	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
992	if (RT_SUCCESS(rc))
993	{
994	#ifdef VBOX_WITH_STATISTICS
995	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
996	switch (Cpu.pCurInstr->opcode)
997	{
998	case OP_INVLPG:
999	STAM_COUNTER_INC(&pStats->StatInvlpg);
1000	break;
1001	case OP_IRET:
1002	STAM_COUNTER_INC(&pStats->StatIret);
1003	break;
1004	case OP_CLI:
1005	STAM_COUNTER_INC(&pStats->StatCli);
1006	emR3RecordCli(pVM, pVCpu, pCtx->rip);
1007	break;
1008	case OP_STI:
1009	STAM_COUNTER_INC(&pStats->StatSti);
1010	break;
1011	case OP_INSB:
1012	case OP_INSWD:
1013	case OP_IN:
1014	case OP_OUTSB:
1015	case OP_OUTSWD:
1016	case OP_OUT:
1017	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
1018	break;
1019
1020	case OP_MOV_CR:
1021	if (Cpu.param1.flags & USE_REG_GEN32)
1022	{
1023	//read
1024	Assert(Cpu.param2.flags & USE_REG_CR);
1025	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
1026	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1027	}
1028	else
1029	{
1030	//write
1031	Assert(Cpu.param1.flags & USE_REG_CR);
1032	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1033	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1034	}
1035	break;
1036
1037	case OP_MOV_DR:
1038	STAM_COUNTER_INC(&pStats->StatMovDRx);
1039	break;
1040	case OP_LLDT:
1041	STAM_COUNTER_INC(&pStats->StatMovLldt);
1042	break;
1043	case OP_LIDT:
1044	STAM_COUNTER_INC(&pStats->StatMovLidt);
1045	break;
1046	case OP_LGDT:
1047	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1048	break;
1049	case OP_SYSENTER:
1050	STAM_COUNTER_INC(&pStats->StatSysEnter);
1051	break;
1052	case OP_SYSEXIT:
1053	STAM_COUNTER_INC(&pStats->StatSysExit);
1054	break;
1055	case OP_SYSCALL:
1056	STAM_COUNTER_INC(&pStats->StatSysCall);
1057	break;
1058	case OP_SYSRET:
1059	STAM_COUNTER_INC(&pStats->StatSysRet);
1060	break;
1061	case OP_HLT:
1062	STAM_COUNTER_INC(&pStats->StatHlt);
1063	break;
1064	default:
1065	STAM_COUNTER_INC(&pStats->StatMisc);
1066	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1067	break;
1068	}
1069	#endif /* VBOX_WITH_STATISTICS */
1070	if ( (pCtx->ss & X86_SEL_RPL) == 0
1071	&& !pCtx->eflags.Bits.u1VM
1072	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1073	{
1074	uint32_t size;
1075
1076	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1077	switch (Cpu.pCurInstr->opcode)
1078	{
1079	case OP_CLI:
1080	pCtx->eflags.u32 &= ~X86_EFL_IF;
1081	Assert(Cpu.opsize == 1);
1082	pCtx->rip += Cpu.opsize;
1083	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1084	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1085
1086	case OP_STI:
1087	pCtx->eflags.u32 \|= X86_EFL_IF;
1088	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
1089	Assert(Cpu.opsize == 1);
1090	pCtx->rip += Cpu.opsize;
1091	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1092	return VINF_SUCCESS;
1093
1094	case OP_HLT:
1095	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1096	{
1097	PATMTRANSSTATE enmState;
1098	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1099
1100	if (enmState == PATMTRANS_OVERWRITTEN)
1101	{
1102	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1103	Assert(rc == VERR_PATCH_DISABLED);
1104	/* Conflict detected, patch disabled */
1105	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1106
1107	enmState = PATMTRANS_SAFE;
1108	}
1109
1110	/* The translation had better be successful. Otherwise we can't recover. */
1111	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1112	if (enmState != PATMTRANS_OVERWRITTEN)
1113	pCtx->eip = pOrgInstrGC;
1114	}
1115	/* no break; we could just return VINF_EM_HALT here */
1116
1117	case OP_MOV_CR:
1118	case OP_MOV_DR:
1119	#ifdef LOG_ENABLED
1120	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1121	{
1122	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1123	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1124	}
1125	#endif
1126
1127	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &size));
1128	if (RT_SUCCESS(rc))
1129	{
1130	pCtx->rip += Cpu.opsize;
1131	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1132
1133	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1134	&& Cpu.param1.flags == USE_REG_CR /* write */
1135	)
1136	{
1137	/* Deal with CR0 updates inside patch code that force
1138	* us to go to the recompiler.
1139	*/
1140	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1141	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1142	{
1143	PATMTRANSSTATE enmState;
1144	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1145
1146	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1147	if (enmState == PATMTRANS_OVERWRITTEN)
1148	{
1149	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1150	Assert(rc == VERR_PATCH_DISABLED);
1151	/* Conflict detected, patch disabled */
1152	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1153	enmState = PATMTRANS_SAFE;
1154	}
1155	/* The translation had better be successful. Otherwise we can't recover. */
1156	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1157	if (enmState != PATMTRANS_OVERWRITTEN)
1158	pCtx->rip = pOrgInstrGC;
1159	}
1160
1161	/* Reschedule is necessary as the execution/paging mode might have changed. */
1162	return VINF_EM_RESCHEDULE;
1163	}
1164	return rc; /* can return VINF_EM_HALT as well. */
1165	}
1166	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1167	break; /* fall back to the recompiler */
1168	}
1169	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1170	}
1171	}
1172
1173	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1174	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1175
1176	return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1177	}
1178
1179
1180	/**
1181	* Update the forced rawmode execution modifier.
1182	*
1183	* This function is called when we're returning from the raw-mode loop(s). If we're
1184	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1185	* if not in patch code, the flag will be cleared.
1186	*
1187	* We should never interrupt patch code while it's being executed. Cli patches can
1188	* contain big code blocks, but they are always executed with IF=0. Other patches
1189	* replace single instructions and should be atomic.
1190	*
1191	* @returns Updated rc.
1192	*
1193	* @param pVM The VM handle.
1194	* @param pVCpu The VMCPU handle.
1195	* @param pCtx The guest CPU context.
1196	* @param rc The result code.
1197	*/
1198	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1199	{
1200	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1201	{
1202	/* ignore reschedule attempts. */
1203	switch (rc)
1204	{
1205	case VINF_EM_RESCHEDULE:
1206	case VINF_EM_RESCHEDULE_REM:
1207	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1208	rc = VINF_SUCCESS;
1209	break;
1210	}
1211	pVCpu->em.s.fForceRAW = true;
1212	}
1213	else
1214	pVCpu->em.s.fForceRAW = false;
1215	return rc;
1216	}
1217
1218
1219	/**
1220	* Check for pending raw actions
1221	*
1222	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1223	* EM statuses.
1224	* @param pVM The VM to operate on.
1225	* @param pVCpu The VMCPU handle.
1226	*/
1227	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1228	{
1229	return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1230	}
1231
1232
1233	/**
1234	* Process raw-mode specific forced actions.
1235	*
1236	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1237	*
1238	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1239	* EM statuses.
1240	* @param pVM The VM handle.
1241	* @param pVCpu The VMCPU handle.
1242	* @param pCtx The guest CPUM register context.
1243	*/
1244	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1245	{
1246	/*
1247	* Note that the order is vitally important!
1248	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1249	*/
1250
1251
1252	/*
1253	* Sync selector tables.
1254	*/
1255	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1256	{
1257	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
1258	if (RT_FAILURE(rc))
1259	return rc;
1260	}
1261
1262	/*
1263	* Sync IDT.
1264	*
1265	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1266	* and PGMShwModifyPage, so we're in for trouble if for instance a
1267	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1268	*/
1269	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1270	{
1271	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1272	&& EMIsRawRing0Enabled(pVM)
1273	&& CSAMIsEnabled(pVM))
1274	{
1275	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1276	if (RT_FAILURE(rc))
1277	return rc;
1278	}
1279
1280	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1281	if (RT_FAILURE(rc))
1282	return rc;
1283	}
1284
1285	/*
1286	* Sync TSS.
1287	*/
1288	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1289	{
1290	int rc = SELMR3SyncTSS(pVM, pVCpu);
1291	if (RT_FAILURE(rc))
1292	return rc;
1293	}
1294
1295	/*
1296	* Sync page directory.
1297	*/
1298	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1299	{
1300	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1301	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1302	if (RT_FAILURE(rc))
1303	return rc;
1304
1305	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1306
1307	/* Prefetch pages for EIP and ESP. */
1308	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1309	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1310	if (rc == VINF_SUCCESS)
1311	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1312	if (rc != VINF_SUCCESS)
1313	{
1314	if (rc != VINF_PGM_SYNC_CR3)
1315	{
1316	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1317	return rc;
1318	}
1319	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1320	if (RT_FAILURE(rc))
1321	return rc;
1322	}
1323	/** @todo maybe prefetch the supervisor stack page as well */
1324	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1325	}
1326
1327	/*
1328	* Allocate handy pages (just in case the above actions have consumed some pages).
1329	*/
1330	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1331	{
1332	int rc = PGMR3PhysAllocateHandyPages(pVM);
1333	if (RT_FAILURE(rc))
1334	return rc;
1335	}
1336
1337	/*
1338	* Check whether we're out of memory now.
1339	*
1340	* This may stem from some of the above actions or operations that has been executed
1341	* since we ran FFs. The allocate handy pages must for instance always be followed by
1342	* this check.
1343	*/
1344	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1345	return VINF_EM_NO_MEMORY;
1346
1347	return VINF_SUCCESS;
1348	}
1349
1350
1351	/**
1352	* Executes raw code.
1353	*
1354	* This function contains the raw-mode version of the inner
1355	* execution loop (the outer loop being in EMR3ExecuteVM()).
1356	*
1357	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1358	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1359	*
1360	* @param pVM VM handle.
1361	* @param pVCpu VMCPU handle.
1362	* @param pfFFDone Where to store an indicator telling whether or not
1363	* FFs were done before returning.
1364	*/
1365	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1366	{
1367	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1368
1369	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1370	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1371	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
1372	pVCpu->em.s.fForceRAW = false;
1373	*pfFFDone = false;
1374
1375
1376	/*
1377	*
1378	* Spin till we get a forced action or raw mode status code resulting in
1379	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1380	*
1381	*/
1382	for (;;)
1383	{
1384	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1385
1386	/*
1387	* Check various preconditions.
1388	*/
1389	#ifdef VBOX_STRICT
1390	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1391	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
1392	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1393	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1394	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1395	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1396	&& PGMMapHasConflicts(pVM))
1397	{
1398	PGMMapCheck(pVM);
1399	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1400	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1401	}
1402	#endif /* VBOX_STRICT */
1403
1404	/*
1405	* Process high priority pre-execution raw-mode FFs.
1406	*/
1407	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1408	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1409	{
1410	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1411	if (rc != VINF_SUCCESS)
1412	break;
1413	}
1414
1415	/*
1416	* If we're going to execute ring-0 code, the guest state needs to
1417	* be modified a bit and some of the state components (IF, SS/CS RPL,
1418	* and perhaps EIP) needs to be stored with PATM.
1419	*/
1420	rc = CPUMR3RawEnter(pVCpu, NULL);
1421	if (rc != VINF_SUCCESS)
1422	{
1423	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1424	break;
1425	}
1426
1427	/*
1428	* Scan code before executing it. Don't bother with user mode or V86 code
1429	*/
1430	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1431	&& !pCtx->eflags.Bits.u1VM
1432	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1433	{
1434	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1435	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1436	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1437	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1438	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1439	{
1440	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1441	if (rc != VINF_SUCCESS)
1442	{
1443	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1444	break;
1445	}
1446	}
1447	}
1448
1449	#ifdef LOG_ENABLED
1450	/*
1451	* Log important stuff before entering GC.
1452	*/
1453	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1454	if (pCtx->eflags.Bits.u1VM)
1455	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1456	else if ((pCtx->ss & X86_SEL_RPL) == 1)
1457	{
1458	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
1459	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
1460	}
1461	else if ((pCtx->ss & X86_SEL_RPL) == 3)
1462	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1463	#endif /* LOG_ENABLED */
1464
1465
1466
1467	/*
1468	* Execute the code.
1469	*/
1470	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1471	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1472	{
1473	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1474	rc = VMMR3RawRunGC(pVM, pVCpu);
1475	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1476	}
1477	else
1478	{
1479	/* Give up this time slice; virtual time continues */
1480	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1481	RTThreadSleep(5);
1482	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1483	rc = VINF_SUCCESS;
1484	}
1485	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1486
1487	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
1488	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1489
1490
1491
1492	/*
1493	* Restore the real CPU state and deal with high priority post
1494	* execution FFs before doing anything else.
1495	*/
1496	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1497	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1498	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1499	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1500	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1501
1502	#ifdef VBOX_STRICT
1503	/*
1504	* Assert TSS consistency & rc vs patch code.
1505	*/
1506	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1507	&& EMIsRawRing0Enabled(pVM))
1508	SELMR3CheckTSS(pVM);
1509	switch (rc)
1510	{
1511	case VINF_SUCCESS:
1512	case VINF_EM_RAW_INTERRUPT:
1513	case VINF_PATM_PATCH_TRAP_PF:
1514	case VINF_PATM_PATCH_TRAP_GP:
1515	case VINF_PATM_PATCH_INT3:
1516	case VINF_PATM_CHECK_PATCH_PAGE:
1517	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1518	case VINF_EM_RAW_GUEST_TRAP:
1519	case VINF_EM_RESCHEDULE_RAW:
1520	break;
1521
1522	default:
1523	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1524	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1525	break;
1526	}
1527	/*
1528	* Let's go paranoid!
1529	*/
1530	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1531	&& PGMMapHasConflicts(pVM))
1532	{
1533	PGMMapCheck(pVM);
1534	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1535	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1536	}
1537	#endif /* VBOX_STRICT */
1538
1539	/*
1540	* Process the returned status code.
1541	*/
1542	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1543	{
1544	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1545	break;
1546	}
1547	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1548	if (rc != VINF_SUCCESS)
1549	{
1550	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1551	if (rc != VINF_SUCCESS)
1552	{
1553	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1554	break;
1555	}
1556	}
1557
1558	/*
1559	* Check and execute forced actions.
1560	*/
1561	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1562	TMTimerPollVoid(pVM, pVCpu);
1563	#endif
1564	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1565	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1566	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1567	{
1568	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
1569
1570	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1571	rc = emR3ForcedActions(pVM, pVCpu, rc);
1572	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1573	if ( rc != VINF_SUCCESS
1574	&& rc != VINF_EM_RESCHEDULE_RAW)
1575	{
1576	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1577	if (rc != VINF_SUCCESS)
1578	{
1579	*pfFFDone = true;
1580	break;
1581	}
1582	}
1583	}
1584	}
1585
1586	/*
1587	* Return to outer loop.
1588	*/
1589	#if defined(LOG_ENABLED) && defined(DEBUG)
1590	RTLogFlush(NULL);
1591	#endif
1592	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1593	return rc;
1594	}
1595

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 39685

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