EMRaw.cpp@ 40360

Last change on this file since 40360 was 40356, checked in by vboxsync, 13 years ago
MWAIT fixes: Only clear the mwait-active flag when actually resuming code execution. Trigger reschedule in the EMMWAIT_FLAG_BREAKIRQIF0 case when VMR3WaitHalted returns and IRQs are pending.
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File size: 55.9 KB

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1	/* $Id: EMRaw.cpp 40356 2012-03-05 13:51:50Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2011 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/pgm.h>
33	#ifdef VBOX_WITH_REM
34	# include <VBox/vmm/rem.h>
35	#endif
36	#include <VBox/vmm/tm.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/vmm/pdmcritsect.h>
41	#include <VBox/vmm/pdmqueue.h>
42	#include <VBox/vmm/patm.h>
43	#include "EMInternal.h"
44	#include "internal/em.h"
45	#include <VBox/vmm/vm.h>
46	#include <VBox/vmm/cpumdis.h>
47	#include <VBox/dis.h>
48	#include <VBox/disopcode.h>
49	#include <VBox/vmm/dbgf.h>
50
51	#include <VBox/log.h>
52	#include <iprt/asm.h>
53	#include <iprt/string.h>
54	#include <iprt/stream.h>
55
56
57
58	/*******************************************************************************
59	* Internal Functions *
60	*******************************************************************************/
61	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
62	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
63	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
64	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
65	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
66	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
67	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
68
69	#define EMHANDLERC_WITH_PATM
70	#include "EMHandleRCTmpl.h"
71
72
73
74	#ifdef VBOX_WITH_STATISTICS
75	/**
76	* Just a braindead function to keep track of cli addresses.
77	* @param pVM VM handle.
78	* @param pVMCPU VMCPU handle.
79	* @param GCPtrInstr The EIP of the cli instruction.
80	*/
81	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
82	{
83	PCLISTAT pRec;
84
85	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
86	if (!pRec)
87	{
88	/* New cli instruction; insert into the tree. */
89	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
90	Assert(pRec);
91	if (!pRec)
92	return;
93	pRec->Core.Key = GCPtrInstr;
94
95	char szCliStatName[32];
96	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
97	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
98
99	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
100	Assert(fRc); NOREF(fRc);
101	}
102	STAM_COUNTER_INC(&pRec->Counter);
103	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
104	}
105	#endif /* VBOX_WITH_STATISTICS */
106
107
108
109	/**
110	* Resumes executing hypervisor after a debug event.
111	*
112	* This is kind of special since our current guest state is
113	* potentially out of sync.
114	*
115	* @returns VBox status code.
116	* @param pVM The VM handle.
117	* @param pVCpu The VMCPU handle.
118	*/
119	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
120	{
121	int rc;
122	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
123	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
124	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
125
126	/*
127	* Resume execution.
128	*/
129	CPUMR3RawEnter(pVCpu, NULL);
130	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
131	rc = VMMR3ResumeHyper(pVM, pVCpu);
132	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
133	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
134	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
135
136	/*
137	* Deal with the return code.
138	*/
139	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
140	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
141	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
142	return rc;
143	}
144
145
146	/**
147	* Steps rawmode.
148	*
149	* @returns VBox status code.
150	* @param pVM The VM handle.
151	* @param pVCpu The VMCPU handle.
152	*/
153	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
154	{
155	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
156	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
157	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
158	int rc;
159	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
160	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
161	#ifndef DEBUG_sandervl
162	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
163	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
164	#endif
165	if (fGuest)
166	{
167	/*
168	* Check vital forced actions, but ignore pending interrupts and timers.
169	*/
170	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
171	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
172	{
173	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
174	if (rc != VINF_SUCCESS)
175	return rc;
176	}
177
178	/*
179	* Set flags for single stepping.
180	*/
181	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
182	}
183	else
184	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
185
186	/*
187	* Single step.
188	* We do not start time or anything, if anything we should just do a few nanoseconds.
189	*/
190	CPUMR3RawEnter(pVCpu, NULL);
191	do
192	{
193	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
194	rc = VMMR3ResumeHyper(pVM, pVCpu);
195	else
196	rc = VMMR3RawRunGC(pVM, pVCpu);
197	#ifndef DEBUG_sandervl
198	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
199	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
200	#endif
201	} while ( rc == VINF_SUCCESS
202	\|\| rc == VINF_EM_RAW_INTERRUPT);
203	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
204	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
205
206	/*
207	* Make sure the trap flag is cleared.
208	* (Too bad if the guest is trying to single step too.)
209	*/
210	if (fGuest)
211	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
212	else
213	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
214
215	/*
216	* Deal with the return codes.
217	*/
218	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
219	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
220	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
221	return rc;
222	}
223
224
225	#ifdef DEBUG
226
227
228	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
229	{
230	int rc = VINF_SUCCESS;
231	EMSTATE enmOldState = pVCpu->em.s.enmState;
232	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
233
234	Log(("Single step BEGIN:\n"));
235	for (uint32_t i = 0; i < cIterations; i++)
236	{
237	DBGFR3PrgStep(pVCpu);
238	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
239	rc = emR3RawStep(pVM, pVCpu);
240	if (rc != VINF_SUCCESS)
241	break;
242	}
243	Log(("Single step END: rc=%Rrc\n", rc));
244	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
245	pVCpu->em.s.enmState = enmOldState;
246	return rc;
247	}
248
249	#endif /* DEBUG */
250
251
252	/**
253	* Executes one (or perhaps a few more) instruction(s).
254	*
255	* @returns VBox status code suitable for EM.
256	*
257	* @param pVM VM handle.
258	* @param pVCpu VMCPU handle
259	* @param rcGC GC return code
260	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
261	* instruction and prefix the log output with this text.
262	*/
263	#ifdef LOG_ENABLED
264	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
265	#else
266	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
267	#endif
268	{
269	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
270	int rc;
271
272	/*
273	*
274	* The simple solution is to use the recompiler.
275	* The better solution is to disassemble the current instruction and
276	* try handle as many as possible without using REM.
277	*
278	*/
279
280	#ifdef LOG_ENABLED
281	/*
282	* Disassemble the instruction if requested.
283	*/
284	if (pszPrefix)
285	{
286	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
287	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
288	}
289	#endif /* LOG_ENABLED */
290
291	/*
292	* PATM is making life more interesting.
293	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
294	* tell PATM there is a trap in this code and have it take the appropriate actions
295	* to allow us execute the code in REM.
296	*/
297	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
298	{
299	Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
300
301	RTGCPTR pNewEip;
302	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
303	switch (rc)
304	{
305	/*
306	* It's not very useful to emulate a single instruction and then go back to raw
307	* mode; just execute the whole block until IF is set again.
308	*/
309	case VINF_SUCCESS:
310	Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
311	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
312	pCtx->eip = pNewEip;
313	Assert(pCtx->eip);
314
315	if (pCtx->eflags.Bits.u1IF)
316	{
317	/*
318	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
319	*/
320	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
321	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
322	}
323	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
324	{
325	/* special case: iret, that sets IF, detected a pending irq/event */
326	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
327	}
328	return VINF_EM_RESCHEDULE_REM;
329
330	/*
331	* One instruction.
332	*/
333	case VINF_PATCH_EMULATE_INSTR:
334	Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
335	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
336	pCtx->eip = pNewEip;
337	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
338
339	/*
340	* The patch was disabled, hand it to the REM.
341	*/
342	case VERR_PATCH_DISABLED:
343	Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
344	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
345	pCtx->eip = pNewEip;
346	if (pCtx->eflags.Bits.u1IF)
347	{
348	/*
349	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
350	*/
351	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
352	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
353	}
354	return VINF_EM_RESCHEDULE_REM;
355
356	/* Force continued patch exection; usually due to write monitored stack. */
357	case VINF_PATCH_CONTINUE:
358	return VINF_SUCCESS;
359
360	default:
361	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
362	return VERR_IPE_UNEXPECTED_STATUS;
363	}
364	}
365
366	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
367	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
368	#ifdef VBOX_WITH_REM
369	EMRemLock(pVM);
370	/* Flush the recompiler TLB if the VCPU has changed. */
371	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
372	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
373	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
374
375	rc = REMR3EmulateInstruction(pVM, pVCpu);
376	EMRemUnlock(pVM);
377	#else
378	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
379	#endif
380	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
381
382	return rc;
383	}
384
385
386	/**
387	* Executes one (or perhaps a few more) instruction(s).
388	* This is just a wrapper for discarding pszPrefix in non-logging builds.
389	*
390	* @returns VBox status code suitable for EM.
391	* @param pVM VM handle.
392	* @param pVCpu VMCPU handle.
393	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
394	* instruction and prefix the log output with this text.
395	* @param rcGC GC return code
396	*/
397	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
398	{
399	#ifdef LOG_ENABLED
400	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
401	#else
402	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
403	#endif
404	}
405
406	/**
407	* Executes one (or perhaps a few more) IO instruction(s).
408	*
409	* @returns VBox status code suitable for EM.
410	* @param pVM VM handle.
411	* @param pVCpu VMCPU handle.
412	*/
413	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
414	{
415	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
416
417	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
418
419	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
420	* as io instructions tend to come in packages of more than one
421	*/
422	DISCPUSTATE Cpu;
423	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
424	if (RT_SUCCESS(rc))
425	{
426	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
427
428	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
429	{
430	switch (Cpu.pCurInstr->opcode)
431	{
432	case OP_IN:
433	{
434	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
435	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
436	break;
437	}
438
439	case OP_OUT:
440	{
441	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
442	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
443	break;
444	}
445	}
446	}
447	else if (Cpu.prefix & PREFIX_REP)
448	{
449	switch (Cpu.pCurInstr->opcode)
450	{
451	case OP_INSB:
452	case OP_INSWD:
453	{
454	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
455	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
456	break;
457	}
458
459	case OP_OUTSB:
460	case OP_OUTSWD:
461	{
462	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
463	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
464	break;
465	}
466	}
467	}
468
469	/*
470	* Handled the I/O return codes.
471	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
472	*/
473	if (IOM_SUCCESS(rcStrict))
474	{
475	pCtx->rip += Cpu.opsize;
476	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
477	return VBOXSTRICTRC_TODO(rcStrict);
478	}
479
480	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
481	{
482	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
483	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
484	return VBOXSTRICTRC_TODO(rcStrict);
485	}
486	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
487
488	if (RT_FAILURE(rcStrict))
489	{
490	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
491	return VBOXSTRICTRC_TODO(rcStrict);
492	}
493	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
494	}
495	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
496	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
497	}
498
499
500	/**
501	* Handle a guest context trap.
502	*
503	* @returns VBox status code suitable for EM.
504	* @param pVM VM handle.
505	* @param pVCpu VMCPU handle.
506	*/
507	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
508	{
509	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
510
511	/*
512	* Get the trap info.
513	*/
514	uint8_t u8TrapNo;
515	TRPMEVENT enmType;
516	RTGCUINT uErrorCode;
517	RTGCUINTPTR uCR2;
518	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
519	if (RT_FAILURE(rc))
520	{
521	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
522	return rc;
523	}
524
525
526	#if 1 /* Experimental: Review, disable if it causes trouble. */
527	/*
528	* Handle traps in patch code first.
529	*
530	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
531	* but several traps isn't handled specially by TRPM in RC and we end up here
532	* instead. One example is #DE.
533	*/
534	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
535	if ( uCpl == 0
536	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
537	{
538	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
539	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
540	}
541	#endif
542
543	/*
544	* If the guest gate is marked unpatched, then we will check again if we can patch it.
545	* (This assumes that we've already tried and failed to dispatch the trap in
546	* RC for the gates that already has been patched. Which is true for most high
547	* volume traps, because these are handled specially, but not for odd ones like #DE.)
548	*/
549	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
550	{
551	CSAMR3CheckGates(pVM, u8TrapNo, 1);
552	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
553
554	/* If it was successful, then we could go back to raw mode. */
555	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
556	{
557	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
558	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
559	AssertRCReturn(rc, rc);
560
561	TRPMERRORCODE enmError = uErrorCode != ~0U
562	? TRPM_TRAP_HAS_ERRORCODE
563	: TRPM_TRAP_NO_ERRORCODE;
564	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
565	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
566	{
567	TRPMResetTrap(pVCpu);
568	return VINF_EM_RESCHEDULE_RAW;
569	}
570	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
571	}
572	}
573
574	/*
575	* Scan kernel code that traps; we might not get another chance.
576	*/
577	/** @todo move this up before the dispatching? */
578	if ( (pCtx->ss & X86_SEL_RPL) <= 1
579	&& !pCtx->eflags.Bits.u1VM)
580	{
581	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
582	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
583	}
584
585	/*
586	* Trap specific handling.
587	*/
588	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
589	{
590	/*
591	* If MONITOR & MWAIT are supported, then interpret them here.
592	*/
593	DISCPUSTATE cpu;
594	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
595	if ( RT_SUCCESS(rc)
596	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
597	{
598	uint32_t u32Dummy, u32Features, u32ExtFeatures;
599	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
600	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
601	{
602	rc = TRPMResetTrap(pVCpu);
603	AssertRC(rc);
604
605	uint32_t opsize;
606	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &opsize));
607	if (RT_SUCCESS(rc))
608	{
609	pCtx->rip += cpu.opsize;
610	return rc;
611	}
612	return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
613	}
614	}
615	}
616	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
617	{
618	/*
619	* Handle I/O bitmap?
620	*/
621	/** @todo We're not supposed to be here with a false guest trap concerning
622	* I/O access. We can easily handle those in RC. */
623	DISCPUSTATE cpu;
624	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
625	if ( RT_SUCCESS(rc)
626	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
627	{
628	/*
629	* We should really check the TSS for the IO bitmap, but it's not like this
630	* lazy approach really makes things worse.
631	*/
632	rc = TRPMResetTrap(pVCpu);
633	AssertRC(rc);
634	return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
635	}
636	}
637
638	#ifdef LOG_ENABLED
639	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
640	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
641
642	/* Get guest page information. */
643	uint64_t fFlags = 0;
644	RTGCPHYS GCPhys = 0;
645	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
646	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
647	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
648	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
649	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
650	#endif
651
652	/*
653	* #PG has CR2.
654	* (Because of stuff like above we must set CR2 in a delayed fashion.)
655	*/
656	if (u8TrapNo == 14 /* #PG */)
657	pCtx->cr2 = uCR2;
658
659	return VINF_EM_RESCHEDULE_REM;
660	}
661
662
663	/**
664	* Handle a ring switch trap.
665	* Need to do statistics and to install patches. The result is going to REM.
666	*
667	* @returns VBox status code suitable for EM.
668	* @param pVM VM handle.
669	* @param pVCpu VMCPU handle.
670	*/
671	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
672	{
673	int rc;
674	DISCPUSTATE Cpu;
675	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
676
677	/*
678	* sysenter, syscall & callgate
679	*/
680	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
681	if (RT_SUCCESS(rc))
682	{
683	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
684	{
685	if (pCtx->SysEnter.cs != 0)
686	{
687	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
688	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
689	if (RT_SUCCESS(rc))
690	{
691	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
692	return VINF_EM_RESCHEDULE_RAW;
693	}
694	}
695	}
696
697	#ifdef VBOX_WITH_STATISTICS
698	switch (Cpu.pCurInstr->opcode)
699	{
700	case OP_SYSENTER:
701	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
702	break;
703	case OP_SYSEXIT:
704	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
705	break;
706	case OP_SYSCALL:
707	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
708	break;
709	case OP_SYSRET:
710	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
711	break;
712	}
713	#endif
714	}
715	else
716	AssertRC(rc);
717
718	/* go to the REM to emulate a single instruction */
719	return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
720	}
721
722
723	/**
724	* Handle a trap (\#PF or \#GP) in patch code
725	*
726	* @returns VBox status code suitable for EM.
727	* @param pVM VM handle.
728	* @param pVCpu VMCPU handle.
729	* @param pCtx CPU context
730	* @param gcret GC return code
731	*/
732	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
733	{
734	uint8_t u8TrapNo;
735	int rc;
736	TRPMEVENT enmType;
737	RTGCUINT uErrorCode;
738	RTGCUINTPTR uCR2;
739
740	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
741
742	if (gcret == VINF_PATM_PATCH_INT3)
743	{
744	u8TrapNo = 3;
745	uCR2 = 0;
746	uErrorCode = 0;
747	}
748	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
749	{
750	/* No active trap in this case. Kind of ugly. */
751	u8TrapNo = X86_XCPT_GP;
752	uCR2 = 0;
753	uErrorCode = 0;
754	}
755	else
756	{
757	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
758	if (RT_FAILURE(rc))
759	{
760	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
761	return rc;
762	}
763	/* Reset the trap as we'll execute the original instruction again. */
764	TRPMResetTrap(pVCpu);
765	}
766
767	/*
768	* Deal with traps inside patch code.
769	* (This code won't run outside GC.)
770	*/
771	if (u8TrapNo != 1)
772	{
773	#ifdef LOG_ENABLED
774	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
775	DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
776
777	DISCPUSTATE Cpu;
778	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
779	if ( RT_SUCCESS(rc)
780	&& Cpu.pCurInstr->opcode == OP_IRET)
781	{
782	uint32_t eip, selCS, uEFlags;
783
784	/* Iret crashes are bad as we have already changed the flags on the stack */
785	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
786	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
787	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
788	if (rc == VINF_SUCCESS)
789	{
790	if ( (uEFlags & X86_EFL_VM)
791	\|\| (selCS & X86_SEL_RPL) == 3)
792	{
793	uint32_t selSS, esp;
794
795	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
796	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
797
798	if (uEFlags & X86_EFL_VM)
799	{
800	uint32_t selDS, selES, selFS, selGS;
801	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
802	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
803	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
804	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
805	if (rc == VINF_SUCCESS)
806	{
807	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
808	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
809	}
810	}
811	else
812	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
813	}
814	else
815	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
816	}
817	}
818	#endif /* LOG_ENABLED */
819	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
820	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
821
822	RTGCPTR pNewEip;
823	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
824	switch (rc)
825	{
826	/*
827	* Execute the faulting instruction.
828	*/
829	case VINF_SUCCESS:
830	{
831	/** @todo execute a whole block */
832	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
833	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
834	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
835
836	pCtx->eip = pNewEip;
837	AssertRelease(pCtx->eip);
838
839	if (pCtx->eflags.Bits.u1IF)
840	{
841	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
842	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
843	*/
844	if ( u8TrapNo == X86_XCPT_GP
845	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
846	{
847	/** @todo move to PATMR3HandleTrap */
848	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
849	PATMR3RemovePatch(pVM, pCtx->eip);
850	}
851
852	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
853	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
854
855	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
856	/* Interrupts are enabled; just go back to the original instruction.
857	return VINF_SUCCESS; */
858	}
859	return VINF_EM_RESCHEDULE_REM;
860	}
861
862	/*
863	* One instruction.
864	*/
865	case VINF_PATCH_EMULATE_INSTR:
866	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
867	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
868	pCtx->eip = pNewEip;
869	AssertRelease(pCtx->eip);
870	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
871
872	/*
873	* The patch was disabled, hand it to the REM.
874	*/
875	case VERR_PATCH_DISABLED:
876	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
877	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
878	pCtx->eip = pNewEip;
879	AssertRelease(pCtx->eip);
880
881	if (pCtx->eflags.Bits.u1IF)
882	{
883	/*
884	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
885	*/
886	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
887	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
888	}
889	return VINF_EM_RESCHEDULE_REM;
890
891	/* Force continued patch exection; usually due to write monitored stack. */
892	case VINF_PATCH_CONTINUE:
893	return VINF_SUCCESS;
894
895	/*
896	* Anything else is fatal.
897	*/
898	default:
899	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
900	return VERR_IPE_UNEXPECTED_STATUS;
901	}
902	}
903	return VINF_SUCCESS;
904	}
905
906
907	/**
908	* Handle a privileged instruction.
909	*
910	* @returns VBox status code suitable for EM.
911	* @param pVM VM handle.
912	* @param pVCpu VMCPU handle;
913	*/
914	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
915	{
916	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
917
918	Assert(!pCtx->eflags.Bits.u1VM);
919
920	if (PATMIsEnabled(pVM))
921	{
922	/*
923	* Check if in patch code.
924	*/
925	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
926	{
927	#ifdef LOG_ENABLED
928	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
929	#endif
930	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
931	return VERR_EM_RAW_PATCH_CONFLICT;
932	}
933	if ( (pCtx->ss & X86_SEL_RPL) == 0
934	&& !pCtx->eflags.Bits.u1VM
935	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
936	{
937	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
938	(SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
939	if (RT_SUCCESS(rc))
940	{
941	#ifdef LOG_ENABLED
942	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
943	#endif
944	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
945	return VINF_SUCCESS;
946	}
947	}
948	}
949
950	#ifdef LOG_ENABLED
951	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
952	{
953	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
954	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
955	}
956	#endif
957
958	/*
959	* Instruction statistics and logging.
960	*/
961	DISCPUSTATE Cpu;
962	int rc;
963
964	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
965	if (RT_SUCCESS(rc))
966	{
967	#ifdef VBOX_WITH_STATISTICS
968	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
969	switch (Cpu.pCurInstr->opcode)
970	{
971	case OP_INVLPG:
972	STAM_COUNTER_INC(&pStats->StatInvlpg);
973	break;
974	case OP_IRET:
975	STAM_COUNTER_INC(&pStats->StatIret);
976	break;
977	case OP_CLI:
978	STAM_COUNTER_INC(&pStats->StatCli);
979	emR3RecordCli(pVM, pVCpu, pCtx->rip);
980	break;
981	case OP_STI:
982	STAM_COUNTER_INC(&pStats->StatSti);
983	break;
984	case OP_INSB:
985	case OP_INSWD:
986	case OP_IN:
987	case OP_OUTSB:
988	case OP_OUTSWD:
989	case OP_OUT:
990	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
991	break;
992
993	case OP_MOV_CR:
994	if (Cpu.param1.flags & USE_REG_GEN32)
995	{
996	//read
997	Assert(Cpu.param2.flags & USE_REG_CR);
998	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
999	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
1000	}
1001	else
1002	{
1003	//write
1004	Assert(Cpu.param1.flags & USE_REG_CR);
1005	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1006	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1007	}
1008	break;
1009
1010	case OP_MOV_DR:
1011	STAM_COUNTER_INC(&pStats->StatMovDRx);
1012	break;
1013	case OP_LLDT:
1014	STAM_COUNTER_INC(&pStats->StatMovLldt);
1015	break;
1016	case OP_LIDT:
1017	STAM_COUNTER_INC(&pStats->StatMovLidt);
1018	break;
1019	case OP_LGDT:
1020	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1021	break;
1022	case OP_SYSENTER:
1023	STAM_COUNTER_INC(&pStats->StatSysEnter);
1024	break;
1025	case OP_SYSEXIT:
1026	STAM_COUNTER_INC(&pStats->StatSysExit);
1027	break;
1028	case OP_SYSCALL:
1029	STAM_COUNTER_INC(&pStats->StatSysCall);
1030	break;
1031	case OP_SYSRET:
1032	STAM_COUNTER_INC(&pStats->StatSysRet);
1033	break;
1034	case OP_HLT:
1035	STAM_COUNTER_INC(&pStats->StatHlt);
1036	break;
1037	default:
1038	STAM_COUNTER_INC(&pStats->StatMisc);
1039	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1040	break;
1041	}
1042	#endif /* VBOX_WITH_STATISTICS */
1043	if ( (pCtx->ss & X86_SEL_RPL) == 0
1044	&& !pCtx->eflags.Bits.u1VM
1045	&& SELMGetCpuModeFromSelector(pVM, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1046	{
1047	uint32_t size;
1048
1049	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1050	switch (Cpu.pCurInstr->opcode)
1051	{
1052	case OP_CLI:
1053	pCtx->eflags.u32 &= ~X86_EFL_IF;
1054	Assert(Cpu.opsize == 1);
1055	pCtx->rip += Cpu.opsize;
1056	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1057	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1058
1059	case OP_STI:
1060	pCtx->eflags.u32 \|= X86_EFL_IF;
1061	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
1062	Assert(Cpu.opsize == 1);
1063	pCtx->rip += Cpu.opsize;
1064	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1065	return VINF_SUCCESS;
1066
1067	case OP_HLT:
1068	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1069	{
1070	PATMTRANSSTATE enmState;
1071	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1072
1073	if (enmState == PATMTRANS_OVERWRITTEN)
1074	{
1075	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1076	Assert(rc == VERR_PATCH_DISABLED);
1077	/* Conflict detected, patch disabled */
1078	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1079
1080	enmState = PATMTRANS_SAFE;
1081	}
1082
1083	/* The translation had better be successful. Otherwise we can't recover. */
1084	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1085	if (enmState != PATMTRANS_OVERWRITTEN)
1086	pCtx->eip = pOrgInstrGC;
1087	}
1088	/* no break; we could just return VINF_EM_HALT here */
1089
1090	case OP_MOV_CR:
1091	case OP_MOV_DR:
1092	#ifdef LOG_ENABLED
1093	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1094	{
1095	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1096	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1097	}
1098	#endif
1099
1100	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCPU(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR, &size));
1101	if (RT_SUCCESS(rc))
1102	{
1103	pCtx->rip += Cpu.opsize;
1104	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1105
1106	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1107	&& Cpu.param1.flags == USE_REG_CR /* write */
1108	)
1109	{
1110	/* Deal with CR0 updates inside patch code that force
1111	* us to go to the recompiler.
1112	*/
1113	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1114	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1115	{
1116	PATMTRANSSTATE enmState;
1117	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1118
1119	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1120	if (enmState == PATMTRANS_OVERWRITTEN)
1121	{
1122	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1123	Assert(rc == VERR_PATCH_DISABLED);
1124	/* Conflict detected, patch disabled */
1125	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1126	enmState = PATMTRANS_SAFE;
1127	}
1128	/* The translation had better be successful. Otherwise we can't recover. */
1129	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1130	if (enmState != PATMTRANS_OVERWRITTEN)
1131	pCtx->rip = pOrgInstrGC;
1132	}
1133
1134	/* Reschedule is necessary as the execution/paging mode might have changed. */
1135	return VINF_EM_RESCHEDULE;
1136	}
1137	return rc; /* can return VINF_EM_HALT as well. */
1138	}
1139	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1140	break; /* fall back to the recompiler */
1141	}
1142	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1143	}
1144	}
1145
1146	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1147	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1148
1149	return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1150	}
1151
1152
1153	/**
1154	* Update the forced rawmode execution modifier.
1155	*
1156	* This function is called when we're returning from the raw-mode loop(s). If we're
1157	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1158	* if not in patch code, the flag will be cleared.
1159	*
1160	* We should never interrupt patch code while it's being executed. Cli patches can
1161	* contain big code blocks, but they are always executed with IF=0. Other patches
1162	* replace single instructions and should be atomic.
1163	*
1164	* @returns Updated rc.
1165	*
1166	* @param pVM The VM handle.
1167	* @param pVCpu The VMCPU handle.
1168	* @param pCtx The guest CPU context.
1169	* @param rc The result code.
1170	*/
1171	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1172	{
1173	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1174	{
1175	/* ignore reschedule attempts. */
1176	switch (rc)
1177	{
1178	case VINF_EM_RESCHEDULE:
1179	case VINF_EM_RESCHEDULE_REM:
1180	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1181	rc = VINF_SUCCESS;
1182	break;
1183	}
1184	pVCpu->em.s.fForceRAW = true;
1185	}
1186	else
1187	pVCpu->em.s.fForceRAW = false;
1188	return rc;
1189	}
1190
1191
1192	/**
1193	* Check for pending raw actions
1194	*
1195	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1196	* EM statuses.
1197	* @param pVM The VM to operate on.
1198	* @param pVCpu The VMCPU handle.
1199	*/
1200	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1201	{
1202	return emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1203	}
1204
1205
1206	/**
1207	* Process raw-mode specific forced actions.
1208	*
1209	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1210	*
1211	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1212	* EM statuses.
1213	* @param pVM The VM handle.
1214	* @param pVCpu The VMCPU handle.
1215	* @param pCtx The guest CPUM register context.
1216	*/
1217	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1218	{
1219	/*
1220	* Note that the order is vitally important!
1221	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1222	*/
1223
1224
1225	/*
1226	* Sync selector tables.
1227	*/
1228	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1229	{
1230	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
1231	if (RT_FAILURE(rc))
1232	return rc;
1233	}
1234
1235	/*
1236	* Sync IDT.
1237	*
1238	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1239	* and PGMShwModifyPage, so we're in for trouble if for instance a
1240	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1241	*/
1242	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1243	{
1244	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1245	&& EMIsRawRing0Enabled(pVM)
1246	&& CSAMIsEnabled(pVM))
1247	{
1248	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1249	if (RT_FAILURE(rc))
1250	return rc;
1251	}
1252
1253	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1254	if (RT_FAILURE(rc))
1255	return rc;
1256	}
1257
1258	/*
1259	* Sync TSS.
1260	*/
1261	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1262	{
1263	int rc = SELMR3SyncTSS(pVM, pVCpu);
1264	if (RT_FAILURE(rc))
1265	return rc;
1266	}
1267
1268	/*
1269	* Sync page directory.
1270	*/
1271	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1272	{
1273	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1274	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1275	if (RT_FAILURE(rc))
1276	return rc;
1277
1278	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1279
1280	/* Prefetch pages for EIP and ESP. */
1281	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1282	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1283	if (rc == VINF_SUCCESS)
1284	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1285	if (rc != VINF_SUCCESS)
1286	{
1287	if (rc != VINF_PGM_SYNC_CR3)
1288	{
1289	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1290	return rc;
1291	}
1292	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1293	if (RT_FAILURE(rc))
1294	return rc;
1295	}
1296	/** @todo maybe prefetch the supervisor stack page as well */
1297	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1298	}
1299
1300	/*
1301	* Allocate handy pages (just in case the above actions have consumed some pages).
1302	*/
1303	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1304	{
1305	int rc = PGMR3PhysAllocateHandyPages(pVM);
1306	if (RT_FAILURE(rc))
1307	return rc;
1308	}
1309
1310	/*
1311	* Check whether we're out of memory now.
1312	*
1313	* This may stem from some of the above actions or operations that has been executed
1314	* since we ran FFs. The allocate handy pages must for instance always be followed by
1315	* this check.
1316	*/
1317	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1318	return VINF_EM_NO_MEMORY;
1319
1320	return VINF_SUCCESS;
1321	}
1322
1323
1324	/**
1325	* Executes raw code.
1326	*
1327	* This function contains the raw-mode version of the inner
1328	* execution loop (the outer loop being in EMR3ExecuteVM()).
1329	*
1330	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1331	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1332	*
1333	* @param pVM VM handle.
1334	* @param pVCpu VMCPU handle.
1335	* @param pfFFDone Where to store an indicator telling whether or not
1336	* FFs were done before returning.
1337	*/
1338	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1339	{
1340	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1341
1342	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1343	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1344	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
1345	pVCpu->em.s.fForceRAW = false;
1346	*pfFFDone = false;
1347
1348
1349	/*
1350	*
1351	* Spin till we get a forced action or raw mode status code resulting in
1352	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1353	*
1354	*/
1355	for (;;)
1356	{
1357	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1358
1359	/*
1360	* Check various preconditions.
1361	*/
1362	#ifdef VBOX_STRICT
1363	# ifdef VBOX_WITH_REM
1364	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1365	# endif
1366	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
1367	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1368	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1369	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1370	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1371	&& PGMMapHasConflicts(pVM))
1372	{
1373	PGMMapCheck(pVM);
1374	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1375	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1376	}
1377	#endif /* VBOX_STRICT */
1378
1379	/*
1380	* Process high priority pre-execution raw-mode FFs.
1381	*/
1382	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1383	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1384	{
1385	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1386	if (rc != VINF_SUCCESS)
1387	break;
1388	}
1389
1390	/*
1391	* If we're going to execute ring-0 code, the guest state needs to
1392	* be modified a bit and some of the state components (IF, SS/CS RPL,
1393	* and perhaps EIP) needs to be stored with PATM.
1394	*/
1395	rc = CPUMR3RawEnter(pVCpu, NULL);
1396	if (rc != VINF_SUCCESS)
1397	{
1398	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1399	break;
1400	}
1401
1402	/*
1403	* Scan code before executing it. Don't bother with user mode or V86 code
1404	*/
1405	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1406	&& !pCtx->eflags.Bits.u1VM
1407	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1408	{
1409	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1410	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1411	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1412	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1413	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1414	{
1415	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1416	if (rc != VINF_SUCCESS)
1417	{
1418	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1419	break;
1420	}
1421	}
1422	}
1423
1424	#ifdef LOG_ENABLED
1425	/*
1426	* Log important stuff before entering GC.
1427	*/
1428	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1429	if (pCtx->eflags.Bits.u1VM)
1430	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1431	else if ((pCtx->ss & X86_SEL_RPL) == 1)
1432	{
1433	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
1434	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
1435	}
1436	else if ((pCtx->ss & X86_SEL_RPL) == 3)
1437	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1438	#endif /* LOG_ENABLED */
1439
1440
1441
1442	/*
1443	* Execute the code.
1444	*/
1445	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1446	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1447	{
1448	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1449	rc = VMMR3RawRunGC(pVM, pVCpu);
1450	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1451	}
1452	else
1453	{
1454	/* Give up this time slice; virtual time continues */
1455	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1456	RTThreadSleep(5);
1457	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1458	rc = VINF_SUCCESS;
1459	}
1460	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1461
1462	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
1463	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1464
1465
1466
1467	/*
1468	* Restore the real CPU state and deal with high priority post
1469	* execution FFs before doing anything else.
1470	*/
1471	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1472	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1473	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1474	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1475	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1476
1477	#ifdef VBOX_STRICT
1478	/*
1479	* Assert TSS consistency & rc vs patch code.
1480	*/
1481	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1482	&& EMIsRawRing0Enabled(pVM))
1483	SELMR3CheckTSS(pVM);
1484	switch (rc)
1485	{
1486	case VINF_SUCCESS:
1487	case VINF_EM_RAW_INTERRUPT:
1488	case VINF_PATM_PATCH_TRAP_PF:
1489	case VINF_PATM_PATCH_TRAP_GP:
1490	case VINF_PATM_PATCH_INT3:
1491	case VINF_PATM_CHECK_PATCH_PAGE:
1492	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1493	case VINF_EM_RAW_GUEST_TRAP:
1494	case VINF_EM_RESCHEDULE_RAW:
1495	break;
1496
1497	default:
1498	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1499	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1500	break;
1501	}
1502	/*
1503	* Let's go paranoid!
1504	*/
1505	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1506	&& PGMMapHasConflicts(pVM))
1507	{
1508	PGMMapCheck(pVM);
1509	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1510	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1511	}
1512	#endif /* VBOX_STRICT */
1513
1514	/*
1515	* Process the returned status code.
1516	*/
1517	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1518	{
1519	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1520	break;
1521	}
1522	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1523	if (rc != VINF_SUCCESS)
1524	{
1525	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1526	if (rc != VINF_SUCCESS)
1527	{
1528	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1529	break;
1530	}
1531	}
1532
1533	/*
1534	* Check and execute forced actions.
1535	*/
1536	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1537	TMTimerPollVoid(pVM, pVCpu);
1538	#endif
1539	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1540	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1541	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1542	{
1543	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
1544
1545	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1546	rc = emR3ForcedActions(pVM, pVCpu, rc);
1547	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1548	if ( rc != VINF_SUCCESS
1549	&& rc != VINF_EM_RESCHEDULE_RAW)
1550	{
1551	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1552	if (rc != VINF_SUCCESS)
1553	{
1554	*pfFFDone = true;
1555	break;
1556	}
1557	}
1558	}
1559	}
1560
1561	/*
1562	* Return to outer loop.
1563	*/
1564	#if defined(LOG_ENABLED) && defined(DEBUG)
1565	RTLogFlush(NULL);
1566	#endif
1567	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1568	return rc;
1569	}
1570

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 40360

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