EMRaw.cpp@ 40449

Last change on this file since 40449 was 40449, checked in by vboxsync, 13 years ago
SELM: Refactoring (PVM -> PVMCPU).
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1	/* $Id: EMRaw.cpp 40449 2012-03-13 15:51:02Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/pgm.h>
33	#ifdef VBOX_WITH_REM
34	# include <VBox/vmm/rem.h>
35	#endif
36	#include <VBox/vmm/tm.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/vmm/pdmcritsect.h>
41	#include <VBox/vmm/pdmqueue.h>
42	#include <VBox/vmm/patm.h>
43	#include "EMInternal.h"
44	#include "internal/em.h"
45	#include <VBox/vmm/vm.h>
46	#include <VBox/vmm/cpumdis.h>
47	#include <VBox/dis.h>
48	#include <VBox/disopcode.h>
49	#include <VBox/vmm/dbgf.h>
50	#include "VMMTracing.h"
51
52	#include <VBox/log.h>
53	#include <iprt/asm.h>
54	#include <iprt/string.h>
55	#include <iprt/stream.h>
56
57
58
59	/*******************************************************************************
60	* Internal Functions *
61	*******************************************************************************/
62	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
63	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
64	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
65	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
66	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
67	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
68	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
69
70	#define EMHANDLERC_WITH_PATM
71	#include "EMHandleRCTmpl.h"
72
73
74
75	#ifdef VBOX_WITH_STATISTICS
76	/**
77	* Just a braindead function to keep track of cli addresses.
78	* @param pVM VM handle.
79	* @param pVMCPU VMCPU handle.
80	* @param GCPtrInstr The EIP of the cli instruction.
81	*/
82	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
83	{
84	PCLISTAT pRec;
85
86	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
87	if (!pRec)
88	{
89	/* New cli instruction; insert into the tree. */
90	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
91	Assert(pRec);
92	if (!pRec)
93	return;
94	pRec->Core.Key = GCPtrInstr;
95
96	char szCliStatName[32];
97	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
98	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
99
100	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
101	Assert(fRc); NOREF(fRc);
102	}
103	STAM_COUNTER_INC(&pRec->Counter);
104	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
105	}
106	#endif /* VBOX_WITH_STATISTICS */
107
108
109
110	/**
111	* Resumes executing hypervisor after a debug event.
112	*
113	* This is kind of special since our current guest state is
114	* potentially out of sync.
115	*
116	* @returns VBox status code.
117	* @param pVM The VM handle.
118	* @param pVCpu The VMCPU handle.
119	*/
120	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
121	{
122	int rc;
123	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
124	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
125	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs, pCtx->eip, pCtx->eflags));
126
127	/*
128	* Resume execution.
129	*/
130	CPUMR3RawEnter(pVCpu, NULL);
131	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
132	rc = VMMR3ResumeHyper(pVM, pVCpu);
133	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs, pCtx->eip, pCtx->eflags, rc));
134	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
135	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
136
137	/*
138	* Deal with the return code.
139	*/
140	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
141	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
142	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
143	return rc;
144	}
145
146
147	/**
148	* Steps rawmode.
149	*
150	* @returns VBox status code.
151	* @param pVM The VM handle.
152	* @param pVCpu The VMCPU handle.
153	*/
154	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
155	{
156	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
157	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
158	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
159	int rc;
160	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
161	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
162	#ifndef DEBUG_sandervl
163	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
164	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
165	#endif
166	if (fGuest)
167	{
168	/*
169	* Check vital forced actions, but ignore pending interrupts and timers.
170	*/
171	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
172	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
173	{
174	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
175	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
176	if (rc != VINF_SUCCESS)
177	return rc;
178	}
179
180	/*
181	* Set flags for single stepping.
182	*/
183	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
184	}
185	else
186	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
187
188	/*
189	* Single step.
190	* We do not start time or anything, if anything we should just do a few nanoseconds.
191	*/
192	CPUMR3RawEnter(pVCpu, NULL);
193	do
194	{
195	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
196	rc = VMMR3ResumeHyper(pVM, pVCpu);
197	else
198	rc = VMMR3RawRunGC(pVM, pVCpu);
199	#ifndef DEBUG_sandervl
200	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
201	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
202	#endif
203	} while ( rc == VINF_SUCCESS
204	\|\| rc == VINF_EM_RAW_INTERRUPT);
205	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
206	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
207
208	/*
209	* Make sure the trap flag is cleared.
210	* (Too bad if the guest is trying to single step too.)
211	*/
212	if (fGuest)
213	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
214	else
215	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
216
217	/*
218	* Deal with the return codes.
219	*/
220	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
221	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
222	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
223	return rc;
224	}
225
226
227	#ifdef DEBUG
228
229
230	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
231	{
232	int rc = VINF_SUCCESS;
233	EMSTATE enmOldState = pVCpu->em.s.enmState;
234	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
235
236	Log(("Single step BEGIN:\n"));
237	for (uint32_t i = 0; i < cIterations; i++)
238	{
239	DBGFR3PrgStep(pVCpu);
240	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
241	rc = emR3RawStep(pVM, pVCpu);
242	if (rc != VINF_SUCCESS)
243	break;
244	}
245	Log(("Single step END: rc=%Rrc\n", rc));
246	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
247	pVCpu->em.s.enmState = enmOldState;
248	return rc;
249	}
250
251	#endif /* DEBUG */
252
253
254	/**
255	* Executes one (or perhaps a few more) instruction(s).
256	*
257	* @returns VBox status code suitable for EM.
258	*
259	* @param pVM VM handle.
260	* @param pVCpu VMCPU handle
261	* @param rcGC GC return code
262	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
263	* instruction and prefix the log output with this text.
264	*/
265	#ifdef LOG_ENABLED
266	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
267	#else
268	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
269	#endif
270	{
271	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
272	int rc;
273
274	/*
275	*
276	* The simple solution is to use the recompiler.
277	* The better solution is to disassemble the current instruction and
278	* try handle as many as possible without using REM.
279	*
280	*/
281
282	#ifdef LOG_ENABLED
283	/*
284	* Disassemble the instruction if requested.
285	*/
286	if (pszPrefix)
287	{
288	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
289	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
290	}
291	#endif /* LOG_ENABLED */
292
293	/*
294	* PATM is making life more interesting.
295	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
296	* tell PATM there is a trap in this code and have it take the appropriate actions
297	* to allow us execute the code in REM.
298	*/
299	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
300	{
301	Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
302
303	RTGCPTR pNewEip;
304	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
305	switch (rc)
306	{
307	/*
308	* It's not very useful to emulate a single instruction and then go back to raw
309	* mode; just execute the whole block until IF is set again.
310	*/
311	case VINF_SUCCESS:
312	Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
313	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
314	pCtx->eip = pNewEip;
315	Assert(pCtx->eip);
316
317	if (pCtx->eflags.Bits.u1IF)
318	{
319	/*
320	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
321	*/
322	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
323	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
324	}
325	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
326	{
327	/* special case: iret, that sets IF, detected a pending irq/event */
328	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
329	}
330	return VINF_EM_RESCHEDULE_REM;
331
332	/*
333	* One instruction.
334	*/
335	case VINF_PATCH_EMULATE_INSTR:
336	Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
337	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
338	pCtx->eip = pNewEip;
339	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
340
341	/*
342	* The patch was disabled, hand it to the REM.
343	*/
344	case VERR_PATCH_DISABLED:
345	Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
346	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
347	pCtx->eip = pNewEip;
348	if (pCtx->eflags.Bits.u1IF)
349	{
350	/*
351	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
352	*/
353	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
354	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
355	}
356	return VINF_EM_RESCHEDULE_REM;
357
358	/* Force continued patch exection; usually due to write monitored stack. */
359	case VINF_PATCH_CONTINUE:
360	return VINF_SUCCESS;
361
362	default:
363	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
364	return VERR_IPE_UNEXPECTED_STATUS;
365	}
366	}
367
368	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
369	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
370	#ifdef VBOX_WITH_REM
371	EMRemLock(pVM);
372	/* Flush the recompiler TLB if the VCPU has changed. */
373	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
374	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
375	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
376
377	rc = REMR3EmulateInstruction(pVM, pVCpu);
378	EMRemUnlock(pVM);
379	#else
380	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
381	#endif
382	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
383
384	return rc;
385	}
386
387
388	/**
389	* Executes one (or perhaps a few more) instruction(s).
390	* This is just a wrapper for discarding pszPrefix in non-logging builds.
391	*
392	* @returns VBox status code suitable for EM.
393	* @param pVM VM handle.
394	* @param pVCpu VMCPU handle.
395	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
396	* instruction and prefix the log output with this text.
397	* @param rcGC GC return code
398	*/
399	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
400	{
401	#ifdef LOG_ENABLED
402	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
403	#else
404	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
405	#endif
406	}
407
408	/**
409	* Executes one (or perhaps a few more) IO instruction(s).
410	*
411	* @returns VBox status code suitable for EM.
412	* @param pVM VM handle.
413	* @param pVCpu VMCPU handle.
414	*/
415	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
416	{
417	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
418
419	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
420
421	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
422	* as io instructions tend to come in packages of more than one
423	*/
424	DISCPUSTATE Cpu;
425	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
426	if (RT_SUCCESS(rc))
427	{
428	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
429
430	if (!(Cpu.prefix & (PREFIX_REP \| PREFIX_REPNE)))
431	{
432	switch (Cpu.pCurInstr->opcode)
433	{
434	case OP_IN:
435	{
436	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
437	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
438	break;
439	}
440
441	case OP_OUT:
442	{
443	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
444	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
445	break;
446	}
447	}
448	}
449	else if (Cpu.prefix & PREFIX_REP)
450	{
451	switch (Cpu.pCurInstr->opcode)
452	{
453	case OP_INSB:
454	case OP_INSWD:
455	{
456	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
457	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
458	break;
459	}
460
461	case OP_OUTSB:
462	case OP_OUTSWD:
463	{
464	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
465	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
466	break;
467	}
468	}
469	}
470
471	/*
472	* Handled the I/O return codes.
473	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
474	*/
475	if (IOM_SUCCESS(rcStrict))
476	{
477	pCtx->rip += Cpu.opsize;
478	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
479	return VBOXSTRICTRC_TODO(rcStrict);
480	}
481
482	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
483	{
484	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
485	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
486	return VBOXSTRICTRC_TODO(rcStrict);
487	}
488	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
489
490	if (RT_FAILURE(rcStrict))
491	{
492	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
493	return VBOXSTRICTRC_TODO(rcStrict);
494	}
495	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
496	}
497	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
498	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
499	}
500
501
502	/**
503	* Handle a guest context trap.
504	*
505	* @returns VBox status code suitable for EM.
506	* @param pVM VM handle.
507	* @param pVCpu VMCPU handle.
508	*/
509	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
510	{
511	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
512
513	/*
514	* Get the trap info.
515	*/
516	uint8_t u8TrapNo;
517	TRPMEVENT enmType;
518	RTGCUINT uErrorCode;
519	RTGCUINTPTR uCR2;
520	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
521	if (RT_FAILURE(rc))
522	{
523	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
524	return rc;
525	}
526
527
528	#if 1 /* Experimental: Review, disable if it causes trouble. */
529	/*
530	* Handle traps in patch code first.
531	*
532	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
533	* but several traps isn't handled specially by TRPM in RC and we end up here
534	* instead. One example is #DE.
535	*/
536	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
537	if ( uCpl == 0
538	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
539	{
540	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
541	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
542	}
543	#endif
544
545	/*
546	* If the guest gate is marked unpatched, then we will check again if we can patch it.
547	* (This assumes that we've already tried and failed to dispatch the trap in
548	* RC for the gates that already has been patched. Which is true for most high
549	* volume traps, because these are handled specially, but not for odd ones like #DE.)
550	*/
551	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
552	{
553	CSAMR3CheckGates(pVM, u8TrapNo, 1);
554	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
555
556	/* If it was successful, then we could go back to raw mode. */
557	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
558	{
559	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
560	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
561	AssertRCReturn(rc, rc);
562
563	TRPMERRORCODE enmError = uErrorCode != ~0U
564	? TRPM_TRAP_HAS_ERRORCODE
565	: TRPM_TRAP_NO_ERRORCODE;
566	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
567	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
568	{
569	TRPMResetTrap(pVCpu);
570	return VINF_EM_RESCHEDULE_RAW;
571	}
572	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
573	}
574	}
575
576	/*
577	* Scan kernel code that traps; we might not get another chance.
578	*/
579	/** @todo move this up before the dispatching? */
580	if ( (pCtx->ss & X86_SEL_RPL) <= 1
581	&& !pCtx->eflags.Bits.u1VM)
582	{
583	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
584	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
585	}
586
587	/*
588	* Trap specific handling.
589	*/
590	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
591	{
592	/*
593	* If MONITOR & MWAIT are supported, then interpret them here.
594	*/
595	DISCPUSTATE cpu;
596	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
597	if ( RT_SUCCESS(rc)
598	&& (cpu.pCurInstr->opcode == OP_MONITOR \|\| cpu.pCurInstr->opcode == OP_MWAIT))
599	{
600	uint32_t u32Dummy, u32Features, u32ExtFeatures;
601	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
602	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
603	{
604	rc = TRPMResetTrap(pVCpu);
605	AssertRC(rc);
606
607	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCpuUpdtPC(pVM, pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
608	if (RT_SUCCESS(rc))
609	return rc;
610	return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
611	}
612	}
613	}
614	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
615	{
616	/*
617	* Handle I/O bitmap?
618	*/
619	/** @todo We're not supposed to be here with a false guest trap concerning
620	* I/O access. We can easily handle those in RC. */
621	DISCPUSTATE cpu;
622	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
623	if ( RT_SUCCESS(rc)
624	&& (cpu.pCurInstr->optype & OPTYPE_PORTIO))
625	{
626	/*
627	* We should really check the TSS for the IO bitmap, but it's not like this
628	* lazy approach really makes things worse.
629	*/
630	rc = TRPMResetTrap(pVCpu);
631	AssertRC(rc);
632	return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
633	}
634	}
635
636	#ifdef LOG_ENABLED
637	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
638	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
639
640	/* Get guest page information. */
641	uint64_t fFlags = 0;
642	RTGCPHYS GCPhys = 0;
643	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
644	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
645	pCtx->cs, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0, (enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
646	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
647	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
648	#endif
649
650	/*
651	* #PG has CR2.
652	* (Because of stuff like above we must set CR2 in a delayed fashion.)
653	*/
654	if (u8TrapNo == 14 /* #PG */)
655	pCtx->cr2 = uCR2;
656
657	return VINF_EM_RESCHEDULE_REM;
658	}
659
660
661	/**
662	* Handle a ring switch trap.
663	* Need to do statistics and to install patches. The result is going to REM.
664	*
665	* @returns VBox status code suitable for EM.
666	* @param pVM VM handle.
667	* @param pVCpu VMCPU handle.
668	*/
669	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
670	{
671	int rc;
672	DISCPUSTATE Cpu;
673	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
674
675	/*
676	* sysenter, syscall & callgate
677	*/
678	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
679	if (RT_SUCCESS(rc))
680	{
681	if (Cpu.pCurInstr->opcode == OP_SYSENTER)
682	{
683	if (pCtx->SysEnter.cs != 0)
684	{
685	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
686	(SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
687	if (RT_SUCCESS(rc))
688	{
689	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
690	return VINF_EM_RESCHEDULE_RAW;
691	}
692	}
693	}
694
695	#ifdef VBOX_WITH_STATISTICS
696	switch (Cpu.pCurInstr->opcode)
697	{
698	case OP_SYSENTER:
699	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
700	break;
701	case OP_SYSEXIT:
702	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
703	break;
704	case OP_SYSCALL:
705	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
706	break;
707	case OP_SYSRET:
708	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
709	break;
710	}
711	#endif
712	}
713	else
714	AssertRC(rc);
715
716	/* go to the REM to emulate a single instruction */
717	return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
718	}
719
720
721	/**
722	* Handle a trap (\#PF or \#GP) in patch code
723	*
724	* @returns VBox status code suitable for EM.
725	* @param pVM VM handle.
726	* @param pVCpu VMCPU handle.
727	* @param pCtx CPU context
728	* @param gcret GC return code
729	*/
730	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
731	{
732	uint8_t u8TrapNo;
733	int rc;
734	TRPMEVENT enmType;
735	RTGCUINT uErrorCode;
736	RTGCUINTPTR uCR2;
737
738	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
739
740	if (gcret == VINF_PATM_PATCH_INT3)
741	{
742	u8TrapNo = 3;
743	uCR2 = 0;
744	uErrorCode = 0;
745	}
746	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
747	{
748	/* No active trap in this case. Kind of ugly. */
749	u8TrapNo = X86_XCPT_GP;
750	uCR2 = 0;
751	uErrorCode = 0;
752	}
753	else
754	{
755	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
756	if (RT_FAILURE(rc))
757	{
758	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
759	return rc;
760	}
761	/* Reset the trap as we'll execute the original instruction again. */
762	TRPMResetTrap(pVCpu);
763	}
764
765	/*
766	* Deal with traps inside patch code.
767	* (This code won't run outside GC.)
768	*/
769	if (u8TrapNo != 1)
770	{
771	#ifdef LOG_ENABLED
772	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
773	DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
774
775	DISCPUSTATE Cpu;
776	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
777	if ( RT_SUCCESS(rc)
778	&& Cpu.pCurInstr->opcode == OP_IRET)
779	{
780	uint32_t eip, selCS, uEFlags;
781
782	/* Iret crashes are bad as we have already changed the flags on the stack */
783	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
784	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
785	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
786	if (rc == VINF_SUCCESS)
787	{
788	if ( (uEFlags & X86_EFL_VM)
789	\|\| (selCS & X86_SEL_RPL) == 3)
790	{
791	uint32_t selSS, esp;
792
793	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
794	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
795
796	if (uEFlags & X86_EFL_VM)
797	{
798	uint32_t selDS, selES, selFS, selGS;
799	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
800	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
801	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
802	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
803	if (rc == VINF_SUCCESS)
804	{
805	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
806	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
807	}
808	}
809	else
810	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
811	}
812	else
813	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
814	}
815	}
816	#endif /* LOG_ENABLED */
817	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
818	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
819
820	RTGCPTR pNewEip;
821	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
822	switch (rc)
823	{
824	/*
825	* Execute the faulting instruction.
826	*/
827	case VINF_SUCCESS:
828	{
829	/** @todo execute a whole block */
830	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
831	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
832	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
833
834	pCtx->eip = pNewEip;
835	AssertRelease(pCtx->eip);
836
837	if (pCtx->eflags.Bits.u1IF)
838	{
839	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
840	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
841	*/
842	if ( u8TrapNo == X86_XCPT_GP
843	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
844	{
845	/** @todo move to PATMR3HandleTrap */
846	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
847	PATMR3RemovePatch(pVM, pCtx->eip);
848	}
849
850	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
851	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
852
853	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
854	/* Interrupts are enabled; just go back to the original instruction.
855	return VINF_SUCCESS; */
856	}
857	return VINF_EM_RESCHEDULE_REM;
858	}
859
860	/*
861	* One instruction.
862	*/
863	case VINF_PATCH_EMULATE_INSTR:
864	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
865	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
866	pCtx->eip = pNewEip;
867	AssertRelease(pCtx->eip);
868	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
869
870	/*
871	* The patch was disabled, hand it to the REM.
872	*/
873	case VERR_PATCH_DISABLED:
874	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
875	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
876	pCtx->eip = pNewEip;
877	AssertRelease(pCtx->eip);
878
879	if (pCtx->eflags.Bits.u1IF)
880	{
881	/*
882	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
883	*/
884	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
885	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
886	}
887	return VINF_EM_RESCHEDULE_REM;
888
889	/* Force continued patch exection; usually due to write monitored stack. */
890	case VINF_PATCH_CONTINUE:
891	return VINF_SUCCESS;
892
893	/*
894	* Anything else is fatal.
895	*/
896	default:
897	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
898	return VERR_IPE_UNEXPECTED_STATUS;
899	}
900	}
901	return VINF_SUCCESS;
902	}
903
904
905	/**
906	* Handle a privileged instruction.
907	*
908	* @returns VBox status code suitable for EM.
909	* @param pVM VM handle.
910	* @param pVCpu VMCPU handle;
911	*/
912	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
913	{
914	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
915
916	Assert(!pCtx->eflags.Bits.u1VM);
917
918	if (PATMIsEnabled(pVM))
919	{
920	/*
921	* Check if in patch code.
922	*/
923	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
924	{
925	#ifdef LOG_ENABLED
926	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
927	#endif
928	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
929	return VERR_EM_RAW_PATCH_CONFLICT;
930	}
931	if ( (pCtx->ss & X86_SEL_RPL) == 0
932	&& !pCtx->eflags.Bits.u1VM
933	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
934	{
935	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
936	(SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT) ? PATMFL_CODE32 : 0);
937	if (RT_SUCCESS(rc))
938	{
939	#ifdef LOG_ENABLED
940	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
941	#endif
942	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
943	return VINF_SUCCESS;
944	}
945	}
946	}
947
948	#ifdef LOG_ENABLED
949	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
950	{
951	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
952	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
953	}
954	#endif
955
956	/*
957	* Instruction statistics and logging.
958	*/
959	DISCPUSTATE Cpu;
960	int rc;
961
962	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
963	if (RT_SUCCESS(rc))
964	{
965	#ifdef VBOX_WITH_STATISTICS
966	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
967	switch (Cpu.pCurInstr->opcode)
968	{
969	case OP_INVLPG:
970	STAM_COUNTER_INC(&pStats->StatInvlpg);
971	break;
972	case OP_IRET:
973	STAM_COUNTER_INC(&pStats->StatIret);
974	break;
975	case OP_CLI:
976	STAM_COUNTER_INC(&pStats->StatCli);
977	emR3RecordCli(pVM, pVCpu, pCtx->rip);
978	break;
979	case OP_STI:
980	STAM_COUNTER_INC(&pStats->StatSti);
981	break;
982	case OP_INSB:
983	case OP_INSWD:
984	case OP_IN:
985	case OP_OUTSB:
986	case OP_OUTSWD:
987	case OP_OUT:
988	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
989	break;
990
991	case OP_MOV_CR:
992	if (Cpu.param1.flags & USE_REG_GEN32)
993	{
994	//read
995	Assert(Cpu.param2.flags & USE_REG_CR);
996	Assert(Cpu.param2.base.reg_ctrl <= USE_REG_CR4);
997	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.param2.base.reg_ctrl]);
998	}
999	else
1000	{
1001	//write
1002	Assert(Cpu.param1.flags & USE_REG_CR);
1003	Assert(Cpu.param1.base.reg_ctrl <= USE_REG_CR4);
1004	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.param1.base.reg_ctrl]);
1005	}
1006	break;
1007
1008	case OP_MOV_DR:
1009	STAM_COUNTER_INC(&pStats->StatMovDRx);
1010	break;
1011	case OP_LLDT:
1012	STAM_COUNTER_INC(&pStats->StatMovLldt);
1013	break;
1014	case OP_LIDT:
1015	STAM_COUNTER_INC(&pStats->StatMovLidt);
1016	break;
1017	case OP_LGDT:
1018	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1019	break;
1020	case OP_SYSENTER:
1021	STAM_COUNTER_INC(&pStats->StatSysEnter);
1022	break;
1023	case OP_SYSEXIT:
1024	STAM_COUNTER_INC(&pStats->StatSysExit);
1025	break;
1026	case OP_SYSCALL:
1027	STAM_COUNTER_INC(&pStats->StatSysCall);
1028	break;
1029	case OP_SYSRET:
1030	STAM_COUNTER_INC(&pStats->StatSysRet);
1031	break;
1032	case OP_HLT:
1033	STAM_COUNTER_INC(&pStats->StatHlt);
1034	break;
1035	default:
1036	STAM_COUNTER_INC(&pStats->StatMisc);
1037	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->opcode));
1038	break;
1039	}
1040	#endif /* VBOX_WITH_STATISTICS */
1041	if ( (pCtx->ss & X86_SEL_RPL) == 0
1042	&& !pCtx->eflags.Bits.u1VM
1043	&& SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs, &pCtx->csHid) == CPUMODE_32BIT)
1044	{
1045	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1046	switch (Cpu.pCurInstr->opcode)
1047	{
1048	case OP_CLI:
1049	pCtx->eflags.u32 &= ~X86_EFL_IF;
1050	Assert(Cpu.opsize == 1);
1051	pCtx->rip += Cpu.opsize;
1052	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1053	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1054
1055	case OP_STI:
1056	pCtx->eflags.u32 \|= X86_EFL_IF;
1057	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.opsize);
1058	Assert(Cpu.opsize == 1);
1059	pCtx->rip += Cpu.opsize;
1060	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1061	return VINF_SUCCESS;
1062
1063	case OP_HLT:
1064	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1065	{
1066	PATMTRANSSTATE enmState;
1067	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1068
1069	if (enmState == PATMTRANS_OVERWRITTEN)
1070	{
1071	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1072	Assert(rc == VERR_PATCH_DISABLED);
1073	/* Conflict detected, patch disabled */
1074	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1075
1076	enmState = PATMTRANS_SAFE;
1077	}
1078
1079	/* The translation had better be successful. Otherwise we can't recover. */
1080	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1081	if (enmState != PATMTRANS_OVERWRITTEN)
1082	pCtx->eip = pOrgInstrGC;
1083	}
1084	/* no break; we could just return VINF_EM_HALT here */
1085
1086	case OP_MOV_CR:
1087	case OP_MOV_DR:
1088	#ifdef LOG_ENABLED
1089	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1090	{
1091	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1092	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1093	}
1094	#endif
1095
1096	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionCpuUpdtPC(pVM, pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1097	if (RT_SUCCESS(rc))
1098	{
1099	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1100
1101	if ( Cpu.pCurInstr->opcode == OP_MOV_CR
1102	&& Cpu.param1.flags == USE_REG_CR /* write */
1103	)
1104	{
1105	/* Deal with CR0 updates inside patch code that force
1106	* us to go to the recompiler.
1107	*/
1108	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1109	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1110	{
1111	PATMTRANSSTATE enmState;
1112	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1113
1114	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1115	if (enmState == PATMTRANS_OVERWRITTEN)
1116	{
1117	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1118	Assert(rc == VERR_PATCH_DISABLED);
1119	/* Conflict detected, patch disabled */
1120	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1121	enmState = PATMTRANS_SAFE;
1122	}
1123	/* The translation had better be successful. Otherwise we can't recover. */
1124	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1125	if (enmState != PATMTRANS_OVERWRITTEN)
1126	pCtx->rip = pOrgInstrGC;
1127	}
1128
1129	/* Reschedule is necessary as the execution/paging mode might have changed. */
1130	return VINF_EM_RESCHEDULE;
1131	}
1132	return rc; /* can return VINF_EM_HALT as well. */
1133	}
1134	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1135	break; /* fall back to the recompiler */
1136	}
1137	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1138	}
1139	}
1140
1141	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1142	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1143
1144	return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1145	}
1146
1147
1148	/**
1149	* Update the forced rawmode execution modifier.
1150	*
1151	* This function is called when we're returning from the raw-mode loop(s). If we're
1152	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1153	* if not in patch code, the flag will be cleared.
1154	*
1155	* We should never interrupt patch code while it's being executed. Cli patches can
1156	* contain big code blocks, but they are always executed with IF=0. Other patches
1157	* replace single instructions and should be atomic.
1158	*
1159	* @returns Updated rc.
1160	*
1161	* @param pVM The VM handle.
1162	* @param pVCpu The VMCPU handle.
1163	* @param pCtx The guest CPU context.
1164	* @param rc The result code.
1165	*/
1166	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1167	{
1168	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1169	{
1170	/* ignore reschedule attempts. */
1171	switch (rc)
1172	{
1173	case VINF_EM_RESCHEDULE:
1174	case VINF_EM_RESCHEDULE_REM:
1175	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1176	rc = VINF_SUCCESS;
1177	break;
1178	}
1179	pVCpu->em.s.fForceRAW = true;
1180	}
1181	else
1182	pVCpu->em.s.fForceRAW = false;
1183	return rc;
1184	}
1185
1186
1187	/**
1188	* Check for pending raw actions
1189	*
1190	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1191	* EM statuses.
1192	* @param pVM The VM to operate on.
1193	* @param pVCpu The VMCPU handle.
1194	*/
1195	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1196	{
1197	int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1198	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1199	return rc;
1200	}
1201
1202
1203	/**
1204	* Process raw-mode specific forced actions.
1205	*
1206	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1207	*
1208	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1209	* EM statuses.
1210	* @param pVM The VM handle.
1211	* @param pVCpu The VMCPU handle.
1212	* @param pCtx The guest CPUM register context.
1213	*/
1214	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1215	{
1216	/*
1217	* Note that the order is vitally important!
1218	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1219	*/
1220	VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1221
1222	/*
1223	* Sync selector tables.
1224	*/
1225	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1226	{
1227	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
1228	if (RT_FAILURE(rc))
1229	return rc;
1230	}
1231
1232	/*
1233	* Sync IDT.
1234	*
1235	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1236	* and PGMShwModifyPage, so we're in for trouble if for instance a
1237	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1238	*/
1239	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1240	{
1241	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1242	&& EMIsRawRing0Enabled(pVM)
1243	&& CSAMIsEnabled(pVM))
1244	{
1245	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1246	if (RT_FAILURE(rc))
1247	return rc;
1248	}
1249
1250	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1251	if (RT_FAILURE(rc))
1252	return rc;
1253	}
1254
1255	/*
1256	* Sync TSS.
1257	*/
1258	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1259	{
1260	int rc = SELMR3SyncTSS(pVM, pVCpu);
1261	if (RT_FAILURE(rc))
1262	return rc;
1263	}
1264
1265	/*
1266	* Sync page directory.
1267	*/
1268	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1269	{
1270	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1271	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1272	if (RT_FAILURE(rc))
1273	return rc;
1274
1275	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1276
1277	/* Prefetch pages for EIP and ESP. */
1278	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1279	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1280	if (rc == VINF_SUCCESS)
1281	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DIS_SELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1282	if (rc != VINF_SUCCESS)
1283	{
1284	if (rc != VINF_PGM_SYNC_CR3)
1285	{
1286	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1287	return rc;
1288	}
1289	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1290	if (RT_FAILURE(rc))
1291	return rc;
1292	}
1293	/** @todo maybe prefetch the supervisor stack page as well */
1294	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1295	}
1296
1297	/*
1298	* Allocate handy pages (just in case the above actions have consumed some pages).
1299	*/
1300	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1301	{
1302	int rc = PGMR3PhysAllocateHandyPages(pVM);
1303	if (RT_FAILURE(rc))
1304	return rc;
1305	}
1306
1307	/*
1308	* Check whether we're out of memory now.
1309	*
1310	* This may stem from some of the above actions or operations that has been executed
1311	* since we ran FFs. The allocate handy pages must for instance always be followed by
1312	* this check.
1313	*/
1314	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1315	return VINF_EM_NO_MEMORY;
1316
1317	return VINF_SUCCESS;
1318	}
1319
1320
1321	/**
1322	* Executes raw code.
1323	*
1324	* This function contains the raw-mode version of the inner
1325	* execution loop (the outer loop being in EMR3ExecuteVM()).
1326	*
1327	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1328	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1329	*
1330	* @param pVM VM handle.
1331	* @param pVCpu VMCPU handle.
1332	* @param pfFFDone Where to store an indicator telling whether or not
1333	* FFs were done before returning.
1334	*/
1335	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1336	{
1337	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1338
1339	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1340	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1341	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs, pCtx->eip));
1342	pVCpu->em.s.fForceRAW = false;
1343	*pfFFDone = false;
1344
1345
1346	/*
1347	*
1348	* Spin till we get a forced action or raw mode status code resulting in
1349	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1350	*
1351	*/
1352	for (;;)
1353	{
1354	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1355
1356	/*
1357	* Check various preconditions.
1358	*/
1359	#ifdef VBOX_STRICT
1360	# ifdef VBOX_WITH_REM
1361	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1362	# endif
1363	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) == 3 \|\| (pCtx->ss & X86_SEL_RPL) == 0);
1364	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1365	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1366	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1367	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1368	&& PGMMapHasConflicts(pVM))
1369	{
1370	PGMMapCheck(pVM);
1371	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1372	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1373	}
1374	#endif /* VBOX_STRICT */
1375
1376	/*
1377	* Process high priority pre-execution raw-mode FFs.
1378	*/
1379	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1380	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1381	{
1382	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1383	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1384	if (rc != VINF_SUCCESS)
1385	break;
1386	}
1387
1388	/*
1389	* If we're going to execute ring-0 code, the guest state needs to
1390	* be modified a bit and some of the state components (IF, SS/CS RPL,
1391	* and perhaps EIP) needs to be stored with PATM.
1392	*/
1393	rc = CPUMR3RawEnter(pVCpu, NULL);
1394	if (rc != VINF_SUCCESS)
1395	{
1396	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1397	break;
1398	}
1399
1400	/*
1401	* Scan code before executing it. Don't bother with user mode or V86 code
1402	*/
1403	if ( (pCtx->ss & X86_SEL_RPL) <= 1
1404	&& !pCtx->eflags.Bits.u1VM
1405	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1406	{
1407	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1408	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1409	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1410	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1411	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1412	{
1413	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1414	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1415	if (rc != VINF_SUCCESS)
1416	{
1417	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1418	break;
1419	}
1420	}
1421	}
1422
1423	#ifdef LOG_ENABLED
1424	/*
1425	* Log important stuff before entering GC.
1426	*/
1427	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1428	if (pCtx->eflags.Bits.u1VM)
1429	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1430	else if ((pCtx->ss & X86_SEL_RPL) == 1)
1431	{
1432	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
1433	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL), fCSAMScanned));
1434	}
1435	else if ((pCtx->ss & X86_SEL_RPL) == 3)
1436	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1437	#endif /* LOG_ENABLED */
1438
1439
1440
1441	/*
1442	* Execute the code.
1443	*/
1444	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1445	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1446	{
1447	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1448	VBOXVMM_EM_RAW_RUN_PRE(pVCpu, pCtx);
1449	rc = VMMR3RawRunGC(pVM, pVCpu);
1450	VBOXVMM_EM_RAW_RUN_RET(pVCpu, pCtx, rc);
1451	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1452	}
1453	else
1454	{
1455	/* Give up this time slice; virtual time continues */
1456	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1457	RTThreadSleep(5);
1458	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1459	rc = VINF_SUCCESS;
1460	}
1461	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1462
1463	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss & X86_SEL_RPL)));
1464	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1465
1466
1467
1468	/*
1469	* Restore the real CPU state and deal with high priority post
1470	* execution FFs before doing anything else.
1471	*/
1472	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1473	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1474	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1475	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1476	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1477
1478	#ifdef VBOX_STRICT
1479	/*
1480	* Assert TSS consistency & rc vs patch code.
1481	*/
1482	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1483	&& EMIsRawRing0Enabled(pVM))
1484	SELMR3CheckTSS(pVM);
1485	switch (rc)
1486	{
1487	case VINF_SUCCESS:
1488	case VINF_EM_RAW_INTERRUPT:
1489	case VINF_PATM_PATCH_TRAP_PF:
1490	case VINF_PATM_PATCH_TRAP_GP:
1491	case VINF_PATM_PATCH_INT3:
1492	case VINF_PATM_CHECK_PATCH_PAGE:
1493	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1494	case VINF_EM_RAW_GUEST_TRAP:
1495	case VINF_EM_RESCHEDULE_RAW:
1496	break;
1497
1498	default:
1499	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1500	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1501	break;
1502	}
1503	/*
1504	* Let's go paranoid!
1505	*/
1506	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1507	&& PGMMapHasConflicts(pVM))
1508	{
1509	PGMMapCheck(pVM);
1510	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1511	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1512	}
1513	#endif /* VBOX_STRICT */
1514
1515	/*
1516	* Process the returned status code.
1517	*/
1518	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1519	{
1520	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1521	break;
1522	}
1523	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1524	if (rc != VINF_SUCCESS)
1525	{
1526	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1527	if (rc != VINF_SUCCESS)
1528	{
1529	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1530	break;
1531	}
1532	}
1533
1534	/*
1535	* Check and execute forced actions.
1536	*/
1537	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1538	TMTimerPollVoid(pVM, pVCpu);
1539	#endif
1540	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1541	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1542	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1543	{
1544	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss & X86_SEL_RPL) != 1);
1545
1546	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1547	rc = emR3ForcedActions(pVM, pVCpu, rc);
1548	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1549	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1550	if ( rc != VINF_SUCCESS
1551	&& rc != VINF_EM_RESCHEDULE_RAW)
1552	{
1553	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1554	if (rc != VINF_SUCCESS)
1555	{
1556	*pfFFDone = true;
1557	break;
1558	}
1559	}
1560	}
1561	}
1562
1563	/*
1564	* Return to outer loop.
1565	*/
1566	#if defined(LOG_ENABLED) && defined(DEBUG)
1567	RTLogFlush(NULL);
1568	#endif
1569	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1570	return rc;
1571	}
1572

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 40449

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