EMRaw.cpp@ 41906

Last change on this file since 41906 was 41906, checked in by vboxsync, 12 years ago
CPUM: Combined the visible and hidden selector register data into one structure. Preparing for lazily resolving+caching of hidden registers in raw-mode.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 56.6 KB

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1	/* $Id: EMRaw.cpp 41906 2012-06-24 15:44:03Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2012 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/pgm.h>
33	#ifdef VBOX_WITH_REM
34	# include <VBox/vmm/rem.h>
35	#endif
36	#include <VBox/vmm/tm.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/vmm/pdmcritsect.h>
41	#include <VBox/vmm/pdmqueue.h>
42	#include <VBox/vmm/patm.h>
43	#include "EMInternal.h"
44	#include "internal/em.h"
45	#include <VBox/vmm/vm.h>
46	#include <VBox/vmm/cpumdis.h>
47	#include <VBox/dis.h>
48	#include <VBox/disopcode.h>
49	#include <VBox/vmm/dbgf.h>
50	#include "VMMTracing.h"
51
52	#include <VBox/log.h>
53	#include <iprt/asm.h>
54	#include <iprt/string.h>
55	#include <iprt/stream.h>
56
57
58
59	/*******************************************************************************
60	* Internal Functions *
61	*******************************************************************************/
62	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
63	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
64	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
65	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
66	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
67	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
68	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
69
70	#define EMHANDLERC_WITH_PATM
71	#include "EMHandleRCTmpl.h"
72
73
74
75	#ifdef VBOX_WITH_STATISTICS
76	/**
77	* Just a braindead function to keep track of cli addresses.
78	* @param pVM Pointer to the VM.
79	* @param pVMCPU Pointer to the VMCPU.
80	* @param GCPtrInstr The EIP of the cli instruction.
81	*/
82	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
83	{
84	PCLISTAT pRec;
85
86	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
87	if (!pRec)
88	{
89	/* New cli instruction; insert into the tree. */
90	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
91	Assert(pRec);
92	if (!pRec)
93	return;
94	pRec->Core.Key = GCPtrInstr;
95
96	char szCliStatName[32];
97	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
98	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
99
100	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
101	Assert(fRc); NOREF(fRc);
102	}
103	STAM_COUNTER_INC(&pRec->Counter);
104	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
105	}
106	#endif /* VBOX_WITH_STATISTICS */
107
108
109
110	/**
111	* Resumes executing hypervisor after a debug event.
112	*
113	* This is kind of special since our current guest state is
114	* potentially out of sync.
115	*
116	* @returns VBox status code.
117	* @param pVM Pointer to the VM.
118	* @param pVCpu Pointer to the VMCPU.
119	*/
120	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
121	{
122	int rc;
123	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
124	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
125	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags));
126
127	/*
128	* Resume execution.
129	*/
130	CPUMR3RawEnter(pVCpu, NULL);
131	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
132	rc = VMMR3ResumeHyper(pVM, pVCpu);
133	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc));
134	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
135	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
136
137	/*
138	* Deal with the return code.
139	*/
140	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
141	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
142	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
143	return rc;
144	}
145
146
147	/**
148	* Steps rawmode.
149	*
150	* @returns VBox status code.
151	* @param pVM Pointer to the VM.
152	* @param pVCpu Pointer to the VMCPU.
153	*/
154	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
155	{
156	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
157	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
158	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
159	int rc;
160	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
161	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
162	#ifndef DEBUG_sandervl
163	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
164	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
165	#endif
166	if (fGuest)
167	{
168	/*
169	* Check vital forced actions, but ignore pending interrupts and timers.
170	*/
171	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
172	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
173	{
174	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
175	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
176	if (rc != VINF_SUCCESS)
177	return rc;
178	}
179
180	/*
181	* Set flags for single stepping.
182	*/
183	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
184	}
185	else
186	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
187
188	/*
189	* Single step.
190	* We do not start time or anything, if anything we should just do a few nanoseconds.
191	*/
192	CPUMR3RawEnter(pVCpu, NULL);
193	do
194	{
195	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
196	rc = VMMR3ResumeHyper(pVM, pVCpu);
197	else
198	rc = VMMR3RawRunGC(pVM, pVCpu);
199	#ifndef DEBUG_sandervl
200	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
201	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
202	#endif
203	} while ( rc == VINF_SUCCESS
204	\|\| rc == VINF_EM_RAW_INTERRUPT);
205	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
206	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
207
208	/*
209	* Make sure the trap flag is cleared.
210	* (Too bad if the guest is trying to single step too.)
211	*/
212	if (fGuest)
213	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
214	else
215	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
216
217	/*
218	* Deal with the return codes.
219	*/
220	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
221	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
222	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
223	return rc;
224	}
225
226
227	#ifdef DEBUG
228
229
230	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
231	{
232	int rc = VINF_SUCCESS;
233	EMSTATE enmOldState = pVCpu->em.s.enmState;
234	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
235
236	Log(("Single step BEGIN:\n"));
237	for (uint32_t i = 0; i < cIterations; i++)
238	{
239	DBGFR3PrgStep(pVCpu);
240	DBGFR3DisasInstrCurrentLog(pVCpu, "RSS: ");
241	rc = emR3RawStep(pVM, pVCpu);
242	if (rc != VINF_SUCCESS)
243	break;
244	}
245	Log(("Single step END: rc=%Rrc\n", rc));
246	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
247	pVCpu->em.s.enmState = enmOldState;
248	return rc;
249	}
250
251	#endif /* DEBUG */
252
253
254	/**
255	* Executes one (or perhaps a few more) instruction(s).
256	*
257	* @returns VBox status code suitable for EM.
258	*
259	* @param pVM Pointer to the VM.
260	* @param pVCpu Pointer to the VMCPU.
261	* @param rcGC GC return code
262	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
263	* instruction and prefix the log output with this text.
264	*/
265	#ifdef LOG_ENABLED
266	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
267	#else
268	static int emR3ExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
269	#endif
270	{
271	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
272	int rc;
273
274	/*
275	*
276	* The simple solution is to use the recompiler.
277	* The better solution is to disassemble the current instruction and
278	* try handle as many as possible without using REM.
279	*
280	*/
281
282	#ifdef LOG_ENABLED
283	/*
284	* Disassemble the instruction if requested.
285	*/
286	if (pszPrefix)
287	{
288	DBGFR3InfoLog(pVM, "cpumguest", pszPrefix);
289	DBGFR3DisasInstrCurrentLog(pVCpu, pszPrefix);
290	}
291	#endif /* LOG_ENABLED */
292
293	/*
294	* PATM is making life more interesting.
295	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
296	* tell PATM there is a trap in this code and have it take the appropriate actions
297	* to allow us execute the code in REM.
298	*/
299	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
300	{
301	Log(("emR3ExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
302
303	RTGCPTR pNewEip;
304	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
305	switch (rc)
306	{
307	/*
308	* It's not very useful to emulate a single instruction and then go back to raw
309	* mode; just execute the whole block until IF is set again.
310	*/
311	case VINF_SUCCESS:
312	Log(("emR3ExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
313	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
314	pCtx->eip = pNewEip;
315	Assert(pCtx->eip);
316
317	if (pCtx->eflags.Bits.u1IF)
318	{
319	/*
320	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
321	*/
322	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
323	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
324	}
325	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
326	{
327	/* special case: iret, that sets IF, detected a pending irq/event */
328	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIRET");
329	}
330	return VINF_EM_RESCHEDULE_REM;
331
332	/*
333	* One instruction.
334	*/
335	case VINF_PATCH_EMULATE_INSTR:
336	Log(("emR3ExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
337	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
338	pCtx->eip = pNewEip;
339	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
340
341	/*
342	* The patch was disabled, hand it to the REM.
343	*/
344	case VERR_PATCH_DISABLED:
345	Log(("emR3ExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
346	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
347	pCtx->eip = pNewEip;
348	if (pCtx->eflags.Bits.u1IF)
349	{
350	/*
351	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
352	*/
353	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
354	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
355	}
356	return VINF_EM_RESCHEDULE_REM;
357
358	/* Force continued patch exection; usually due to write monitored stack. */
359	case VINF_PATCH_CONTINUE:
360	return VINF_SUCCESS;
361
362	default:
363	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
364	return VERR_IPE_UNEXPECTED_STATUS;
365	}
366	}
367
368	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, a);
369	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
370	#ifdef VBOX_WITH_REM
371	EMRemLock(pVM);
372	/* Flush the recompiler TLB if the VCPU has changed. */
373	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
374	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
375	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
376
377	rc = REMR3EmulateInstruction(pVM, pVCpu);
378	EMRemUnlock(pVM);
379	#else
380	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
381	#endif
382	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, a);
383
384	return rc;
385	}
386
387
388	/**
389	* Executes one (or perhaps a few more) instruction(s).
390	* This is just a wrapper for discarding pszPrefix in non-logging builds.
391	*
392	* @returns VBox status code suitable for EM.
393	* @param pVM Pointer to the VM.
394	* @param pVCpu Pointer to the VMCPU.
395	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
396	* instruction and prefix the log output with this text.
397	* @param rcGC GC return code
398	*/
399	DECLINLINE(int) emR3ExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
400	{
401	#ifdef LOG_ENABLED
402	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
403	#else
404	return emR3ExecuteInstructionWorker(pVM, pVCpu, rcGC);
405	#endif
406	}
407
408	/**
409	* Executes one (or perhaps a few more) IO instruction(s).
410	*
411	* @returns VBox status code suitable for EM.
412	* @param pVM Pointer to the VM.
413	* @param pVCpu Pointer to the VMCPU.
414	*/
415	static int emR3ExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
416	{
417	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
418
419	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
420
421	/** @todo probably we should fall back to the recompiler; otherwise we'll go back and forth between HC & GC
422	* as io instructions tend to come in packages of more than one
423	*/
424	DISCPUSTATE Cpu;
425	int rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "IO EMU");
426	if (RT_SUCCESS(rc))
427	{
428	VBOXSTRICTRC rcStrict = VINF_EM_RAW_EMULATE_INSTR;
429
430	if (!(Cpu.fPrefix & (DISPREFIX_REP \| DISPREFIX_REPNE)))
431	{
432	switch (Cpu.pCurInstr->uOpcode)
433	{
434	case OP_IN:
435	{
436	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
437	rcStrict = IOMInterpretIN(pVM, CPUMCTX2CORE(pCtx), &Cpu);
438	break;
439	}
440
441	case OP_OUT:
442	{
443	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
444	rcStrict = IOMInterpretOUT(pVM, CPUMCTX2CORE(pCtx), &Cpu);
445	break;
446	}
447	}
448	}
449	else if (Cpu.fPrefix & DISPREFIX_REP)
450	{
451	switch (Cpu.pCurInstr->uOpcode)
452	{
453	case OP_INSB:
454	case OP_INSWD:
455	{
456	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIn);
457	rcStrict = IOMInterpretINS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
458	break;
459	}
460
461	case OP_OUTSB:
462	case OP_OUTSWD:
463	{
464	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatOut);
465	rcStrict = IOMInterpretOUTS(pVM, CPUMCTX2CORE(pCtx), &Cpu);
466	break;
467	}
468	}
469	}
470
471	/*
472	* Handled the I/O return codes.
473	* (The unhandled cases end up with rcStrict == VINF_EM_RAW_EMULATE_INSTR.)
474	*/
475	if (IOM_SUCCESS(rcStrict))
476	{
477	pCtx->rip += Cpu.cbInstr;
478	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
479	return VBOXSTRICTRC_TODO(rcStrict);
480	}
481
482	if (rcStrict == VINF_EM_RAW_GUEST_TRAP)
483	{
484	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
485	rcStrict = emR3RawGuestTrap(pVM, pVCpu);
486	return VBOXSTRICTRC_TODO(rcStrict);
487	}
488	AssertMsg(rcStrict != VINF_TRPM_XCPT_DISPATCHED, ("Handle VINF_TRPM_XCPT_DISPATCHED\n"));
489
490	if (RT_FAILURE(rcStrict))
491	{
492	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
493	return VBOXSTRICTRC_TODO(rcStrict);
494	}
495	AssertMsg(rcStrict == VINF_EM_RAW_EMULATE_INSTR \|\| rcStrict == VINF_EM_RESCHEDULE_REM, ("rcStrict=%Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
496	}
497	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
498	return emR3ExecuteInstruction(pVM, pVCpu, "IO: ");
499	}
500
501
502	/**
503	* Handle a guest context trap.
504	*
505	* @returns VBox status code suitable for EM.
506	* @param pVM Pointer to the VM.
507	* @param pVCpu Pointer to the VMCPU.
508	*/
509	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
510	{
511	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
512
513	/*
514	* Get the trap info.
515	*/
516	uint8_t u8TrapNo;
517	TRPMEVENT enmType;
518	RTGCUINT uErrorCode;
519	RTGCUINTPTR uCR2;
520	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
521	if (RT_FAILURE(rc))
522	{
523	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
524	return rc;
525	}
526
527
528	#if 1 /* Experimental: Review, disable if it causes trouble. */
529	/*
530	* Handle traps in patch code first.
531	*
532	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
533	* but several traps isn't handled specially by TRPM in RC and we end up here
534	* instead. One example is #DE.
535	*/
536	uint32_t uCpl = CPUMGetGuestCPL(pVCpu, CPUMCTX2CORE(pCtx));
537	if ( uCpl == 0
538	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
539	{
540	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
541	return emR3PatchTrap(pVM, pVCpu, pCtx, rc);
542	}
543	#endif
544
545	/*
546	* If the guest gate is marked unpatched, then we will check again if we can patch it.
547	* (This assumes that we've already tried and failed to dispatch the trap in
548	* RC for the gates that already has been patched. Which is true for most high
549	* volume traps, because these are handled specially, but not for odd ones like #DE.)
550	*/
551	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
552	{
553	CSAMR3CheckGates(pVM, u8TrapNo, 1);
554	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
555
556	/* If it was successful, then we could go back to raw mode. */
557	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
558	{
559	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
560	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
561	AssertRCReturn(rc, rc);
562
563	TRPMERRORCODE enmError = uErrorCode != ~0U
564	? TRPM_TRAP_HAS_ERRORCODE
565	: TRPM_TRAP_NO_ERRORCODE;
566	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
567	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
568	{
569	TRPMResetTrap(pVCpu);
570	return VINF_EM_RESCHEDULE_RAW;
571	}
572	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
573	}
574	}
575
576	/*
577	* Scan kernel code that traps; we might not get another chance.
578	*/
579	/** @todo move this up before the dispatching? */
580	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
581	&& !pCtx->eflags.Bits.u1VM)
582	{
583	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
584	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
585	}
586
587	/*
588	* Trap specific handling.
589	*/
590	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
591	{
592	/*
593	* If MONITOR & MWAIT are supported, then interpret them here.
594	*/
595	DISCPUSTATE cpu;
596	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
597	if ( RT_SUCCESS(rc)
598	&& (cpu.pCurInstr->uOpcode == OP_MONITOR \|\| cpu.pCurInstr->uOpcode == OP_MWAIT))
599	{
600	uint32_t u32Dummy, u32Features, u32ExtFeatures;
601	CPUMGetGuestCpuId(pVCpu, 1, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
602	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
603	{
604	rc = TRPMResetTrap(pVCpu);
605	AssertRC(rc);
606
607	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
608	if (RT_SUCCESS(rc))
609	return rc;
610	return emR3ExecuteInstruction(pVM, pVCpu, "Monitor: ");
611	}
612	}
613	}
614	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
615	{
616	/*
617	* Handle I/O bitmap?
618	*/
619	/** @todo We're not supposed to be here with a false guest trap concerning
620	* I/O access. We can easily handle those in RC. */
621	DISCPUSTATE cpu;
622	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
623	if ( RT_SUCCESS(rc)
624	&& (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
625	{
626	/*
627	* We should really check the TSS for the IO bitmap, but it's not like this
628	* lazy approach really makes things worse.
629	*/
630	rc = TRPMResetTrap(pVCpu);
631	AssertRC(rc);
632	return emR3ExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
633	}
634	}
635
636	#ifdef LOG_ENABLED
637	DBGFR3InfoLog(pVM, "cpumguest", "Guest trap");
638	DBGFR3DisasInstrCurrentLog(pVCpu, "Guest trap");
639
640	/* Get guest page information. */
641	uint64_t fFlags = 0;
642	RTGCPHYS GCPhys = 0;
643	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
644	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
645	pCtx->cs.Sel, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0,
646	(enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
647	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
648	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
649	#endif
650
651	/*
652	* #PG has CR2.
653	* (Because of stuff like above we must set CR2 in a delayed fashion.)
654	*/
655	if (u8TrapNo == 14 /* #PG */)
656	pCtx->cr2 = uCR2;
657
658	return VINF_EM_RESCHEDULE_REM;
659	}
660
661
662	/**
663	* Handle a ring switch trap.
664	* Need to do statistics and to install patches. The result is going to REM.
665	*
666	* @returns VBox status code suitable for EM.
667	* @param pVM Pointer to the VM.
668	* @param pVCpu Pointer to the VMCPU.
669	*/
670	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
671	{
672	int rc;
673	DISCPUSTATE Cpu;
674	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
675
676	/*
677	* sysenter, syscall & callgate
678	*/
679	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
680	if (RT_SUCCESS(rc))
681	{
682	if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
683	{
684	if (pCtx->SysEnter.cs != 0)
685	{
686	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
687	SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs.Sel, &pCtx->cs)
688	== DISCPUMODE_32BIT ? PATMFL_CODE32 : 0);
689	if (RT_SUCCESS(rc))
690	{
691	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched sysenter instruction");
692	return VINF_EM_RESCHEDULE_RAW;
693	}
694	}
695	}
696
697	#ifdef VBOX_WITH_STATISTICS
698	switch (Cpu.pCurInstr->uOpcode)
699	{
700	case OP_SYSENTER:
701	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
702	break;
703	case OP_SYSEXIT:
704	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
705	break;
706	case OP_SYSCALL:
707	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
708	break;
709	case OP_SYSRET:
710	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
711	break;
712	}
713	#endif
714	}
715	else
716	AssertRC(rc);
717
718	/* go to the REM to emulate a single instruction */
719	return emR3ExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
720	}
721
722
723	/**
724	* Handle a trap (\#PF or \#GP) in patch code
725	*
726	* @returns VBox status code suitable for EM.
727	* @param pVM Pointer to the VM.
728	* @param pVCpu Pointer to the VMCPU.
729	* @param pCtx Pointer to the guest CPU context.
730	* @param gcret GC return code.
731	*/
732	static int emR3PatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
733	{
734	uint8_t u8TrapNo;
735	int rc;
736	TRPMEVENT enmType;
737	RTGCUINT uErrorCode;
738	RTGCUINTPTR uCR2;
739
740	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
741
742	if (gcret == VINF_PATM_PATCH_INT3)
743	{
744	u8TrapNo = 3;
745	uCR2 = 0;
746	uErrorCode = 0;
747	}
748	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
749	{
750	/* No active trap in this case. Kind of ugly. */
751	u8TrapNo = X86_XCPT_GP;
752	uCR2 = 0;
753	uErrorCode = 0;
754	}
755	else
756	{
757	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2);
758	if (RT_FAILURE(rc))
759	{
760	AssertReleaseMsgFailed(("emR3PatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
761	return rc;
762	}
763	/* Reset the trap as we'll execute the original instruction again. */
764	TRPMResetTrap(pVCpu);
765	}
766
767	/*
768	* Deal with traps inside patch code.
769	* (This code won't run outside GC.)
770	*/
771	if (u8TrapNo != 1)
772	{
773	#ifdef LOG_ENABLED
774	DBGFR3InfoLog(pVM, "cpumguest", "Trap in patch code");
775	DBGFR3DisasInstrCurrentLog(pVCpu, "Patch code");
776
777	DISCPUSTATE Cpu;
778	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
779	if ( RT_SUCCESS(rc)
780	&& Cpu.pCurInstr->uOpcode == OP_IRET)
781	{
782	uint32_t eip, selCS, uEFlags;
783
784	/* Iret crashes are bad as we have already changed the flags on the stack */
785	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
786	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
787	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
788	if (rc == VINF_SUCCESS)
789	{
790	if ( (uEFlags & X86_EFL_VM)
791	\|\| (selCS & X86_SEL_RPL) == 3)
792	{
793	uint32_t selSS, esp;
794
795	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
796	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
797
798	if (uEFlags & X86_EFL_VM)
799	{
800	uint32_t selDS, selES, selFS, selGS;
801	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
802	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
803	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
804	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
805	if (rc == VINF_SUCCESS)
806	{
807	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
808	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
809	}
810	}
811	else
812	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
813	}
814	else
815	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
816	}
817	}
818	#endif /* LOG_ENABLED */
819	Log(("emR3PatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
820	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
821
822	RTGCPTR pNewEip;
823	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &pNewEip);
824	switch (rc)
825	{
826	/*
827	* Execute the faulting instruction.
828	*/
829	case VINF_SUCCESS:
830	{
831	/** @todo execute a whole block */
832	Log(("emR3PatchTrap: Executing faulting instruction at new address %RGv\n", pNewEip));
833	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
834	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
835
836	pCtx->eip = pNewEip;
837	AssertRelease(pCtx->eip);
838
839	if (pCtx->eflags.Bits.u1IF)
840	{
841	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
842	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
843	*/
844	if ( u8TrapNo == X86_XCPT_GP
845	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
846	{
847	/** @todo move to PATMR3HandleTrap */
848	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
849	PATMR3RemovePatch(pVM, pCtx->eip);
850	}
851
852	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
853	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
854
855	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
856	/* Interrupts are enabled; just go back to the original instruction.
857	return VINF_SUCCESS; */
858	}
859	return VINF_EM_RESCHEDULE_REM;
860	}
861
862	/*
863	* One instruction.
864	*/
865	case VINF_PATCH_EMULATE_INSTR:
866	Log(("emR3PatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
867	pNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
868	pCtx->eip = pNewEip;
869	AssertRelease(pCtx->eip);
870	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
871
872	/*
873	* The patch was disabled, hand it to the REM.
874	*/
875	case VERR_PATCH_DISABLED:
876	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
877	Log(("emR3PatchTrap: Virtual IF flag disabled!!\n"));
878	pCtx->eip = pNewEip;
879	AssertRelease(pCtx->eip);
880
881	if (pCtx->eflags.Bits.u1IF)
882	{
883	/*
884	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
885	*/
886	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
887	return emR3ExecuteInstruction(pVM, pVCpu, "PATCHIR");
888	}
889	return VINF_EM_RESCHEDULE_REM;
890
891	/* Force continued patch exection; usually due to write monitored stack. */
892	case VINF_PATCH_CONTINUE:
893	return VINF_SUCCESS;
894
895	/*
896	* Anything else is fatal.
897	*/
898	default:
899	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
900	return VERR_IPE_UNEXPECTED_STATUS;
901	}
902	}
903	return VINF_SUCCESS;
904	}
905
906
907	/**
908	* Handle a privileged instruction.
909	*
910	* @returns VBox status code suitable for EM.
911	* @param pVM Pointer to the VM.
912	* @param pVCpu Pointer to the VMCPU.
913	*/
914	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
915	{
916	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
917
918	Assert(!pCtx->eflags.Bits.u1VM);
919
920	if (PATMIsEnabled(pVM))
921	{
922	/*
923	* Check if in patch code.
924	*/
925	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
926	{
927	#ifdef LOG_ENABLED
928	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
929	#endif
930	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08X\n", pCtx->eip));
931	return VERR_EM_RAW_PATCH_CONFLICT;
932	}
933	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
934	&& !pCtx->eflags.Bits.u1VM
935	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
936	{
937	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
938	( SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs.Sel, &pCtx->cs)
939	== DISCPUMODE_32BIT) ? PATMFL_CODE32 : 0);
940	if (RT_SUCCESS(rc))
941	{
942	#ifdef LOG_ENABLED
943	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
944	#endif
945	DBGFR3DisasInstrCurrentLog(pVCpu, "Patched privileged instruction");
946	return VINF_SUCCESS;
947	}
948	}
949	}
950
951	#ifdef LOG_ENABLED
952	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
953	{
954	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
955	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
956	}
957	#endif
958
959	/*
960	* Instruction statistics and logging.
961	*/
962	DISCPUSTATE Cpu;
963	int rc;
964
965	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
966	if (RT_SUCCESS(rc))
967	{
968	#ifdef VBOX_WITH_STATISTICS
969	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
970	switch (Cpu.pCurInstr->uOpcode)
971	{
972	case OP_INVLPG:
973	STAM_COUNTER_INC(&pStats->StatInvlpg);
974	break;
975	case OP_IRET:
976	STAM_COUNTER_INC(&pStats->StatIret);
977	break;
978	case OP_CLI:
979	STAM_COUNTER_INC(&pStats->StatCli);
980	emR3RecordCli(pVM, pVCpu, pCtx->rip);
981	break;
982	case OP_STI:
983	STAM_COUNTER_INC(&pStats->StatSti);
984	break;
985	case OP_INSB:
986	case OP_INSWD:
987	case OP_IN:
988	case OP_OUTSB:
989	case OP_OUTSWD:
990	case OP_OUT:
991	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
992	break;
993
994	case OP_MOV_CR:
995	if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
996	{
997	//read
998	Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
999	Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
1000	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
1001	}
1002	else
1003	{
1004	//write
1005	Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
1006	Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
1007	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
1008	}
1009	break;
1010
1011	case OP_MOV_DR:
1012	STAM_COUNTER_INC(&pStats->StatMovDRx);
1013	break;
1014	case OP_LLDT:
1015	STAM_COUNTER_INC(&pStats->StatMovLldt);
1016	break;
1017	case OP_LIDT:
1018	STAM_COUNTER_INC(&pStats->StatMovLidt);
1019	break;
1020	case OP_LGDT:
1021	STAM_COUNTER_INC(&pStats->StatMovLgdt);
1022	break;
1023	case OP_SYSENTER:
1024	STAM_COUNTER_INC(&pStats->StatSysEnter);
1025	break;
1026	case OP_SYSEXIT:
1027	STAM_COUNTER_INC(&pStats->StatSysExit);
1028	break;
1029	case OP_SYSCALL:
1030	STAM_COUNTER_INC(&pStats->StatSysCall);
1031	break;
1032	case OP_SYSRET:
1033	STAM_COUNTER_INC(&pStats->StatSysRet);
1034	break;
1035	case OP_HLT:
1036	STAM_COUNTER_INC(&pStats->StatHlt);
1037	break;
1038	default:
1039	STAM_COUNTER_INC(&pStats->StatMisc);
1040	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
1041	break;
1042	}
1043	#endif /* VBOX_WITH_STATISTICS */
1044	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
1045	&& !pCtx->eflags.Bits.u1VM
1046	&& SELMGetCpuModeFromSelector(pVCpu, pCtx->eflags, pCtx->cs.Sel, &pCtx->cs) == DISCPUMODE_32BIT)
1047	{
1048	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
1049	switch (Cpu.pCurInstr->uOpcode)
1050	{
1051	case OP_CLI:
1052	pCtx->eflags.u32 &= ~X86_EFL_IF;
1053	Assert(Cpu.cbInstr == 1);
1054	pCtx->rip += Cpu.cbInstr;
1055	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1056	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1057
1058	case OP_STI:
1059	pCtx->eflags.u32 \|= X86_EFL_IF;
1060	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr);
1061	Assert(Cpu.cbInstr == 1);
1062	pCtx->rip += Cpu.cbInstr;
1063	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1064	return VINF_SUCCESS;
1065
1066	case OP_HLT:
1067	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1068	{
1069	PATMTRANSSTATE enmState;
1070	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1071
1072	if (enmState == PATMTRANS_OVERWRITTEN)
1073	{
1074	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1075	Assert(rc == VERR_PATCH_DISABLED);
1076	/* Conflict detected, patch disabled */
1077	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1078
1079	enmState = PATMTRANS_SAFE;
1080	}
1081
1082	/* The translation had better be successful. Otherwise we can't recover. */
1083	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1084	if (enmState != PATMTRANS_OVERWRITTEN)
1085	pCtx->eip = pOrgInstrGC;
1086	}
1087	/* no break; we could just return VINF_EM_HALT here */
1088
1089	case OP_MOV_CR:
1090	case OP_MOV_DR:
1091	#ifdef LOG_ENABLED
1092	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1093	{
1094	DBGFR3InfoLog(pVM, "cpumguest", "PRIV");
1095	DBGFR3DisasInstrCurrentLog(pVCpu, "Privileged instr: ");
1096	}
1097	#endif
1098
1099	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1100	if (RT_SUCCESS(rc))
1101	{
1102	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1103
1104	if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1105	&& Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1106	)
1107	{
1108	/* Deal with CR0 updates inside patch code that force
1109	* us to go to the recompiler.
1110	*/
1111	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1112	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1113	{
1114	PATMTRANSSTATE enmState;
1115	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1116
1117	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1118	if (enmState == PATMTRANS_OVERWRITTEN)
1119	{
1120	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1121	Assert(rc == VERR_PATCH_DISABLED);
1122	/* Conflict detected, patch disabled */
1123	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1124	enmState = PATMTRANS_SAFE;
1125	}
1126	/* The translation had better be successful. Otherwise we can't recover. */
1127	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1128	if (enmState != PATMTRANS_OVERWRITTEN)
1129	pCtx->rip = pOrgInstrGC;
1130	}
1131
1132	/* Reschedule is necessary as the execution/paging mode might have changed. */
1133	return VINF_EM_RESCHEDULE;
1134	}
1135	return rc; /* can return VINF_EM_HALT as well. */
1136	}
1137	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1138	break; /* fall back to the recompiler */
1139	}
1140	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1141	}
1142	}
1143
1144	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1145	return emR3PatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1146
1147	return emR3ExecuteInstruction(pVM, pVCpu, "PRIV");
1148	}
1149
1150
1151	/**
1152	* Update the forced rawmode execution modifier.
1153	*
1154	* This function is called when we're returning from the raw-mode loop(s). If we're
1155	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1156	* if not in patch code, the flag will be cleared.
1157	*
1158	* We should never interrupt patch code while it's being executed. Cli patches can
1159	* contain big code blocks, but they are always executed with IF=0. Other patches
1160	* replace single instructions and should be atomic.
1161	*
1162	* @returns Updated rc.
1163	*
1164	* @param pVM Pointer to the VM.
1165	* @param pVCpu Pointer to the VMCPU.
1166	* @param pCtx Pointer to the guest CPU context.
1167	* @param rc The result code.
1168	*/
1169	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1170	{
1171	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1172	{
1173	/* ignore reschedule attempts. */
1174	switch (rc)
1175	{
1176	case VINF_EM_RESCHEDULE:
1177	case VINF_EM_RESCHEDULE_REM:
1178	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1179	rc = VINF_SUCCESS;
1180	break;
1181	}
1182	pVCpu->em.s.fForceRAW = true;
1183	}
1184	else
1185	pVCpu->em.s.fForceRAW = false;
1186	return rc;
1187	}
1188
1189
1190	/**
1191	* Check for pending raw actions
1192	*
1193	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1194	* EM statuses.
1195	* @param pVM Pointer to the VM.
1196	* @param pVCpu Pointer to the VMCPU.
1197	*/
1198	VMMR3DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1199	{
1200	int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1201	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1202	return rc;
1203	}
1204
1205
1206	/**
1207	* Process raw-mode specific forced actions.
1208	*
1209	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1210	*
1211	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1212	* EM statuses.
1213	* @param pVM Pointer to the VM.
1214	* @param pVCpu Pointer to the VMCPU.
1215	* @param pCtx Pointer to the guest CPU context.
1216	*/
1217	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1218	{
1219	/*
1220	* Note that the order is vitally important!
1221	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1222	*/
1223	VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1224
1225	/*
1226	* Sync selector tables.
1227	*/
1228	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1229	{
1230	int rc = SELMR3UpdateFromCPUM(pVM, pVCpu);
1231	if (RT_FAILURE(rc))
1232	return rc;
1233	}
1234
1235	/*
1236	* Sync IDT.
1237	*
1238	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1239	* and PGMShwModifyPage, so we're in for trouble if for instance a
1240	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1241	*/
1242	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1243	{
1244	if ( VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1245	&& EMIsRawRing0Enabled(pVM)
1246	&& CSAMIsEnabled(pVM))
1247	{
1248	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1249	if (RT_FAILURE(rc))
1250	return rc;
1251	}
1252
1253	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1254	if (RT_FAILURE(rc))
1255	return rc;
1256	}
1257
1258	/*
1259	* Sync TSS.
1260	*/
1261	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1262	{
1263	int rc = SELMR3SyncTSS(pVM, pVCpu);
1264	if (RT_FAILURE(rc))
1265	return rc;
1266	}
1267
1268	/*
1269	* Sync page directory.
1270	*/
1271	if (VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1272	{
1273	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1274	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1275	if (RT_FAILURE(rc))
1276	return rc;
1277
1278	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1279
1280	/* Prefetch pages for EIP and ESP. */
1281	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1282	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1283	if (rc == VINF_SUCCESS)
1284	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1285	if (rc != VINF_SUCCESS)
1286	{
1287	if (rc != VINF_PGM_SYNC_CR3)
1288	{
1289	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1290	return rc;
1291	}
1292	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_ISSET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1293	if (RT_FAILURE(rc))
1294	return rc;
1295	}
1296	/** @todo maybe prefetch the supervisor stack page as well */
1297	Assert(!VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1298	}
1299
1300	/*
1301	* Allocate handy pages (just in case the above actions have consumed some pages).
1302	*/
1303	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1304	{
1305	int rc = PGMR3PhysAllocateHandyPages(pVM);
1306	if (RT_FAILURE(rc))
1307	return rc;
1308	}
1309
1310	/*
1311	* Check whether we're out of memory now.
1312	*
1313	* This may stem from some of the above actions or operations that has been executed
1314	* since we ran FFs. The allocate handy pages must for instance always be followed by
1315	* this check.
1316	*/
1317	if (VM_FF_ISPENDING(pVM, VM_FF_PGM_NO_MEMORY))
1318	return VINF_EM_NO_MEMORY;
1319
1320	return VINF_SUCCESS;
1321	}
1322
1323
1324	/**
1325	* Executes raw code.
1326	*
1327	* This function contains the raw-mode version of the inner
1328	* execution loop (the outer loop being in EMR3ExecuteVM()).
1329	*
1330	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1331	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1332	*
1333	* @param pVM Pointer to the VM.
1334	* @param pVCpu Pointer to the VMCPU.
1335	* @param pfFFDone Where to store an indicator telling whether or not
1336	* FFs were done before returning.
1337	*/
1338	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1339	{
1340	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1341
1342	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1343	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1344	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs.Sel, pCtx->eip));
1345	pVCpu->em.s.fForceRAW = false;
1346	*pfFFDone = false;
1347
1348
1349	/*
1350	*
1351	* Spin till we get a forced action or raw mode status code resulting in
1352	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1353	*
1354	*/
1355	for (;;)
1356	{
1357	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1358
1359	/*
1360	* Check various preconditions.
1361	*/
1362	#ifdef VBOX_STRICT
1363	# ifdef VBOX_WITH_REM
1364	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1365	# endif
1366	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 3 \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 0);
1367	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1368	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1369	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1370	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1371	&& PGMMapHasConflicts(pVM))
1372	{
1373	PGMMapCheck(pVM);
1374	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1375	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1376	}
1377	#endif /* VBOX_STRICT */
1378
1379	/*
1380	* Process high priority pre-execution raw-mode FFs.
1381	*/
1382	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1383	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1384	{
1385	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1386	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1387	if (rc != VINF_SUCCESS)
1388	break;
1389	}
1390
1391	/*
1392	* If we're going to execute ring-0 code, the guest state needs to
1393	* be modified a bit and some of the state components (IF, SS/CS RPL,
1394	* and perhaps EIP) needs to be stored with PATM.
1395	*/
1396	rc = CPUMR3RawEnter(pVCpu, NULL);
1397	if (rc != VINF_SUCCESS)
1398	{
1399	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1400	break;
1401	}
1402
1403	/*
1404	* Scan code before executing it. Don't bother with user mode or V86 code
1405	*/
1406	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
1407	&& !pCtx->eflags.Bits.u1VM
1408	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1409	{
1410	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1411	CSAMR3CheckCodeEx(pVM, CPUMCTX2CORE(pCtx), pCtx->eip);
1412	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1413	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1414	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1415	{
1416	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1417	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1418	if (rc != VINF_SUCCESS)
1419	{
1420	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1421	break;
1422	}
1423	}
1424	}
1425
1426	#ifdef LOG_ENABLED
1427	/*
1428	* Log important stuff before entering GC.
1429	*/
1430	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1431	if (pCtx->eflags.Bits.u1VM)
1432	Log(("RV86: %04X:%08X IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1433	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 1)
1434	{
1435	bool fCSAMScanned = CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip);
1436	Log(("RR0: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL), fCSAMScanned));
1437	}
1438	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 3)
1439	Log(("RR3: %08X ESP=%08X IF=%d VMFlags=%x\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1440	#endif /* LOG_ENABLED */
1441
1442
1443
1444	/*
1445	* Execute the code.
1446	*/
1447	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1448	if (RT_LIKELY(EMR3IsExecutionAllowed(pVM, pVCpu)))
1449	{
1450	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1451	VBOXVMM_EM_RAW_RUN_PRE(pVCpu, pCtx);
1452	rc = VMMR3RawRunGC(pVM, pVCpu);
1453	VBOXVMM_EM_RAW_RUN_RET(pVCpu, pCtx, rc);
1454	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1455	}
1456	else
1457	{
1458	/* Give up this time slice; virtual time continues */
1459	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1460	RTThreadSleep(5);
1461	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1462	rc = VINF_SUCCESS;
1463	}
1464	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1465
1466	LogFlow(("RR0-E: %08X ESP=%08X IF=%d VMFlags=%x PIF=%d CPL=%d\n", pCtx->eip, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL)));
1467	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1468
1469
1470
1471	/*
1472	* Restore the real CPU state and deal with high priority post
1473	* execution FFs before doing anything else.
1474	*/
1475	rc = CPUMR3RawLeave(pVCpu, NULL, rc);
1476	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1477	if ( VM_FF_ISPENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1478	\|\| VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1479	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1480
1481	#ifdef VBOX_STRICT
1482	/*
1483	* Assert TSS consistency & rc vs patch code.
1484	*/
1485	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1486	&& EMIsRawRing0Enabled(pVM))
1487	SELMR3CheckTSS(pVM);
1488	switch (rc)
1489	{
1490	case VINF_SUCCESS:
1491	case VINF_EM_RAW_INTERRUPT:
1492	case VINF_PATM_PATCH_TRAP_PF:
1493	case VINF_PATM_PATCH_TRAP_GP:
1494	case VINF_PATM_PATCH_INT3:
1495	case VINF_PATM_CHECK_PATCH_PAGE:
1496	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1497	case VINF_EM_RAW_GUEST_TRAP:
1498	case VINF_EM_RESCHEDULE_RAW:
1499	break;
1500
1501	default:
1502	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1503	LogIt(NULL, 0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1504	break;
1505	}
1506	/*
1507	* Let's go paranoid!
1508	*/
1509	if ( !VMCPU_FF_ISPENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1510	&& PGMMapHasConflicts(pVM))
1511	{
1512	PGMMapCheck(pVM);
1513	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1514	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1515	}
1516	#endif /* VBOX_STRICT */
1517
1518	/*
1519	* Process the returned status code.
1520	*/
1521	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1522	{
1523	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1524	break;
1525	}
1526	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1527	if (rc != VINF_SUCCESS)
1528	{
1529	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1530	if (rc != VINF_SUCCESS)
1531	{
1532	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1533	break;
1534	}
1535	}
1536
1537	/*
1538	* Check and execute forced actions.
1539	*/
1540	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1541	TMTimerPollVoid(pVM, pVCpu);
1542	#endif
1543	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1544	if ( VM_FF_ISPENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1545	\|\| VMCPU_FF_ISPENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1546	{
1547	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) != 1);
1548
1549	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1550	rc = emR3ForcedActions(pVM, pVCpu, rc);
1551	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1552	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1553	if ( rc != VINF_SUCCESS
1554	&& rc != VINF_EM_RESCHEDULE_RAW)
1555	{
1556	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1557	if (rc != VINF_SUCCESS)
1558	{
1559	*pfFFDone = true;
1560	break;
1561	}
1562	}
1563	}
1564	}
1565
1566	/*
1567	* Return to outer loop.
1568	*/
1569	#if defined(LOG_ENABLED) && defined(DEBUG)
1570	RTLogFlush(NULL);
1571	#endif
1572	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1573	return rc;
1574	}
1575

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 41906

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