EMRaw.cpp@ 57008

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1	/* $Id: EMRaw.cpp 56287 2015-06-09 11:15:22Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2015 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/pgm.h>
33	#ifdef VBOX_WITH_REM
34	# include <VBox/vmm/rem.h>
35	#endif
36	#include <VBox/vmm/tm.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/vmm/pdmcritsect.h>
41	#include <VBox/vmm/pdmqueue.h>
42	#include <VBox/vmm/patm.h>
43	#include "EMInternal.h"
44	#include <VBox/vmm/vm.h>
45	#include <VBox/vmm/cpumdis.h>
46	#include <VBox/dis.h>
47	#include <VBox/disopcode.h>
48	#include <VBox/vmm/dbgf.h>
49	#include "VMMTracing.h"
50
51	#include <VBox/log.h>
52	#include <iprt/asm.h>
53	#include <iprt/string.h>
54	#include <iprt/stream.h>
55
56
57
58	/*******************************************************************************
59	* Internal Functions *
60	*******************************************************************************/
61	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
62	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
63	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
64	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
65	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
66	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
67	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
68
69	#define EMHANDLERC_WITH_PATM
70	#define emR3ExecuteInstruction emR3RawExecuteInstruction
71	#define emR3ExecuteIOInstruction emR3RawExecuteIOInstruction
72	#include "EMHandleRCTmpl.h"
73
74
75
76	#ifdef VBOX_WITH_STATISTICS
77	/**
78	* Just a braindead function to keep track of cli addresses.
79	* @param pVM Pointer to the VM.
80	* @param pVMCPU Pointer to the VMCPU.
81	* @param GCPtrInstr The EIP of the cli instruction.
82	*/
83	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
84	{
85	PCLISTAT pRec;
86
87	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
88	if (!pRec)
89	{
90	/* New cli instruction; insert into the tree. */
91	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
92	Assert(pRec);
93	if (!pRec)
94	return;
95	pRec->Core.Key = GCPtrInstr;
96
97	char szCliStatName[32];
98	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
99	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
100
101	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
102	Assert(fRc); NOREF(fRc);
103	}
104	STAM_COUNTER_INC(&pRec->Counter);
105	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
106	}
107	#endif /* VBOX_WITH_STATISTICS */
108
109
110
111	/**
112	* Resumes executing hypervisor after a debug event.
113	*
114	* This is kind of special since our current guest state is
115	* potentially out of sync.
116	*
117	* @returns VBox status code.
118	* @param pVM Pointer to the VM.
119	* @param pVCpu Pointer to the VMCPU.
120	*/
121	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
122	{
123	int rc;
124	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
125	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
126	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags));
127
128	/*
129	* Resume execution.
130	*/
131	CPUMRawEnter(pVCpu);
132	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
133	rc = VMMR3ResumeHyper(pVM, pVCpu);
134	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc));
135	rc = CPUMRawLeave(pVCpu, rc);
136	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
137
138	/*
139	* Deal with the return code.
140	*/
141	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
142	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
143	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
144	return rc;
145	}
146
147
148	/**
149	* Steps rawmode.
150	*
151	* @returns VBox status code.
152	* @param pVM Pointer to the VM.
153	* @param pVCpu Pointer to the VMCPU.
154	*/
155	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
156	{
157	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
158	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
159	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
160	int rc;
161	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
162	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
163	#ifndef DEBUG_sander
164	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
165	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
166	#endif
167	if (fGuest)
168	{
169	/*
170	* Check vital forced actions, but ignore pending interrupts and timers.
171	*/
172	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
173	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
174	{
175	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
176	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
177	if (rc != VINF_SUCCESS)
178	return rc;
179	}
180
181	/*
182	* Set flags for single stepping.
183	*/
184	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
185	}
186	else
187	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
188
189	/*
190	* Single step.
191	* We do not start time or anything, if anything we should just do a few nanoseconds.
192	*/
193	CPUMRawEnter(pVCpu);
194	do
195	{
196	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
197	rc = VMMR3ResumeHyper(pVM, pVCpu);
198	else
199	rc = VMMR3RawRunGC(pVM, pVCpu);
200	#ifndef DEBUG_sander
201	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
202	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
203	#endif
204	} while ( rc == VINF_SUCCESS
205	\|\| rc == VINF_EM_RAW_INTERRUPT);
206	rc = CPUMRawLeave(pVCpu, rc);
207	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
208
209	/*
210	* Make sure the trap flag is cleared.
211	* (Too bad if the guest is trying to single step too.)
212	*/
213	if (fGuest)
214	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
215	else
216	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
217
218	/*
219	* Deal with the return codes.
220	*/
221	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
222	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
223	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
224	return rc;
225	}
226
227
228	#ifdef DEBUG
229
230
231	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
232	{
233	int rc = VINF_SUCCESS;
234	EMSTATE enmOldState = pVCpu->em.s.enmState;
235	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
236
237	Log(("Single step BEGIN:\n"));
238	for (uint32_t i = 0; i < cIterations; i++)
239	{
240	DBGFR3PrgStep(pVCpu);
241	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
242	rc = emR3RawStep(pVM, pVCpu);
243	if ( rc != VINF_SUCCESS
244	&& rc != VINF_EM_DBG_STEPPED)
245	break;
246	}
247	Log(("Single step END: rc=%Rrc\n", rc));
248	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
249	pVCpu->em.s.enmState = enmOldState;
250	return rc;
251	}
252
253	#endif /* DEBUG */
254
255
256	/**
257	* Executes one (or perhaps a few more) instruction(s).
258	*
259	* @returns VBox status code suitable for EM.
260	*
261	* @param pVM Pointer to the VM.
262	* @param pVCpu Pointer to the VMCPU.
263	* @param rcGC GC return code
264	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
265	* instruction and prefix the log output with this text.
266	*/
267	#ifdef LOG_ENABLED
268	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
269	#else
270	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
271	#endif
272	{
273	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
274	int rc;
275
276	#ifdef LOG_ENABLED
277	/*
278	* Disassemble the instruction if requested.
279	*/
280	if (pszPrefix)
281	{
282	DBGFR3_INFO_LOG(pVM, "cpumguest", pszPrefix);
283	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
284	}
285	#endif /* LOG_ENABLED */
286
287	/*
288	* PATM is making life more interesting.
289	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
290	* tell PATM there is a trap in this code and have it take the appropriate actions
291	* to allow us execute the code in REM.
292	*/
293	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
294	{
295	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
296
297	RTGCPTR uNewEip;
298	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &uNewEip);
299	switch (rc)
300	{
301	/*
302	* It's not very useful to emulate a single instruction and then go back to raw
303	* mode; just execute the whole block until IF is set again.
304	*/
305	case VINF_SUCCESS:
306	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
307	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
308	pCtx->eip = uNewEip;
309	Assert(pCtx->eip);
310
311	if (pCtx->eflags.Bits.u1IF)
312	{
313	/*
314	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
315	*/
316	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
317	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
318	}
319	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
320	{
321	/* special case: iret, that sets IF, detected a pending irq/event */
322	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
323	}
324	return VINF_EM_RESCHEDULE_REM;
325
326	/*
327	* One instruction.
328	*/
329	case VINF_PATCH_EMULATE_INSTR:
330	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
331	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
332	pCtx->eip = uNewEip;
333	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
334
335	/*
336	* The patch was disabled, hand it to the REM.
337	*/
338	case VERR_PATCH_DISABLED:
339	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
340	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
341	pCtx->eip = uNewEip;
342	if (pCtx->eflags.Bits.u1IF)
343	{
344	/*
345	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
346	*/
347	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
348	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
349	}
350	return VINF_EM_RESCHEDULE_REM;
351
352	/* Force continued patch exection; usually due to write monitored stack. */
353	case VINF_PATCH_CONTINUE:
354	return VINF_SUCCESS;
355
356	default:
357	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
358	return VERR_IPE_UNEXPECTED_STATUS;
359	}
360	}
361
362
363	/*
364	* Use IEM and fallback on REM if the functionality is missing.
365	* Once IEM gets mature enough, nothing should ever fall back.
366	*/
367	//#define VBOX_WITH_FIRST_IEM_STEP_B
368	#if defined(VBOX_WITH_FIRST_IEM_STEP_B) \|\| !defined(VBOX_WITH_REM)
369	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
370	STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
371	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
372	STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
373	if (RT_SUCCESS(rc))
374	{
375	if (rc == VINF_SUCCESS \|\| rc == VINF_EM_RESCHEDULE)
376	rc = VINF_EM_RESCHEDULE;
377	# ifdef DEBUG_bird
378	else
379	AssertMsgFailed(("%Rrc\n", rc));
380	# endif
381	}
382	else if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
383	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)
384	#endif
385	{
386	#ifdef VBOX_WITH_REM
387	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
388	# ifndef VBOX_WITH_FIRST_IEM_STEP_B
389	Log(("EMINS[rem]: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
390	//# elif defined(DEBUG_bird)
391	// AssertFailed();
392	# endif
393	EMRemLock(pVM);
394	/* Flush the recompiler TLB if the VCPU has changed. */
395	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
396	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
397	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
398
399	rc = REMR3EmulateInstruction(pVM, pVCpu);
400	EMRemUnlock(pVM);
401	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
402	#else /* !VBOX_WITH_REM */
403	NOREF(pVM);
404	#endif /* !VBOX_WITH_REM */
405	}
406	return rc;
407	}
408
409
410	/**
411	* Executes one (or perhaps a few more) instruction(s).
412	* This is just a wrapper for discarding pszPrefix in non-logging builds.
413	*
414	* @returns VBox status code suitable for EM.
415	* @param pVM Pointer to the VM.
416	* @param pVCpu Pointer to the VMCPU.
417	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
418	* instruction and prefix the log output with this text.
419	* @param rcGC GC return code
420	*/
421	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
422	{
423	#ifdef LOG_ENABLED
424	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
425	#else
426	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
427	#endif
428	}
429
430	/**
431	* Executes one (or perhaps a few more) IO instruction(s).
432	*
433	* @returns VBox status code suitable for EM.
434	* @param pVM Pointer to the VM.
435	* @param pVCpu Pointer to the VMCPU.
436	*/
437	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
438	{
439	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
440
441	/* Hand it over to the interpreter. */
442	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
443	LogFlow(("emR3RawExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
444	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
445	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
446	return VBOXSTRICTRC_TODO(rcStrict);
447	}
448
449
450	/**
451	* Handle a guest context trap.
452	*
453	* @returns VBox status code suitable for EM.
454	* @param pVM Pointer to the VM.
455	* @param pVCpu Pointer to the VMCPU.
456	*/
457	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
458	{
459	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
460
461	/*
462	* Get the trap info.
463	*/
464	uint8_t u8TrapNo;
465	TRPMEVENT enmType;
466	RTGCUINT uErrorCode;
467	RTGCUINTPTR uCR2;
468	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
469	if (RT_FAILURE(rc))
470	{
471	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
472	return rc;
473	}
474
475
476	#if 1 /* Experimental: Review, disable if it causes trouble. */
477	/*
478	* Handle traps in patch code first.
479	*
480	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
481	* but several traps isn't handled specially by TRPM in RC and we end up here
482	* instead. One example is #DE.
483	*/
484	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
485	if ( uCpl == 0
486	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
487	{
488	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
489	return emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
490	}
491	#endif
492
493	/*
494	* If the guest gate is marked unpatched, then we will check again if we can patch it.
495	* (This assumes that we've already tried and failed to dispatch the trap in
496	* RC for the gates that already has been patched. Which is true for most high
497	* volume traps, because these are handled specially, but not for odd ones like #DE.)
498	*/
499	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
500	{
501	CSAMR3CheckGates(pVM, u8TrapNo, 1);
502	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
503
504	/* If it was successful, then we could go back to raw mode. */
505	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
506	{
507	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
508	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
509	AssertRCReturn(rc, rc);
510
511	TRPMERRORCODE enmError = uErrorCode != ~0U
512	? TRPM_TRAP_HAS_ERRORCODE
513	: TRPM_TRAP_NO_ERRORCODE;
514	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
515	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
516	{
517	TRPMResetTrap(pVCpu);
518	return VINF_EM_RESCHEDULE_RAW;
519	}
520	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
521	}
522	}
523
524	/*
525	* Scan kernel code that traps; we might not get another chance.
526	*/
527	/** @todo move this up before the dispatching? */
528	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
529	&& !pCtx->eflags.Bits.u1VM)
530	{
531	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
532	CSAMR3CheckCodeEx(pVM, pCtx, pCtx->eip);
533	}
534
535	/*
536	* Trap specific handling.
537	*/
538	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
539	{
540	/*
541	* If MONITOR & MWAIT are supported, then interpret them here.
542	*/
543	DISCPUSTATE cpu;
544	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
545	if ( RT_SUCCESS(rc)
546	&& (cpu.pCurInstr->uOpcode == OP_MONITOR \|\| cpu.pCurInstr->uOpcode == OP_MWAIT))
547	{
548	uint32_t u32Dummy, u32Features, u32ExtFeatures;
549	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
550	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
551	{
552	rc = TRPMResetTrap(pVCpu);
553	AssertRC(rc);
554
555	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
556	if (RT_SUCCESS(rc))
557	return rc;
558	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
559	}
560	}
561	}
562	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
563	{
564	/*
565	* Handle I/O bitmap?
566	*/
567	/** @todo We're not supposed to be here with a false guest trap concerning
568	* I/O access. We can easily handle those in RC. */
569	DISCPUSTATE cpu;
570	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
571	if ( RT_SUCCESS(rc)
572	&& (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
573	{
574	/*
575	* We should really check the TSS for the IO bitmap, but it's not like this
576	* lazy approach really makes things worse.
577	*/
578	rc = TRPMResetTrap(pVCpu);
579	AssertRC(rc);
580	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
581	}
582	}
583
584	#ifdef LOG_ENABLED
585	DBGFR3_INFO_LOG(pVM, "cpumguest", "Guest trap");
586	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Guest trap");
587
588	/* Get guest page information. */
589	uint64_t fFlags = 0;
590	RTGCPHYS GCPhys = 0;
591	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
592	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
593	pCtx->cs.Sel, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0,
594	(enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
595	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
596	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
597	#endif
598
599	/*
600	* #PG has CR2.
601	* (Because of stuff like above we must set CR2 in a delayed fashion.)
602	*/
603	if (u8TrapNo == 14 /* #PG */)
604	pCtx->cr2 = uCR2;
605
606	return VINF_EM_RESCHEDULE_REM;
607	}
608
609
610	/**
611	* Handle a ring switch trap.
612	* Need to do statistics and to install patches. The result is going to REM.
613	*
614	* @returns VBox status code suitable for EM.
615	* @param pVM Pointer to the VM.
616	* @param pVCpu Pointer to the VMCPU.
617	*/
618	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
619	{
620	int rc;
621	DISCPUSTATE Cpu;
622	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
623
624	/*
625	* sysenter, syscall & callgate
626	*/
627	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
628	if (RT_SUCCESS(rc))
629	{
630	if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
631	{
632	if (pCtx->SysEnter.cs != 0)
633	{
634	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
635	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
636	if (RT_SUCCESS(rc))
637	{
638	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched sysenter instruction");
639	return VINF_EM_RESCHEDULE_RAW;
640	}
641	}
642	}
643
644	#ifdef VBOX_WITH_STATISTICS
645	switch (Cpu.pCurInstr->uOpcode)
646	{
647	case OP_SYSENTER:
648	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
649	break;
650	case OP_SYSEXIT:
651	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
652	break;
653	case OP_SYSCALL:
654	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
655	break;
656	case OP_SYSRET:
657	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
658	break;
659	}
660	#endif
661	}
662	else
663	AssertRC(rc);
664
665	/* go to the REM to emulate a single instruction */
666	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
667	}
668
669
670	/**
671	* Handle a trap (\#PF or \#GP) in patch code
672	*
673	* @returns VBox status code suitable for EM.
674	* @param pVM Pointer to the VM.
675	* @param pVCpu Pointer to the VMCPU.
676	* @param pCtx Pointer to the guest CPU context.
677	* @param gcret GC return code.
678	*/
679	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
680	{
681	uint8_t u8TrapNo;
682	int rc;
683	TRPMEVENT enmType;
684	RTGCUINT uErrorCode;
685	RTGCUINTPTR uCR2;
686
687	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
688
689	if (gcret == VINF_PATM_PATCH_INT3)
690	{
691	u8TrapNo = 3;
692	uCR2 = 0;
693	uErrorCode = 0;
694	}
695	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
696	{
697	/* No active trap in this case. Kind of ugly. */
698	u8TrapNo = X86_XCPT_GP;
699	uCR2 = 0;
700	uErrorCode = 0;
701	}
702	else
703	{
704	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
705	if (RT_FAILURE(rc))
706	{
707	AssertReleaseMsgFailed(("emR3RawPatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
708	return rc;
709	}
710	/* Reset the trap as we'll execute the original instruction again. */
711	TRPMResetTrap(pVCpu);
712	}
713
714	/*
715	* Deal with traps inside patch code.
716	* (This code won't run outside GC.)
717	*/
718	if (u8TrapNo != 1)
719	{
720	#ifdef LOG_ENABLED
721	DBGFR3_INFO_LOG(pVM, "cpumguest", "Trap in patch code");
722	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patch code");
723
724	DISCPUSTATE Cpu;
725	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
726	if ( RT_SUCCESS(rc)
727	&& Cpu.pCurInstr->uOpcode == OP_IRET)
728	{
729	uint32_t eip, selCS, uEFlags;
730
731	/* Iret crashes are bad as we have already changed the flags on the stack */
732	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
733	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
734	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
735	if (rc == VINF_SUCCESS)
736	{
737	if ( (uEFlags & X86_EFL_VM)
738	\|\| (selCS & X86_SEL_RPL) == 3)
739	{
740	uint32_t selSS, esp;
741
742	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
743	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
744
745	if (uEFlags & X86_EFL_VM)
746	{
747	uint32_t selDS, selES, selFS, selGS;
748	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
749	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
750	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
751	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
752	if (rc == VINF_SUCCESS)
753	{
754	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
755	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
756	}
757	}
758	else
759	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
760	}
761	else
762	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
763	}
764	}
765	#endif /* LOG_ENABLED */
766	Log(("emR3RawPatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
767	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
768
769	RTGCPTR uNewEip;
770	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &uNewEip);
771	switch (rc)
772	{
773	/*
774	* Execute the faulting instruction.
775	*/
776	case VINF_SUCCESS:
777	{
778	/** @todo execute a whole block */
779	Log(("emR3RawPatchTrap: Executing faulting instruction at new address %RGv\n", uNewEip));
780	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
781	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
782
783	pCtx->eip = uNewEip;
784	AssertRelease(pCtx->eip);
785
786	if (pCtx->eflags.Bits.u1IF)
787	{
788	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
789	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
790	*/
791	if ( u8TrapNo == X86_XCPT_GP
792	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
793	{
794	/** @todo move to PATMR3HandleTrap */
795	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
796	PATMR3RemovePatch(pVM, pCtx->eip);
797	}
798
799	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
800	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
801
802	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
803	/* Interrupts are enabled; just go back to the original instruction.
804	return VINF_SUCCESS; */
805	}
806	return VINF_EM_RESCHEDULE_REM;
807	}
808
809	/*
810	* One instruction.
811	*/
812	case VINF_PATCH_EMULATE_INSTR:
813	Log(("emR3RawPatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
814	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
815	pCtx->eip = uNewEip;
816	AssertRelease(pCtx->eip);
817	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
818
819	/*
820	* The patch was disabled, hand it to the REM.
821	*/
822	case VERR_PATCH_DISABLED:
823	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
824	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
825	pCtx->eip = uNewEip;
826	AssertRelease(pCtx->eip);
827
828	if (pCtx->eflags.Bits.u1IF)
829	{
830	/*
831	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
832	*/
833	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
834	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
835	}
836	return VINF_EM_RESCHEDULE_REM;
837
838	/* Force continued patch exection; usually due to write monitored stack. */
839	case VINF_PATCH_CONTINUE:
840	return VINF_SUCCESS;
841
842	/*
843	* Anything else is fatal.
844	*/
845	default:
846	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
847	return VERR_IPE_UNEXPECTED_STATUS;
848	}
849	}
850	return VINF_SUCCESS;
851	}
852
853
854	/**
855	* Handle a privileged instruction.
856	*
857	* @returns VBox status code suitable for EM.
858	* @param pVM Pointer to the VM.
859	* @param pVCpu Pointer to the VMCPU.
860	*/
861	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
862	{
863	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
864
865	Assert(!pCtx->eflags.Bits.u1VM);
866
867	if (PATMIsEnabled(pVM))
868	{
869	/*
870	* Check if in patch code.
871	*/
872	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
873	{
874	#ifdef LOG_ENABLED
875	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
876	#endif
877	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pCtx->eip));
878	return VERR_EM_RAW_PATCH_CONFLICT;
879	}
880	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
881	&& !pCtx->eflags.Bits.u1VM
882	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
883	{
884	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
885	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
886	if (RT_SUCCESS(rc))
887	{
888	#ifdef LOG_ENABLED
889	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
890	#endif
891	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched privileged instruction");
892	return VINF_SUCCESS;
893	}
894	}
895	}
896
897	#ifdef LOG_ENABLED
898	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
899	{
900	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
901	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
902	}
903	#endif
904
905	/*
906	* Instruction statistics and logging.
907	*/
908	DISCPUSTATE Cpu;
909	int rc;
910
911	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
912	if (RT_SUCCESS(rc))
913	{
914	#ifdef VBOX_WITH_STATISTICS
915	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
916	switch (Cpu.pCurInstr->uOpcode)
917	{
918	case OP_INVLPG:
919	STAM_COUNTER_INC(&pStats->StatInvlpg);
920	break;
921	case OP_IRET:
922	STAM_COUNTER_INC(&pStats->StatIret);
923	break;
924	case OP_CLI:
925	STAM_COUNTER_INC(&pStats->StatCli);
926	emR3RecordCli(pVM, pVCpu, pCtx->rip);
927	break;
928	case OP_STI:
929	STAM_COUNTER_INC(&pStats->StatSti);
930	break;
931	case OP_INSB:
932	case OP_INSWD:
933	case OP_IN:
934	case OP_OUTSB:
935	case OP_OUTSWD:
936	case OP_OUT:
937	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
938	break;
939
940	case OP_MOV_CR:
941	if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
942	{
943	//read
944	Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
945	Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
946	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
947	}
948	else
949	{
950	//write
951	Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
952	Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
953	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
954	}
955	break;
956
957	case OP_MOV_DR:
958	STAM_COUNTER_INC(&pStats->StatMovDRx);
959	break;
960	case OP_LLDT:
961	STAM_COUNTER_INC(&pStats->StatMovLldt);
962	break;
963	case OP_LIDT:
964	STAM_COUNTER_INC(&pStats->StatMovLidt);
965	break;
966	case OP_LGDT:
967	STAM_COUNTER_INC(&pStats->StatMovLgdt);
968	break;
969	case OP_SYSENTER:
970	STAM_COUNTER_INC(&pStats->StatSysEnter);
971	break;
972	case OP_SYSEXIT:
973	STAM_COUNTER_INC(&pStats->StatSysExit);
974	break;
975	case OP_SYSCALL:
976	STAM_COUNTER_INC(&pStats->StatSysCall);
977	break;
978	case OP_SYSRET:
979	STAM_COUNTER_INC(&pStats->StatSysRet);
980	break;
981	case OP_HLT:
982	STAM_COUNTER_INC(&pStats->StatHlt);
983	break;
984	default:
985	STAM_COUNTER_INC(&pStats->StatMisc);
986	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
987	break;
988	}
989	#endif /* VBOX_WITH_STATISTICS */
990	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
991	&& !pCtx->eflags.Bits.u1VM
992	&& CPUMGetGuestCodeBits(pVCpu) == 32)
993	{
994	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
995	switch (Cpu.pCurInstr->uOpcode)
996	{
997	case OP_CLI:
998	pCtx->eflags.u32 &= ~X86_EFL_IF;
999	Assert(Cpu.cbInstr == 1);
1000	pCtx->rip += Cpu.cbInstr;
1001	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1002	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1003
1004	case OP_STI:
1005	pCtx->eflags.u32 \|= X86_EFL_IF;
1006	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr);
1007	Assert(Cpu.cbInstr == 1);
1008	pCtx->rip += Cpu.cbInstr;
1009	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1010	return VINF_SUCCESS;
1011
1012	case OP_HLT:
1013	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1014	{
1015	PATMTRANSSTATE enmState;
1016	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1017
1018	if (enmState == PATMTRANS_OVERWRITTEN)
1019	{
1020	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1021	Assert(rc == VERR_PATCH_DISABLED);
1022	/* Conflict detected, patch disabled */
1023	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1024
1025	enmState = PATMTRANS_SAFE;
1026	}
1027
1028	/* The translation had better be successful. Otherwise we can't recover. */
1029	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1030	if (enmState != PATMTRANS_OVERWRITTEN)
1031	pCtx->eip = pOrgInstrGC;
1032	}
1033	/* no break; we could just return VINF_EM_HALT here */
1034
1035	case OP_MOV_CR:
1036	case OP_MOV_DR:
1037	#ifdef LOG_ENABLED
1038	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1039	{
1040	DBGFR3_INFO_LOG(pVM, "cpumguest", "PRIV");
1041	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
1042	}
1043	#endif
1044
1045	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1046	if (RT_SUCCESS(rc))
1047	{
1048	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1049
1050	if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1051	&& Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1052	)
1053	{
1054	/* Deal with CR0 updates inside patch code that force
1055	* us to go to the recompiler.
1056	*/
1057	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1058	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1059	{
1060	PATMTRANSSTATE enmState;
1061	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1062
1063	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1064	if (enmState == PATMTRANS_OVERWRITTEN)
1065	{
1066	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1067	Assert(rc == VERR_PATCH_DISABLED);
1068	/* Conflict detected, patch disabled */
1069	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1070	enmState = PATMTRANS_SAFE;
1071	}
1072	/* The translation had better be successful. Otherwise we can't recover. */
1073	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1074	if (enmState != PATMTRANS_OVERWRITTEN)
1075	pCtx->rip = pOrgInstrGC;
1076	}
1077
1078	/* Reschedule is necessary as the execution/paging mode might have changed. */
1079	return VINF_EM_RESCHEDULE;
1080	}
1081	return rc; /* can return VINF_EM_HALT as well. */
1082	}
1083	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1084	break; /* fall back to the recompiler */
1085	}
1086	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1087	}
1088	}
1089
1090	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1091	return emR3RawPatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1092
1093	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
1094	}
1095
1096
1097	/**
1098	* Update the forced rawmode execution modifier.
1099	*
1100	* This function is called when we're returning from the raw-mode loop(s). If we're
1101	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1102	* if not in patch code, the flag will be cleared.
1103	*
1104	* We should never interrupt patch code while it's being executed. Cli patches can
1105	* contain big code blocks, but they are always executed with IF=0. Other patches
1106	* replace single instructions and should be atomic.
1107	*
1108	* @returns Updated rc.
1109	*
1110	* @param pVM Pointer to the VM.
1111	* @param pVCpu Pointer to the VMCPU.
1112	* @param pCtx Pointer to the guest CPU context.
1113	* @param rc The result code.
1114	*/
1115	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1116	{
1117	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1118	{
1119	/* ignore reschedule attempts. */
1120	switch (rc)
1121	{
1122	case VINF_EM_RESCHEDULE:
1123	case VINF_EM_RESCHEDULE_REM:
1124	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1125	rc = VINF_SUCCESS;
1126	break;
1127	}
1128	pVCpu->em.s.fForceRAW = true;
1129	}
1130	else
1131	pVCpu->em.s.fForceRAW = false;
1132	return rc;
1133	}
1134
1135
1136	/**
1137	* Check for pending raw actions
1138	*
1139	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1140	* EM statuses.
1141	* @param pVM Pointer to the VM.
1142	* @param pVCpu Pointer to the VMCPU.
1143	*/
1144	VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1145	{
1146	int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1147	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1148	return rc;
1149	}
1150
1151
1152	/**
1153	* Process raw-mode specific forced actions.
1154	*
1155	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1156	*
1157	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1158	* EM statuses.
1159	* @param pVM Pointer to the VM.
1160	* @param pVCpu Pointer to the VMCPU.
1161	* @param pCtx Pointer to the guest CPU context.
1162	*/
1163	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1164	{
1165	/*
1166	* Note that the order is vitally important!
1167	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1168	*/
1169	VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1170
1171	/*
1172	* Sync selector tables.
1173	*/
1174	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1175	{
1176	VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1177	if (rcStrict != VINF_SUCCESS)
1178	return VBOXSTRICTRC_TODO(rcStrict);
1179	}
1180
1181	/*
1182	* Sync IDT.
1183	*
1184	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1185	* and PGMShwModifyPage, so we're in for trouble if for instance a
1186	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1187	*/
1188	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1189	{
1190	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1191	&& EMIsRawRing0Enabled(pVM)
1192	&& CSAMIsEnabled(pVM))
1193	{
1194	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1195	if (RT_FAILURE(rc))
1196	return rc;
1197	}
1198
1199	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1200	if (RT_FAILURE(rc))
1201	return rc;
1202	}
1203
1204	/*
1205	* Sync TSS.
1206	*/
1207	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1208	{
1209	int rc = SELMR3SyncTSS(pVM, pVCpu);
1210	if (RT_FAILURE(rc))
1211	return rc;
1212	}
1213
1214	/*
1215	* Sync page directory.
1216	*/
1217	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1218	{
1219	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1220	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1221	if (RT_FAILURE(rc))
1222	return rc;
1223
1224	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1225
1226	/* Prefetch pages for EIP and ESP. */
1227	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1228	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1229	if (rc == VINF_SUCCESS)
1230	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1231	if (rc != VINF_SUCCESS)
1232	{
1233	if (rc != VINF_PGM_SYNC_CR3)
1234	{
1235	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1236	return rc;
1237	}
1238	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1239	if (RT_FAILURE(rc))
1240	return rc;
1241	}
1242	/** @todo maybe prefetch the supervisor stack page as well */
1243	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1244	}
1245
1246	/*
1247	* Allocate handy pages (just in case the above actions have consumed some pages).
1248	*/
1249	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1250	{
1251	int rc = PGMR3PhysAllocateHandyPages(pVM);
1252	if (RT_FAILURE(rc))
1253	return rc;
1254	}
1255
1256	/*
1257	* Check whether we're out of memory now.
1258	*
1259	* This may stem from some of the above actions or operations that has been executed
1260	* since we ran FFs. The allocate handy pages must for instance always be followed by
1261	* this check.
1262	*/
1263	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1264	return VINF_EM_NO_MEMORY;
1265
1266	return VINF_SUCCESS;
1267	}
1268
1269
1270	/**
1271	* Executes raw code.
1272	*
1273	* This function contains the raw-mode version of the inner
1274	* execution loop (the outer loop being in EMR3ExecuteVM()).
1275	*
1276	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1277	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1278	*
1279	* @param pVM Pointer to the VM.
1280	* @param pVCpu Pointer to the VMCPU.
1281	* @param pfFFDone Where to store an indicator telling whether or not
1282	* FFs were done before returning.
1283	*/
1284	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1285	{
1286	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1287
1288	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1289	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1290	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs.Sel, pCtx->eip));
1291	pVCpu->em.s.fForceRAW = false;
1292	*pfFFDone = false;
1293
1294
1295	/*
1296	*
1297	* Spin till we get a forced action or raw mode status code resulting in
1298	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1299	*
1300	*/
1301	for (;;)
1302	{
1303	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1304
1305	/*
1306	* Check various preconditions.
1307	*/
1308	#ifdef VBOX_STRICT
1309	# ifdef VBOX_WITH_REM
1310	Assert(REMR3QueryPendingInterrupt(pVM, pVCpu) == REM_NO_PENDING_IRQ);
1311	# endif
1312	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 3 \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 0
1313	\|\| (EMIsRawRing1Enabled(pVM) && (pCtx->ss.Sel & X86_SEL_RPL) == 1));
1314	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1315	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1316	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1317	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1318	&& PGMMapHasConflicts(pVM))
1319	{
1320	PGMMapCheck(pVM);
1321	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1322	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1323	}
1324	#endif /* VBOX_STRICT */
1325
1326	/*
1327	* Process high priority pre-execution raw-mode FFs.
1328	*/
1329	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1330	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1331	{
1332	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1333	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1334	if (rc != VINF_SUCCESS)
1335	break;
1336	}
1337
1338	/*
1339	* If we're going to execute ring-0 code, the guest state needs to
1340	* be modified a bit and some of the state components (IF, SS/CS RPL,
1341	* and perhaps EIP) needs to be stored with PATM.
1342	*/
1343	rc = CPUMRawEnter(pVCpu);
1344	if (rc != VINF_SUCCESS)
1345	{
1346	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1347	break;
1348	}
1349
1350	/*
1351	* Scan code before executing it. Don't bother with user mode or V86 code
1352	*/
1353	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
1354	&& !pCtx->eflags.Bits.u1VM
1355	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1356	{
1357	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1358	CSAMR3CheckCodeEx(pVM, pCtx, pCtx->eip);
1359	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1360	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1361	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1362	{
1363	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1364	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1365	if (rc != VINF_SUCCESS)
1366	{
1367	rc = CPUMRawLeave(pVCpu, rc);
1368	break;
1369	}
1370	}
1371	}
1372
1373	#ifdef LOG_ENABLED
1374	/*
1375	* Log important stuff before entering GC.
1376	*/
1377	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1378	if (pCtx->eflags.Bits.u1VM)
1379	Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1380	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 1)
1381	Log(("RR0: %x:%08x ESP=%x:%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n",
1382	pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, CPUMRawGetEFlags(pVCpu), !!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF,
1383	pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL), CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip)));
1384	# ifdef VBOX_WITH_RAW_RING1
1385	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 2)
1386	Log(("RR1: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x CPL=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, (pCtx->ss.Sel & X86_SEL_RPL)));
1387	# endif
1388	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 3)
1389	Log(("RR3: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1390	#endif /* LOG_ENABLED */
1391
1392
1393
1394	/*
1395	* Execute the code.
1396	*/
1397	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1398	if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1399	{
1400	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1401	VBOXVMM_EM_RAW_RUN_PRE(pVCpu, pCtx);
1402	rc = VMMR3RawRunGC(pVM, pVCpu);
1403	VBOXVMM_EM_RAW_RUN_RET(pVCpu, pCtx, rc);
1404	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1405	}
1406	else
1407	{
1408	/* Give up this time slice; virtual time continues */
1409	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1410	RTThreadSleep(5);
1411	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1412	rc = VINF_SUCCESS;
1413	}
1414	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1415
1416	LogFlow(("RR%u-E: %08x ESP=%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d\n",
1417	(pCtx->ss.Sel & X86_SEL_RPL), pCtx->eip, pCtx->esp, CPUMRawGetEFlags(pVCpu),
1418	!!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1419	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1420
1421
1422
1423	/*
1424	* Restore the real CPU state and deal with high priority post
1425	* execution FFs before doing anything else.
1426	*/
1427	rc = CPUMRawLeave(pVCpu, rc);
1428	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1429	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1430	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1431	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1432
1433	#ifdef VBOX_STRICT
1434	/*
1435	* Assert TSS consistency & rc vs patch code.
1436	*/
1437	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1438	&& EMIsRawRing0Enabled(pVM))
1439	SELMR3CheckTSS(pVM);
1440	switch (rc)
1441	{
1442	case VINF_SUCCESS:
1443	case VINF_EM_RAW_INTERRUPT:
1444	case VINF_PATM_PATCH_TRAP_PF:
1445	case VINF_PATM_PATCH_TRAP_GP:
1446	case VINF_PATM_PATCH_INT3:
1447	case VINF_PATM_CHECK_PATCH_PAGE:
1448	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1449	case VINF_EM_RAW_GUEST_TRAP:
1450	case VINF_EM_RESCHEDULE_RAW:
1451	break;
1452
1453	default:
1454	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1455	LogIt(0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1456	break;
1457	}
1458	/*
1459	* Let's go paranoid!
1460	*/
1461	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1462	&& PGMMapHasConflicts(pVM))
1463	{
1464	PGMMapCheck(pVM);
1465	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1466	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1467	}
1468	#endif /* VBOX_STRICT */
1469
1470	/*
1471	* Process the returned status code.
1472	*/
1473	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1474	{
1475	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1476	break;
1477	}
1478	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1479	if (rc != VINF_SUCCESS)
1480	{
1481	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1482	if (rc != VINF_SUCCESS)
1483	{
1484	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1485	break;
1486	}
1487	}
1488
1489	/*
1490	* Check and execute forced actions.
1491	*/
1492	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1493	TMTimerPollVoid(pVM, pVCpu);
1494	#endif
1495	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1496	if ( VM_FF_IS_PENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1497	\|\| VMCPU_FF_IS_PENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1498	{
1499	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2 : 1));
1500
1501	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1502	rc = emR3ForcedActions(pVM, pVCpu, rc);
1503	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1504	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1505	if ( rc != VINF_SUCCESS
1506	&& rc != VINF_EM_RESCHEDULE_RAW)
1507	{
1508	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1509	if (rc != VINF_SUCCESS)
1510	{
1511	*pfFFDone = true;
1512	break;
1513	}
1514	}
1515	}
1516	}
1517
1518	/*
1519	* Return to outer loop.
1520	*/
1521	#if defined(LOG_ENABLED) && defined(DEBUG)
1522	RTLogFlush(NULL);
1523	#endif
1524	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1525	return rc;
1526	}
1527

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 57008

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