EMRaw.cpp@ 69175

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1	/* $Id: EMRaw.cpp 69111 2017-10-17 14:26:02Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#include <VBox/vmm/em.h>
24	#include <VBox/vmm/vmm.h>
25	#include <VBox/vmm/patm.h>
26	#include <VBox/vmm/csam.h>
27	#include <VBox/vmm/selm.h>
28	#include <VBox/vmm/trpm.h>
29	#include <VBox/vmm/iem.h>
30	#include <VBox/vmm/iom.h>
31	#include <VBox/vmm/dbgf.h>
32	#include <VBox/vmm/pgm.h>
33	#ifdef VBOX_WITH_REM
34	# include <VBox/vmm/rem.h>
35	#endif
36	#include <VBox/vmm/tm.h>
37	#include <VBox/vmm/mm.h>
38	#include <VBox/vmm/ssm.h>
39	#include <VBox/vmm/pdmapi.h>
40	#include <VBox/vmm/pdmcritsect.h>
41	#include <VBox/vmm/pdmqueue.h>
42	#include <VBox/vmm/patm.h>
43	#include "EMInternal.h"
44	#include <VBox/vmm/vm.h>
45	#include <VBox/vmm/gim.h>
46	#include <VBox/vmm/cpumdis.h>
47	#include <VBox/dis.h>
48	#include <VBox/disopcode.h>
49	#include <VBox/vmm/dbgf.h>
50	#include "VMMTracing.h"
51
52	#include <VBox/log.h>
53	#include <iprt/asm.h>
54	#include <iprt/string.h>
55	#include <iprt/stream.h>
56
57
58
59	/*********************************************************************************************************************************
60	* Internal Functions *
61	*********************************************************************************************************************************/
62	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx);
63	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
64	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
65	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret);
66	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
67	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
68	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
69
70	#define EMHANDLERC_WITH_PATM
71	#define emR3ExecuteInstruction emR3RawExecuteInstruction
72	#define emR3ExecuteIOInstruction emR3RawExecuteIOInstruction
73	#include "EMHandleRCTmpl.h"
74
75
76
77	#ifdef VBOX_WITH_STATISTICS
78	/**
79	* Just a braindead function to keep track of cli addresses.
80	* @param pVM The cross context VM structure.
81	* @param pVCpu The cross context virtual CPU structure.
82	* @param GCPtrInstr The EIP of the cli instruction.
83	*/
84	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
85	{
86	PCLISTAT pRec;
87
88	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
89	if (!pRec)
90	{
91	/* New cli instruction; insert into the tree. */
92	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
93	Assert(pRec);
94	if (!pRec)
95	return;
96	pRec->Core.Key = GCPtrInstr;
97
98	char szCliStatName[32];
99	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
100	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
101
102	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
103	Assert(fRc); NOREF(fRc);
104	}
105	STAM_COUNTER_INC(&pRec->Counter);
106	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
107	}
108	#endif /* VBOX_WITH_STATISTICS */
109
110
111
112	/**
113	* Resumes executing hypervisor after a debug event.
114	*
115	* This is kind of special since our current guest state is
116	* potentially out of sync.
117	*
118	* @returns VBox status code.
119	* @param pVM The cross context VM structure.
120	* @param pVCpu The cross context virtual CPU structure.
121	*/
122	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
123	{
124	int rc;
125	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
126	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
127	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags));
128
129	/*
130	* Resume execution.
131	*/
132	CPUMRawEnter(pVCpu);
133	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
134	rc = VMMR3ResumeHyper(pVM, pVCpu);
135	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags, rc));
136	rc = CPUMRawLeave(pVCpu, rc);
137	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
138
139	/*
140	* Deal with the return code.
141	*/
142	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
143	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
144	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
145	return rc;
146	}
147
148
149	/**
150	* Steps rawmode.
151	*
152	* @returns VBox status code.
153	* @param pVM The cross context VM structure.
154	* @param pVCpu The cross context virtual CPU structure.
155	*/
156	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
157	{
158	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
159	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
160	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
161	int rc;
162	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
163	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
164	#ifndef DEBUG_sander
165	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
166	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
167	#endif
168	if (fGuest)
169	{
170	/*
171	* Check vital forced actions, but ignore pending interrupts and timers.
172	*/
173	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
174	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
175	{
176	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
177	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
178	if (rc != VINF_SUCCESS)
179	return rc;
180	}
181
182	/*
183	* Set flags for single stepping.
184	*/
185	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
186	}
187	else
188	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
189
190	/*
191	* Single step.
192	* We do not start time or anything, if anything we should just do a few nanoseconds.
193	*/
194	CPUMRawEnter(pVCpu);
195	do
196	{
197	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
198	rc = VMMR3ResumeHyper(pVM, pVCpu);
199	else
200	rc = VMMR3RawRunGC(pVM, pVCpu);
201	#ifndef DEBUG_sander
202	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
203	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
204	#endif
205	} while ( rc == VINF_SUCCESS
206	\|\| rc == VINF_EM_RAW_INTERRUPT);
207	rc = CPUMRawLeave(pVCpu, rc);
208	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
209
210	/*
211	* Make sure the trap flag is cleared.
212	* (Too bad if the guest is trying to single step too.)
213	*/
214	if (fGuest)
215	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
216	else
217	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
218
219	/*
220	* Deal with the return codes.
221	*/
222	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
223	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
224	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
225	return rc;
226	}
227
228
229	#ifdef DEBUG
230
231
232	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
233	{
234	int rc = VINF_SUCCESS;
235	EMSTATE enmOldState = pVCpu->em.s.enmState;
236	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
237
238	Log(("Single step BEGIN:\n"));
239	for (uint32_t i = 0; i < cIterations; i++)
240	{
241	DBGFR3PrgStep(pVCpu);
242	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
243	rc = emR3RawStep(pVM, pVCpu);
244	if ( rc != VINF_SUCCESS
245	&& rc != VINF_EM_DBG_STEPPED)
246	break;
247	}
248	Log(("Single step END: rc=%Rrc\n", rc));
249	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
250	pVCpu->em.s.enmState = enmOldState;
251	return rc;
252	}
253
254	#endif /* DEBUG */
255
256
257	/**
258	* Executes one (or perhaps a few more) instruction(s).
259	*
260	* @returns VBox status code suitable for EM.
261	*
262	* @param pVM The cross context VM structure.
263	* @param pVCpu The cross context virtual CPU structure.
264	* @param rcGC GC return code
265	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
266	* instruction and prefix the log output with this text.
267	*/
268	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
269	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
270	#else
271	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
272	#endif
273	{
274	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
275	int rc;
276
277	#ifdef LOG_ENABLED
278	/*
279	* Disassemble the instruction if requested.
280	*/
281	if (pszPrefix)
282	{
283	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", pszPrefix);
284	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
285	}
286	#endif /* LOG_ENABLED */
287
288	/*
289	* PATM is making life more interesting.
290	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
291	* tell PATM there is a trap in this code and have it take the appropriate actions
292	* to allow us execute the code in REM.
293	*/
294	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
295	{
296	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pCtx->eip));
297
298	RTGCPTR uNewEip;
299	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &uNewEip);
300	switch (rc)
301	{
302	/*
303	* It's not very useful to emulate a single instruction and then go back to raw
304	* mode; just execute the whole block until IF is set again.
305	*/
306	case VINF_SUCCESS:
307	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
308	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
309	pCtx->eip = uNewEip;
310	Assert(pCtx->eip);
311
312	if (pCtx->eflags.Bits.u1IF)
313	{
314	/*
315	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
316	*/
317	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
318	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
319	}
320	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
321	{
322	/* special case: iret, that sets IF, detected a pending irq/event */
323	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
324	}
325	return VINF_EM_RESCHEDULE_REM;
326
327	/*
328	* One instruction.
329	*/
330	case VINF_PATCH_EMULATE_INSTR:
331	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
332	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
333	pCtx->eip = uNewEip;
334	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
335
336	/*
337	* The patch was disabled, hand it to the REM.
338	*/
339	case VERR_PATCH_DISABLED:
340	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
341	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
342	pCtx->eip = uNewEip;
343	if (pCtx->eflags.Bits.u1IF)
344	{
345	/*
346	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
347	*/
348	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
349	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
350	}
351	return VINF_EM_RESCHEDULE_REM;
352
353	/* Force continued patch exection; usually due to write monitored stack. */
354	case VINF_PATCH_CONTINUE:
355	return VINF_SUCCESS;
356
357	default:
358	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
359	return VERR_IPE_UNEXPECTED_STATUS;
360	}
361	}
362
363
364	/*
365	* Use IEM and fallback on REM if the functionality is missing.
366	* Once IEM gets mature enough, nothing should ever fall back.
367	*/
368	#define VBOX_WITH_FIRST_IEM_STEP_B
369	#if defined(VBOX_WITH_FIRST_IEM_STEP_B) \|\| !defined(VBOX_WITH_REM)
370	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
371	STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
372	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
373	STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
374	if (RT_SUCCESS(rc))
375	{
376	if (rc == VINF_SUCCESS \|\| rc == VINF_EM_RESCHEDULE)
377	rc = VINF_EM_RESCHEDULE;
378	}
379	else if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
380	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)
381	#endif
382	{
383	#ifdef VBOX_WITH_REM
384	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
385	# ifndef VBOX_WITH_FIRST_IEM_STEP_B
386	Log(("EMINS[rem]: %04x:%RGv RSP=%RGv\n", pCtx->cs.Sel, (RTGCPTR)pCtx->rip, (RTGCPTR)pCtx->rsp));
387	//# elif defined(DEBUG_bird)
388	// AssertFailed();
389	# endif
390	EMRemLock(pVM);
391	/* Flush the recompiler TLB if the VCPU has changed. */
392	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
393	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
394	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
395
396	rc = REMR3EmulateInstruction(pVM, pVCpu);
397	EMRemUnlock(pVM);
398	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
399	#else /* !VBOX_WITH_REM */
400	NOREF(pVM);
401	#endif /* !VBOX_WITH_REM */
402	}
403	return rc;
404	}
405
406
407	/**
408	* Executes one (or perhaps a few more) instruction(s).
409	* This is just a wrapper for discarding pszPrefix in non-logging builds.
410	*
411	* @returns VBox status code suitable for EM.
412	* @param pVM The cross context VM structure.
413	* @param pVCpu The cross context virtual CPU structure.
414	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
415	* instruction and prefix the log output with this text.
416	* @param rcGC GC return code
417	*/
418	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
419	{
420	#ifdef LOG_ENABLED
421	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
422	#else
423	RT_NOREF_PV(pszPrefix);
424	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
425	#endif
426	}
427
428	/**
429	* Executes one (or perhaps a few more) IO instruction(s).
430	*
431	* @returns VBox status code suitable for EM.
432	* @param pVM The cross context VM structure.
433	* @param pVCpu The cross context virtual CPU structure.
434	*/
435	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
436	{
437	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
438	RT_NOREF_PV(pVM);
439
440	/* Hand it over to the interpreter. */
441	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
442	LogFlow(("emR3RawExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
443	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
444	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
445	return VBOXSTRICTRC_TODO(rcStrict);
446	}
447
448
449	/**
450	* Handle a guest context trap.
451	*
452	* @returns VBox status code suitable for EM.
453	* @param pVM The cross context VM structure.
454	* @param pVCpu The cross context virtual CPU structure.
455	*/
456	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
457	{
458	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
459
460	/*
461	* Get the trap info.
462	*/
463	uint8_t u8TrapNo;
464	TRPMEVENT enmType;
465	RTGCUINT uErrorCode;
466	RTGCUINTPTR uCR2;
467	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
468	if (RT_FAILURE(rc))
469	{
470	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
471	return rc;
472	}
473
474
475	#if 1 /* Experimental: Review, disable if it causes trouble. */
476	/*
477	* Handle traps in patch code first.
478	*
479	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
480	* but several traps isn't handled specially by TRPM in RC and we end up here
481	* instead. One example is #DE.
482	*/
483	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
484	if ( uCpl == 0
485	&& PATMIsPatchGCAddr(pVM, pCtx->eip))
486	{
487	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pCtx->eip));
488	return emR3RawPatchTrap(pVM, pVCpu, pCtx, rc);
489	}
490	#endif
491
492	/*
493	* If the guest gate is marked unpatched, then we will check again if we can patch it.
494	* (This assumes that we've already tried and failed to dispatch the trap in
495	* RC for the gates that already has been patched. Which is true for most high
496	* volume traps, because these are handled specially, but not for odd ones like #DE.)
497	*/
498	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
499	{
500	CSAMR3CheckGates(pVM, u8TrapNo, 1);
501	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
502
503	/* If it was successful, then we could go back to raw mode. */
504	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
505	{
506	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
507	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
508	AssertRCReturn(rc, rc);
509
510	TRPMERRORCODE enmError = uErrorCode != ~0U
511	? TRPM_TRAP_HAS_ERRORCODE
512	: TRPM_TRAP_NO_ERRORCODE;
513	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(pCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
514	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
515	{
516	TRPMResetTrap(pVCpu);
517	return VINF_EM_RESCHEDULE_RAW;
518	}
519	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
520	}
521	}
522
523	/*
524	* Scan kernel code that traps; we might not get another chance.
525	*/
526	/** @todo move this up before the dispatching? */
527	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
528	&& !pCtx->eflags.Bits.u1VM)
529	{
530	Assert(!PATMIsPatchGCAddr(pVM, pCtx->eip));
531	CSAMR3CheckCodeEx(pVM, pCtx, pCtx->eip);
532	}
533
534	/*
535	* Trap specific handling.
536	*/
537	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
538	{
539	/*
540	* If MONITOR & MWAIT are supported, then interpret them here.
541	*/
542	DISCPUSTATE cpu;
543	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap (#UD): ");
544	if ( RT_SUCCESS(rc)
545	&& (cpu.pCurInstr->uOpcode == OP_MONITOR \|\| cpu.pCurInstr->uOpcode == OP_MWAIT))
546	{
547	uint32_t u32Dummy, u32Features, u32ExtFeatures;
548	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
549	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
550	{
551	rc = TRPMResetTrap(pVCpu);
552	AssertRC(rc);
553
554	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
555	if (RT_SUCCESS(rc))
556	return rc;
557	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
558	}
559	}
560	}
561	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
562	{
563	/*
564	* Handle I/O bitmap?
565	*/
566	/** @todo We're not supposed to be here with a false guest trap concerning
567	* I/O access. We can easily handle those in RC. */
568	DISCPUSTATE cpu;
569	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &cpu, "Guest Trap: ");
570	if ( RT_SUCCESS(rc)
571	&& (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
572	{
573	/*
574	* We should really check the TSS for the IO bitmap, but it's not like this
575	* lazy approach really makes things worse.
576	*/
577	rc = TRPMResetTrap(pVCpu);
578	AssertRC(rc);
579	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
580	}
581	}
582
583	#ifdef LOG_ENABLED
584	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "Guest trap");
585	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Guest trap");
586
587	/* Get guest page information. */
588	uint64_t fFlags = 0;
589	RTGCPHYS GCPhys = 0;
590	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
591	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
592	pCtx->cs.Sel, pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0,
593	(enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
594	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
595	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
596	#endif
597
598	/*
599	* #PG has CR2.
600	* (Because of stuff like above we must set CR2 in a delayed fashion.)
601	*/
602	if (u8TrapNo == 14 /* #PG */)
603	pCtx->cr2 = uCR2;
604
605	return VINF_EM_RESCHEDULE_REM;
606	}
607
608
609	/**
610	* Handle a ring switch trap.
611	* Need to do statistics and to install patches. The result is going to REM.
612	*
613	* @returns VBox status code suitable for EM.
614	* @param pVM The cross context VM structure.
615	* @param pVCpu The cross context virtual CPU structure.
616	*/
617	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
618	{
619	int rc;
620	DISCPUSTATE Cpu;
621	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
622
623	/*
624	* sysenter, syscall & callgate
625	*/
626	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "RSWITCH: ");
627	if (RT_SUCCESS(rc))
628	{
629	if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
630	{
631	if (pCtx->SysEnter.cs != 0)
632	{
633	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
634	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
635	if (RT_SUCCESS(rc))
636	{
637	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched sysenter instruction");
638	return VINF_EM_RESCHEDULE_RAW;
639	}
640	}
641	}
642
643	#ifdef VBOX_WITH_STATISTICS
644	switch (Cpu.pCurInstr->uOpcode)
645	{
646	case OP_SYSENTER:
647	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
648	break;
649	case OP_SYSEXIT:
650	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
651	break;
652	case OP_SYSCALL:
653	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
654	break;
655	case OP_SYSRET:
656	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
657	break;
658	}
659	#endif
660	}
661	else
662	AssertRC(rc);
663
664	/* go to the REM to emulate a single instruction */
665	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
666	}
667
668
669	/**
670	* Handle a trap (\#PF or \#GP) in patch code
671	*
672	* @returns VBox status code suitable for EM.
673	* @param pVM The cross context VM structure.
674	* @param pVCpu The cross context virtual CPU structure.
675	* @param pCtx Pointer to the guest CPU context.
676	* @param gcret GC return code.
677	*/
678	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int gcret)
679	{
680	uint8_t u8TrapNo;
681	int rc;
682	TRPMEVENT enmType;
683	RTGCUINT uErrorCode;
684	RTGCUINTPTR uCR2;
685
686	Assert(PATMIsPatchGCAddr(pVM, pCtx->eip));
687
688	if (gcret == VINF_PATM_PATCH_INT3)
689	{
690	u8TrapNo = 3;
691	uCR2 = 0;
692	uErrorCode = 0;
693	}
694	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
695	{
696	/* No active trap in this case. Kind of ugly. */
697	u8TrapNo = X86_XCPT_GP;
698	uCR2 = 0;
699	uErrorCode = 0;
700	}
701	else
702	{
703	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
704	if (RT_FAILURE(rc))
705	{
706	AssertReleaseMsgFailed(("emR3RawPatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
707	return rc;
708	}
709	/* Reset the trap as we'll execute the original instruction again. */
710	TRPMResetTrap(pVCpu);
711	}
712
713	/*
714	* Deal with traps inside patch code.
715	* (This code won't run outside GC.)
716	*/
717	if (u8TrapNo != 1)
718	{
719	#ifdef LOG_ENABLED
720	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "Trap in patch code");
721	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patch code");
722
723	DISCPUSTATE Cpu;
724	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->eip, &Cpu, "Patch code: ");
725	if ( RT_SUCCESS(rc)
726	&& Cpu.pCurInstr->uOpcode == OP_IRET)
727	{
728	uint32_t eip, selCS, uEFlags;
729
730	/* Iret crashes are bad as we have already changed the flags on the stack */
731	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pCtx->esp, 4);
732	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pCtx->esp+4, 4);
733	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pCtx->esp+8, 4);
734	if (rc == VINF_SUCCESS)
735	{
736	if ( (uEFlags & X86_EFL_VM)
737	\|\| (selCS & X86_SEL_RPL) == 3)
738	{
739	uint32_t selSS, esp;
740
741	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pCtx->esp + 12, 4);
742	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pCtx->esp + 16, 4);
743
744	if (uEFlags & X86_EFL_VM)
745	{
746	uint32_t selDS, selES, selFS, selGS;
747	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pCtx->esp + 20, 4);
748	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pCtx->esp + 24, 4);
749	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pCtx->esp + 28, 4);
750	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pCtx->esp + 32, 4);
751	if (rc == VINF_SUCCESS)
752	{
753	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
754	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
755	}
756	}
757	else
758	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
759	}
760	else
761	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
762	}
763	}
764	#endif /* LOG_ENABLED */
765	Log(("emR3RawPatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
766	pCtx->eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pCtx->cr0));
767
768	RTGCPTR uNewEip;
769	rc = PATMR3HandleTrap(pVM, pCtx, pCtx->eip, &uNewEip);
770	switch (rc)
771	{
772	/*
773	* Execute the faulting instruction.
774	*/
775	case VINF_SUCCESS:
776	{
777	/** @todo execute a whole block */
778	Log(("emR3RawPatchTrap: Executing faulting instruction at new address %RGv\n", uNewEip));
779	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
780	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
781
782	pCtx->eip = uNewEip;
783	AssertRelease(pCtx->eip);
784
785	if (pCtx->eflags.Bits.u1IF)
786	{
787	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
788	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
789	*/
790	if ( u8TrapNo == X86_XCPT_GP
791	&& PATMIsInt3Patch(pVM, pCtx->eip, NULL, NULL))
792	{
793	/** @todo move to PATMR3HandleTrap */
794	Log(("Possible Windows XP iret fault at %08RX32\n", pCtx->eip));
795	PATMR3RemovePatch(pVM, pCtx->eip);
796	}
797
798	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
799	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
800
801	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
802	/* Interrupts are enabled; just go back to the original instruction.
803	return VINF_SUCCESS; */
804	}
805	return VINF_EM_RESCHEDULE_REM;
806	}
807
808	/*
809	* One instruction.
810	*/
811	case VINF_PATCH_EMULATE_INSTR:
812	Log(("emR3RawPatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
813	uNewEip, pCtx->eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
814	pCtx->eip = uNewEip;
815	AssertRelease(pCtx->eip);
816	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
817
818	/*
819	* The patch was disabled, hand it to the REM.
820	*/
821	case VERR_PATCH_DISABLED:
822	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
823	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
824	pCtx->eip = uNewEip;
825	AssertRelease(pCtx->eip);
826
827	if (pCtx->eflags.Bits.u1IF)
828	{
829	/*
830	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
831	*/
832	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
833	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
834	}
835	return VINF_EM_RESCHEDULE_REM;
836
837	/* Force continued patch exection; usually due to write monitored stack. */
838	case VINF_PATCH_CONTINUE:
839	return VINF_SUCCESS;
840
841	/*
842	* Anything else is fatal.
843	*/
844	default:
845	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
846	return VERR_IPE_UNEXPECTED_STATUS;
847	}
848	}
849	return VINF_SUCCESS;
850	}
851
852
853	/**
854	* Handle a privileged instruction.
855	*
856	* @returns VBox status code suitable for EM.
857	* @param pVM The cross context VM structure.
858	* @param pVCpu The cross context virtual CPU structure.
859	*/
860	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
861	{
862	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
863
864	Assert(!pCtx->eflags.Bits.u1VM);
865
866	if (PATMIsEnabled(pVM))
867	{
868	/*
869	* Check if in patch code.
870	*/
871	if (PATMR3IsInsidePatchJump(pVM, pCtx->eip, NULL))
872	{
873	#ifdef LOG_ENABLED
874	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
875	#endif
876	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pCtx->eip));
877	return VERR_EM_RAW_PATCH_CONFLICT;
878	}
879	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
880	&& !pCtx->eflags.Bits.u1VM
881	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
882	{
883	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->eip),
884	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
885	if (RT_SUCCESS(rc))
886	{
887	#ifdef LOG_ENABLED
888	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
889	#endif
890	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched privileged instruction");
891	return VINF_SUCCESS;
892	}
893	}
894	}
895
896	#ifdef LOG_ENABLED
897	if (!PATMIsPatchGCAddr(pVM, pCtx->eip))
898	{
899	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
900	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
901	}
902	#endif
903
904	/*
905	* Instruction statistics and logging.
906	*/
907	DISCPUSTATE Cpu;
908	int rc;
909
910	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, pCtx, pCtx->rip, &Cpu, "PRIV: ");
911	if (RT_SUCCESS(rc))
912	{
913	#ifdef VBOX_WITH_STATISTICS
914	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
915	switch (Cpu.pCurInstr->uOpcode)
916	{
917	case OP_INVLPG:
918	STAM_COUNTER_INC(&pStats->StatInvlpg);
919	break;
920	case OP_IRET:
921	STAM_COUNTER_INC(&pStats->StatIret);
922	break;
923	case OP_CLI:
924	STAM_COUNTER_INC(&pStats->StatCli);
925	emR3RecordCli(pVM, pVCpu, pCtx->rip);
926	break;
927	case OP_STI:
928	STAM_COUNTER_INC(&pStats->StatSti);
929	break;
930	case OP_INSB:
931	case OP_INSWD:
932	case OP_IN:
933	case OP_OUTSB:
934	case OP_OUTSWD:
935	case OP_OUT:
936	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
937	break;
938
939	case OP_MOV_CR:
940	if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
941	{
942	//read
943	Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
944	Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
945	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
946	}
947	else
948	{
949	//write
950	Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
951	Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
952	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
953	}
954	break;
955
956	case OP_MOV_DR:
957	STAM_COUNTER_INC(&pStats->StatMovDRx);
958	break;
959	case OP_LLDT:
960	STAM_COUNTER_INC(&pStats->StatMovLldt);
961	break;
962	case OP_LIDT:
963	STAM_COUNTER_INC(&pStats->StatMovLidt);
964	break;
965	case OP_LGDT:
966	STAM_COUNTER_INC(&pStats->StatMovLgdt);
967	break;
968	case OP_SYSENTER:
969	STAM_COUNTER_INC(&pStats->StatSysEnter);
970	break;
971	case OP_SYSEXIT:
972	STAM_COUNTER_INC(&pStats->StatSysExit);
973	break;
974	case OP_SYSCALL:
975	STAM_COUNTER_INC(&pStats->StatSysCall);
976	break;
977	case OP_SYSRET:
978	STAM_COUNTER_INC(&pStats->StatSysRet);
979	break;
980	case OP_HLT:
981	STAM_COUNTER_INC(&pStats->StatHlt);
982	break;
983	default:
984	STAM_COUNTER_INC(&pStats->StatMisc);
985	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
986	break;
987	}
988	#endif /* VBOX_WITH_STATISTICS */
989	if ( (pCtx->ss.Sel & X86_SEL_RPL) == 0
990	&& !pCtx->eflags.Bits.u1VM
991	&& CPUMGetGuestCodeBits(pVCpu) == 32)
992	{
993	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
994	switch (Cpu.pCurInstr->uOpcode)
995	{
996	case OP_CLI:
997	pCtx->eflags.u32 &= ~X86_EFL_IF;
998	Assert(Cpu.cbInstr == 1);
999	pCtx->rip += Cpu.cbInstr;
1000	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1001	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
1002
1003	case OP_STI:
1004	pCtx->eflags.u32 \|= X86_EFL_IF;
1005	EMSetInhibitInterruptsPC(pVCpu, pCtx->rip + Cpu.cbInstr);
1006	Assert(Cpu.cbInstr == 1);
1007	pCtx->rip += Cpu.cbInstr;
1008	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1009	return VINF_SUCCESS;
1010
1011	case OP_HLT:
1012	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1013	{
1014	PATMTRANSSTATE enmState;
1015	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->eip, &enmState);
1016
1017	if (enmState == PATMTRANS_OVERWRITTEN)
1018	{
1019	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1020	Assert(rc == VERR_PATCH_DISABLED);
1021	/* Conflict detected, patch disabled */
1022	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pCtx->eip));
1023
1024	enmState = PATMTRANS_SAFE;
1025	}
1026
1027	/* The translation had better be successful. Otherwise we can't recover. */
1028	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pCtx->eip));
1029	if (enmState != PATMTRANS_OVERWRITTEN)
1030	pCtx->eip = pOrgInstrGC;
1031	}
1032	/* no break; we could just return VINF_EM_HALT here */
1033	RT_FALL_THRU();
1034
1035	case OP_MOV_CR:
1036	case OP_MOV_DR:
1037	#ifdef LOG_ENABLED
1038	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1039	{
1040	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
1041	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
1042	}
1043	#endif
1044
1045	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(pCtx), 0, EMCODETYPE_SUPERVISOR));
1046	if (RT_SUCCESS(rc))
1047	{
1048	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1049
1050	if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1051	&& Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1052	)
1053	{
1054	/* Deal with CR0 updates inside patch code that force
1055	* us to go to the recompiler.
1056	*/
1057	if ( PATMIsPatchGCAddr(pVM, pCtx->rip)
1058	&& (pCtx->cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1059	{
1060	PATMTRANSSTATE enmState;
1061	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pCtx->rip, &enmState);
1062
1063	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pCtx->cr0, pCtx->rip, pOrgInstrGC, enmState));
1064	if (enmState == PATMTRANS_OVERWRITTEN)
1065	{
1066	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1067	Assert(rc == VERR_PATCH_DISABLED);
1068	/* Conflict detected, patch disabled */
1069	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pCtx->rip));
1070	enmState = PATMTRANS_SAFE;
1071	}
1072	/* The translation had better be successful. Otherwise we can't recover. */
1073	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pCtx->rip));
1074	if (enmState != PATMTRANS_OVERWRITTEN)
1075	pCtx->rip = pOrgInstrGC;
1076	}
1077
1078	/* Reschedule is necessary as the execution/paging mode might have changed. */
1079	return VINF_EM_RESCHEDULE;
1080	}
1081	return rc; /* can return VINF_EM_HALT as well. */
1082	}
1083	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1084	break; /* fall back to the recompiler */
1085	}
1086	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1087	}
1088	}
1089
1090	if (PATMIsPatchGCAddr(pVM, pCtx->eip))
1091	return emR3RawPatchTrap(pVM, pVCpu, pCtx, VINF_PATM_PATCH_TRAP_GP);
1092
1093	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
1094	}
1095
1096
1097	/**
1098	* Update the forced rawmode execution modifier.
1099	*
1100	* This function is called when we're returning from the raw-mode loop(s). If we're
1101	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1102	* if not in patch code, the flag will be cleared.
1103	*
1104	* We should never interrupt patch code while it's being executed. Cli patches can
1105	* contain big code blocks, but they are always executed with IF=0. Other patches
1106	* replace single instructions and should be atomic.
1107	*
1108	* @returns Updated rc.
1109	*
1110	* @param pVM The cross context VM structure.
1111	* @param pVCpu The cross context virtual CPU structure.
1112	* @param pCtx Pointer to the guest CPU context.
1113	* @param rc The result code.
1114	*/
1115	int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx, int rc)
1116	{
1117	if (PATMIsPatchGCAddr(pVM, pCtx->eip)) /** @todo check cs selector base/type */
1118	{
1119	/* ignore reschedule attempts. */
1120	switch (rc)
1121	{
1122	case VINF_EM_RESCHEDULE:
1123	case VINF_EM_RESCHEDULE_REM:
1124	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1125	rc = VINF_SUCCESS;
1126	break;
1127	}
1128	pVCpu->em.s.fForceRAW = true;
1129	}
1130	else
1131	pVCpu->em.s.fForceRAW = false;
1132	return rc;
1133	}
1134
1135
1136	/**
1137	* Check for pending raw actions
1138	*
1139	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1140	* EM statuses.
1141	* @param pVM The cross context VM structure.
1142	* @param pVCpu The cross context virtual CPU structure.
1143	*/
1144	VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1145	{
1146	int rc = emR3RawForcedActions(pVM, pVCpu, pVCpu->em.s.pCtx);
1147	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1148	return rc;
1149	}
1150
1151
1152	/**
1153	* Process raw-mode specific forced actions.
1154	*
1155	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1156	*
1157	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1158	* EM statuses.
1159	* @param pVM The cross context VM structure.
1160	* @param pVCpu The cross context virtual CPU structure.
1161	* @param pCtx Pointer to the guest CPU context.
1162	*/
1163	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
1164	{
1165	/*
1166	* Note that the order is vitally important!
1167	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1168	*/
1169	VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1170
1171	/*
1172	* Sync selector tables.
1173	*/
1174	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1175	{
1176	VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1177	if (rcStrict != VINF_SUCCESS)
1178	return VBOXSTRICTRC_TODO(rcStrict);
1179	}
1180
1181	/*
1182	* Sync IDT.
1183	*
1184	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1185	* and PGMShwModifyPage, so we're in for trouble if for instance a
1186	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1187	*/
1188	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1189	{
1190	if ( VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1191	&& EMIsRawRing0Enabled(pVM)
1192	&& CSAMIsEnabled(pVM))
1193	{
1194	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1195	if (RT_FAILURE(rc))
1196	return rc;
1197	}
1198
1199	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1200	if (RT_FAILURE(rc))
1201	return rc;
1202	}
1203
1204	/*
1205	* Sync TSS.
1206	*/
1207	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1208	{
1209	int rc = SELMR3SyncTSS(pVM, pVCpu);
1210	if (RT_FAILURE(rc))
1211	return rc;
1212	}
1213
1214	/*
1215	* Sync page directory.
1216	*/
1217	if (VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1218	{
1219	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1220	int rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1221	if (RT_FAILURE(rc))
1222	return rc == VERR_PGM_NO_HYPERVISOR_ADDRESS ? VINF_EM_RESCHEDULE_REM : rc;
1223
1224	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1225
1226	/* Prefetch pages for EIP and ESP. */
1227	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1228	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(pCtx), pCtx->rip));
1229	if (rc == VINF_SUCCESS)
1230	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(pCtx), pCtx->rsp));
1231	if (rc != VINF_SUCCESS)
1232	{
1233	if (rc != VINF_PGM_SYNC_CR3)
1234	{
1235	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1236	return rc;
1237	}
1238	rc = PGMSyncCR3(pVCpu, pCtx->cr0, pCtx->cr3, pCtx->cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1239	if (RT_FAILURE(rc))
1240	return rc;
1241	}
1242	/** @todo maybe prefetch the supervisor stack page as well */
1243	Assert(!VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1244	}
1245
1246	/*
1247	* Allocate handy pages (just in case the above actions have consumed some pages).
1248	*/
1249	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1250	{
1251	int rc = PGMR3PhysAllocateHandyPages(pVM);
1252	if (RT_FAILURE(rc))
1253	return rc;
1254	}
1255
1256	/*
1257	* Check whether we're out of memory now.
1258	*
1259	* This may stem from some of the above actions or operations that has been executed
1260	* since we ran FFs. The allocate handy pages must for instance always be followed by
1261	* this check.
1262	*/
1263	if (VM_FF_IS_PENDING(pVM, VM_FF_PGM_NO_MEMORY))
1264	return VINF_EM_NO_MEMORY;
1265
1266	return VINF_SUCCESS;
1267	}
1268
1269
1270	/**
1271	* Executes raw code.
1272	*
1273	* This function contains the raw-mode version of the inner
1274	* execution loop (the outer loop being in EMR3ExecuteVM()).
1275	*
1276	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1277	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1278	*
1279	* @param pVM The cross context VM structure.
1280	* @param pVCpu The cross context virtual CPU structure.
1281	* @param pfFFDone Where to store an indicator telling whether or not
1282	* FFs were done before returning.
1283	*/
1284	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1285	{
1286	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1287
1288	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1289	PCPUMCTX pCtx = pVCpu->em.s.pCtx;
1290	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pCtx->cs.Sel, pCtx->eip));
1291	pVCpu->em.s.fForceRAW = false;
1292	*pfFFDone = false;
1293
1294
1295	/*
1296	*
1297	* Spin till we get a forced action or raw mode status code resulting in
1298	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1299	*
1300	*/
1301	for (;;)
1302	{
1303	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1304
1305	/*
1306	* Check various preconditions.
1307	*/
1308	#ifdef VBOX_STRICT
1309	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 3 \|\| (pCtx->ss.Sel & X86_SEL_RPL) == 0
1310	\|\| (EMIsRawRing1Enabled(pVM) && (pCtx->ss.Sel & X86_SEL_RPL) == 1));
1311	AssertMsg( (pCtx->eflags.u32 & X86_EFL_IF)
1312	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pCtx->eip),
1313	("Tried to execute code with IF at EIP=%08x!\n", pCtx->eip));
1314	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1315	&& PGMMapHasConflicts(pVM))
1316	{
1317	PGMMapCheck(pVM);
1318	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1319	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1320	}
1321	#endif /* VBOX_STRICT */
1322
1323	/*
1324	* Process high priority pre-execution raw-mode FFs.
1325	*/
1326	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1327	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1328	{
1329	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1330	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1331	if (rc != VINF_SUCCESS)
1332	break;
1333	}
1334
1335	/*
1336	* If we're going to execute ring-0 code, the guest state needs to
1337	* be modified a bit and some of the state components (IF, SS/CS RPL,
1338	* and perhaps EIP) needs to be stored with PATM.
1339	*/
1340	rc = CPUMRawEnter(pVCpu);
1341	if (rc != VINF_SUCCESS)
1342	{
1343	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1344	break;
1345	}
1346
1347	/*
1348	* Scan code before executing it. Don't bother with user mode or V86 code
1349	*/
1350	if ( (pCtx->ss.Sel & X86_SEL_RPL) <= 1
1351	&& !pCtx->eflags.Bits.u1VM
1352	&& !PATMIsPatchGCAddr(pVM, pCtx->eip))
1353	{
1354	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1355	CSAMR3CheckCodeEx(pVM, pCtx, pCtx->eip);
1356	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1357	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1358	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1359	{
1360	rc = emR3RawForcedActions(pVM, pVCpu, pCtx);
1361	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1362	if (rc != VINF_SUCCESS)
1363	{
1364	rc = CPUMRawLeave(pVCpu, rc);
1365	break;
1366	}
1367	}
1368	}
1369
1370	#ifdef LOG_ENABLED
1371	/*
1372	* Log important stuff before entering GC.
1373	*/
1374	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1375	if (pCtx->eflags.Bits.u1VM)
1376	Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1377	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 1)
1378	Log(("RR0: %x:%08x ESP=%x:%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n",
1379	pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, CPUMRawGetEFlags(pVCpu), !!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF,
1380	pGCState->uVMFlags, pGCState->fPIF, (pCtx->ss.Sel & X86_SEL_RPL), CSAMIsPageScanned(pVM, (RTGCPTR)pCtx->eip)));
1381	# ifdef VBOX_WITH_RAW_RING1
1382	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 2)
1383	Log(("RR1: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x CPL=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, (pCtx->ss.Sel & X86_SEL_RPL)));
1384	# endif
1385	else if ((pCtx->ss.Sel & X86_SEL_RPL) == 3)
1386	Log(("RR3: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x\n", pCtx->cs.Sel, pCtx->eip, pCtx->ss.Sel, pCtx->esp, pCtx->eflags.Bits.u1IF, pGCState->uVMFlags));
1387	#endif /* LOG_ENABLED */
1388
1389
1390
1391	/*
1392	* Execute the code.
1393	*/
1394	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1395	if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1396	{
1397	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1398	VBOXVMM_EM_RAW_RUN_PRE(pVCpu, pCtx);
1399	rc = VMMR3RawRunGC(pVM, pVCpu);
1400	VBOXVMM_EM_RAW_RUN_RET(pVCpu, pCtx, rc);
1401	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1402	}
1403	else
1404	{
1405	/* Give up this time slice; virtual time continues */
1406	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1407	RTThreadSleep(5);
1408	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1409	rc = VINF_SUCCESS;
1410	}
1411	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1412
1413	LogFlow(("RR%u-E: %08x ESP=%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d\n",
1414	(pCtx->ss.Sel & X86_SEL_RPL), pCtx->eip, pCtx->esp, CPUMRawGetEFlags(pVCpu),
1415	!!(pGCState->uVMFlags & X86_EFL_IF), pCtx->eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1416	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1417
1418
1419
1420	/*
1421	* Restore the real CPU state and deal with high priority post
1422	* execution FFs before doing anything else.
1423	*/
1424	rc = CPUMRawLeave(pVCpu, rc);
1425	VMCPU_FF_CLEAR(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1426	if ( VM_FF_IS_PENDING(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1427	\|\| VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1428	rc = emR3HighPriorityPostForcedActions(pVM, pVCpu, rc);
1429
1430	#ifdef VBOX_STRICT
1431	/*
1432	* Assert TSS consistency & rc vs patch code.
1433	*/
1434	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1435	&& EMIsRawRing0Enabled(pVM))
1436	SELMR3CheckTSS(pVM);
1437	switch (rc)
1438	{
1439	case VINF_SUCCESS:
1440	case VINF_EM_RAW_INTERRUPT:
1441	case VINF_PATM_PATCH_TRAP_PF:
1442	case VINF_PATM_PATCH_TRAP_GP:
1443	case VINF_PATM_PATCH_INT3:
1444	case VINF_PATM_CHECK_PATCH_PAGE:
1445	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1446	case VINF_EM_RAW_GUEST_TRAP:
1447	case VINF_EM_RESCHEDULE_RAW:
1448	break;
1449
1450	default:
1451	if (PATMIsPatchGCAddr(pVM, pCtx->eip) && !(pCtx->eflags.u32 & X86_EFL_TF))
1452	LogIt(0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1453	break;
1454	}
1455	/*
1456	* Let's go paranoid!
1457	*/
1458	if ( !VMCPU_FF_IS_PENDING(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1459	&& PGMMapHasConflicts(pVM))
1460	{
1461	PGMMapCheck(pVM);
1462	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1463	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1464	}
1465	#endif /* VBOX_STRICT */
1466
1467	/*
1468	* Process the returned status code.
1469	*/
1470	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1471	{
1472	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1473	break;
1474	}
1475	rc = emR3RawHandleRC(pVM, pVCpu, pCtx, rc);
1476	if (rc != VINF_SUCCESS)
1477	{
1478	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1479	if (rc != VINF_SUCCESS)
1480	{
1481	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1482	break;
1483	}
1484	}
1485
1486	/*
1487	* Check and execute forced actions.
1488	*/
1489	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1490	TMTimerPollVoid(pVM, pVCpu);
1491	#endif
1492	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1493	if ( VM_FF_IS_PENDING(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1494	\|\| VMCPU_FF_IS_PENDING(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1495	{
1496	Assert(pCtx->eflags.Bits.u1VM \|\| (pCtx->ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2U : 1U));
1497
1498	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1499	rc = emR3ForcedActions(pVM, pVCpu, rc);
1500	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1501	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1502	if ( rc != VINF_SUCCESS
1503	&& rc != VINF_EM_RESCHEDULE_RAW)
1504	{
1505	rc = emR3RawUpdateForceFlag(pVM, pVCpu, pCtx, rc);
1506	if (rc != VINF_SUCCESS)
1507	{
1508	*pfFFDone = true;
1509	break;
1510	}
1511	}
1512	}
1513	}
1514
1515	/*
1516	* Return to outer loop.
1517	*/
1518	#if defined(LOG_ENABLED) && defined(DEBUG)
1519	RTLogFlush(NULL);
1520	#endif
1521	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1522	return rc;
1523	}
1524

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 69175

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