EMRaw.cpp@ 78043

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1	/* $Id: EMRaw.cpp 76553 2019-01-01 01:45:53Z vboxsync $ */
2	/** @file
3	* EM - Execution Monitor / Manager - software virtualization
4	*/
5
6	/*
7	* Copyright (C) 2006-2019 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*********************************************************************************************************************************
20	* Header Files *
21	*********************************************************************************************************************************/
22	#define LOG_GROUP LOG_GROUP_EM
23	#define VMCPU_INCL_CPUM_GST_CTX
24	#include <VBox/vmm/em.h>
25	#include <VBox/vmm/vmm.h>
26	#include <VBox/vmm/patm.h>
27	#include <VBox/vmm/csam.h>
28	#include <VBox/vmm/selm.h>
29	#include <VBox/vmm/trpm.h>
30	#include <VBox/vmm/iem.h>
31	#include <VBox/vmm/iom.h>
32	#include <VBox/vmm/dbgf.h>
33	#include <VBox/vmm/pgm.h>
34	#ifdef VBOX_WITH_REM
35	# include <VBox/vmm/rem.h>
36	#endif
37	#include <VBox/vmm/tm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/ssm.h>
40	#include <VBox/vmm/pdmapi.h>
41	#include <VBox/vmm/pdmcritsect.h>
42	#include <VBox/vmm/pdmqueue.h>
43	#include <VBox/vmm/patm.h>
44	#include "EMInternal.h"
45	#include <VBox/vmm/vm.h>
46	#include <VBox/vmm/gim.h>
47	#include <VBox/vmm/cpumdis.h>
48	#include <VBox/dis.h>
49	#include <VBox/disopcode.h>
50	#include <VBox/vmm/dbgf.h>
51	#include "VMMTracing.h"
52
53	#include <VBox/err.h>
54	#include <VBox/log.h>
55	#include <iprt/asm.h>
56	#include <iprt/string.h>
57	#include <iprt/stream.h>
58
59
60
61	/*********************************************************************************************************************************
62	* Internal Functions *
63	*********************************************************************************************************************************/
64	static int emR3RawHandleRC(PVM pVM, PVMCPU pVCpu, int rc);
65	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu);
66	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC = VINF_SUCCESS);
67	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu);
68	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, int gcret);
69	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu);
70	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu);
71	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu);
72	static int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, int rc);
73
74	#define EMHANDLERC_WITH_PATM
75	#define emR3ExecuteInstruction emR3RawExecuteInstruction
76	#define emR3ExecuteIOInstruction emR3RawExecuteIOInstruction
77	#include "EMHandleRCTmpl.h"
78
79
80
81	#ifdef VBOX_WITH_STATISTICS
82	/**
83	* Just a braindead function to keep track of cli addresses.
84	* @param pVM The cross context VM structure.
85	* @param pVCpu The cross context virtual CPU structure.
86	* @param GCPtrInstr The EIP of the cli instruction.
87	*/
88	static void emR3RecordCli(PVM pVM, PVMCPU pVCpu, RTGCPTR GCPtrInstr)
89	{
90	PCLISTAT pRec;
91
92	pRec = (PCLISTAT)RTAvlGCPtrGet(&pVCpu->em.s.pCliStatTree, GCPtrInstr);
93	if (!pRec)
94	{
95	/* New cli instruction; insert into the tree. */
96	pRec = (PCLISTAT)MMR3HeapAllocZ(pVM, MM_TAG_EM, sizeof(*pRec));
97	Assert(pRec);
98	if (!pRec)
99	return;
100	pRec->Core.Key = GCPtrInstr;
101
102	char szCliStatName[32];
103	RTStrPrintf(szCliStatName, sizeof(szCliStatName), "/EM/Cli/0x%RGv", GCPtrInstr);
104	STAM_REG(pVM, &pRec->Counter, STAMTYPE_COUNTER, szCliStatName, STAMUNIT_OCCURENCES, "Number of times cli was executed.");
105
106	bool fRc = RTAvlGCPtrInsert(&pVCpu->em.s.pCliStatTree, &pRec->Core);
107	Assert(fRc); NOREF(fRc);
108	}
109	STAM_COUNTER_INC(&pRec->Counter);
110	STAM_COUNTER_INC(&pVCpu->em.s.StatTotalClis);
111	}
112	#endif /* VBOX_WITH_STATISTICS */
113
114
115
116	/**
117	* Resumes executing hypervisor after a debug event.
118	*
119	* This is kind of special since our current guest state is
120	* potentially out of sync.
121	*
122	* @returns VBox status code.
123	* @param pVM The cross context VM structure.
124	* @param pVCpu The cross context virtual CPU structure.
125	*/
126	int emR3RawResumeHyper(PVM pVM, PVMCPU pVCpu)
127	{
128	int rc;
129	Assert(pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER);
130	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags));
131
132	/*
133	* Resume execution.
134	*/
135	CPUMRawEnter(pVCpu);
136	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_RF);
137	rc = VMMR3ResumeHyper(pVM, pVCpu);
138	Log(("emR3RawResumeHyper: cs:eip=%RTsel:%RGr efl=%RGr - returned from GC with rc=%Rrc\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags, rc));
139	rc = CPUMRawLeave(pVCpu, rc);
140	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
141
142	/*
143	* Deal with the return code.
144	*/
145	rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
146	rc = emR3RawHandleRC(pVM, pVCpu, rc);
147	rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
148	return rc;
149	}
150
151
152	/**
153	* Steps rawmode.
154	*
155	* @returns VBox status code.
156	* @param pVM The cross context VM structure.
157	* @param pVCpu The cross context virtual CPU structure.
158	*/
159	int emR3RawStep(PVM pVM, PVMCPU pVCpu)
160	{
161	Assert( pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER
162	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_RAW
163	\|\| pVCpu->em.s.enmState == EMSTATE_DEBUG_GUEST_REM);
164	int rc;
165	bool fGuest = pVCpu->em.s.enmState != EMSTATE_DEBUG_HYPER;
166	#ifndef DEBUG_sander
167	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
168	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu)));
169	#endif
170	if (fGuest)
171	{
172	/*
173	* Check vital forced actions, but ignore pending interrupts and timers.
174	*/
175	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
176	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
177	{
178	rc = emR3RawForcedActions(pVM, pVCpu);
179	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
180	if (rc != VINF_SUCCESS)
181	return rc;
182	}
183
184	/*
185	* Set flags for single stepping.
186	*/
187	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
188	}
189	else
190	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) \| X86_EFL_TF \| X86_EFL_RF);
191
192	/*
193	* Single step.
194	* We do not start time or anything, if anything we should just do a few nanoseconds.
195	*/
196	CPUMRawEnter(pVCpu);
197	do
198	{
199	if (pVCpu->em.s.enmState == EMSTATE_DEBUG_HYPER)
200	rc = VMMR3ResumeHyper(pVM, pVCpu);
201	else
202	rc = VMMR3RawRunGC(pVM, pVCpu);
203	#ifndef DEBUG_sander
204	Log(("emR3RawStep: cs:eip=%RTsel:%RGr efl=%RGr - GC rc %Rrc\n", fGuest ? CPUMGetGuestCS(pVCpu) : CPUMGetHyperCS(pVCpu),
205	fGuest ? CPUMGetGuestEIP(pVCpu) : CPUMGetHyperEIP(pVCpu), fGuest ? CPUMGetGuestEFlags(pVCpu) : CPUMGetHyperEFlags(pVCpu), rc));
206	#endif
207	} while ( rc == VINF_SUCCESS
208	\|\| rc == VINF_EM_RAW_INTERRUPT);
209	rc = CPUMRawLeave(pVCpu, rc);
210	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
211
212	/*
213	* Make sure the trap flag is cleared.
214	* (Too bad if the guest is trying to single step too.)
215	*/
216	if (fGuest)
217	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
218	else
219	CPUMSetHyperEFlags(pVCpu, CPUMGetHyperEFlags(pVCpu) & ~X86_EFL_TF);
220
221	/*
222	* Deal with the return codes.
223	*/
224	rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
225	rc = emR3RawHandleRC(pVM, pVCpu, rc);
226	rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
227	return rc;
228	}
229
230
231	#ifdef DEBUG
232
233
234	int emR3SingleStepExecRaw(PVM pVM, PVMCPU pVCpu, uint32_t cIterations)
235	{
236	int rc = VINF_SUCCESS;
237	EMSTATE enmOldState = pVCpu->em.s.enmState;
238	pVCpu->em.s.enmState = EMSTATE_DEBUG_GUEST_RAW;
239
240	Log(("Single step BEGIN:\n"));
241	for (uint32_t i = 0; i < cIterations; i++)
242	{
243	DBGFR3PrgStep(pVCpu);
244	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "RSS");
245	rc = emR3RawStep(pVM, pVCpu);
246	if ( rc != VINF_SUCCESS
247	&& rc != VINF_EM_DBG_STEPPED)
248	break;
249	}
250	Log(("Single step END: rc=%Rrc\n", rc));
251	CPUMSetGuestEFlags(pVCpu, CPUMGetGuestEFlags(pVCpu) & ~X86_EFL_TF);
252	pVCpu->em.s.enmState = enmOldState;
253	return rc;
254	}
255
256	#endif /* DEBUG */
257
258
259	/**
260	* Executes one (or perhaps a few more) instruction(s).
261	*
262	* @returns VBox status code suitable for EM.
263	*
264	* @param pVM The cross context VM structure.
265	* @param pVCpu The cross context virtual CPU structure.
266	* @param rcGC GC return code
267	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
268	* instruction and prefix the log output with this text.
269	*/
270	#if defined(LOG_ENABLED) \|\| defined(DOXYGEN_RUNNING)
271	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC, const char *pszPrefix)
272	#else
273	static int emR3RawExecuteInstructionWorker(PVM pVM, PVMCPU pVCpu, int rcGC)
274	#endif
275	{
276	int rc;
277
278	#ifdef LOG_ENABLED
279	/*
280	* Disassemble the instruction if requested.
281	*/
282	if (pszPrefix)
283	{
284	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", pszPrefix);
285	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, pszPrefix);
286	}
287	#endif /* LOG_ENABLED */
288
289	/*
290	* PATM is making life more interesting.
291	* We cannot hand anything to REM which has an EIP inside patch code. So, we'll
292	* tell PATM there is a trap in this code and have it take the appropriate actions
293	* to allow us execute the code in REM.
294	*/
295	if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
296	{
297	Log(("emR3RawExecuteInstruction: In patch block. eip=%RRv\n", (RTRCPTR)pVCpu->cpum.GstCtx.eip));
298
299	RTGCPTR uNewEip;
300	rc = PATMR3HandleTrap(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &uNewEip);
301	switch (rc)
302	{
303	/*
304	* It's not very useful to emulate a single instruction and then go back to raw
305	* mode; just execute the whole block until IF is set again.
306	*/
307	case VINF_SUCCESS:
308	Log(("emR3RawExecuteInstruction: Executing instruction starting at new address %RGv IF=%d VMIF=%x\n",
309	uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
310	pVCpu->cpum.GstCtx.eip = uNewEip;
311	Assert(pVCpu->cpum.GstCtx.eip);
312
313	if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
314	{
315	/*
316	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
317	*/
318	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
319	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
320	}
321	else if (rcGC == VINF_PATM_PENDING_IRQ_AFTER_IRET)
322	{
323	/* special case: iret, that sets IF, detected a pending irq/event */
324	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIRET");
325	}
326	return VINF_EM_RESCHEDULE_REM;
327
328	/*
329	* One instruction.
330	*/
331	case VINF_PATCH_EMULATE_INSTR:
332	Log(("emR3RawExecuteInstruction: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
333	uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
334	pVCpu->cpum.GstCtx.eip = uNewEip;
335	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
336
337	/*
338	* The patch was disabled, hand it to the REM.
339	*/
340	case VERR_PATCH_DISABLED:
341	Log(("emR3RawExecuteInstruction: Disabled patch -> new eip %RGv IF=%d VMIF=%x\n",
342	uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
343	pVCpu->cpum.GstCtx.eip = uNewEip;
344	if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
345	{
346	/*
347	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
348	*/
349	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
350	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
351	}
352	return VINF_EM_RESCHEDULE_REM;
353
354	/* Force continued patch exection; usually due to write monitored stack. */
355	case VINF_PATCH_CONTINUE:
356	return VINF_SUCCESS;
357
358	default:
359	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap\n", rc));
360	return VERR_IPE_UNEXPECTED_STATUS;
361	}
362	}
363
364
365	/*
366	* Use IEM and fallback on REM if the functionality is missing.
367	* Once IEM gets mature enough, nothing should ever fall back.
368	*/
369	#define VBOX_WITH_FIRST_IEM_STEP_B
370	#if defined(VBOX_WITH_FIRST_IEM_STEP_B) \|\| !defined(VBOX_WITH_REM)
371	Log(("EMINS: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
372	STAM_PROFILE_START(&pVCpu->em.s.StatIEMEmu, a);
373	rc = VBOXSTRICTRC_TODO(IEMExecOne(pVCpu));
374	STAM_PROFILE_STOP(&pVCpu->em.s.StatIEMEmu, a);
375	if (RT_SUCCESS(rc))
376	{
377	if (rc == VINF_SUCCESS \|\| rc == VINF_EM_RESCHEDULE)
378	rc = VINF_EM_RESCHEDULE;
379	}
380	else if ( rc == VERR_IEM_ASPECT_NOT_IMPLEMENTED
381	\|\| rc == VERR_IEM_INSTR_NOT_IMPLEMENTED)
382	#endif
383	{
384	#ifdef VBOX_WITH_REM
385	STAM_PROFILE_START(&pVCpu->em.s.StatREMEmu, b);
386	# ifndef VBOX_WITH_FIRST_IEM_STEP_B
387	Log(("EMINS[rem]: %04x:%RGv RSP=%RGv\n", pVCpu->cpum.GstCtx.cs.Sel, (RTGCPTR)pVCpu->cpum.GstCtx.rip, (RTGCPTR)pVCpu->cpum.GstCtx.rsp));
388	//# elif defined(DEBUG_bird)
389	// AssertFailed();
390	# endif
391	EMRemLock(pVM);
392	/* Flush the recompiler TLB if the VCPU has changed. */
393	if (pVM->em.s.idLastRemCpu != pVCpu->idCpu)
394	CPUMSetChangedFlags(pVCpu, CPUM_CHANGED_ALL);
395	pVM->em.s.idLastRemCpu = pVCpu->idCpu;
396
397	rc = REMR3EmulateInstruction(pVM, pVCpu);
398	EMRemUnlock(pVM);
399	STAM_PROFILE_STOP(&pVCpu->em.s.StatREMEmu, b);
400	#else /* !VBOX_WITH_REM */
401	NOREF(pVM);
402	#endif /* !VBOX_WITH_REM */
403	}
404	return rc;
405	}
406
407
408	/**
409	* Executes one (or perhaps a few more) instruction(s).
410	* This is just a wrapper for discarding pszPrefix in non-logging builds.
411	*
412	* @returns VBox status code suitable for EM.
413	* @param pVM The cross context VM structure.
414	* @param pVCpu The cross context virtual CPU structure.
415	* @param pszPrefix Disassembly prefix. If not NULL we'll disassemble the
416	* instruction and prefix the log output with this text.
417	* @param rcGC GC return code
418	*/
419	DECLINLINE(int) emR3RawExecuteInstruction(PVM pVM, PVMCPU pVCpu, const char *pszPrefix, int rcGC)
420	{
421	#ifdef LOG_ENABLED
422	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC, pszPrefix);
423	#else
424	RT_NOREF_PV(pszPrefix);
425	return emR3RawExecuteInstructionWorker(pVM, pVCpu, rcGC);
426	#endif
427	}
428
429	/**
430	* Executes one (or perhaps a few more) IO instruction(s).
431	*
432	* @returns VBox status code suitable for EM.
433	* @param pVM The cross context VM structure.
434	* @param pVCpu The cross context virtual CPU structure.
435	*/
436	static int emR3RawExecuteIOInstruction(PVM pVM, PVMCPU pVCpu)
437	{
438	STAM_PROFILE_START(&pVCpu->em.s.StatIOEmu, a);
439	RT_NOREF_PV(pVM);
440
441	/* Hand it over to the interpreter. */
442	VBOXSTRICTRC rcStrict = IEMExecOne(pVCpu);
443	LogFlow(("emR3RawExecuteIOInstruction: %Rrc\n", VBOXSTRICTRC_VAL(rcStrict)));
444	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatIoIem);
445	STAM_PROFILE_STOP(&pVCpu->em.s.StatIOEmu, a);
446	return VBOXSTRICTRC_TODO(rcStrict);
447	}
448
449
450	/**
451	* Handle a guest context trap.
452	*
453	* @returns VBox status code suitable for EM.
454	* @param pVM The cross context VM structure.
455	* @param pVCpu The cross context virtual CPU structure.
456	*/
457	static int emR3RawGuestTrap(PVM pVM, PVMCPU pVCpu)
458	{
459	/*
460	* Get the trap info.
461	*/
462	uint8_t u8TrapNo;
463	TRPMEVENT enmType;
464	RTGCUINT uErrorCode;
465	RTGCUINTPTR uCR2;
466	int rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
467	if (RT_FAILURE(rc))
468	{
469	AssertReleaseMsgFailed(("No trap! (rc=%Rrc)\n", rc));
470	return rc;
471	}
472
473
474	#if 1 /* Experimental: Review, disable if it causes trouble. */
475	/*
476	* Handle traps in patch code first.
477	*
478	* We catch a few of these cases in RC before returning to R3 (#PF, #GP, #BP)
479	* but several traps isn't handled specially by TRPM in RC and we end up here
480	* instead. One example is #DE.
481	*/
482	uint32_t uCpl = CPUMGetGuestCPL(pVCpu);
483	if ( uCpl == 0
484	&& PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
485	{
486	LogFlow(("emR3RawGuestTrap: trap %#x in patch code; eip=%08x\n", u8TrapNo, pVCpu->cpum.GstCtx.eip));
487	return emR3RawPatchTrap(pVM, pVCpu, rc);
488	}
489	#endif
490
491	/*
492	* If the guest gate is marked unpatched, then we will check again if we can patch it.
493	* (This assumes that we've already tried and failed to dispatch the trap in
494	* RC for the gates that already has been patched. Which is true for most high
495	* volume traps, because these are handled specially, but not for odd ones like #DE.)
496	*/
497	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) == TRPM_INVALID_HANDLER)
498	{
499	CSAMR3CheckGates(pVM, u8TrapNo, 1);
500	Log(("emR3RawHandleRC: recheck gate %x -> valid=%d\n", u8TrapNo, TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER));
501
502	/* If it was successful, then we could go back to raw mode. */
503	if (TRPMR3GetGuestTrapHandler(pVM, u8TrapNo) != TRPM_INVALID_HANDLER)
504	{
505	/* Must check pending forced actions as our IDT or GDT might be out of sync. */
506	rc = EMR3CheckRawForcedActions(pVM, pVCpu);
507	AssertRCReturn(rc, rc);
508
509	TRPMERRORCODE enmError = uErrorCode != ~0U
510	? TRPM_TRAP_HAS_ERRORCODE
511	: TRPM_TRAP_NO_ERRORCODE;
512	rc = TRPMForwardTrap(pVCpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), u8TrapNo, uErrorCode, enmError, TRPM_TRAP, -1);
513	if (rc == VINF_SUCCESS /* Don't use RT_SUCCESS */)
514	{
515	TRPMResetTrap(pVCpu);
516	return VINF_EM_RESCHEDULE_RAW;
517	}
518	AssertMsg(rc == VINF_EM_RAW_GUEST_TRAP, ("%Rrc\n", rc));
519	}
520	}
521
522	/*
523	* Scan kernel code that traps; we might not get another chance.
524	*/
525	/** @todo move this up before the dispatching? */
526	if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) <= 1
527	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
528	{
529	Assert(!PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip));
530	CSAMR3CheckCodeEx(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip);
531	}
532
533	/*
534	* Trap specific handling.
535	*/
536	if (u8TrapNo == 6) /* (#UD) Invalid opcode. */
537	{
538	/*
539	* If MONITOR & MWAIT are supported, then interpret them here.
540	*/
541	DISCPUSTATE cpu;
542	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &cpu, "Guest Trap (#UD): ");
543	if ( RT_SUCCESS(rc)
544	&& (cpu.pCurInstr->uOpcode == OP_MONITOR \|\| cpu.pCurInstr->uOpcode == OP_MWAIT))
545	{
546	uint32_t u32Dummy, u32Features, u32ExtFeatures;
547	CPUMGetGuestCpuId(pVCpu, 1, 0, &u32Dummy, &u32Dummy, &u32ExtFeatures, &u32Features);
548	if (u32ExtFeatures & X86_CPUID_FEATURE_ECX_MONITOR)
549	{
550	rc = TRPMResetTrap(pVCpu);
551	AssertRC(rc);
552
553	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &cpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx),
554	0, EMCODETYPE_SUPERVISOR));
555	if (RT_SUCCESS(rc))
556	return rc;
557	return emR3RawExecuteInstruction(pVM, pVCpu, "Monitor: ");
558	}
559	}
560	}
561	else if (u8TrapNo == 13) /* (#GP) Privileged exception */
562	{
563	/*
564	* Handle I/O bitmap?
565	*/
566	/** @todo We're not supposed to be here with a false guest trap concerning
567	* I/O access. We can easily handle those in RC. */
568	DISCPUSTATE cpu;
569	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &cpu, "Guest Trap: ");
570	if ( RT_SUCCESS(rc)
571	&& (cpu.pCurInstr->fOpType & DISOPTYPE_PORTIO))
572	{
573	/*
574	* We should really check the TSS for the IO bitmap, but it's not like this
575	* lazy approach really makes things worse.
576	*/
577	rc = TRPMResetTrap(pVCpu);
578	AssertRC(rc);
579	return emR3RawExecuteInstruction(pVM, pVCpu, "IO Guest Trap: ");
580	}
581	}
582
583	#ifdef LOG_ENABLED
584	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "Guest trap");
585	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Guest trap");
586
587	/* Get guest page information. */
588	uint64_t fFlags = 0;
589	RTGCPHYS GCPhys = 0;
590	int rc2 = PGMGstGetPage(pVCpu, uCR2, &fFlags, &GCPhys);
591	Log(("emR3RawGuestTrap: cs:eip=%04x:%08x: trap=%02x err=%08x cr2=%08x cr0=%08x%s: Phys=%RGp fFlags=%08llx %s %s %s%s rc2=%d\n",
592	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pVCpu->cpum.GstCtx.cr0,
593	(enmType == TRPM_SOFTWARE_INT) ? " software" : "", GCPhys, fFlags,
594	fFlags & X86_PTE_P ? "P " : "NP", fFlags & X86_PTE_US ? "U" : "S",
595	fFlags & X86_PTE_RW ? "RW" : "R0", fFlags & X86_PTE_G ? " G" : "", rc2));
596	#endif
597
598	/*
599	* #PG has CR2.
600	* (Because of stuff like above we must set CR2 in a delayed fashion.)
601	*/
602	if (u8TrapNo == 14 /* #PG */)
603	pVCpu->cpum.GstCtx.cr2 = uCR2;
604
605	return VINF_EM_RESCHEDULE_REM;
606	}
607
608
609	/**
610	* Handle a ring switch trap.
611	* Need to do statistics and to install patches. The result is going to REM.
612	*
613	* @returns VBox status code suitable for EM.
614	* @param pVM The cross context VM structure.
615	* @param pVCpu The cross context virtual CPU structure.
616	*/
617	static int emR3RawRingSwitch(PVM pVM, PVMCPU pVCpu)
618	{
619	int rc;
620	DISCPUSTATE Cpu;
621
622	/*
623	* sysenter, syscall & callgate
624	*/
625	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &Cpu, "RSWITCH: ");
626	if (RT_SUCCESS(rc))
627	{
628	if (Cpu.pCurInstr->uOpcode == OP_SYSENTER)
629	{
630	if (pVCpu->cpum.GstCtx.SysEnter.cs != 0)
631	{
632	rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.eip),
633	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
634	if (RT_SUCCESS(rc))
635	{
636	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched sysenter instruction");
637	return VINF_EM_RESCHEDULE_RAW;
638	}
639	}
640	}
641
642	#ifdef VBOX_WITH_STATISTICS
643	switch (Cpu.pCurInstr->uOpcode)
644	{
645	case OP_SYSENTER:
646	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysEnter);
647	break;
648	case OP_SYSEXIT:
649	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysExit);
650	break;
651	case OP_SYSCALL:
652	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysCall);
653	break;
654	case OP_SYSRET:
655	STAM_COUNTER_INC(&pVCpu->em.s.CTX_SUFF(pStats)->StatSysRet);
656	break;
657	}
658	#endif
659	}
660	else
661	AssertRC(rc);
662
663	/* go to the REM to emulate a single instruction */
664	return emR3RawExecuteInstruction(pVM, pVCpu, "RSWITCH: ");
665	}
666
667
668	/**
669	* Handle a trap (\#PF or \#GP) in patch code
670	*
671	* @returns VBox status code suitable for EM.
672	* @param pVM The cross context VM structure.
673	* @param pVCpu The cross context virtual CPU structure.
674	* @param gcret GC return code.
675	*/
676	static int emR3RawPatchTrap(PVM pVM, PVMCPU pVCpu, int gcret)
677	{
678	uint8_t u8TrapNo;
679	int rc;
680	TRPMEVENT enmType;
681	RTGCUINT uErrorCode;
682	RTGCUINTPTR uCR2;
683
684	Assert(PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip));
685
686	if (gcret == VINF_PATM_PATCH_INT3)
687	{
688	u8TrapNo = 3;
689	uCR2 = 0;
690	uErrorCode = 0;
691	}
692	else if (gcret == VINF_PATM_PATCH_TRAP_GP)
693	{
694	/* No active trap in this case. Kind of ugly. */
695	u8TrapNo = X86_XCPT_GP;
696	uCR2 = 0;
697	uErrorCode = 0;
698	}
699	else
700	{
701	rc = TRPMQueryTrapAll(pVCpu, &u8TrapNo, &enmType, &uErrorCode, &uCR2, NULL /* pu8InstrLen */);
702	if (RT_FAILURE(rc))
703	{
704	AssertReleaseMsgFailed(("emR3RawPatchTrap: no trap! (rc=%Rrc) gcret=%Rrc\n", rc, gcret));
705	return rc;
706	}
707	/* Reset the trap as we'll execute the original instruction again. */
708	TRPMResetTrap(pVCpu);
709	}
710
711	/*
712	* Deal with traps inside patch code.
713	* (This code won't run outside GC.)
714	*/
715	if (u8TrapNo != 1)
716	{
717	#ifdef LOG_ENABLED
718	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "Trap in patch code");
719	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patch code");
720
721	DISCPUSTATE Cpu;
722	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &Cpu, "Patch code: ");
723	if ( RT_SUCCESS(rc)
724	&& Cpu.pCurInstr->uOpcode == OP_IRET)
725	{
726	uint32_t eip, selCS, uEFlags;
727
728	/* Iret crashes are bad as we have already changed the flags on the stack */
729	rc = PGMPhysSimpleReadGCPtr(pVCpu, &eip, pVCpu->cpum.GstCtx.esp, 4);
730	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selCS, pVCpu->cpum.GstCtx.esp+4, 4);
731	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &uEFlags, pVCpu->cpum.GstCtx.esp+8, 4);
732	if (rc == VINF_SUCCESS)
733	{
734	if ( (uEFlags & X86_EFL_VM)
735	\|\| (selCS & X86_SEL_RPL) == 3)
736	{
737	uint32_t selSS, esp;
738
739	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &esp, pVCpu->cpum.GstCtx.esp + 12, 4);
740	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selSS, pVCpu->cpum.GstCtx.esp + 16, 4);
741
742	if (uEFlags & X86_EFL_VM)
743	{
744	uint32_t selDS, selES, selFS, selGS;
745	rc = PGMPhysSimpleReadGCPtr(pVCpu, &selES, pVCpu->cpum.GstCtx.esp + 20, 4);
746	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selDS, pVCpu->cpum.GstCtx.esp + 24, 4);
747	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selFS, pVCpu->cpum.GstCtx.esp + 28, 4);
748	rc \|= PGMPhysSimpleReadGCPtr(pVCpu, &selGS, pVCpu->cpum.GstCtx.esp + 32, 4);
749	if (rc == VINF_SUCCESS)
750	{
751	Log(("Patch code: IRET->VM stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
752	Log(("Patch code: IRET->VM stack frame: DS=%04X ES=%04X FS=%04X GS=%04X\n", selDS, selES, selFS, selGS));
753	}
754	}
755	else
756	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x ss:esp=%04X:%08RX32\n", selCS, eip, uEFlags, selSS, esp));
757	}
758	else
759	Log(("Patch code: IRET stack frame: return address %04X:%08RX32 eflags=%08x\n", selCS, eip, uEFlags));
760	}
761	}
762	#endif /* LOG_ENABLED */
763	Log(("emR3RawPatchTrap: in patch: eip=%08x: trap=%02x err=%08x cr2=%08x cr0=%08x\n",
764	pVCpu->cpum.GstCtx.eip, u8TrapNo, uErrorCode, uCR2, (uint32_t)pVCpu->cpum.GstCtx.cr0));
765
766	RTGCPTR uNewEip;
767	rc = PATMR3HandleTrap(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip, &uNewEip);
768	switch (rc)
769	{
770	/*
771	* Execute the faulting instruction.
772	*/
773	case VINF_SUCCESS:
774	{
775	/** @todo execute a whole block */
776	Log(("emR3RawPatchTrap: Executing faulting instruction at new address %RGv\n", uNewEip));
777	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
778	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
779
780	pVCpu->cpum.GstCtx.eip = uNewEip;
781	AssertRelease(pVCpu->cpum.GstCtx.eip);
782
783	if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
784	{
785	/* Windows XP lets irets fault intentionally and then takes action based on the opcode; an
786	* int3 patch overwrites it and leads to blue screens. Remove the patch in this case.
787	*/
788	if ( u8TrapNo == X86_XCPT_GP
789	&& PATMIsInt3Patch(pVM, pVCpu->cpum.GstCtx.eip, NULL, NULL))
790	{
791	/** @todo move to PATMR3HandleTrap */
792	Log(("Possible Windows XP iret fault at %08RX32\n", pVCpu->cpum.GstCtx.eip));
793	PATMR3RemovePatch(pVM, pVCpu->cpum.GstCtx.eip);
794	}
795
796	/** @todo Knoppix 5 regression when returning VINF_SUCCESS here and going back to raw mode. */
797	/* Note: possibly because a reschedule is required (e.g. iret to V86 code) */
798
799	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
800	/* Interrupts are enabled; just go back to the original instruction.
801	return VINF_SUCCESS; */
802	}
803	return VINF_EM_RESCHEDULE_REM;
804	}
805
806	/*
807	* One instruction.
808	*/
809	case VINF_PATCH_EMULATE_INSTR:
810	Log(("emR3RawPatchTrap: Emulate patched instruction at %RGv IF=%d VMIF=%x\n",
811	uNewEip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pVCpu->em.s.pPatmGCState->uVMFlags));
812	pVCpu->cpum.GstCtx.eip = uNewEip;
813	AssertRelease(pVCpu->cpum.GstCtx.eip);
814	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHEMUL: ");
815
816	/*
817	* The patch was disabled, hand it to the REM.
818	*/
819	case VERR_PATCH_DISABLED:
820	if (!(pVCpu->em.s.pPatmGCState->uVMFlags & X86_EFL_IF))
821	Log(("emR3RawPatchTrap: Virtual IF flag disabled!!\n"));
822	pVCpu->cpum.GstCtx.eip = uNewEip;
823	AssertRelease(pVCpu->cpum.GstCtx.eip);
824
825	if (pVCpu->cpum.GstCtx.eflags.Bits.u1IF)
826	{
827	/*
828	* The last instruction in the patch block needs to be executed!! (sti/sysexit for example)
829	*/
830	Log(("PATCH: IF=1 -> emulate last instruction as it can't be interrupted!!\n"));
831	return emR3RawExecuteInstruction(pVM, pVCpu, "PATCHIR");
832	}
833	return VINF_EM_RESCHEDULE_REM;
834
835	/* Force continued patch exection; usually due to write monitored stack. */
836	case VINF_PATCH_CONTINUE:
837	return VINF_SUCCESS;
838
839	/*
840	* Anything else is fatal.
841	*/
842	default:
843	AssertReleaseMsgFailed(("Unknown return code %Rrc from PATMR3HandleTrap!\n", rc));
844	return VERR_IPE_UNEXPECTED_STATUS;
845	}
846	}
847	return VINF_SUCCESS;
848	}
849
850
851	/**
852	* Handle a privileged instruction.
853	*
854	* @returns VBox status code suitable for EM.
855	* @param pVM The cross context VM structure.
856	* @param pVCpu The cross context virtual CPU structure.
857	*/
858	static int emR3RawPrivileged(PVM pVM, PVMCPU pVCpu)
859	{
860	Assert(!pVCpu->cpum.GstCtx.eflags.Bits.u1VM);
861
862	if (PATMIsEnabled(pVM))
863	{
864	/*
865	* Check if in patch code.
866	*/
867	if (PATMR3IsInsidePatchJump(pVM, pVCpu->cpum.GstCtx.eip, NULL))
868	{
869	#ifdef LOG_ENABLED
870	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
871	#endif
872	AssertMsgFailed(("FATAL ERROR: executing random instruction inside generated patch jump %08x\n", pVCpu->cpum.GstCtx.eip));
873	return VERR_EM_RAW_PATCH_CONFLICT;
874	}
875	if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
876	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
877	&& !PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
878	{
879	int rc = PATMR3InstallPatch(pVM, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.eip),
880	CPUMGetGuestCodeBits(pVCpu) == 32 ? PATMFL_CODE32 : 0);
881	if (RT_SUCCESS(rc))
882	{
883	#ifdef LOG_ENABLED
884	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
885	#endif
886	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Patched privileged instruction");
887	return VINF_SUCCESS;
888	}
889	}
890	}
891
892	#ifdef LOG_ENABLED
893	if (!PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
894	{
895	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
896	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
897	}
898	#endif
899
900	/*
901	* Instruction statistics and logging.
902	*/
903	DISCPUSTATE Cpu;
904	int rc;
905
906	rc = CPUMR3DisasmInstrCPU(pVM, pVCpu, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.rip, &Cpu, "PRIV: ");
907	if (RT_SUCCESS(rc))
908	{
909	#ifdef VBOX_WITH_STATISTICS
910	PEMSTATS pStats = pVCpu->em.s.CTX_SUFF(pStats);
911	switch (Cpu.pCurInstr->uOpcode)
912	{
913	case OP_INVLPG:
914	STAM_COUNTER_INC(&pStats->StatInvlpg);
915	break;
916	case OP_IRET:
917	STAM_COUNTER_INC(&pStats->StatIret);
918	break;
919	case OP_CLI:
920	STAM_COUNTER_INC(&pStats->StatCli);
921	emR3RecordCli(pVM, pVCpu, pVCpu->cpum.GstCtx.rip);
922	break;
923	case OP_STI:
924	STAM_COUNTER_INC(&pStats->StatSti);
925	break;
926	case OP_INSB:
927	case OP_INSWD:
928	case OP_IN:
929	case OP_OUTSB:
930	case OP_OUTSWD:
931	case OP_OUT:
932	AssertMsgFailed(("Unexpected privileged exception due to port IO\n"));
933	break;
934
935	case OP_MOV_CR:
936	if (Cpu.Param1.fUse & DISUSE_REG_GEN32)
937	{
938	//read
939	Assert(Cpu.Param2.fUse & DISUSE_REG_CR);
940	Assert(Cpu.Param2.Base.idxCtrlReg <= DISCREG_CR4);
941	STAM_COUNTER_INC(&pStats->StatMovReadCR[Cpu.Param2.Base.idxCtrlReg]);
942	}
943	else
944	{
945	//write
946	Assert(Cpu.Param1.fUse & DISUSE_REG_CR);
947	Assert(Cpu.Param1.Base.idxCtrlReg <= DISCREG_CR4);
948	STAM_COUNTER_INC(&pStats->StatMovWriteCR[Cpu.Param1.Base.idxCtrlReg]);
949	}
950	break;
951
952	case OP_MOV_DR:
953	STAM_COUNTER_INC(&pStats->StatMovDRx);
954	break;
955	case OP_LLDT:
956	STAM_COUNTER_INC(&pStats->StatMovLldt);
957	break;
958	case OP_LIDT:
959	STAM_COUNTER_INC(&pStats->StatMovLidt);
960	break;
961	case OP_LGDT:
962	STAM_COUNTER_INC(&pStats->StatMovLgdt);
963	break;
964	case OP_SYSENTER:
965	STAM_COUNTER_INC(&pStats->StatSysEnter);
966	break;
967	case OP_SYSEXIT:
968	STAM_COUNTER_INC(&pStats->StatSysExit);
969	break;
970	case OP_SYSCALL:
971	STAM_COUNTER_INC(&pStats->StatSysCall);
972	break;
973	case OP_SYSRET:
974	STAM_COUNTER_INC(&pStats->StatSysRet);
975	break;
976	case OP_HLT:
977	STAM_COUNTER_INC(&pStats->StatHlt);
978	break;
979	default:
980	STAM_COUNTER_INC(&pStats->StatMisc);
981	Log4(("emR3RawPrivileged: opcode=%d\n", Cpu.pCurInstr->uOpcode));
982	break;
983	}
984	#endif /* VBOX_WITH_STATISTICS */
985	if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
986	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
987	&& CPUMGetGuestCodeBits(pVCpu) == 32)
988	{
989	STAM_PROFILE_START(&pVCpu->em.s.StatPrivEmu, a);
990	switch (Cpu.pCurInstr->uOpcode)
991	{
992	case OP_CLI:
993	pVCpu->cpum.GstCtx.eflags.u32 &= ~X86_EFL_IF;
994	Assert(Cpu.cbInstr == 1);
995	pVCpu->cpum.GstCtx.rip += Cpu.cbInstr;
996	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
997	return VINF_EM_RESCHEDULE_REM; /* must go to the recompiler now! */
998
999	case OP_STI:
1000	pVCpu->cpum.GstCtx.eflags.u32 \|= X86_EFL_IF;
1001	EMSetInhibitInterruptsPC(pVCpu, pVCpu->cpum.GstCtx.rip + Cpu.cbInstr);
1002	Assert(Cpu.cbInstr == 1);
1003	pVCpu->cpum.GstCtx.rip += Cpu.cbInstr;
1004	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1005	return VINF_SUCCESS;
1006
1007	case OP_HLT:
1008	if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1009	{
1010	PATMTRANSSTATE enmState;
1011	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pVCpu->cpum.GstCtx.eip, &enmState);
1012
1013	if (enmState == PATMTRANS_OVERWRITTEN)
1014	{
1015	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1016	Assert(rc == VERR_PATCH_DISABLED);
1017	/* Conflict detected, patch disabled */
1018	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %08RX32\n", pVCpu->cpum.GstCtx.eip));
1019
1020	enmState = PATMTRANS_SAFE;
1021	}
1022
1023	/* The translation had better be successful. Otherwise we can't recover. */
1024	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %08RX32\n", pVCpu->cpum.GstCtx.eip));
1025	if (enmState != PATMTRANS_OVERWRITTEN)
1026	pVCpu->cpum.GstCtx.eip = pOrgInstrGC;
1027	}
1028	/* no break; we could just return VINF_EM_HALT here */
1029	RT_FALL_THRU();
1030
1031	case OP_MOV_CR:
1032	case OP_MOV_DR:
1033	#ifdef LOG_ENABLED
1034	if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1035	{
1036	DBGFR3_INFO_LOG(pVM, pVCpu, "cpumguest", "PRIV");
1037	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Privileged instr");
1038	}
1039	#endif
1040
1041	rc = VBOXSTRICTRC_TODO(EMInterpretInstructionDisasState(pVCpu, &Cpu, CPUMCTX2CORE(&pVCpu->cpum.GstCtx),
1042	0, EMCODETYPE_SUPERVISOR));
1043	if (RT_SUCCESS(rc))
1044	{
1045	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1046
1047	if ( Cpu.pCurInstr->uOpcode == OP_MOV_CR
1048	&& Cpu.Param1.fUse == DISUSE_REG_CR /* write */
1049	)
1050	{
1051	/* Deal with CR0 updates inside patch code that force
1052	* us to go to the recompiler.
1053	*/
1054	if ( PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.rip)
1055	&& (pVCpu->cpum.GstCtx.cr0 & (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE)) != (X86_CR0_WP\|X86_CR0_PG\|X86_CR0_PE))
1056	{
1057	PATMTRANSSTATE enmState;
1058	RTGCPTR pOrgInstrGC = PATMR3PatchToGCPtr(pVM, pVCpu->cpum.GstCtx.rip, &enmState);
1059
1060	Log(("Force recompiler switch due to cr0 (%RGp) update rip=%RGv -> %RGv (enmState=%d)\n", pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.rip, pOrgInstrGC, enmState));
1061	if (enmState == PATMTRANS_OVERWRITTEN)
1062	{
1063	rc = PATMR3DetectConflict(pVM, pOrgInstrGC, pOrgInstrGC);
1064	Assert(rc == VERR_PATCH_DISABLED);
1065	/* Conflict detected, patch disabled */
1066	Log(("emR3RawPrivileged: detected conflict -> disabled patch at %RGv\n", (RTGCPTR)pVCpu->cpum.GstCtx.rip));
1067	enmState = PATMTRANS_SAFE;
1068	}
1069	/* The translation had better be successful. Otherwise we can't recover. */
1070	AssertReleaseMsg(pOrgInstrGC && enmState != PATMTRANS_OVERWRITTEN, ("Unable to translate instruction address at %RGv\n", (RTGCPTR)pVCpu->cpum.GstCtx.rip));
1071	if (enmState != PATMTRANS_OVERWRITTEN)
1072	pVCpu->cpum.GstCtx.rip = pOrgInstrGC;
1073	}
1074
1075	/* Reschedule is necessary as the execution/paging mode might have changed. */
1076	return VINF_EM_RESCHEDULE;
1077	}
1078	return rc; /* can return VINF_EM_HALT as well. */
1079	}
1080	AssertMsgReturn(rc == VERR_EM_INTERPRETER, ("%Rrc\n", rc), rc);
1081	break; /* fall back to the recompiler */
1082	}
1083	STAM_PROFILE_STOP(&pVCpu->em.s.StatPrivEmu, a);
1084	}
1085	}
1086
1087	if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1088	return emR3RawPatchTrap(pVM, pVCpu, VINF_PATM_PATCH_TRAP_GP);
1089
1090	return emR3RawExecuteInstruction(pVM, pVCpu, "PRIV");
1091	}
1092
1093
1094	/**
1095	* Update the forced rawmode execution modifier.
1096	*
1097	* This function is called when we're returning from the raw-mode loop(s). If we're
1098	* in patch code, it will set a flag forcing execution to be resumed in raw-mode,
1099	* if not in patch code, the flag will be cleared.
1100	*
1101	* We should never interrupt patch code while it's being executed. Cli patches can
1102	* contain big code blocks, but they are always executed with IF=0. Other patches
1103	* replace single instructions and should be atomic.
1104	*
1105	* @returns Updated rc.
1106	*
1107	* @param pVM The cross context VM structure.
1108	* @param pVCpu The cross context virtual CPU structure.
1109	* @param rc The result code.
1110	*/
1111	static int emR3RawUpdateForceFlag(PVM pVM, PVMCPU pVCpu, int rc)
1112	{
1113	if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip)) /** @todo check cs selector base/type */
1114	{
1115	/* ignore reschedule attempts. */
1116	switch (rc)
1117	{
1118	case VINF_EM_RESCHEDULE:
1119	case VINF_EM_RESCHEDULE_REM:
1120	LogFlow(("emR3RawUpdateForceFlag: patch address -> force raw reschedule\n"));
1121	rc = VINF_SUCCESS;
1122	break;
1123	}
1124	pVCpu->em.s.fForceRAW = true;
1125	}
1126	else
1127	pVCpu->em.s.fForceRAW = false;
1128	return rc;
1129	}
1130
1131
1132	/**
1133	* Check for pending raw actions
1134	*
1135	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1136	* EM statuses.
1137	* @param pVM The cross context VM structure.
1138	* @param pVCpu The cross context virtual CPU structure.
1139	*/
1140	VMMR3_INT_DECL(int) EMR3CheckRawForcedActions(PVM pVM, PVMCPU pVCpu)
1141	{
1142	int rc = emR3RawForcedActions(pVM, pVCpu);
1143	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1144	return rc;
1145	}
1146
1147
1148	/**
1149	* Process raw-mode specific forced actions.
1150	*
1151	* This function is called when any FFs in the VM_FF_HIGH_PRIORITY_PRE_RAW_MASK is pending.
1152	*
1153	* @returns VBox status code. May return VINF_EM_NO_MEMORY but none of the other
1154	* EM statuses.
1155	* @param pVM The cross context VM structure.
1156	* @param pVCpu The cross context virtual CPU structure.
1157	*/
1158	static int emR3RawForcedActions(PVM pVM, PVMCPU pVCpu)
1159	{
1160	/*
1161	* Note that the order is vitally important!
1162	* Also note that SELMR3UpdateFromCPUM may trigger VM_FF_SELM_SYNC_TSS.
1163	*/
1164	VBOXVMM_EM_FF_RAW(pVCpu, pVM->fGlobalForcedActions, pVCpu->fLocalForcedActions);
1165
1166	/*
1167	* Sync selector tables.
1168	*/
1169	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT))
1170	{
1171	VBOXSTRICTRC rcStrict = SELMR3UpdateFromCPUM(pVM, pVCpu);
1172	if (rcStrict != VINF_SUCCESS)
1173	return VBOXSTRICTRC_TODO(rcStrict);
1174	}
1175
1176	/*
1177	* Sync IDT.
1178	*
1179	* The CSAMR3CheckGates call in TRPMR3SyncIDT may call PGMPrefetchPage
1180	* and PGMShwModifyPage, so we're in for trouble if for instance a
1181	* PGMSyncCR3+pgmR3PoolClearAll is pending.
1182	*/
1183	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_TRPM_SYNC_IDT))
1184	{
1185	if ( VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3)
1186	&& EMIsRawRing0Enabled(pVM)
1187	&& CSAMIsEnabled(pVM))
1188	{
1189	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1190	if (RT_FAILURE(rc))
1191	return rc;
1192	}
1193
1194	int rc = TRPMR3SyncIDT(pVM, pVCpu);
1195	if (RT_FAILURE(rc))
1196	return rc;
1197	}
1198
1199	/*
1200	* Sync TSS.
1201	*/
1202	if (VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS))
1203	{
1204	int rc = SELMR3SyncTSS(pVM, pVCpu);
1205	if (RT_FAILURE(rc))
1206	return rc;
1207	}
1208
1209	/*
1210	* Sync page directory.
1211	*/
1212	if (VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL))
1213	{
1214	Assert(pVCpu->em.s.enmState != EMSTATE_WAIT_SIPI);
1215	int rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1216	if (RT_FAILURE(rc))
1217	return rc == VERR_PGM_NO_HYPERVISOR_ADDRESS ? VINF_EM_RESCHEDULE_REM : rc;
1218
1219	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1220
1221	/* Prefetch pages for EIP and ESP. */
1222	/** @todo This is rather expensive. Should investigate if it really helps at all. */
1223	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_CS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.rip));
1224	if (rc == VINF_SUCCESS)
1225	rc = PGMPrefetchPage(pVCpu, SELMToFlat(pVM, DISSELREG_SS, CPUMCTX2CORE(&pVCpu->cpum.GstCtx), pVCpu->cpum.GstCtx.rsp));
1226	if (rc != VINF_SUCCESS)
1227	{
1228	if (rc != VINF_PGM_SYNC_CR3)
1229	{
1230	AssertLogRelMsgReturn(RT_FAILURE(rc), ("%Rrc\n", rc), VERR_IPE_UNEXPECTED_INFO_STATUS);
1231	return rc;
1232	}
1233	rc = PGMSyncCR3(pVCpu, pVCpu->cpum.GstCtx.cr0, pVCpu->cpum.GstCtx.cr3, pVCpu->cpum.GstCtx.cr4, VMCPU_FF_IS_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3));
1234	if (RT_FAILURE(rc))
1235	return rc;
1236	}
1237	/** @todo maybe prefetch the supervisor stack page as well */
1238	Assert(!VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_GDT \| VMCPU_FF_SELM_SYNC_LDT));
1239	}
1240
1241	/*
1242	* Allocate handy pages (just in case the above actions have consumed some pages).
1243	*/
1244	if (VM_FF_IS_PENDING_EXCEPT(pVM, VM_FF_PGM_NEED_HANDY_PAGES, VM_FF_PGM_NO_MEMORY))
1245	{
1246	int rc = PGMR3PhysAllocateHandyPages(pVM);
1247	if (RT_FAILURE(rc))
1248	return rc;
1249	}
1250
1251	/*
1252	* Check whether we're out of memory now.
1253	*
1254	* This may stem from some of the above actions or operations that has been executed
1255	* since we ran FFs. The allocate handy pages must for instance always be followed by
1256	* this check.
1257	*/
1258	if (VM_FF_IS_SET(pVM, VM_FF_PGM_NO_MEMORY))
1259	return VINF_EM_NO_MEMORY;
1260
1261	return VINF_SUCCESS;
1262	}
1263
1264
1265	/**
1266	* Executes raw code.
1267	*
1268	* This function contains the raw-mode version of the inner
1269	* execution loop (the outer loop being in EMR3ExecuteVM()).
1270	*
1271	* @returns VBox status code. The most important ones are: VINF_EM_RESCHEDULE,
1272	* VINF_EM_RESCHEDULE_REM, VINF_EM_SUSPEND, VINF_EM_RESET and VINF_EM_TERMINATE.
1273	*
1274	* @param pVM The cross context VM structure.
1275	* @param pVCpu The cross context virtual CPU structure.
1276	* @param pfFFDone Where to store an indicator telling whether or not
1277	* FFs were done before returning.
1278	*/
1279	int emR3RawExecute(PVM pVM, PVMCPU pVCpu, bool *pfFFDone)
1280	{
1281	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTotal, a);
1282
1283	int rc = VERR_IPE_UNINITIALIZED_STATUS;
1284	LogFlow(("emR3RawExecute: (cs:eip=%04x:%08x)\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip));
1285	pVCpu->em.s.fForceRAW = false;
1286	*pfFFDone = false;
1287
1288
1289	/*
1290	*
1291	* Spin till we get a forced action or raw mode status code resulting in
1292	* in anything but VINF_SUCCESS or VINF_EM_RESCHEDULE_RAW.
1293	*
1294	*/
1295	for (;;)
1296	{
1297	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWEntry, b);
1298
1299	/*
1300	* Check various preconditions.
1301	*/
1302	#ifdef VBOX_STRICT
1303	Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1VM \|\| (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 3 \|\| (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 0
1304	\|\| (EMIsRawRing1Enabled(pVM) && (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 1));
1305	AssertMsg( (pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_IF)
1306	\|\| PATMShouldUseRawMode(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip),
1307	("Tried to execute code with IF at EIP=%08x!\n", pVCpu->cpum.GstCtx.eip));
1308	if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1309	&& PGMMapHasConflicts(pVM))
1310	{
1311	PGMMapCheck(pVM);
1312	AssertMsgFailed(("We should not get conflicts any longer!!!\n"));
1313	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1314	}
1315	#endif /* VBOX_STRICT */
1316
1317	/*
1318	* Process high priority pre-execution raw-mode FFs.
1319	*/
1320	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1321	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1322	{
1323	rc = emR3RawForcedActions(pVM, pVCpu);
1324	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1325	if (rc != VINF_SUCCESS)
1326	break;
1327	}
1328
1329	/*
1330	* If we're going to execute ring-0 code, the guest state needs to
1331	* be modified a bit and some of the state components (IF, SS/CS RPL,
1332	* and perhaps EIP) needs to be stored with PATM.
1333	*/
1334	rc = CPUMRawEnter(pVCpu);
1335	if (rc != VINF_SUCCESS)
1336	{
1337	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1338	break;
1339	}
1340
1341	/*
1342	* Scan code before executing it. Don't bother with user mode or V86 code
1343	*/
1344	if ( (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) <= 1
1345	&& !pVCpu->cpum.GstCtx.eflags.Bits.u1VM
1346	&& !PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip))
1347	{
1348	STAM_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWEntry, b);
1349	CSAMR3CheckCodeEx(pVM, &pVCpu->cpum.GstCtx, pVCpu->cpum.GstCtx.eip);
1350	STAM_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWEntry, b);
1351	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_PRE_RAW_MASK)
1352	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1353	{
1354	rc = emR3RawForcedActions(pVM, pVCpu);
1355	VBOXVMM_EM_FF_RAW_RET(pVCpu, rc);
1356	if (rc != VINF_SUCCESS)
1357	{
1358	rc = CPUMRawLeave(pVCpu, rc);
1359	break;
1360	}
1361	}
1362	}
1363
1364	#ifdef LOG_ENABLED
1365	/*
1366	* Log important stuff before entering GC.
1367	*/
1368	PPATMGCSTATE pGCState = PATMR3QueryGCStateHC(pVM);
1369	if (pVCpu->cpum.GstCtx.eflags.Bits.u1VM)
1370	Log(("RV86: %04x:%08x IF=%d VMFlags=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags));
1371	else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 1)
1372	Log(("RR0: %x:%08x ESP=%x:%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d CPL=%d (Scanned=%d)\n",
1373	pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, CPUMRawGetEFlags(pVCpu), !!(pGCState->uVMFlags & X86_EFL_IF), pVCpu->cpum.GstCtx.eflags.Bits.u1IF,
1374	pGCState->uVMFlags, pGCState->fPIF, (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL), CSAMIsPageScanned(pVM, (RTGCPTR)pVCpu->cpum.GstCtx.eip)));
1375	# ifdef VBOX_WITH_RAW_RING1
1376	else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 2)
1377	Log(("RR1: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x CPL=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags, (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL)));
1378	# endif
1379	else if ((pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) == 3)
1380	Log(("RR3: %x:%08x ESP=%x:%08x IF=%d VMFlags=%x\n", pVCpu->cpum.GstCtx.cs.Sel, pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.ss.Sel, pVCpu->cpum.GstCtx.esp, pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags));
1381	#endif /* LOG_ENABLED */
1382
1383
1384
1385	/*
1386	* Execute the code.
1387	*/
1388	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWEntry, b);
1389	if (RT_LIKELY(emR3IsExecutionAllowed(pVM, pVCpu)))
1390	{
1391	STAM_PROFILE_START(&pVCpu->em.s.StatRAWExec, c);
1392	VBOXVMM_EM_RAW_RUN_PRE(pVCpu, &pVCpu->cpum.GstCtx);
1393	rc = VMMR3RawRunGC(pVM, pVCpu);
1394	VBOXVMM_EM_RAW_RUN_RET(pVCpu, &pVCpu->cpum.GstCtx, rc);
1395	STAM_PROFILE_STOP(&pVCpu->em.s.StatRAWExec, c);
1396	}
1397	else
1398	{
1399	/* Give up this time slice; virtual time continues */
1400	STAM_REL_PROFILE_ADV_START(&pVCpu->em.s.StatCapped, u);
1401	RTThreadSleep(5);
1402	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatCapped, u);
1403	rc = VINF_SUCCESS;
1404	}
1405	STAM_PROFILE_ADV_START(&pVCpu->em.s.StatRAWTail, d);
1406
1407	LogFlow(("RR%u-E: %08x ESP=%08x EFL=%x IF=%d/%d VMFlags=%x PIF=%d\n",
1408	(pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL), pVCpu->cpum.GstCtx.eip, pVCpu->cpum.GstCtx.esp, CPUMRawGetEFlags(pVCpu),
1409	!!(pGCState->uVMFlags & X86_EFL_IF), pVCpu->cpum.GstCtx.eflags.Bits.u1IF, pGCState->uVMFlags, pGCState->fPIF));
1410	LogFlow(("VMMR3RawRunGC returned %Rrc\n", rc));
1411
1412
1413
1414	/*
1415	* Restore the real CPU state and deal with high priority post
1416	* execution FFs before doing anything else.
1417	*/
1418	rc = CPUMRawLeave(pVCpu, rc);
1419	VMCPU_FF_CLEAR_MASK(pVCpu, VMCPU_FF_RESUME_GUEST_MASK);
1420	if ( VM_FF_IS_ANY_SET(pVM, VM_FF_HIGH_PRIORITY_POST_MASK)
1421	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_HIGH_PRIORITY_POST_MASK))
1422	rc = VBOXSTRICTRC_TODO(emR3HighPriorityPostForcedActions(pVM, pVCpu, rc));
1423
1424	#ifdef VBOX_STRICT
1425	/*
1426	* Assert TSS consistency & rc vs patch code.
1427	*/
1428	if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_SELM_SYNC_TSS \| VMCPU_FF_SELM_SYNC_GDT) /* GDT implies TSS at the moment. */
1429	&& EMIsRawRing0Enabled(pVM))
1430	SELMR3CheckTSS(pVM);
1431	switch (rc)
1432	{
1433	case VINF_SUCCESS:
1434	case VINF_EM_RAW_INTERRUPT:
1435	case VINF_PATM_PATCH_TRAP_PF:
1436	case VINF_PATM_PATCH_TRAP_GP:
1437	case VINF_PATM_PATCH_INT3:
1438	case VINF_PATM_CHECK_PATCH_PAGE:
1439	case VINF_EM_RAW_EXCEPTION_PRIVILEGED:
1440	case VINF_EM_RAW_GUEST_TRAP:
1441	case VINF_EM_RESCHEDULE_RAW:
1442	break;
1443
1444	default:
1445	if (PATMIsPatchGCAddr(pVM, pVCpu->cpum.GstCtx.eip) && !(pVCpu->cpum.GstCtx.eflags.u32 & X86_EFL_TF))
1446	LogIt(0, LOG_GROUP_PATM, ("Patch code interrupted at %RRv for reason %Rrc\n", (RTRCPTR)CPUMGetGuestEIP(pVCpu), rc));
1447	break;
1448	}
1449	/*
1450	* Let's go paranoid!
1451	*/
1452	if ( !VMCPU_FF_IS_ANY_SET(pVCpu, VMCPU_FF_PGM_SYNC_CR3 \| VMCPU_FF_PGM_SYNC_CR3_NON_GLOBAL)
1453	&& PGMMapHasConflicts(pVM))
1454	{
1455	PGMMapCheck(pVM);
1456	AssertMsgFailed(("We should not get conflicts any longer!!! rc=%Rrc\n", rc));
1457	return VERR_EM_UNEXPECTED_MAPPING_CONFLICT;
1458	}
1459	#endif /* VBOX_STRICT */
1460
1461	/*
1462	* Process the returned status code.
1463	*/
1464	if (rc >= VINF_EM_FIRST && rc <= VINF_EM_LAST)
1465	{
1466	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1467	break;
1468	}
1469	rc = emR3RawHandleRC(pVM, pVCpu, rc);
1470	if (rc != VINF_SUCCESS)
1471	{
1472	rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
1473	if (rc != VINF_SUCCESS)
1474	{
1475	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1476	break;
1477	}
1478	}
1479
1480	/*
1481	* Check and execute forced actions.
1482	*/
1483	#ifdef VBOX_HIGH_RES_TIMERS_HACK
1484	TMTimerPollVoid(pVM, pVCpu);
1485	#endif
1486	STAM_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTail, d);
1487	if ( VM_FF_IS_ANY_SET(pVM, ~VM_FF_HIGH_PRIORITY_PRE_RAW_MASK \| VM_FF_PGM_NO_MEMORY)
1488	\|\| VMCPU_FF_IS_ANY_SET(pVCpu, ~VMCPU_FF_HIGH_PRIORITY_PRE_RAW_MASK))
1489	{
1490	Assert(pVCpu->cpum.GstCtx.eflags.Bits.u1VM \|\| (pVCpu->cpum.GstCtx.ss.Sel & X86_SEL_RPL) != (EMIsRawRing1Enabled(pVM) ? 2U : 1U));
1491
1492	STAM_REL_PROFILE_ADV_SUSPEND(&pVCpu->em.s.StatRAWTotal, a);
1493	rc = emR3ForcedActions(pVM, pVCpu, rc);
1494	VBOXVMM_EM_FF_ALL_RET(pVCpu, rc);
1495	STAM_REL_PROFILE_ADV_RESUME(&pVCpu->em.s.StatRAWTotal, a);
1496	if ( rc != VINF_SUCCESS
1497	&& rc != VINF_EM_RESCHEDULE_RAW)
1498	{
1499	rc = emR3RawUpdateForceFlag(pVM, pVCpu, rc);
1500	if (rc != VINF_SUCCESS)
1501	{
1502	*pfFFDone = true;
1503	break;
1504	}
1505	}
1506	}
1507	}
1508
1509	/*
1510	* Return to outer loop.
1511	*/
1512	#if defined(LOG_ENABLED) && defined(DEBUG)
1513	RTLogFlush(NULL);
1514	#endif
1515	STAM_REL_PROFILE_ADV_STOP(&pVCpu->em.s.StatRAWTotal, a);
1516	return rc;
1517	}
1518

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source: vbox/trunk/src/VBox/VMM/VMMR3/EMRaw.cpp@ 78043

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