VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 100746

Last change on this file since 100746 was 100165, checked in by vboxsync, 18 months ago

VMM/GIC: Updates to the emulation, implement interrupt priority support, bugref:10404
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1/* $Id: GICR3.cpp 100165 2023-06-13 11:56:42Z vboxsync $ */
2/** @file
3 * GIC - Generic Interrupt Controller Architecture (GICv3).
4 */
5
6/*
7 * Copyright (C) 2023 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_APIC
33#include <VBox/log.h>
34#include "GICInternal.h"
35#include <VBox/vmm/gic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/hm.h>
38#include <VBox/vmm/mm.h>
39#include <VBox/vmm/pdmdev.h>
40#include <VBox/vmm/ssm.h>
41#include <VBox/vmm/vm.h>
42
43#include <iprt/armv8.h>
44
45
46#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49/*********************************************************************************************************************************
50* Defined Constants And Macros *
51*********************************************************************************************************************************/
52# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
53 { (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicV3Icc, kCpumSysRegWrFn_GicV3Icc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
54
55
56/*********************************************************************************************************************************
57* Global Variables *
58*********************************************************************************************************************************/
59/**
60 * System register ranges for the GICv3.
61 */
62static CPUMSYSREGRANGE const g_aSysRegRanges_GICv3[] =
63{
64 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
65 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
66 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
67 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
68 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
69};
70
71
72/**
73 * Dumps basic APIC state.
74 *
75 * @param pVM The cross context VM structure.
76 * @param pHlp The info helpers.
77 * @param pszArgs Arguments, ignored.
78 */
79static DECLCALLBACK(void) gicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
80{
81 RT_NOREF(pVM, pHlp, pszArgs);
82}
83
84
85/**
86 * Dumps GIC Distributor information.
87 *
88 * @param pVM The cross context VM structure.
89 * @param pHlp The info helpers.
90 * @param pszArgs Arguments, ignored.
91 */
92static DECLCALLBACK(void) gicR3InfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
93{
94 RT_NOREF(pszArgs);
95
96 PGIC pGic = VM_TO_GIC(pVM);
97 PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
98 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
99
100 pHlp->pfnPrintf(pHlp, "GICv3 Distributor:\n");
101 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->u32RegIGrp0);
102 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->u32RegICfg0);
103 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->u32RegICfg1);
104 pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicDev->bmIntEnabled);
105 pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicDev->bmIntPending);
106 pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicDev->bmIntActive);
107 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
108 for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntPriority); i++)
109 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->abIntPriority[i]);
110
111 pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicDev->fIrqGrp0Enabled);
112 pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicDev->fIrqGrp1Enabled);
113}
114
115
116/**
117 * Dumps the GIC Redistributor information.
118 *
119 * @param pVM The cross context VM structure.
120 * @param pHlp The info helpers.
121 * @param pszArgs Arguments, ignored.
122 */
123static DECLCALLBACK(void) gicR3InfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
124{
125 NOREF(pszArgs);
126 PVMCPU pVCpu = VMMGetCpu(pVM);
127 if (!pVCpu)
128 pVCpu = pVM->apCpusR3[0];
129
130 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
131
132 pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
133 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicVCpu->u32RegIGrp0);
134 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicVCpu->u32RegICfg0);
135 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicVCpu->u32RegICfg1);
136 pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicVCpu->bmIntEnabled);
137 pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicVCpu->bmIntPending);
138 pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicVCpu->bmIntActive);
139 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
140 for (uint32_t i = 0; i < RT_ELEMENTS(pGicVCpu->abIntPriority); i++)
141 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", i, pGicVCpu->abIntPriority[i]);
142
143 pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
144 pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicVCpu->fIrqGrp0Enabled);
145 pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicVCpu->fIrqGrp1Enabled);
146 pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicVCpu->bInterruptPriority);
147 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicVCpu->bBinaryPointGrp0);
148 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicVCpu->bBinaryPointGrp1);
149 pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicVCpu->idxRunningPriority);
150 pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicVCpu->abRunningPriorities[pGicVCpu->idxRunningPriority]);
151}
152
153
154/**
155 * @interface_method_impl{PDMDEVREG,pfnReset}
156 */
157DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
158{
159 PVM pVM = PDMDevHlpGetVM(pDevIns);
160 VM_ASSERT_EMT0(pVM);
161 VM_ASSERT_IS_NOT_RUNNING(pVM);
162
163 LogFlow(("GIC: gicR3Reset\n"));
164
165 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
166 {
167 PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
168
169 gicResetCpu(pVCpuDest);
170 }
171}
172
173
174/**
175 * @interface_method_impl{PDMDEVREG,pfnRelocate}
176 */
177DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
178{
179 RT_NOREF(pDevIns, offDelta);
180}
181
182
183/**
184 * Initializes the GIC state.
185 *
186 * @returns VBox status code.
187 * @param pVM The cross context VM structure.
188 */
189static int gicR3InitState(PVM pVM)
190{
191 LogFlowFunc(("pVM=%p\n", pVM));
192
193 RT_NOREF(pVM);
194 return VINF_SUCCESS;
195}
196
197
198/**
199 * @interface_method_impl{PDMDEVREG,pfnDestruct}
200 */
201DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
202{
203 LogFlowFunc(("pDevIns=%p\n", pDevIns));
204 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
205
206 return VINF_SUCCESS;
207}
208
209
210/**
211 * @interface_method_impl{PDMDEVREG,pfnConstruct}
212 */
213DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
214{
215 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
216 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
217 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
218 PVM pVM = PDMDevHlpGetVM(pDevIns);
219 PGIC pGic = VM_TO_GIC(pVM);
220 Assert(iInstance == 0); NOREF(iInstance);
221
222 /*
223 * Init the data.
224 */
225 pGic->pDevInsR3 = pDevIns;
226
227 /*
228 * Validate GIC settings.
229 */
230 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase|RedistributorMmioBase", "");
231
232#if 0
233 /*
234 * Disable automatic PDM locking for this device.
235 */
236 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
237 AssertRCReturn(rc, rc);
238#else
239 int rc;
240#endif
241
242 /*
243 * Register the GIC with PDM.
244 */
245 rc = PDMDevHlpApicRegister(pDevIns);
246 AssertLogRelRCReturn(rc, rc);
247
248 /*
249 * Initialize the GIC state.
250 */
251 for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GICv3); i++)
252 {
253 rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GICv3[i]);
254 AssertLogRelRCReturn(rc, rc);
255 }
256
257 /* Finally, initialize the state. */
258 rc = gicR3InitState(pVM);
259 AssertRCReturn(rc, rc);
260
261 /*
262 * Register the MMIO ranges.
263 */
264 RTGCPHYS GCPhysMmioBase = 0;
265 rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
266 if (RT_FAILURE(rc))
267 return PDMDEV_SET_ERROR(pDevIns, rc,
268 N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
269
270 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
271 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_Dist", &pGicDev->hMmioDist);
272 AssertRCReturn(rc, rc);
273
274 rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
275 if (RT_FAILURE(rc))
276 return PDMDEV_SET_ERROR(pDevIns, rc,
277 N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
278
279 RTGCPHYS cbRegion = pVM->cCpus * (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
280 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
281 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_ReDist", &pGicDev->hMmioReDist);
282 AssertRCReturn(rc, rc);
283
284 /*
285 * Register debugger info callbacks.
286 *
287 * We use separate callbacks rather than arguments so they can also be
288 * dumped in an automated fashion while collecting crash diagnostics and
289 * not just used during live debugging via the VM debugger.
290 */
291 DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
292 DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC Distributor information.", gicR3InfoDist, DBGFINFO_FLAGS_ALL_EMTS);
293 DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC Redistributor information.", gicR3InfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
294
295 /*
296 * Statistics.
297 */
298#define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
299 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
300 STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
301#define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
302 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
303 STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
304
305#ifdef VBOX_WITH_STATISTICS
306 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
307 {
308 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
309 PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
310
311# if 0 /* No R0 for now. */
312 GIC_REG_COUNTER(&pGicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
313 GIC_REG_COUNTER(&pGicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
314 GIC_REG_COUNTER(&pGicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
315 GIC_REG_COUNTER(&pGicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
316# endif
317
318 GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/R3/MmioRead", "Number of APIC MMIO reads in R3.");
319 GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/R3/MmioWrite", "Number of APIC MMIO writes in R3.");
320 GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/R3/SysRegRead", "Number of GIC system register reads in R3.");
321 GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/R3/SysRegWrite", "Number of GIC system register writes in R3.");
322 }
323#endif
324
325# undef GIC_PROF_COUNTER
326
327 gicR3Reset(pDevIns);
328 return VINF_SUCCESS;
329}
330
331#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
332
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