VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 107308

Last change on this file since 107308 was 107308, checked in by vboxsync, 5 weeks ago

VMM: bugref:10759 Refactor GIC for use with different backends.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 20.2 KB
Line 
1/* $Id: GICR3.cpp 107308 2024-12-13 08:09:39Z vboxsync $ */
2/** @file
3 * GIC - Generic Interrupt Controller Architecture (GICv3).
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_APIC
33#include <VBox/log.h>
34#include "GICInternal.h"
35#include <VBox/vmm/pdmgic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/hm.h>
38#include <VBox/vmm/mm.h>
39#include <VBox/vmm/pdmdev.h>
40#include <VBox/vmm/ssm.h>
41#include <VBox/vmm/vm.h>
42
43#include <iprt/armv8.h>
44
45
46#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49/*********************************************************************************************************************************
50* Defined Constants And Macros *
51*********************************************************************************************************************************/
52/** Some ancient version... */
53#define GIC_SAVED_STATE_VERSION 1
54
55# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
56 { (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicV3Icc, kCpumSysRegWrFn_GicV3Icc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57
58
59/*********************************************************************************************************************************
60* Global Variables *
61*********************************************************************************************************************************/
62/**
63 * System register ranges for the GICv3.
64 */
65static CPUMSYSREGRANGE const g_aSysRegRanges_GICv3[] =
66{
67 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
68 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
69 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
70 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
71 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
72 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2")
73};
74
75
76/**
77 * Dumps basic APIC state.
78 *
79 * @param pVM The cross context VM structure.
80 * @param pHlp The info helpers.
81 * @param pszArgs Arguments, ignored.
82 */
83static DECLCALLBACK(void) gicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
84{
85 RT_NOREF(pVM, pHlp, pszArgs);
86}
87
88
89/**
90 * Dumps GIC Distributor information.
91 *
92 * @param pVM The cross context VM structure.
93 * @param pHlp The info helpers.
94 * @param pszArgs Arguments, ignored.
95 */
96static DECLCALLBACK(void) gicR3InfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
97{
98 RT_NOREF(pszArgs);
99
100 PGIC pGic = VM_TO_GIC(pVM);
101 PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
102 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
103
104 pHlp->pfnPrintf(pHlp, "GICv3 Distributor:\n");
105 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->u32RegIGrp0);
106 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->u32RegICfg0);
107 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->u32RegICfg1);
108 pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicDev->bmIntEnabled);
109 pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicDev->bmIntPending);
110 pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicDev->bmIntActive);
111 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
112 for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntPriority); i++)
113 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->abIntPriority[i]);
114
115 pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
116 for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->au32IntRouting); i++)
117 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->au32IntRouting[i]);
118
119 pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicDev->fIrqGrp0Enabled);
120 pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicDev->fIrqGrp1Enabled);
121}
122
123
124/**
125 * Dumps the GIC Redistributor information.
126 *
127 * @param pVM The cross context VM structure.
128 * @param pHlp The info helpers.
129 * @param pszArgs Arguments, ignored.
130 */
131static DECLCALLBACK(void) gicR3InfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
132{
133 NOREF(pszArgs);
134 PVMCPU pVCpu = VMMGetCpu(pVM);
135 if (!pVCpu)
136 pVCpu = pVM->apCpusR3[0];
137
138 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
139
140 pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
141 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicVCpu->u32RegIGrp0);
142 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicVCpu->u32RegICfg0);
143 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicVCpu->u32RegICfg1);
144 pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicVCpu->bmIntEnabled);
145 pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicVCpu->bmIntPending);
146 pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicVCpu->bmIntActive);
147 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
148 for (uint32_t i = 0; i < RT_ELEMENTS(pGicVCpu->abIntPriority); i++)
149 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", i, pGicVCpu->abIntPriority[i]);
150
151 pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
152 pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicVCpu->fIrqGrp0Enabled);
153 pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicVCpu->fIrqGrp1Enabled);
154 pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicVCpu->bInterruptPriority);
155 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicVCpu->bBinaryPointGrp0);
156 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicVCpu->bBinaryPointGrp1);
157 pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicVCpu->idxRunningPriority);
158 pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicVCpu->abRunningPriorities[pGicVCpu->idxRunningPriority]);
159}
160
161
162/**
163 * Worker for saving per-VM GIC data.
164 *
165 * @returns VBox status code.
166 * @param pDevIns The device instance.
167 * @param pVM The cross context VM structure.
168 * @param pSSM The SSM handle.
169 */
170static int gicR3SaveVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
171{
172 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
173 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
174
175 pHlp->pfnSSMPutU32( pSSM, pVM->cCpus);
176 pHlp->pfnSSMPutU32( pSSM, GIC_SPI_MAX);
177 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegIGrp0);
178 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg0);
179 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg1);
180 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntEnabled);
181 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntPending);
182 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntActive);
183 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
184 pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp0Enabled);
185
186 return pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp1Enabled);
187}
188
189
190/**
191 * Worker for loading per-VM GIC data.
192 *
193 * @returns VBox status code.
194 * @param pDevIns The device instance.
195 * @param pVM The cross context VM structure.
196 * @param pSSM The SSM handle.
197 */
198static int gicR3LoadVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
199{
200 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
201 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
202
203 /* Load and verify number of CPUs. */
204 uint32_t cCpus;
205 int rc = pHlp->pfnSSMGetU32(pSSM, &cCpus);
206 AssertRCReturn(rc, rc);
207 if (cCpus != pVM->cCpus)
208 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
209
210 /* Load and verify maximum number of SPIs. */
211 uint32_t cSpisMax;
212 rc = pHlp->pfnSSMGetU32(pSSM, &cSpisMax);
213 AssertRCReturn(rc, rc);
214 if (cSpisMax != GIC_SPI_MAX)
215 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cSpisMax: saved=%u config=%u"),
216 cSpisMax, GIC_SPI_MAX);
217
218 /* Load the state. */
219 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegIGrp0);
220 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg0);
221 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg1);
222 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntEnabled);
223 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntPending);
224 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntActive);
225 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
226 pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp0Enabled);
227 pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp1Enabled);
228
229 return VINF_SUCCESS;
230}
231
232
233/**
234 * @copydoc FNSSMDEVSAVEEXEC
235 */
236static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
237{
238 PVM pVM = PDMDevHlpGetVM(pDevIns);
239 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
240
241 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
242
243 LogFlow(("GIC: gicR3SaveExec\n"));
244
245 /* Save per-VM data. */
246 int rc = gicR3SaveVMData(pDevIns, pVM, pSSM);
247 AssertRCReturn(rc, rc);
248
249 /* Save per-VCPU data.*/
250 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
251 {
252 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
253 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
254
255 /* Load the redistributor state. */
256 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegIGrp0);
257 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg0);
258 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg1);
259 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntEnabled);
260 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntPending);
261 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntActive);
262 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
263
264 pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp0Enabled);
265 pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp1Enabled);
266 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bInterruptPriority);
267 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp0);
268 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp1);
269 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
270 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->idxRunningPriority);
271 }
272
273 return rc;
274}
275
276
277/**
278 * @copydoc FNSSMDEVLOADEXEC
279 */
280static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
281{
282 PVM pVM = PDMDevHlpGetVM(pDevIns);
283 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
284
285 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
286 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
287
288 LogFlow(("GIC: gicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
289
290 /* Weed out invalid versions. */
291 if (uVersion != GIC_SAVED_STATE_VERSION)
292 {
293 LogRel(("GIC: gicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
294 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
295 }
296
297 int rc = gicR3LoadVMData(pDevIns, pVM, pSSM);
298 AssertRCReturn(rc, rc);
299
300 /*
301 * Restore per CPU state.
302 *
303 * Note! PDM will restore the VMCPU_FF_INTERRUPT_IRQ and VMCPU_FF_INTERRUPT_FIQ flags for us.
304 * This code doesn't touch it. No devices should make us touch
305 * it later during the restore either, only during the 'done' phase.
306 */
307 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
308 {
309 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
310 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
311
312 /* Load the redistributor state. */
313 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegIGrp0);
314 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg0);
315 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg1);
316 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntEnabled);
317 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntPending);
318 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntActive);
319 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
320
321 pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp0Enabled);
322 pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp1Enabled);
323 pHlp->pfnSSMGetU8V( pSSM, &pGicVCpu->bInterruptPriority);
324 pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp0);
325 pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp1);
326 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
327 rc = pHlp->pfnSSMGetU8V(pSSM, &pGicVCpu->idxRunningPriority);
328 if (RT_FAILURE(rc))
329 return rc;
330 }
331
332 return rc;
333}
334
335
336/**
337 * @interface_method_impl{PDMDEVREG,pfnReset}
338 */
339DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
340{
341 PVM pVM = PDMDevHlpGetVM(pDevIns);
342 VM_ASSERT_EMT0(pVM);
343 VM_ASSERT_IS_NOT_RUNNING(pVM);
344
345 LogFlow(("GIC: gicR3Reset\n"));
346
347 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
348 {
349 PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
350
351 gicResetCpu(pVCpuDest);
352 }
353}
354
355
356/**
357 * @interface_method_impl{PDMDEVREG,pfnRelocate}
358 */
359DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
360{
361 RT_NOREF(pDevIns, offDelta);
362}
363
364
365/**
366 * Initializes the GIC state.
367 *
368 * @returns VBox status code.
369 * @param pVM The cross context VM structure.
370 */
371static int gicR3InitState(PVM pVM)
372{
373 LogFlowFunc(("pVM=%p\n", pVM));
374
375 RT_NOREF(pVM);
376 return VINF_SUCCESS;
377}
378
379
380/**
381 * @interface_method_impl{PDMDEVREG,pfnDestruct}
382 */
383DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
384{
385 LogFlowFunc(("pDevIns=%p\n", pDevIns));
386 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
387
388 return VINF_SUCCESS;
389}
390
391
392/**
393 * @interface_method_impl{PDMDEVREG,pfnConstruct}
394 */
395DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
396{
397 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
398 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
399 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
400 PVM pVM = PDMDevHlpGetVM(pDevIns);
401 PGIC pGic = VM_TO_GIC(pVM);
402 Assert(iInstance == 0); NOREF(iInstance);
403
404 /*
405 * Init the data.
406 */
407 pGic->pDevInsR3 = pDevIns;
408
409 /*
410 * Validate GIC settings.
411 */
412 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase|RedistributorMmioBase|ItsMmioBase", "");
413
414#if 0
415 /*
416 * Disable automatic PDM locking for this device.
417 */
418 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
419 AssertRCReturn(rc, rc);
420#else
421 int rc;
422#endif
423
424 /*
425 * Register the GIC with PDM.
426 */
427 rc = PDMDevHlpIcRegister(pDevIns);
428 AssertLogRelRCReturn(rc, rc);
429
430 rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
431 AssertLogRelRCReturn(rc, rc);
432
433 /*
434 * Initialize the GIC state.
435 */
436 for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GICv3); i++)
437 {
438 rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GICv3[i]);
439 AssertLogRelRCReturn(rc, rc);
440 }
441
442 /* Finally, initialize the state. */
443 rc = gicR3InitState(pVM);
444 AssertRCReturn(rc, rc);
445
446 /*
447 * Register the MMIO ranges.
448 */
449 RTGCPHYS GCPhysMmioBase = 0;
450 rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
451 if (RT_FAILURE(rc))
452 return PDMDEV_SET_ERROR(pDevIns, rc,
453 N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
454
455 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
456 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_Dist", &pGicDev->hMmioDist);
457 AssertRCReturn(rc, rc);
458
459 rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
460 if (RT_FAILURE(rc))
461 return PDMDEV_SET_ERROR(pDevIns, rc,
462 N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
463
464 RTGCPHYS cbRegion = pVM->cCpus * (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
465 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
466 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GICv3_ReDist", &pGicDev->hMmioReDist);
467 AssertRCReturn(rc, rc);
468
469 /*
470 * Register saved state callbacks.
471 */
472 rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
473 AssertRCReturn(rc, rc);
474
475 /*
476 * Register debugger info callbacks.
477 *
478 * We use separate callbacks rather than arguments so they can also be
479 * dumped in an automated fashion while collecting crash diagnostics and
480 * not just used during live debugging via the VM debugger.
481 */
482 DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
483 DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC Distributor information.", gicR3InfoDist, DBGFINFO_FLAGS_ALL_EMTS);
484 DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC Redistributor information.", gicR3InfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
485
486 /*
487 * Statistics.
488 */
489#define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
490 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
491 STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
492#define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
493 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
494 STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
495
496#ifdef VBOX_WITH_STATISTICS
497 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
498 {
499 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
500 PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
501
502# if 0 /* No R0 for now. */
503 GIC_REG_COUNTER(&pGicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
504 GIC_REG_COUNTER(&pGicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
505 GIC_REG_COUNTER(&pGicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
506 GIC_REG_COUNTER(&pGicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
507# endif
508
509 GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/R3/MmioRead", "Number of APIC MMIO reads in R3.");
510 GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/R3/MmioWrite", "Number of APIC MMIO writes in R3.");
511 GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/R3/SysRegRead", "Number of GIC system register reads in R3.");
512 GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/R3/SysRegWrite", "Number of GIC system register writes in R3.");
513 }
514#endif
515
516# undef GIC_PROF_COUNTER
517
518 gicR3Reset(pDevIns);
519 return VINF_SUCCESS;
520}
521
522#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
523
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette