GICR3.cpp@ 108387

Last change on this file since 108387 was 107984, checked in by vboxsync, 3 months ago
VMM/GIC: bugref:10404 CFGM bits.
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1	/* $Id: GICR3.cpp 107984 2025-01-30 06:43:18Z vboxsync $ */
2	/** @file
3	* GIC - Generic Interrupt Controller Architecture (GIC).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/log.h>
34	#include "GICInternal.h"
35	#include <VBox/vmm/pdmgic.h>
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/pdmdev.h>
40	#include <VBox/vmm/ssm.h>
41	#include <VBox/vmm/vm.h>
42
43	#include <iprt/armv8.h>
44
45
46	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	/** GIC saved state version. */
53	#define GIC_SAVED_STATE_VERSION 1
54
55	# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
56	{ (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicIcc, kCpumSysRegWrFn_GicIcc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57
58
59	/*********************************************************************************************************************************
60	* Global Variables *
61	*********************************************************************************************************************************/
62	/**
63	* System register ranges for the GIC.
64	*/
65	static CPUMSYSREGRANGE const g_aSysRegRanges_GIC[] =
66	{
67	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
68	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
69	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
70	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
71	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
72	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2"),
73	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, "ICC_SRE_EL3")
74	};
75
76
77	/**
78	* Dumps basic APIC state.
79	*
80	* @param pVM The cross context VM structure.
81	* @param pHlp The info helpers.
82	* @param pszArgs Arguments, ignored.
83	*/
84	static DECLCALLBACK(void) gicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
85	{
86	RT_NOREF(pVM, pHlp, pszArgs);
87	}
88
89
90	/**
91	* Dumps GIC Distributor information.
92	*
93	* @param pVM The cross context VM structure.
94	* @param pHlp The info helpers.
95	* @param pszArgs Arguments, ignored.
96	*/
97	static DECLCALLBACK(void) gicR3InfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
98	{
99	RT_NOREF(pszArgs);
100
101	PGIC pGic = VM_TO_GIC(pVM);
102	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
103	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
104
105	pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
106	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->u32RegIGrp0);
107	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->u32RegICfg0);
108	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->u32RegICfg1);
109	pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicDev->bmIntEnabled);
110	pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicDev->bmIntPending);
111	pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicDev->bmIntActive);
112	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
113	for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntPriority); i++)
114	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->abIntPriority[i]);
115
116	pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
117	for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->au32IntRouting); i++)
118	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->au32IntRouting[i]);
119
120	pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicDev->fIrqGrp0Enabled);
121	pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicDev->fIrqGrp1Enabled);
122	}
123
124
125	/**
126	* Dumps the GIC Redistributor information.
127	*
128	* @param pVM The cross context VM structure.
129	* @param pHlp The info helpers.
130	* @param pszArgs Arguments, ignored.
131	*/
132	static DECLCALLBACK(void) gicR3InfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
133	{
134	NOREF(pszArgs);
135	PVMCPU pVCpu = VMMGetCpu(pVM);
136	if (!pVCpu)
137	pVCpu = pVM->apCpusR3[0];
138
139	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
140
141	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
142	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicVCpu->u32RegIGrp0);
143	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicVCpu->u32RegICfg0);
144	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicVCpu->u32RegICfg1);
145	pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicVCpu->bmIntEnabled);
146	pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicVCpu->bmIntPending);
147	pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicVCpu->bmIntActive);
148	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
149	for (uint32_t i = 0; i < RT_ELEMENTS(pGicVCpu->abIntPriority); i++)
150	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", i, pGicVCpu->abIntPriority[i]);
151
152	pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
153	pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicVCpu->fIrqGrp0Enabled);
154	pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicVCpu->fIrqGrp1Enabled);
155	pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicVCpu->bInterruptPriority);
156	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicVCpu->bBinaryPointGrp0);
157	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicVCpu->bBinaryPointGrp1);
158	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicVCpu->idxRunningPriority);
159	pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicVCpu->abRunningPriorities[pGicVCpu->idxRunningPriority]);
160	}
161
162
163	/**
164	* Worker for saving per-VM GIC data.
165	*
166	* @returns VBox status code.
167	* @param pDevIns The device instance.
168	* @param pVM The cross context VM structure.
169	* @param pSSM The SSM handle.
170	*/
171	static int gicR3SaveVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
172	{
173	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
174	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
175
176	pHlp->pfnSSMPutU32( pSSM, pVM->cCpus);
177	pHlp->pfnSSMPutU32( pSSM, GIC_SPI_MAX);
178	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegIGrp0);
179	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg0);
180	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg1);
181	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntEnabled);
182	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntPending);
183	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntActive);
184	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
185	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp0Enabled);
186
187	return pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp1Enabled);
188	}
189
190
191	/**
192	* Worker for loading per-VM GIC data.
193	*
194	* @returns VBox status code.
195	* @param pDevIns The device instance.
196	* @param pVM The cross context VM structure.
197	* @param pSSM The SSM handle.
198	*/
199	static int gicR3LoadVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
200	{
201	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
202	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
203
204	/* Load and verify number of CPUs. */
205	uint32_t cCpus;
206	int rc = pHlp->pfnSSMGetU32(pSSM, &cCpus);
207	AssertRCReturn(rc, rc);
208	if (cCpus != pVM->cCpus)
209	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
210
211	/* Load and verify maximum number of SPIs. */
212	uint32_t cSpisMax;
213	rc = pHlp->pfnSSMGetU32(pSSM, &cSpisMax);
214	AssertRCReturn(rc, rc);
215	if (cSpisMax != GIC_SPI_MAX)
216	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cSpisMax: saved=%u config=%u"),
217	cSpisMax, GIC_SPI_MAX);
218
219	/* Load the state. */
220	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegIGrp0);
221	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg0);
222	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg1);
223	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntEnabled);
224	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntPending);
225	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntActive);
226	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
227	pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp0Enabled);
228	pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp1Enabled);
229
230	return VINF_SUCCESS;
231	}
232
233
234	/**
235	* @copydoc FNSSMDEVSAVEEXEC
236	*/
237	static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
238	{
239	PVM pVM = PDMDevHlpGetVM(pDevIns);
240	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
241
242	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
243
244	LogFlow(("GIC: gicR3SaveExec\n"));
245
246	/* Save per-VM data. */
247	int rc = gicR3SaveVMData(pDevIns, pVM, pSSM);
248	AssertRCReturn(rc, rc);
249
250	/* Save per-VCPU data.*/
251	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
252	{
253	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
254	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
255
256	/* Load the redistributor state. */
257	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegIGrp0);
258	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg0);
259	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg1);
260	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntEnabled);
261	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntPending);
262	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntActive);
263	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
264
265	pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp0Enabled);
266	pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp1Enabled);
267	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bInterruptPriority);
268	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp0);
269	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp1);
270	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
271	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->idxRunningPriority);
272	}
273
274	return rc;
275	}
276
277
278	/**
279	* @copydoc FNSSMDEVLOADEXEC
280	*/
281	static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
282	{
283	PVM pVM = PDMDevHlpGetVM(pDevIns);
284	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
285
286	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
287	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
288
289	LogFlow(("GIC: gicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
290
291	/* Weed out invalid versions. */
292	if (uVersion != GIC_SAVED_STATE_VERSION)
293	{
294	LogRel(("GIC: gicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
295	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
296	}
297
298	int rc = gicR3LoadVMData(pDevIns, pVM, pSSM);
299	AssertRCReturn(rc, rc);
300
301	/*
302	* Restore per CPU state.
303	*
304	* Note! PDM will restore the VMCPU_FF_INTERRUPT_IRQ and VMCPU_FF_INTERRUPT_FIQ flags for us.
305	* This code doesn't touch it. No devices should make us touch
306	* it later during the restore either, only during the 'done' phase.
307	*/
308	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
309	{
310	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
311	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
312
313	/* Load the redistributor state. */
314	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegIGrp0);
315	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg0);
316	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg1);
317	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntEnabled);
318	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntPending);
319	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntActive);
320	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
321
322	pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp0Enabled);
323	pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp1Enabled);
324	pHlp->pfnSSMGetU8V( pSSM, &pGicVCpu->bInterruptPriority);
325	pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp0);
326	pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp1);
327	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
328	rc = pHlp->pfnSSMGetU8V(pSSM, &pGicVCpu->idxRunningPriority);
329	if (RT_FAILURE(rc))
330	return rc;
331	}
332
333	return rc;
334	}
335
336
337	/**
338	* @interface_method_impl{PDMDEVREG,pfnReset}
339	*/
340	DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
341	{
342	PVM pVM = PDMDevHlpGetVM(pDevIns);
343	VM_ASSERT_EMT0(pVM);
344	VM_ASSERT_IS_NOT_RUNNING(pVM);
345
346	LogFlow(("GIC: gicR3Reset\n"));
347
348	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
349	{
350	PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
351
352	gicResetCpu(pVCpuDest);
353	}
354	}
355
356
357	/**
358	* @interface_method_impl{PDMDEVREG,pfnRelocate}
359	*/
360	DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
361	{
362	RT_NOREF(pDevIns, offDelta);
363	}
364
365
366	/**
367	* @interface_method_impl{PDMDEVREG,pfnDestruct}
368	*/
369	DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
370	{
371	LogFlowFunc(("pDevIns=%p\n", pDevIns));
372	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
373
374	return VINF_SUCCESS;
375	}
376
377
378	/**
379	* @interface_method_impl{PDMDEVREG,pfnConstruct}
380	*/
381	DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
382	{
383	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
384	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
385	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
386	PVM pVM = PDMDevHlpGetVM(pDevIns);
387	PGIC pGic = VM_TO_GIC(pVM);
388	Assert(iInstance == 0); NOREF(iInstance);
389
390	/*
391	* Init the data.
392	*/
393	pGic->pDevInsR3 = pDevIns;
394
395	/*
396	* Validate GIC settings.
397	*/
398	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase\|RedistributorMmioBase\|ItsMmioBase"
399	"\|ArchRev"
400	"\|Nmi"
401	"\|MaxSpi"
402	"\|MaxExtSpi"
403	"\|PpiNum", "");
404
405	#if 0
406	/*
407	* Disable automatic PDM locking for this device.
408	*/
409	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
410	AssertRCReturn(rc, rc);
411	#else
412	int rc;
413	#endif
414
415	/** @devcfgm{gic, ArchRev, uint8_t, 3}
416	* Configures the GIC architecture revision (GICD_PIDR2.ArchRev and
417	* GICR_PIDR2.ArchRev).
418	*
419	* Currently we only support GICv3. */
420	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRev", &pGicDev->uArchRev, 3);
421	AssertLogRelRCReturn(rc, rc);
422	if (pGicDev->uArchRev == 3)
423	{ /* likely */ }
424	else
425	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
426	N_("Configuration error: \"ArchRev\" value %u is not supported"), pGicDev->uArchRev);
427
428	/** @devcfgm{gic, Nmi, bool, false}
429	* Configures whether NMIs are supported (GICD_TYPER.NMI). */
430	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Nmi", &pGicDev->fNmi, false);
431	AssertLogRelRCReturn(rc, rc);
432
433	/** @devcfgm{gic, ExtSpi, bool, false}
434	* Configures whether extended SPIs are supported (GICD_TYPER.ESPI). */
435	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtSpi", &pGicDev->fExtSpi, false);
436	AssertLogRelRCReturn(rc, rc);
437
438	/** @devcfgm{gic, MaxSpi, uint16_t, 1}
439	* Configures GICD_TYPER.ItLinesNumber.
440	*
441	* For the INTID range [32,1023], configures the maximum SPI supported. Valid values
442	* are [1,31] which equates to interrupt IDs [63,1023]. A value of 0 implies SPIs
443	* are supported. We don't allow configuring this value as it's expected that
444	* most guests would assume support for SPIs. */
445	AssertCompile(GIC_DIST_REG_TYPER_NUM_ITLINES == 31);
446	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxSpi", &pGicDev->uMaxSpi, 1 /* 63 INTIDs */);
447	AssertLogRelRCReturn(rc, rc);
448	if (pGicDev->uMaxSpi - 1 < 31)
449	{ /* likely */ }
450	else
451	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
452	N_("Configuration error: \"MaxSpi\" must be in the range [1,%u]"),
453	GIC_DIST_REG_TYPER_NUM_ITLINES);
454
455	/** @devcfgm{gic, MaxExtSpi, uint16_t, 31}
456	* Configures GICD_TYPER.ESPI_range.
457	*
458	* For the extended SPI range [4096,5119], configures the maximum extended SPI
459	* supported. Valid values are [0,31] which equates to extended SPI INTIDs
460	* [4096,5119]. This is ignored (set to 0) when extended SPIs are disabled. */
461	AssertCompile(GIC_DIST_REG_TYPER_ESPI_RANGE >> GIC_DIST_REG_TYPER_ESPI_RANGE_BIT == 31);
462	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxExtSpi", &pGicDev->uMaxExtSpi, 31);
463	AssertLogRelRCReturn(rc, rc);
464	if (pGicDev->uMaxExtSpi <= 31)
465	{ /* likely */ }
466	else
467	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
468	N_("Configuration error: \"MaxExtSpi\" must be in the range [0,31]"));
469
470	/** @devcfgm{gic, MaxExtPpi, uint16_t, 0}
471	* Configures GICR_TYPER.PPInum.
472	*
473	* For the extended PPI INTIDs [31,1056,1119], configures the maximum extended
474	* PPI supported. Valid values are [0,1,2] which equates [31,1087,1119]. A value of
475	* 0 implies extended PPIs are not supported. */
476	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "PpiNum", &pGicDev->fPpiNum, 0);
477	AssertLogRelRCReturn(rc, rc);
478	if (pGicDev->fPpiNum <= GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
479	{ /* likely */ }
480	else
481	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
482	N_("Configuration error: \"PpiNum\" must be in the range [0,2]"));
483
484	/*
485	* Register the GIC with PDM.
486	*/
487	rc = PDMDevHlpIcRegister(pDevIns);
488	AssertLogRelRCReturn(rc, rc);
489
490	rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
491	AssertLogRelRCReturn(rc, rc);
492
493	/*
494	* Insert the GIC system registers.
495	*/
496	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GIC); i++)
497	{
498	rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GIC[i]);
499	AssertLogRelRCReturn(rc, rc);
500	}
501
502	/*
503	* Register the MMIO ranges.
504	*/
505	RTGCPHYS GCPhysMmioBase = 0;
506	rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
507	if (RT_FAILURE(rc))
508	return PDMDEV_SET_ERROR(pDevIns, rc,
509	N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
510
511	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
512	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC_Dist", &pGicDev->hMmioDist);
513	AssertRCReturn(rc, rc);
514
515	rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
516	if (RT_FAILURE(rc))
517	return PDMDEV_SET_ERROR(pDevIns, rc,
518	N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
519
520	RTGCPHYS cbRegion = (RTGCPHYS)pVM->cCpus * (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
521	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
522	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC_ReDist", &pGicDev->hMmioReDist);
523	AssertRCReturn(rc, rc);
524
525	/*
526	* Register saved state callbacks.
527	*/
528	rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
529	AssertRCReturn(rc, rc);
530
531	/*
532	* Register debugger info callbacks.
533	*
534	* We use separate callbacks rather than arguments so they can also be
535	* dumped in an automated fashion while collecting crash diagnostics and
536	* not just used during live debugging via the VM debugger.
537	*/
538	DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
539	DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC Distributor information.", gicR3InfoDist, DBGFINFO_FLAGS_ALL_EMTS);
540	DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC Redistributor information.", gicR3InfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
541
542	/*
543	* Statistics.
544	*/
545	#define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
546	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
547	STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
548	#define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
549	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
550	STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
551
552	#ifdef VBOX_WITH_STATISTICS
553	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
554	{
555	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
556	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
557
558	# if 0 /* No R0 for now. */
559	GIC_REG_COUNTER(&pGicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
560	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
561	GIC_REG_COUNTER(&pGicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
562	GIC_REG_COUNTER(&pGicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
563	# endif
564
565	GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/R3/MmioRead", "Number of APIC MMIO reads in R3.");
566	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/R3/MmioWrite", "Number of APIC MMIO writes in R3.");
567	GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/R3/SysRegRead", "Number of GIC system register reads in R3.");
568	GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/R3/SysRegWrite", "Number of GIC system register writes in R3.");
569	}
570	#endif
571
572	# undef GIC_PROF_COUNTER
573
574	gicR3Reset(pDevIns);
575	return VINF_SUCCESS;
576	}
577
578	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
579

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source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 108387

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