GICR3.cpp@ 108435

Last change on this file since 108435 was 108427, checked in by vboxsync, 2 months ago
VMM/GIC: bugref:10404 Extend the interrupt lines to the full extent supported by the GIC spec. Added range-selector support while broadcasting SGIs. Added highest priority interrupt calculation (still not complete, binary-point support is still a todo) Other miscellaneous changes related to the above.
Property svn:eol-style set to `native` Property svn:keywords set to `Author Date Id Revision`
File size: 28.8 KB

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1	/* $Id: GICR3.cpp 108427 2025-03-04 08:21:36Z vboxsync $ */
2	/** @file
3	* GIC - Generic Interrupt Controller Architecture (GIC).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_APIC
33	#include <VBox/log.h>
34	#include "GICInternal.h"
35	#include <VBox/vmm/pdmgic.h>
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/pdmdev.h>
40	#include <VBox/vmm/ssm.h>
41	#include <VBox/vmm/vm.h>
42
43	#include <iprt/armv8.h>
44
45
46	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	/** GIC saved state version. */
53	#define GIC_SAVED_STATE_VERSION 1
54
55	# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
56	{ (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicIcc, kCpumSysRegWrFn_GicIcc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57
58
59	/*********************************************************************************************************************************
60	* Global Variables *
61	*********************************************************************************************************************************/
62	/**
63	* System register ranges for the GIC.
64	*/
65	static CPUMSYSREGRANGE const g_aSysRegRanges_GIC[] =
66	{
67	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
68	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
69	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
70	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
71	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
72	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2"),
73	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, "ICC_SRE_EL3")
74	};
75
76
77	/**
78	* Dumps basic APIC state.
79	*
80	* @param pVM The cross context VM structure.
81	* @param pHlp The info helpers.
82	* @param pszArgs Arguments, ignored.
83	*/
84	static DECLCALLBACK(void) gicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
85	{
86	RT_NOREF(pszArgs);
87
88	PCGIC pGic = VM_TO_GIC(pVM);
89	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
90	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
91
92	pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
93	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->bmIntrGroup[0]);
94	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->bmIntrConfig[0]);
95	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->bmIntrConfig[1]);
96	pHlp->pfnPrintf(pHlp, " bmIntrEnabled = %#RX32\n", pGicDev->bmIntrEnabled[0]);
97	pHlp->pfnPrintf(pHlp, " bmIntrPending = %#RX32\n", pGicDev->bmIntrPending[0]);
98	pHlp->pfnPrintf(pHlp, " bmIntrActive = %#RX32\n", pGicDev->bmIntrActive[0]);
99
100	PVMCPU pVCpu = VMMGetCpu(pVM);
101	if (!pVCpu)
102	pVCpu = pVM->apCpusR3[0];
103	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
104
105	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
106	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicCpu->bmIntrGroup[0]);
107	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicCpu->bmIntrConfig[0]);
108	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicCpu->bmIntrConfig[1]);
109	pHlp->pfnPrintf(pHlp, " bmIntrEnabled = %#RX32\n", pGicCpu->bmIntrEnabled[0]);
110	pHlp->pfnPrintf(pHlp, " bmIntrPending = %#RX32\n", pGicCpu->bmIntrPending[0]);
111	pHlp->pfnPrintf(pHlp, " bmIntrActive = %#RX32\n", pGicCpu->bmIntrActive[0]);
112
113	pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
114	pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicCpu->fIrqGrp0Enabled);
115	pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicCpu->fIrqGrp1Enabled);
116	pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicCpu->bInterruptPriority);
117	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicCpu->bBinaryPointGrp0);
118	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicCpu->bBinaryPointGrp1);
119	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicCpu->idxRunningPriority);
120	pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicCpu->abRunningPriorities[pGicCpu->idxRunningPriority]);
121	}
122
123
124	/**
125	* Dumps GIC Distributor information.
126	*
127	* @param pVM The cross context VM structure.
128	* @param pHlp The info helpers.
129	* @param pszArgs Arguments, ignored.
130	*/
131	static DECLCALLBACK(void) gicR3InfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
132	{
133	RT_NOREF(pszArgs);
134
135	PGIC pGic = VM_TO_GIC(pVM);
136	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
137	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
138
139	pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
140	#if 0
141	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->u32RegIGrp0);
142	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->u32RegICfg0);
143	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->u32RegICfg1);
144	pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicDev->bmIntEnabled);
145	pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicDev->bmIntPending);
146	pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicDev->bmIntActive);
147	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
148	for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntPriority); i++)
149	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->abIntPriority[i]);
150
151	pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
152	for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->au32IntRouting); i++)
153	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->au32IntRouting[i]);
154	#else
155	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->bmIntrGroup[0]);
156	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->bmIntrConfig[0]);
157	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->bmIntrConfig[1]);
158	pHlp->pfnPrintf(pHlp, " bmIntrEnabled = %#RX32\n", pGicDev->bmIntrEnabled[0]);
159	pHlp->pfnPrintf(pHlp, " bmIntrPending = %#RX32\n", pGicDev->bmIntrPending[0]);
160	pHlp->pfnPrintf(pHlp, " bmIntrActive = %#RX32\n", pGicDev->bmIntrActive[0]);
161	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
162	for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntrPriority); i++)
163	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", gicDistGetIntIdFromIndex(i), pGicDev->abIntrPriority[i]);
164	pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
165	for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->au32IntrRouting); i++)
166	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", gicDistGetIntIdFromIndex(i), pGicDev->au32IntrRouting[i]);
167	#endif
168
169	pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicDev->fIrqGrp0Enabled);
170	pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicDev->fIrqGrp1Enabled);
171	}
172
173
174	/**
175	* Dumps the GIC Redistributor information.
176	*
177	* @param pVM The cross context VM structure.
178	* @param pHlp The info helpers.
179	* @param pszArgs Arguments, ignored.
180	*/
181	static DECLCALLBACK(void) gicR3InfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
182	{
183	NOREF(pszArgs);
184	PVMCPU pVCpu = VMMGetCpu(pVM);
185	if (!pVCpu)
186	pVCpu = pVM->apCpusR3[0];
187
188	#if 0
189	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
190
191	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
192	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicVCpu->u32RegIGrp0);
193	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicVCpu->u32RegICfg0);
194	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicVCpu->u32RegICfg1);
195	pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicVCpu->bmIntEnabled);
196	pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicVCpu->bmIntPending);
197	pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicVCpu->bmIntActive);
198	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
199	for (uint32_t i = 0; i < RT_ELEMENTS(pGicVCpu->abIntPriority); i++)
200	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", i, pGicVCpu->abIntPriority[i]);
201
202	pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
203	pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicVCpu->fIrqGrp0Enabled);
204	pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicVCpu->fIrqGrp1Enabled);
205	pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicVCpu->bInterruptPriority);
206	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicVCpu->bBinaryPointGrp0);
207	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicVCpu->bBinaryPointGrp1);
208	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicVCpu->idxRunningPriority);
209	pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicVCpu->abRunningPriorities[pGicVCpu->idxRunningPriority]);
210	#else
211	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
212
213	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
214	pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicCpu->bmIntrGroup[0]);
215	pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicCpu->bmIntrConfig[0]);
216	pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicCpu->bmIntrConfig[1]);
217	pHlp->pfnPrintf(pHlp, " bmIntrEnabled = %#RX32\n", pGicCpu->bmIntrEnabled[0]);
218	pHlp->pfnPrintf(pHlp, " bmIntrPending = %#RX32\n", pGicCpu->bmIntrPending[0]);
219	pHlp->pfnPrintf(pHlp, " bmIntrActive = %#RX32\n", pGicCpu->bmIntrActive[0]);
220	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
221	for (uint32_t i = 0; i < RT_ELEMENTS(pGicCpu->abIntrPriority); i++)
222	pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", gicReDistGetIntIdFromIndex(i), pGicCpu->abIntrPriority[i]);
223
224	pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
225	pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicCpu->fIrqGrp0Enabled);
226	pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicCpu->fIrqGrp1Enabled);
227	pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicCpu->bInterruptPriority);
228	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicCpu->bBinaryPointGrp0);
229	pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicCpu->bBinaryPointGrp1);
230	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicCpu->idxRunningPriority);
231	pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicCpu->abRunningPriorities[pGicCpu->idxRunningPriority]);
232	#endif
233	}
234
235
236	#if 0
237	/**
238	* Worker for saving per-VM GIC data.
239	*
240	* @returns VBox status code.
241	* @param pDevIns The device instance.
242	* @param pVM The cross context VM structure.
243	* @param pSSM The SSM handle.
244	*/
245	static int gicR3SaveVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
246	{
247	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
248	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
249
250	pHlp->pfnSSMPutU32( pSSM, pVM->cCpus);
251	pHlp->pfnSSMPutU32( pSSM, GIC_SPI_MAX);
252	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegIGrp0);
253	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg0);
254	pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg1);
255	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntEnabled);
256	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntPending);
257	pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntActive);
258	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
259	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp0Enabled);
260
261	return pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp1Enabled);
262	}
263	#endif
264
265
266	#if 0
267	/**
268	* Worker for loading per-VM GIC data.
269	*
270	* @returns VBox status code.
271	* @param pDevIns The device instance.
272	* @param pVM The cross context VM structure.
273	* @param pSSM The SSM handle.
274	*/
275	static int gicR3LoadVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
276	{
277	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
278	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
279
280	/* Load and verify number of CPUs. */
281	uint32_t cCpus;
282	int rc = pHlp->pfnSSMGetU32(pSSM, &cCpus);
283	AssertRCReturn(rc, rc);
284	if (cCpus != pVM->cCpus)
285	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
286
287	/* Load and verify maximum number of SPIs. */
288	uint32_t cSpisMax;
289	rc = pHlp->pfnSSMGetU32(pSSM, &cSpisMax);
290	AssertRCReturn(rc, rc);
291	if (cSpisMax != GIC_SPI_MAX)
292	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cSpisMax: saved=%u config=%u"),
293	cSpisMax, GIC_SPI_MAX);
294
295	/* Load the state. */
296	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegIGrp0);
297	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg0);
298	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg1);
299	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntEnabled);
300	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntPending);
301	pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntActive);
302	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
303	pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp0Enabled);
304	pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp1Enabled);
305
306	return VINF_SUCCESS;
307	}
308	#endif
309
310
311	/**
312	* @copydoc FNSSMDEVSAVEEXEC
313	*/
314	static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
315	{
316	#if 0
317	PVM pVM = PDMDevHlpGetVM(pDevIns);
318	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
319
320	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
321
322	LogFlow(("GIC: gicR3SaveExec\n"));
323
324	/* Save per-VM data. */
325	int rc = gicR3SaveVMData(pDevIns, pVM, pSSM);
326	AssertRCReturn(rc, rc);
327
328	/* Save per-VCPU data.*/
329	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
330	{
331	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
332	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
333
334	/* Load the redistributor state. */
335	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegIGrp0);
336	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg0);
337	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg1);
338	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntEnabled);
339	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntPending);
340	pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntActive);
341	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
342
343	pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp0Enabled);
344	pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp1Enabled);
345	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bInterruptPriority);
346	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp0);
347	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp1);
348	pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
349	pHlp->pfnSSMPutU8( pSSM, pGicVCpu->idxRunningPriority);
350	}
351
352	return rc;
353	#else
354	RT_NOREF2(pDevIns, pSSM);
355	return VERR_NOT_IMPLEMENTED;
356	#endif
357	}
358
359
360	/**
361	* @copydoc FNSSMDEVLOADEXEC
362	*/
363	static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
364	{
365	#if 0
366	PVM pVM = PDMDevHlpGetVM(pDevIns);
367	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
368
369	AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
370	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
371
372	LogFlow(("GIC: gicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
373
374	/* Weed out invalid versions. */
375	if (uVersion != GIC_SAVED_STATE_VERSION)
376	{
377	LogRel(("GIC: gicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
378	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
379	}
380
381	int rc = gicR3LoadVMData(pDevIns, pVM, pSSM);
382	AssertRCReturn(rc, rc);
383
384	/*
385	* Restore per CPU state.
386	*
387	* Note! PDM will restore the VMCPU_FF_INTERRUPT_IRQ and VMCPU_FF_INTERRUPT_FIQ flags for us.
388	* This code doesn't touch it. No devices should make us touch
389	* it later during the restore either, only during the 'done' phase.
390	*/
391	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
392	{
393	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
394	PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
395
396	/* Load the redistributor state. */
397	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegIGrp0);
398	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg0);
399	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg1);
400	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntEnabled);
401	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntPending);
402	pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntActive);
403	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
404
405	pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp0Enabled);
406	pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp1Enabled);
407	pHlp->pfnSSMGetU8V( pSSM, &pGicVCpu->bInterruptPriority);
408	pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp0);
409	pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp1);
410	pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
411	rc = pHlp->pfnSSMGetU8V(pSSM, &pGicVCpu->idxRunningPriority);
412	if (RT_FAILURE(rc))
413	return rc;
414	}
415
416	return rc;
417	#else
418	RT_NOREF4(pDevIns, pSSM, uVersion, uPass);
419	return VERR_NOT_IMPLEMENTED;
420	#endif
421	}
422
423
424	/**
425	* @interface_method_impl{PDMDEVREG,pfnReset}
426	*/
427	DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
428	{
429	PVM pVM = PDMDevHlpGetVM(pDevIns);
430	VM_ASSERT_EMT0(pVM);
431	VM_ASSERT_IS_NOT_RUNNING(pVM);
432
433	LogFlow(("GIC: gicR3Reset\n"));
434
435	gicReset(pDevIns);
436	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
437	{
438	#if 0
439	PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
440
441	gicResetCpu(pVCpuDest);
442	#else
443	PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
444	gicResetCpu(pDevIns, pVCpuDest);
445	#endif
446	}
447	}
448
449
450	/**
451	* @interface_method_impl{PDMDEVREG,pfnRelocate}
452	*/
453	DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
454	{
455	RT_NOREF(pDevIns, offDelta);
456	}
457
458
459	/**
460	* @interface_method_impl{PDMDEVREG,pfnDestruct}
461	*/
462	DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
463	{
464	LogFlowFunc(("pDevIns=%p\n", pDevIns));
465	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
466
467	return VINF_SUCCESS;
468	}
469
470
471	/**
472	* @interface_method_impl{PDMDEVREG,pfnConstruct}
473	*/
474	DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
475	{
476	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
477	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
478	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
479	PVM pVM = PDMDevHlpGetVM(pDevIns);
480	PGIC pGic = VM_TO_GIC(pVM);
481	Assert(iInstance == 0); NOREF(iInstance);
482
483	/*
484	* Init the data.
485	*/
486	pGic->pDevInsR3 = pDevIns;
487
488	/*
489	* Validate GIC settings.
490	*/
491	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase\|RedistributorMmioBase\|ItsMmioBase"
492	"\|ArchRev"
493	"\|Nmi"
494	"\|MaxSpi"
495	"\|MaxExtSpi"
496	"\|PpiNum", "");
497
498	#if 0
499	/*
500	* Disable automatic PDM locking for this device.
501	*/
502	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
503	AssertRCReturn(rc, rc);
504	#else
505	int rc;
506	#endif
507
508	/** @devcfgm{gic, ArchRev, uint8_t, 3}
509	* Configures the GIC architecture revision (GICD_PIDR2.ArchRev and
510	* GICR_PIDR2.ArchRev).
511	*
512	* Currently we only support GICv3. */
513	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRev", &pGicDev->uArchRev, 3);
514	AssertLogRelRCReturn(rc, rc);
515	if (pGicDev->uArchRev == 3)
516	{ /* likely */ }
517	else
518	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
519	N_("Configuration error: \"ArchRev\" value %u is not supported"), pGicDev->uArchRev);
520
521	/** @devcfgm{gic, Nmi, bool, false}
522	* Configures whether NMIs are supported (GICD_TYPER.NMI). */
523	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Nmi", &pGicDev->fNmi, false);
524	AssertLogRelRCReturn(rc, rc);
525
526	/** @devcfgm{gic, ExtSpi, bool, false}
527	* Configures whether extended SPIs are supported (GICD_TYPER.ESPI). */
528	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtSpi", &pGicDev->fExtSpi, false);
529	AssertLogRelRCReturn(rc, rc);
530
531	/** @devcfgm{gic, MaxSpi, uint16_t, 1}
532	* Configures GICD_TYPER.ItLinesNumber.
533	*
534	* For the INTID range [32,1023], configures the maximum SPI supported. Valid values
535	* are [1,31] which equates to interrupt IDs [63,1023]. A value of 0 implies SPIs
536	* are not supported. We don't allow configuring this value as it's expected that
537	* most guests would assume support for SPIs. */
538	AssertCompile(GIC_DIST_REG_TYPER_NUM_ITLINES == 31);
539	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxSpi", &pGicDev->uMaxSpi, 1 /* 63 INTIDs */);
540	AssertLogRelRCReturn(rc, rc);
541	if (pGicDev->uMaxSpi - 1 < 31)
542	{ /* likely */ }
543	else
544	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
545	N_("Configuration error: \"MaxSpi\" must be in the range [1,%u]"),
546	GIC_DIST_REG_TYPER_NUM_ITLINES);
547
548	/** @devcfgm{gic, MaxExtSpi, uint16_t, 31}
549	* Configures GICD_TYPER.ESPI_range.
550	*
551	* For the extended SPI range [4096,5119], configures the maximum extended SPI
552	* supported. Valid values are [0,31] which equates to extended SPI INTIDs
553	* [4096,5119]. This is ignored (set to 0) when extended SPIs are disabled. */
554	AssertCompile(GIC_DIST_REG_TYPER_ESPI_RANGE >> GIC_DIST_REG_TYPER_ESPI_RANGE_BIT == 31);
555	rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxExtSpi", &pGicDev->uMaxExtSpi, 31);
556	AssertLogRelRCReturn(rc, rc);
557	if (pGicDev->uMaxExtSpi <= 31)
558	{ /* likely */ }
559	else
560	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
561	N_("Configuration error: \"MaxExtSpi\" must be in the range [0,31]"));
562
563	/** @devcfgm{gic, MaxExtPpi, uint16_t, 0}
564	* Configures GICR_TYPER.PPInum.
565	*
566	* For the extended PPI INTIDs [31,1056,1119], configures the maximum extended
567	* PPI supported. Valid values are [0,1,2] which equates [31,1087,1119]. A value of
568	* 0 implies extended PPIs are not supported. */
569	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "PpiNum", &pGicDev->fPpiNum, 0);
570	AssertLogRelRCReturn(rc, rc);
571	if (pGicDev->fPpiNum <= GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
572	{ /* likely */ }
573	else
574	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
575	N_("Configuration error: \"PpiNum\" must be in the range [0,2]"));
576
577	/** @devcfgm{gic, ExtSpi, bool, false}
578	* Configures whether range-selector support is enabled (GICD_TYPER.RSS and
579	* ICC_CTLR_EL1.RSS). */
580	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RangeSelSupport", &pGicDev->fRangeSelSupport, true);
581	AssertLogRelRCReturn(rc, rc);
582
583	/*
584	* Register the GIC with PDM.
585	*/
586	rc = PDMDevHlpIcRegister(pDevIns);
587	AssertLogRelRCReturn(rc, rc);
588
589	rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
590	AssertLogRelRCReturn(rc, rc);
591
592	/*
593	* Insert the GIC system registers.
594	*/
595	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GIC); i++)
596	{
597	rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GIC[i]);
598	AssertLogRelRCReturn(rc, rc);
599	}
600
601	/*
602	* Register the MMIO ranges.
603	*/
604	RTGCPHYS GCPhysMmioBase = 0;
605	rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
606	if (RT_FAILURE(rc))
607	return PDMDEV_SET_ERROR(pDevIns, rc,
608	N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
609
610	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
611	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC_Dist", &pGicDev->hMmioDist);
612	AssertRCReturn(rc, rc);
613
614	rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
615	if (RT_FAILURE(rc))
616	return PDMDEV_SET_ERROR(pDevIns, rc,
617	N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
618
619	RTGCPHYS cbRegion = (RTGCPHYS)pVM->cCpus * (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
620	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
621	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC_ReDist", &pGicDev->hMmioReDist);
622	AssertRCReturn(rc, rc);
623
624	/*
625	* Register saved state callbacks.
626	*/
627	rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
628	AssertRCReturn(rc, rc);
629
630	/*
631	* Register debugger info callbacks.
632	*
633	* We use separate callbacks rather than arguments so they can also be
634	* dumped in an automated fashion while collecting crash diagnostics and
635	* not just used during live debugging via the VM debugger.
636	*/
637	DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
638	DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC Distributor information.", gicR3InfoDist, DBGFINFO_FLAGS_ALL_EMTS);
639	DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC Redistributor information.", gicR3InfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
640
641	/*
642	* Statistics.
643	*/
644	#define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
645	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
646	STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
647	#define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
648	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
649	STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
650
651	#ifdef VBOX_WITH_STATISTICS
652	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
653	{
654	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
655	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
656
657	# if 0 /* No R0 for now. */
658	GIC_REG_COUNTER(&pGicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
659	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
660	GIC_REG_COUNTER(&pGicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
661	GIC_REG_COUNTER(&pGicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
662	# endif
663
664	GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/R3/MmioRead", "Number of APIC MMIO reads in R3.");
665	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/R3/MmioWrite", "Number of APIC MMIO writes in R3.");
666	GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/R3/SysRegRead", "Number of GIC system register reads in R3.");
667	GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/R3/SysRegWrite", "Number of GIC system register writes in R3.");
668	}
669	#endif
670
671	# undef GIC_PROF_COUNTER
672
673	gicR3Reset(pDevIns);
674	return VINF_SUCCESS;
675	}
676
677	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
678

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source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 108435

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