VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 108443

Last change on this file since 108443 was 108443, checked in by vboxsync, 2 months ago

VMM/GIC: bugref:10404 Fixes to the interrupt priority logic which fixes hang during arm64 Windows 11 guest boot.
Other minor cleanups.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Author Date Id Revision
File size: 36.1 KB
Line 
1/* $Id: GICR3.cpp 108443 2025-03-04 20:15:22Z vboxsync $ */
2/** @file
3 * GIC - Generic Interrupt Controller Architecture (GIC).
4 */
5
6/*
7 * Copyright (C) 2023-2024 Oracle and/or its affiliates.
8 *
9 * This file is part of VirtualBox base platform packages, as
10 * available from https://www.virtualbox.org.
11 *
12 * This program is free software; you can redistribute it and/or
13 * modify it under the terms of the GNU General Public License
14 * as published by the Free Software Foundation, in version 3 of the
15 * License.
16 *
17 * This program is distributed in the hope that it will be useful, but
18 * WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20 * General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, see <https://www.gnu.org/licenses>.
24 *
25 * SPDX-License-Identifier: GPL-3.0-only
26 */
27
28
29/*********************************************************************************************************************************
30* Header Files *
31*********************************************************************************************************************************/
32#define LOG_GROUP LOG_GROUP_DEV_APIC
33#include <VBox/log.h>
34#include "GICInternal.h"
35#include <VBox/vmm/pdmgic.h>
36#include <VBox/vmm/cpum.h>
37#include <VBox/vmm/hm.h>
38#include <VBox/vmm/mm.h>
39#include <VBox/vmm/pdmdev.h>
40#include <VBox/vmm/ssm.h>
41#include <VBox/vmm/vm.h>
42
43#include <iprt/armv8.h>
44
45
46#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49/*********************************************************************************************************************************
50* Defined Constants And Macros *
51*********************************************************************************************************************************/
52/** GIC saved state version. */
53#define GIC_SAVED_STATE_VERSION 2
54
55# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
56 { (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicIcc, kCpumSysRegWrFn_GicIcc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57
58
59/*********************************************************************************************************************************
60* Global Variables *
61*********************************************************************************************************************************/
62/**
63 * System register ranges for the GIC.
64 */
65static CPUMSYSREGRANGE const g_aSysRegRanges_GIC[] =
66{
67 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
68 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
69 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
70 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
71 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
72 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2"),
73 GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, "ICC_SRE_EL3")
74};
75
76
77/**
78 * Dumps basic APIC state.
79 *
80 * @param pVM The cross context VM structure.
81 * @param pHlp The info helpers.
82 * @param pszArgs Arguments, ignored.
83 */
84static DECLCALLBACK(void) gicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
85{
86 RT_NOREF(pszArgs);
87
88 PCGIC pGic = VM_TO_GIC(pVM);
89 PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
90 PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
91
92 pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
93 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->bmIntrGroup[0]);
94 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->bmIntrConfig[0]);
95 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->bmIntrConfig[1]);
96 pHlp->pfnPrintf(pHlp, " bmIntrEnabled = %#RX32\n", pGicDev->bmIntrEnabled[0]);
97 pHlp->pfnPrintf(pHlp, " bmIntrPending = %#RX32\n", pGicDev->bmIntrPending[0]);
98 pHlp->pfnPrintf(pHlp, " bmIntrActive = %#RX32\n", pGicDev->bmIntrActive[0]);
99
100 PVMCPU pVCpu = VMMGetCpu(pVM);
101 if (!pVCpu)
102 pVCpu = pVM->apCpusR3[0];
103 PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
104
105 pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
106 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicCpu->bmIntrGroup[0]);
107 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicCpu->bmIntrConfig[0]);
108 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicCpu->bmIntrConfig[1]);
109 pHlp->pfnPrintf(pHlp, " bmIntrEnabled = %#RX32\n", pGicCpu->bmIntrEnabled[0]);
110 pHlp->pfnPrintf(pHlp, " bmIntrPending = %#RX32\n", pGicCpu->bmIntrPending[0]);
111 pHlp->pfnPrintf(pHlp, " bmIntrActive = %#RX32\n", pGicCpu->bmIntrActive[0]);
112
113 pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
114 pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicCpu->fIntrGroup0Enabled);
115 pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicCpu->fIntrGroup1Enabled);
116 pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicCpu->bInterruptPriority);
117 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicCpu->bBinaryPointGrp0);
118 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicCpu->bBinaryPointGrp1);
119 pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicCpu->idxRunningPriority);
120 pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicCpu->abRunningPriorities[pGicCpu->idxRunningPriority]);
121}
122
123
124/**
125 * Dumps GIC Distributor information.
126 *
127 * @param pVM The cross context VM structure.
128 * @param pHlp The info helpers.
129 * @param pszArgs Arguments, ignored.
130 */
131static DECLCALLBACK(void) gicR3InfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
132{
133 RT_NOREF(pszArgs);
134
135 PGIC pGic = VM_TO_GIC(pVM);
136 PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
137 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
138
139 pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
140#if 0
141 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->u32RegIGrp0);
142 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->u32RegICfg0);
143 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->u32RegICfg1);
144 pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicDev->bmIntEnabled);
145 pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicDev->bmIntPending);
146 pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicDev->bmIntActive);
147 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
148 for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntPriority); i++)
149 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->abIntPriority[i]);
150
151 pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
152 for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->au32IntRouting); i++)
153 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", GIC_INTID_RANGE_SPI_START + i, pGicDev->au32IntRouting[i]);
154#else
155 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicDev->bmIntrGroup[0]);
156 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicDev->bmIntrConfig[0]);
157 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicDev->bmIntrConfig[1]);
158 pHlp->pfnPrintf(pHlp, " bmIntrEnabled = %#RX32\n", pGicDev->bmIntrEnabled[0]);
159 pHlp->pfnPrintf(pHlp, " bmIntrPending = %#RX32\n", pGicDev->bmIntrPending[0]);
160 pHlp->pfnPrintf(pHlp, " bmIntrActive = %#RX32\n", pGicDev->bmIntrActive[0]);
161 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
162 for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->abIntrPriority); i++)
163 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", gicDistGetIntIdFromIndex(i), pGicDev->abIntrPriority[i]);
164 pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
165 for (uint32_t i = 0; i < RT_ELEMENTS(pGicDev->au32IntrRouting); i++)
166 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", gicDistGetIntIdFromIndex(i), pGicDev->au32IntrRouting[i]);
167#endif
168
169 pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicDev->fIntrGroup0Enabled);
170 pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicDev->fIntrGroup1Enabled);
171}
172
173
174/**
175 * Dumps the GIC Redistributor information.
176 *
177 * @param pVM The cross context VM structure.
178 * @param pHlp The info helpers.
179 * @param pszArgs Arguments, ignored.
180 */
181static DECLCALLBACK(void) gicR3InfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
182{
183 NOREF(pszArgs);
184 PVMCPU pVCpu = VMMGetCpu(pVM);
185 if (!pVCpu)
186 pVCpu = pVM->apCpusR3[0];
187
188#if 0
189 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
190
191 pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
192 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicVCpu->u32RegIGrp0);
193 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicVCpu->u32RegICfg0);
194 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicVCpu->u32RegICfg1);
195 pHlp->pfnPrintf(pHlp, " bmIntEnabled = %#RX32\n", pGicVCpu->bmIntEnabled);
196 pHlp->pfnPrintf(pHlp, " bmIntPending = %#RX32\n", pGicVCpu->bmIntPending);
197 pHlp->pfnPrintf(pHlp, " bmIntActive = %#RX32\n", pGicVCpu->bmIntActive);
198 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
199 for (uint32_t i = 0; i < RT_ELEMENTS(pGicVCpu->abIntPriority); i++)
200 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", i, pGicVCpu->abIntPriority[i]);
201
202 pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
203 pHlp->pfnPrintf(pHlp, " fIrqGrp0Enabled = %RTbool\n", pGicVCpu->fIrqGrp0Enabled);
204 pHlp->pfnPrintf(pHlp, " fIrqGrp1Enabled = %RTbool\n", pGicVCpu->fIrqGrp1Enabled);
205 pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicVCpu->bInterruptPriority);
206 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicVCpu->bBinaryPointGrp0);
207 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicVCpu->bBinaryPointGrp1);
208 pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicVCpu->idxRunningPriority);
209 pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicVCpu->abRunningPriorities[pGicVCpu->idxRunningPriority]);
210#else
211 PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
212
213 pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
214 pHlp->pfnPrintf(pHlp, " IGRP0 = %#RX32\n", pGicCpu->bmIntrGroup[0]);
215 pHlp->pfnPrintf(pHlp, " ICFG0 = %#RX32\n", pGicCpu->bmIntrConfig[0]);
216 pHlp->pfnPrintf(pHlp, " ICFG1 = %#RX32\n", pGicCpu->bmIntrConfig[1]);
217 pHlp->pfnPrintf(pHlp, " bmIntrEnabled = %#RX32\n", pGicCpu->bmIntrEnabled[0]);
218 pHlp->pfnPrintf(pHlp, " bmIntrPending = %#RX32\n", pGicCpu->bmIntrPending[0]);
219 pHlp->pfnPrintf(pHlp, " bmIntrActive = %#RX32\n", pGicCpu->bmIntrActive[0]);
220 pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
221 for (uint32_t i = 0; i < RT_ELEMENTS(pGicCpu->abIntrPriority); i++)
222 pHlp->pfnPrintf(pHlp, " INTID %u = %u\n", gicReDistGetIntIdFromIndex(i), pGicCpu->abIntrPriority[i]);
223
224 pHlp->pfnPrintf(pHlp, "VCPU[%u] ICC state:\n", pVCpu->idCpu);
225 pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicCpu->fIntrGroup0Enabled);
226 pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicCpu->fIntrGroup1Enabled);
227 pHlp->pfnPrintf(pHlp, " bInterruptPriority = %u\n", pGicCpu->bInterruptPriority);
228 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp0 = %u\n", pGicCpu->bBinaryPointGrp0);
229 pHlp->pfnPrintf(pHlp, " bBinaryPointGrp1 = %u\n", pGicCpu->bBinaryPointGrp1);
230 pHlp->pfnPrintf(pHlp, " idxRunningPriority = %u\n", pGicCpu->idxRunningPriority);
231 pHlp->pfnPrintf(pHlp, " Running priority = %u\n", pGicCpu->abRunningPriorities[pGicCpu->idxRunningPriority]);
232#endif
233}
234
235
236#if 0
237/**
238 * Worker for saving per-VM GIC data.
239 *
240 * @returns VBox status code.
241 * @param pDevIns The device instance.
242 * @param pVM The cross context VM structure.
243 * @param pSSM The SSM handle.
244 */
245static int gicR3SaveVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
246{
247 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
248 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
249
250 pHlp->pfnSSMPutU32( pSSM, pVM->cCpus);
251 pHlp->pfnSSMPutU32( pSSM, GIC_SPI_MAX);
252 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegIGrp0);
253 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg0);
254 pHlp->pfnSSMPutU32( pSSM, pGicDev->u32RegICfg1);
255 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntEnabled);
256 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntPending);
257 pHlp->pfnSSMPutU32( pSSM, pGicDev->bmIntActive);
258 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
259 pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp0Enabled);
260
261 return pHlp->pfnSSMPutBool(pSSM, pGicDev->fIrqGrp1Enabled);
262}
263#endif
264
265
266#if 0
267/**
268 * Worker for loading per-VM GIC data.
269 *
270 * @returns VBox status code.
271 * @param pDevIns The device instance.
272 * @param pVM The cross context VM structure.
273 * @param pSSM The SSM handle.
274 */
275static int gicR3LoadVMData(PPDMDEVINS pDevIns, PVM pVM, PSSMHANDLE pSSM)
276{
277 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
278 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
279
280 /* Load and verify number of CPUs. */
281 uint32_t cCpus;
282 int rc = pHlp->pfnSSMGetU32(pSSM, &cCpus);
283 AssertRCReturn(rc, rc);
284 if (cCpus != pVM->cCpus)
285 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cCpus: saved=%u config=%u"), cCpus, pVM->cCpus);
286
287 /* Load and verify maximum number of SPIs. */
288 uint32_t cSpisMax;
289 rc = pHlp->pfnSSMGetU32(pSSM, &cSpisMax);
290 AssertRCReturn(rc, rc);
291 if (cSpisMax != GIC_SPI_MAX)
292 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch - cSpisMax: saved=%u config=%u"),
293 cSpisMax, GIC_SPI_MAX);
294
295 /* Load the state. */
296 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegIGrp0);
297 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg0);
298 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->u32RegICfg1);
299 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntEnabled);
300 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntPending);
301 pHlp->pfnSSMGetU32V( pSSM, &pGicDev->bmIntActive);
302 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicDev->abIntPriority[0], sizeof(pGicDev->abIntPriority));
303 pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp0Enabled);
304 pHlp->pfnSSMGetBoolV(pSSM, &pGicDev->fIrqGrp1Enabled);
305
306 return VINF_SUCCESS;
307}
308#endif
309
310
311/**
312 * @copydoc FNSSMDEVSAVEEXEC
313 */
314static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
315{
316#if 0
317 PVM pVM = PDMDevHlpGetVM(pDevIns);
318 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
319
320 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
321
322 LogFlow(("GIC: gicR3SaveExec\n"));
323
324 /* Save per-VM data. */
325 int rc = gicR3SaveVMData(pDevIns, pVM, pSSM);
326 AssertRCReturn(rc, rc);
327
328 /* Save per-VCPU data.*/
329 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
330 {
331 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
332 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
333
334 /* Load the redistributor state. */
335 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegIGrp0);
336 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg0);
337 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->u32RegICfg1);
338 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntEnabled);
339 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntPending);
340 pHlp->pfnSSMPutU32( pSSM, pGicVCpu->bmIntActive);
341 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
342
343 pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp0Enabled);
344 pHlp->pfnSSMPutBool(pSSM, pGicVCpu->fIrqGrp1Enabled);
345 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bInterruptPriority);
346 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp0);
347 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->bBinaryPointGrp1);
348 pHlp->pfnSSMPutMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
349 pHlp->pfnSSMPutU8( pSSM, pGicVCpu->idxRunningPriority);
350 }
351
352 return rc;
353#else
354
355 PCVM pVM = PDMDevHlpGetVM(pDevIns);
356 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
357 PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
358 AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
359 LogFlowFunc(("\n"));
360
361#define GIC_SSM_PUT_ARRAY(a_pfnSSM, a_Array) \
362 do \
363 { \
364 pHlp->pfnSSMPutU32(pSSM, RT_ELEMENTS(a_Array)); \
365 for (uint32_t i = 0; i < RT_ELEMENTS(a_Array); i++) \
366 (a_pfnSSM)(pSSM, (a_Array)[i]); \
367 } while (0)
368
369 /*
370 * Save per-VM data.
371 */
372 pHlp->pfnSSMPutU32(pSSM, pVM->cCpus);
373 pHlp->pfnSSMPutU8(pSSM, pGicDev->uArchRev);
374 pHlp->pfnSSMPutBool(pSSM, pGicDev->fNmi);
375 /** @todo I am not sure we really benefit offering this amount of customization
376 * right now. It makes the code way more complicated (lots of extra bounds
377 * checking in lots of places we cannot really test) and it only reduces
378 * functionality rather than increase it in the end. */
379#if 0
380 pHlp->pfnSSMPutU16(pSSM, pGicDev->uMaxSpi);
381 pHlp->pfnSSMPutU16(pSSM, pGicDev->uMaxExtSpi);
382 pHlp->pfnSSMPutU8(pSSM, pGicDev->fPpiNum);
383 pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtSpi);
384 pHlp->pfnSSMPutBool(pSSM, pGicDev->fRangeSelSupport);
385#endif
386 pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup0Enabled);
387 pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup1Enabled);
388 pHlp->pfnSSMPutBool(pSSM, pGicDev->fAffRoutingEnabled);
389 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicDev->bmIntrGroup);
390 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicDev->bmIntrConfig);
391 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicDev->bmIntrEnabled);
392 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicDev->bmIntrPending);
393 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicDev->bmIntrActive);
394 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU8, pGicDev->abIntrPriority);
395 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicDev->au32IntrRouting);
396 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicDev->bmIntrRoutingMode);
397
398 /*
399 * Save per-VCPU data.
400 */
401 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
402 {
403 PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
404 Assert(pGicCpu);
405
406 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicCpu->bmIntrGroup);
407 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicCpu->bmIntrConfig);
408 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicCpu->bmIntrEnabled);
409 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicCpu->bmIntrPending);
410 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU32, pGicCpu->bmIntrActive);
411 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU8, pGicCpu->abIntrPriority);
412
413 pHlp->pfnSSMPutU64(pSSM, pGicCpu->uIccCtlr);
414 GIC_SSM_PUT_ARRAY(pHlp->pfnSSMPutU8, pGicCpu->abRunningPriorities);
415 pHlp->pfnSSMPutU8(pSSM, pGicCpu->idxRunningPriority);
416 pHlp->pfnSSMPutU8(pSSM, pGicCpu->bInterruptPriority);
417 pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPointGrp0);
418 pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPointGrp1);
419 pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup0Enabled);
420 pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup1Enabled);
421 }
422
423 return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
424#undef GIC_SSM_PUT_ARRAY
425#endif
426}
427
428
429/**
430 * @copydoc FNSSMDEVLOADEXEC
431 */
432static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
433{
434#if 0
435 PVM pVM = PDMDevHlpGetVM(pDevIns);
436 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
437
438 AssertReturn(pVM, VERR_INVALID_VM_HANDLE);
439 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
440
441 LogFlow(("GIC: gicR3LoadExec: uVersion=%u uPass=%#x\n", uVersion, uPass));
442
443 /* Weed out invalid versions. */
444 if (uVersion != GIC_SAVED_STATE_VERSION)
445 {
446 LogRel(("GIC: gicR3LoadExec: Invalid/unrecognized saved-state version %u (%#x)\n", uVersion, uVersion));
447 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
448 }
449
450 int rc = gicR3LoadVMData(pDevIns, pVM, pSSM);
451 AssertRCReturn(rc, rc);
452
453 /*
454 * Restore per CPU state.
455 *
456 * Note! PDM will restore the VMCPU_FF_INTERRUPT_IRQ and VMCPU_FF_INTERRUPT_FIQ flags for us.
457 * This code doesn't touch it. No devices should make us touch
458 * it later during the restore either, only during the 'done' phase.
459 */
460 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
461 {
462 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
463 PGICCPU pGicVCpu = VMCPU_TO_GICCPU(pVCpu);
464
465 /* Load the redistributor state. */
466 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegIGrp0);
467 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg0);
468 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->u32RegICfg1);
469 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntEnabled);
470 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntPending);
471 pHlp->pfnSSMGetU32V( pSSM, &pGicVCpu->bmIntActive);
472 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abIntPriority[0], sizeof(pGicVCpu->abIntPriority));
473
474 pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp0Enabled);
475 pHlp->pfnSSMGetBoolV( pSSM, &pGicVCpu->fIrqGrp1Enabled);
476 pHlp->pfnSSMGetU8V( pSSM, &pGicVCpu->bInterruptPriority);
477 pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp0);
478 pHlp->pfnSSMGetU8( pSSM, &pGicVCpu->bBinaryPointGrp1);
479 pHlp->pfnSSMGetMem( pSSM, (void *)&pGicVCpu->abRunningPriorities[0], sizeof(pGicVCpu->abRunningPriorities));
480 rc = pHlp->pfnSSMGetU8V(pSSM, &pGicVCpu->idxRunningPriority);
481 if (RT_FAILURE(rc))
482 return rc;
483 }
484
485 return rc;
486#else
487 PVM pVM = PDMDevHlpGetVM(pDevIns);
488 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
489
490 AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
491 AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
492 LogFlowFunc(("uVersion=%u uPass=%#x\n", uVersion, uPass));
493
494 /*
495 * Validate supported saved-state versions.
496 */
497 if (uVersion != GIC_SAVED_STATE_VERSION)
498 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid saved-state version %u (%#x)"), uVersion, uVersion);
499
500#define GIC_SSM_GET_ARRAY(a_pfnSSM, a_Array) \
501 do \
502 { \
503 uint32_t cItems = 0; \
504 uint32_t const cExpected = RT_ELEMENTS(a_Array); \
505 int const rcSsm = pHlp->pfnSSMGetU32(pSSM, &cItems); \
506 AssertRCReturn(rcSsm, rcSsm); \
507 if (cItems != cExpected) \
508 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, \
509 N_("Config mismatch: number of elements in " RT_STR(a_Array) ": got=%u expected=%u"), \
510 cItems, cExpected); \
511 for (uint32_t i = 0; i < cExpected; i++) \
512 (a_pfnSSM)(pSSM, &(a_Array)[i]); \
513 } while (0)
514
515 /*
516 * Load per-VM data.
517 */
518 uint32_t cCpus;
519 pHlp->pfnSSMGetU32(pSSM, &cCpus);
520 if (cCpus != pVM->cCpus)
521 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cCpus: got=%u expected=%u"), cCpus, pVM->cCpus);
522
523 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
524 pHlp->pfnSSMGetU8(pSSM, &pGicDev->uArchRev);
525 pHlp->pfnSSMGetBool(pSSM, &pGicDev->fNmi);
526#if 0
527 pHlp->pfnSSMGetU16(pSSM, &pGicDev->uMaxSpi);
528 pHlp->pfnSSMGetU16(pSSM, &pGicDev->uMaxExtSpi);
529 pHlp->pfnSSMGetU8(pSSM, &pGicDev->fPpiNum);
530 pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtSpi);
531 pHlp->pfnSSMGetBool(pSSM, &pGicDev->fRangeSelSupport);
532#endif
533 pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup0Enabled);
534 pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup1Enabled);
535 pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAffRoutingEnabled);
536 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicDev->bmIntrGroup);
537 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicDev->bmIntrConfig);
538 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicDev->bmIntrEnabled);
539 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicDev->bmIntrPending);
540 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicDev->bmIntrActive);
541 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU8, pGicDev->abIntrPriority);
542 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicDev->au32IntrRouting);
543 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicDev->bmIntrRoutingMode);
544
545 /*
546 * Load per-VCPU data.
547 */
548 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
549 {
550 PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
551 Assert(pGicCpu);
552
553 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicCpu->bmIntrGroup);
554 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicCpu->bmIntrConfig);
555 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicCpu->bmIntrEnabled);
556 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicCpu->bmIntrPending);
557 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU32, pGicCpu->bmIntrActive);
558 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU8, pGicCpu->abIntrPriority);
559
560 pHlp->pfnSSMGetU64(pSSM, &pGicCpu->uIccCtlr);
561 GIC_SSM_GET_ARRAY(pHlp->pfnSSMGetU8, pGicCpu->abRunningPriorities);
562 pHlp->pfnSSMGetU8(pSSM, &pGicCpu->idxRunningPriority);
563 pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bInterruptPriority);
564 pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPointGrp0);
565 pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPointGrp1);
566 pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup0Enabled);
567 pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup1Enabled);
568 }
569
570 /*
571 * Check that we're still good wrt restored data.
572 */
573 int rc = pHlp->pfnSSMHandleGetStatus(pSSM);
574 AssertRCReturn(rc, rc);
575
576 uint32_t uMarker = 0;
577 rc = pHlp->pfnSSMGetU32(pSSM, &uMarker);
578 AssertRCReturn(rc, rc);
579 if (uMarker == UINT32_MAX)
580 { /* likely */ }
581 else
582 return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Marker: got=%u expected=%u"), uMarker, UINT32_MAX);
583 return rc;
584#undef GIC_SSM_GET_ARRAY
585#endif
586}
587
588
589/**
590 * @interface_method_impl{PDMDEVREG,pfnReset}
591 */
592DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
593{
594 PVM pVM = PDMDevHlpGetVM(pDevIns);
595 VM_ASSERT_EMT0(pVM);
596 VM_ASSERT_IS_NOT_RUNNING(pVM);
597
598 LogFlow(("GIC: gicR3Reset\n"));
599
600 gicReset(pDevIns);
601 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
602 {
603#if 0
604 PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
605
606 gicResetCpu(pVCpuDest);
607#else
608 PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
609 gicResetCpu(pDevIns, pVCpuDest);
610#endif
611 }
612}
613
614
615/**
616 * @interface_method_impl{PDMDEVREG,pfnRelocate}
617 */
618DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
619{
620 RT_NOREF(pDevIns, offDelta);
621}
622
623
624/**
625 * @interface_method_impl{PDMDEVREG,pfnDestruct}
626 */
627DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
628{
629 LogFlowFunc(("pDevIns=%p\n", pDevIns));
630 PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
631
632 return VINF_SUCCESS;
633}
634
635
636/**
637 * @interface_method_impl{PDMDEVREG,pfnConstruct}
638 */
639DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
640{
641 PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
642 PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
643 PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
644 PVM pVM = PDMDevHlpGetVM(pDevIns);
645 PGIC pGic = VM_TO_GIC(pVM);
646 Assert(iInstance == 0); NOREF(iInstance);
647
648 /*
649 * Init the data.
650 */
651 pGic->pDevInsR3 = pDevIns;
652
653 /*
654 * Validate GIC settings.
655 */
656 PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase|RedistributorMmioBase|ItsMmioBase"
657 "|ArchRev"
658 "|Nmi"
659 "|MaxSpi"
660 "|MaxExtSpi"
661 "|PpiNum", "");
662
663#if 0
664 /*
665 * Disable automatic PDM locking for this device.
666 */
667 int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
668 AssertRCReturn(rc, rc);
669#else
670 int rc;
671#endif
672
673 /** @devcfgm{gic, ArchRev, uint8_t, 3}
674 * Configures the GIC architecture revision (GICD_PIDR2.ArchRev and
675 * GICR_PIDR2.ArchRev).
676 *
677 * Currently we only support GICv3. */
678 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRev", &pGicDev->uArchRev, 3);
679 AssertLogRelRCReturn(rc, rc);
680 if (pGicDev->uArchRev == 3)
681 { /* likely */ }
682 else
683 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
684 N_("Configuration error: \"ArchRev\" value %u is not supported"), pGicDev->uArchRev);
685
686 /** @devcfgm{gic, Nmi, bool, false}
687 * Configures whether NMIs are supported (GICD_TYPER.NMI). */
688 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Nmi", &pGicDev->fNmi, false);
689 AssertLogRelRCReturn(rc, rc);
690
691 /** @devcfgm{gic, ExtSpi, bool, false}
692 * Configures whether extended SPIs are supported (GICD_TYPER.ESPI). */
693 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtSpi", &pGicDev->fExtSpi, false);
694 AssertLogRelRCReturn(rc, rc);
695
696 /** @devcfgm{gic, MaxSpi, uint16_t, 1}
697 * Configures GICD_TYPER.ItLinesNumber.
698 *
699 * For the INTID range [32,1023], configures the maximum SPI supported. Valid values
700 * are [1,31] which equates to interrupt IDs [63,1023]. A value of 0 implies SPIs
701 * are not supported. We don't allow configuring this value as it's expected that
702 * most guests would assume support for SPIs. */
703 AssertCompile(GIC_DIST_REG_TYPER_NUM_ITLINES == 31);
704 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxSpi", &pGicDev->uMaxSpi, 1 /* 63 INTIDs */);
705 AssertLogRelRCReturn(rc, rc);
706 if (pGicDev->uMaxSpi - 1 < 31)
707 { /* likely */ }
708 else
709 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
710 N_("Configuration error: \"MaxSpi\" must be in the range [1,%u]"),
711 GIC_DIST_REG_TYPER_NUM_ITLINES);
712
713 /** @devcfgm{gic, MaxExtSpi, uint16_t, 31}
714 * Configures GICD_TYPER.ESPI_range.
715 *
716 * For the extended SPI range [4096,5119], configures the maximum extended SPI
717 * supported. Valid values are [0,31] which equates to extended SPI INTIDs
718 * [4096,5119]. This is ignored (set to 0) when extended SPIs are disabled. */
719 AssertCompile(GIC_DIST_REG_TYPER_ESPI_RANGE >> GIC_DIST_REG_TYPER_ESPI_RANGE_BIT == 31);
720 rc = pHlp->pfnCFGMQueryU16Def(pCfg, "MaxExtSpi", &pGicDev->uMaxExtSpi, 31);
721 AssertLogRelRCReturn(rc, rc);
722 if (pGicDev->uMaxExtSpi <= 31)
723 { /* likely */ }
724 else
725 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
726 N_("Configuration error: \"MaxExtSpi\" must be in the range [0,31]"));
727
728 /** @devcfgm{gic, MaxExtPpi, uint16_t, 0}
729 * Configures GICR_TYPER.PPInum.
730 *
731 * For the extended PPI INTIDs [31,1056,1119], configures the maximum extended
732 * PPI supported. Valid values are [0,1,2] which equates [31,1087,1119]. A value of
733 * 0 implies extended PPIs are not supported. */
734 rc = pHlp->pfnCFGMQueryU8Def(pCfg, "PpiNum", &pGicDev->fPpiNum, 0);
735 AssertLogRelRCReturn(rc, rc);
736 if (pGicDev->fPpiNum <= GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
737 { /* likely */ }
738 else
739 return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
740 N_("Configuration error: \"PpiNum\" must be in the range [0,2]"));
741
742 /** @devcfgm{gic, ExtSpi, bool, false}
743 * Configures whether range-selector support is enabled (GICD_TYPER.RSS and
744 * ICC_CTLR_EL1.RSS). */
745 rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RangeSelSupport", &pGicDev->fRangeSelSupport, true);
746 AssertLogRelRCReturn(rc, rc);
747
748 /*
749 * Register the GIC with PDM.
750 */
751 rc = PDMDevHlpIcRegister(pDevIns);
752 AssertLogRelRCReturn(rc, rc);
753
754 rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
755 AssertLogRelRCReturn(rc, rc);
756
757 /*
758 * Insert the GIC system registers.
759 */
760 for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GIC); i++)
761 {
762 rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GIC[i]);
763 AssertLogRelRCReturn(rc, rc);
764 }
765
766 /*
767 * Register the MMIO ranges.
768 */
769 RTGCPHYS GCPhysMmioBase = 0;
770 rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
771 if (RT_FAILURE(rc))
772 return PDMDEV_SET_ERROR(pDevIns, rc,
773 N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
774
775 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
776 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC_Dist", &pGicDev->hMmioDist);
777 AssertRCReturn(rc, rc);
778
779 rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
780 if (RT_FAILURE(rc))
781 return PDMDEV_SET_ERROR(pDevIns, rc,
782 N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
783
784 RTGCPHYS cbRegion = (RTGCPHYS)pVM->cCpus * (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
785 rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
786 IOMMMIO_FLAGS_READ_DWORD | IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC_ReDist", &pGicDev->hMmioReDist);
787 AssertRCReturn(rc, rc);
788
789 /*
790 * Register saved state callbacks.
791 */
792 rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
793 AssertRCReturn(rc, rc);
794
795 /*
796 * Register debugger info callbacks.
797 *
798 * We use separate callbacks rather than arguments so they can also be
799 * dumped in an automated fashion while collecting crash diagnostics and
800 * not just used during live debugging via the VM debugger.
801 */
802 DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
803 DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC Distributor information.", gicR3InfoDist, DBGFINFO_FLAGS_ALL_EMTS);
804 DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC Redistributor information.", gicR3InfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
805
806 /*
807 * Statistics.
808 */
809#define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
810 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, \
811 STAMUNIT_OCCURENCES, a_pszDesc, a_pszNameFmt, idCpu)
812#define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
813 PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, \
814 STAMUNIT_TICKS_PER_CALL, a_pszDesc, a_pszNameFmt, idCpu)
815
816#ifdef VBOX_WITH_STATISTICS
817 for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
818 {
819 PVMCPU pVCpu = pVM->apCpusR3[idCpu];
820 PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
821
822# if 0 /* No R0 for now. */
823 GIC_REG_COUNTER(&pGicCpu->StatMmioReadRZ, "%u/RZ/MmioRead", "Number of APIC MMIO reads in RZ.");
824 GIC_REG_COUNTER(&pGicCpu->StatMmioWriteRZ, "%u/RZ/MmioWrite", "Number of APIC MMIO writes in RZ.");
825 GIC_REG_COUNTER(&pGicCpu->StatMsrReadRZ, "%u/RZ/MsrRead", "Number of APIC MSR reads in RZ.");
826 GIC_REG_COUNTER(&pGicCpu->StatMsrWriteRZ, "%u/RZ/MsrWrite", "Number of APIC MSR writes in RZ.");
827# endif
828
829 GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/R3/MmioRead", "Number of APIC MMIO reads in R3.");
830 GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/R3/MmioWrite", "Number of APIC MMIO writes in R3.");
831 GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/R3/SysRegRead", "Number of GIC system register reads in R3.");
832 GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/R3/SysRegWrite", "Number of GIC system register writes in R3.");
833 }
834#endif
835
836# undef GIC_PROF_COUNTER
837
838 gicR3Reset(pDevIns);
839 return VINF_SUCCESS;
840}
841
842#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
843
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