GICR3.cpp@ 108531

Last change on this file since 108531 was 108531, checked in by vboxsync, 6 weeks ago
VMM/GIC: bugref:10404 Log GIC features/config.
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1	/* $Id: GICR3.cpp 108531 2025-03-12 10:12:19Z vboxsync $ */
2	/** @file
3	* GIC - Generic Interrupt Controller Architecture (GIC).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_GIC
33	#include <VBox/log.h>
34	#include "GICInternal.h"
35	#include <VBox/vmm/pdmgic.h>
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/pdmdev.h>
40	#include <VBox/vmm/ssm.h>
41	#include <VBox/vmm/vm.h>
42
43	#include <iprt/armv8.h>
44
45
46	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	/** GIC saved state version. */
53	#define GIC_SAVED_STATE_VERSION 6
54
55	# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
56	{ (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicIcc, kCpumSysRegWrFn_GicIcc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57
58
59	/*********************************************************************************************************************************
60	* Global Variables *
61	*********************************************************************************************************************************/
62	/**
63	* System register ranges for the GIC.
64	*/
65	static CPUMSYSREGRANGE const g_aSysRegRanges_GIC[] =
66	{
67	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
68	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
69	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
70	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
71	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
72	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2"),
73	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, "ICC_SRE_EL3")
74	};
75
76
77	/**
78	* Dumps basic GIC state.
79	*
80	* @param pVM The cross context VM structure.
81	* @param pHlp The info helpers.
82	* @param pszArgs Arguments, ignored.
83	*/
84	static DECLCALLBACK(void) gicR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
85	{
86	RT_NOREF(pszArgs);
87	PCGIC pGic = VM_TO_GIC(pVM);
88	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
89	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
90
91	pHlp->pfnPrintf(pHlp, "GIC:\n");
92	pHlp->pfnPrintf(pHlp, " uArchRev = %u\n", pGicDev->uArchRev);
93	pHlp->pfnPrintf(pHlp, " uMaxSpi = %u (upto IntId %u)\n", pGicDev->uMaxSpi, 32 * (pGicDev->uMaxSpi + 1));
94	pHlp->pfnPrintf(pHlp, " fExtSpi = %RTbool\n", pGicDev->fExtSpi);
95	pHlp->pfnPrintf(pHlp, " uMaxExtSpi = %u (upto IntId %u)\n", pGicDev->uMaxExtSpi,
96	GIC_INTID_RANGE_EXT_SPI_START - 1 + 32 * (pGicDev->uMaxExtSpi + 1));
97	pHlp->pfnPrintf(pHlp, " fExtPpi = %RTbool\n", pGicDev->fExtPpi);
98	pHlp->pfnPrintf(pHlp, " uMaxExtPpi = %u (upto IntId %u)\n", pGicDev->uMaxExtPpi,
99	pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 ? 1087 : GIC_INTID_RANGE_EXT_PPI_LAST);
100	pHlp->pfnPrintf(pHlp, " fRangeSelSupport = %RTbool\n", pGicDev->fRangeSel);
101	pHlp->pfnPrintf(pHlp, " fNmi = %RTbool\n", pGicDev->fNmi);
102	pHlp->pfnPrintf(pHlp, " fMbi = %RTbool\n", pGicDev->fMbi);
103	pHlp->pfnPrintf(pHlp, " fAff3Levels = %RTbool\n", pGicDev->fAff3Levels);
104	}
105
106
107	/**
108	* Dumps GIC Distributor information.
109	*
110	* @param pVM The cross context VM structure.
111	* @param pHlp The info helpers.
112	* @param pszArgs Arguments, ignored.
113	*/
114	static DECLCALLBACK(void) gicR3InfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
115	{
116	RT_NOREF(pszArgs);
117
118	PGIC pGic = VM_TO_GIC(pVM);
119	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
120	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
121
122	#define GIC_DBGFINFO_DIST_INTR_BITMAP(a_Name, a_bmIntr) \
123	do \
124	{ \
125	pHlp->pfnPrintf(pHlp, " " a_Name " =\n"); \
126	for (uint32_t i = 0; i < RT_ELEMENTS(a_bmIntr); i += 8) \
127	pHlp->pfnPrintf(pHlp, " [%2u..%-2u] %#010x %#010x %#010x %#010x %#010x %#010x %#010x %#010x\n", i, i + 7, \
128	(a_bmIntr)[i], (a_bmIntr)[i+1], (a_bmIntr)[i+2], (a_bmIntr)[i+3], \
129	(a_bmIntr)[i+4], (a_bmIntr)[i+5], (a_bmIntr)[i+6], (a_bmIntr)[i+7]); \
130	} while (0)
131
132	pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
133	pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicDev->fIntrGroup0Enabled);
134	pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicDev->fIntrGroup1Enabled);
135	pHlp->pfnPrintf(pHlp, " fAffRoutingEnabled = %RTbool\n", pGicDev->fAffRoutingEnabled);
136	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrGroup", pGicDev->bmIntrGroup);
137	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrEnabled", pGicDev->bmIntrEnabled);
138	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrPending", pGicDev->bmIntrPending);
139	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrActive", pGicDev->bmIntrActive);
140
141	/* Interrupt priorities.*/
142	{
143	uint32_t const cPriorities = RT_ELEMENTS(pGicDev->abIntrPriority);
144	AssertCompile(!(cPriorities % 16));
145	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
146	for (uint32_t i = 0; i < cPriorities; i += 16)
147	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
148	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
149	gicDistGetIntIdFromIndex(i), gicDistGetIntIdFromIndex(i + 7),
150	pGicDev->abIntrPriority[i], pGicDev->abIntrPriority[i + 1],
151	pGicDev->abIntrPriority[i + 2], pGicDev->abIntrPriority[i + 3],
152	pGicDev->abIntrPriority[i + 4], pGicDev->abIntrPriority[i + 5],
153	pGicDev->abIntrPriority[i + 6], pGicDev->abIntrPriority[i + 7],
154	gicDistGetIntIdFromIndex(i + 8), gicDistGetIntIdFromIndex(i + 15),
155	pGicDev->abIntrPriority[i + 8], pGicDev->abIntrPriority[i + 9],
156	pGicDev->abIntrPriority[i + 10], pGicDev->abIntrPriority[i + 11],
157	pGicDev->abIntrPriority[i + 12], pGicDev->abIntrPriority[i + 13],
158	pGicDev->abIntrPriority[i + 14], pGicDev->abIntrPriority[i + 15]);
159	}
160
161	/* Interrupt routing.*/
162	{
163	/** @todo Interrupt rounting mode. */
164	uint32_t const cRouting = RT_ELEMENTS(pGicDev->au32IntrRouting);
165	AssertCompile(!(cRouting % 16));
166	pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
167	for (uint32_t i = 0; i < cRouting; i += 16)
168	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
169	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
170	gicDistGetIntIdFromIndex(i), gicDistGetIntIdFromIndex(i + 7),
171	pGicDev->au32IntrRouting[i], pGicDev->au32IntrRouting[i + 1],
172	pGicDev->au32IntrRouting[i + 2], pGicDev->au32IntrRouting[i + 3],
173	pGicDev->au32IntrRouting[i + 4], pGicDev->au32IntrRouting[i + 5],
174	pGicDev->au32IntrRouting[i + 6], pGicDev->au32IntrRouting[i + 7],
175	gicDistGetIntIdFromIndex(i + 8), gicDistGetIntIdFromIndex(i + 15),
176	pGicDev->au32IntrRouting[i + 8], pGicDev->au32IntrRouting[i + 9],
177	pGicDev->au32IntrRouting[i + 10], pGicDev->au32IntrRouting[i + 11],
178	pGicDev->au32IntrRouting[i + 12], pGicDev->au32IntrRouting[i + 13],
179	pGicDev->au32IntrRouting[i + 14], pGicDev->au32IntrRouting[i + 15]);
180	}
181
182	#undef GIC_DBGFINFO_DIST_INTR_BITMAP
183	}
184
185
186	/**
187	* Dumps the GIC Redistributor information.
188	*
189	* @param pVM The cross context VM structure.
190	* @param pHlp The info helpers.
191	* @param pszArgs Arguments, ignored.
192	*/
193	static DECLCALLBACK(void) gicR3InfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
194	{
195	NOREF(pszArgs);
196	PVMCPU pVCpu = VMMGetCpu(pVM);
197	if (!pVCpu)
198	pVCpu = pVM->apCpusR3[0];
199
200	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
201
202	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
203	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrGroup) >= 3);
204	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrEnabled) >= 3);
205	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrPending) >= 3);
206	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrActive) >= 3);
207	pHlp->pfnPrintf(pHlp, " bmIntrGroup[0..2] = %#010x %#010x %#010x\n", pGicCpu->bmIntrGroup[0], pGicCpu->bmIntrGroup[1], pGicCpu->bmIntrGroup[2]);
208	pHlp->pfnPrintf(pHlp, " bmIntrEnabled[0..2] = %#010x %#010x %#010x\n", pGicCpu->bmIntrEnabled[0], pGicCpu->bmIntrEnabled[1], pGicCpu->bmIntrEnabled[2]);
209	pHlp->pfnPrintf(pHlp, " bmIntrPending[0..2] = %#010x %#010x %#010x\n", pGicCpu->bmIntrPending[0], pGicCpu->bmIntrPending[1], pGicCpu->bmIntrPending[2]);
210	pHlp->pfnPrintf(pHlp, " bmIntrActive[0..2] = %#010x %#010x %#010x\n", pGicCpu->bmIntrActive[0], pGicCpu->bmIntrActive[1], pGicCpu->bmIntrActive[2]);
211
212	/* Interrupt priorities. */
213	{
214	uint32_t const cPriorities = RT_ELEMENTS(pGicCpu->abIntrPriority);
215	AssertCompile(!(cPriorities % 16));
216	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
217	for (uint32_t i = 0; i < cPriorities; i += 16)
218	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
219	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
220	gicReDistGetIntIdFromIndex(i), gicReDistGetIntIdFromIndex(i + 7),
221	pGicCpu->abIntrPriority[i], pGicCpu->abIntrPriority[i + 1],
222	pGicCpu->abIntrPriority[i + 2], pGicCpu->abIntrPriority[i + 3],
223	pGicCpu->abIntrPriority[i + 4], pGicCpu->abIntrPriority[i + 5],
224	pGicCpu->abIntrPriority[i + 6], pGicCpu->abIntrPriority[i + 7],
225	gicReDistGetIntIdFromIndex(i + 8), gicReDistGetIntIdFromIndex(i + 15),
226	pGicCpu->abIntrPriority[i + 8], pGicCpu->abIntrPriority[i + 9],
227	pGicCpu->abIntrPriority[i + 10], pGicCpu->abIntrPriority[i + 11],
228	pGicCpu->abIntrPriority[i + 12], pGicCpu->abIntrPriority[i + 13],
229	pGicCpu->abIntrPriority[i + 14], pGicCpu->abIntrPriority[i + 15]);
230	}
231
232	pHlp->pfnPrintf(pHlp, "\nVCPU[%u] ICC system register state:\n", pVCpu->idCpu);
233	pHlp->pfnPrintf(pHlp, " uIccCtlr = %#RX64\n", pGicCpu->uIccCtlr);
234	pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicCpu->fIntrGroup0Enabled);
235	pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicCpu->fIntrGroup1Enabled);
236	pHlp->pfnPrintf(pHlp, " bBinaryPtGroup0 = %#x\n", pGicCpu->bBinaryPtGroup0);
237	pHlp->pfnPrintf(pHlp, " bBinaryPtGroup1 = %#x\n", pGicCpu->bBinaryPtGroup1);
238	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %#x\n", pGicCpu->idxRunningPriority);
239	pHlp->pfnPrintf(pHlp, " Running priority = %#x\n", pGicCpu->abRunningPriorities[pGicCpu->idxRunningPriority]);
240
241	/* Running interrupt priorities. */
242	{
243	uint32_t const cPriorities = RT_ELEMENTS(pGicCpu->abRunningPriorities);
244	AssertCompile(!(cPriorities % 16));
245	pHlp->pfnPrintf(pHlp, " Running-interrupt priorities:\n");
246	for (uint32_t i = 0; i < cPriorities; i += 16)
247	pHlp->pfnPrintf(pHlp, " [%3u..%-3u] = %3u %3u %3u %3u %3u %3u %3u %3u"
248	" [%3u..%-3u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
249	i, i + 7,
250	pGicCpu->abRunningPriorities[i], pGicCpu->abRunningPriorities[i + 1],
251	pGicCpu->abRunningPriorities[i + 2], pGicCpu->abRunningPriorities[i + 3],
252	pGicCpu->abRunningPriorities[i + 4], pGicCpu->abRunningPriorities[i + 5],
253	pGicCpu->abRunningPriorities[i + 6], pGicCpu->abRunningPriorities[i + 7],
254	i + 8, i + 15,
255	pGicCpu->abRunningPriorities[i + 8], pGicCpu->abRunningPriorities[i + 9],
256	pGicCpu->abRunningPriorities[i + 10], pGicCpu->abRunningPriorities[i + 11],
257	pGicCpu->abRunningPriorities[i + 12], pGicCpu->abRunningPriorities[i + 13],
258	pGicCpu->abRunningPriorities[i + 14], pGicCpu->abRunningPriorities[i + 15]);
259	}
260
261	AssertCompile(RT_ELEMENTS(pGicCpu->bmActivePriorityGroup0) >= 4);
262	pHlp->pfnPrintf(pHlp, " Active-interrupt priorities Group 0:\n");
263	pHlp->pfnPrintf(pHlp, " [0..3] = %#010x %#010x %#010x %#010x\n",
264	pGicCpu->bmActivePriorityGroup0[0], pGicCpu->bmActivePriorityGroup0[1],
265	pGicCpu->bmActivePriorityGroup0[2], pGicCpu->bmActivePriorityGroup0[3]);
266	AssertCompile(RT_ELEMENTS(pGicCpu->bmActivePriorityGroup1) >= 4);
267	pHlp->pfnPrintf(pHlp, " Active-interrupt priorities Group 1:\n");
268	pHlp->pfnPrintf(pHlp, " [0..3] = %#010x %#010x %#010x %#010x\n",
269	pGicCpu->bmActivePriorityGroup1[0], pGicCpu->bmActivePriorityGroup1[1],
270	pGicCpu->bmActivePriorityGroup1[2], pGicCpu->bmActivePriorityGroup1[3]);
271	}
272
273
274	/**
275	* @copydoc FNSSMDEVSAVEEXEC
276	*/
277	static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
278	{
279	PCVM pVM = PDMDevHlpGetVM(pDevIns);
280	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
281	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
282	AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
283	LogFlowFunc(("\n"));
284
285	/*
286	* Save per-VM data.
287	*/
288	pHlp->pfnSSMPutU32(pSSM, pVM->cCpus);
289	pHlp->pfnSSMPutU8(pSSM, pGicDev->uArchRev);
290	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxSpi);
291	pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtSpi);
292	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxExtSpi);
293	pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtPpi);
294	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxExtPpi);
295	pHlp->pfnSSMPutBool(pSSM, pGicDev->fRangeSel);
296	pHlp->pfnSSMPutBool(pSSM, pGicDev->fNmi);
297	pHlp->pfnSSMPutBool(pSSM, pGicDev->fMbi);
298	pHlp->pfnSSMPutBool(pSSM, pGicDev->fAff3Levels);
299
300	/* Distributor state. */
301	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup0Enabled);
302	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup1Enabled);
303	pHlp->pfnSSMPutBool(pSSM, pGicDev->fAffRoutingEnabled);
304	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrGroup[0], sizeof(pGicDev->bmIntrGroup));
305	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrConfig[0], sizeof(pGicDev->bmIntrConfig));
306	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrEnabled[0], sizeof(pGicDev->bmIntrEnabled));
307	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrPending[0], sizeof(pGicDev->bmIntrPending));
308	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrActive[0], sizeof(pGicDev->bmIntrActive));
309	pHlp->pfnSSMPutMem(pSSM, &pGicDev->abIntrPriority[0], sizeof(pGicDev->abIntrPriority));
310	pHlp->pfnSSMPutMem(pSSM, &pGicDev->au32IntrRouting[0], sizeof(pGicDev->au32IntrRouting));
311	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrRoutingMode[0], sizeof(pGicDev->bmIntrRoutingMode));
312
313	/*
314	* Save per-VCPU data.
315	*/
316	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
317	{
318	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
319	Assert(pGicCpu);
320
321	/* Redistributor state. */
322	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrGroup[0], sizeof(pGicCpu->bmIntrGroup));
323	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrConfig[0], sizeof(pGicCpu->bmIntrConfig));
324	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrEnabled[0], sizeof(pGicCpu->bmIntrEnabled));
325	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrPending[0], sizeof(pGicCpu->bmIntrPending));
326	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrActive[0], sizeof(pGicCpu->bmIntrActive));
327	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->abIntrPriority[0], sizeof(pGicCpu->abIntrPriority));
328
329	/* ICC system register state. */
330	pHlp->pfnSSMPutU64(pSSM, pGicCpu->uIccCtlr);
331	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bIntrPriorityMask);
332	pHlp->pfnSSMPutU8(pSSM, pGicCpu->idxRunningPriority);
333	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->abRunningPriorities[0], sizeof(pGicCpu->abRunningPriorities));
334	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmActivePriorityGroup0[0], sizeof(pGicCpu->bmActivePriorityGroup0));
335	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmActivePriorityGroup1[0], sizeof(pGicCpu->bmActivePriorityGroup1));
336	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPtGroup0);
337	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPtGroup1);
338	pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup0Enabled);
339	pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup1Enabled);
340	}
341
342	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
343	}
344
345
346	/**
347	* @copydoc FNSSMDEVLOADEXEC
348	*/
349	static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
350	{
351	PVM pVM = PDMDevHlpGetVM(pDevIns);
352	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
353
354	AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
355	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
356	LogFlowFunc(("uVersion=%u uPass=%#x\n", uVersion, uPass));
357
358	/*
359	* Validate supported saved-state versions.
360	*/
361	if (uVersion != GIC_SAVED_STATE_VERSION)
362	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid saved-state version %u"), uVersion);
363
364	/*
365	* Load per-VM data.
366	*/
367	uint32_t cCpus;
368	pHlp->pfnSSMGetU32(pSSM, &cCpus);
369	if (cCpus != pVM->cCpus)
370	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cCpus: got=%u expected=%u"), cCpus, pVM->cCpus);
371
372	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
373	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uArchRev);
374	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxSpi);
375	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtSpi);
376	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxExtSpi);
377	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtPpi);
378	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxExtPpi);
379	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fRangeSel);
380	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fNmi);
381	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fMbi);
382	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAff3Levels);
383
384	/* Distributor state. */
385	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup0Enabled);
386	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup1Enabled);
387	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAffRoutingEnabled);
388	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrGroup[0], sizeof(pGicDev->bmIntrGroup));
389	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrConfig[0], sizeof(pGicDev->bmIntrConfig));
390	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrEnabled[0], sizeof(pGicDev->bmIntrEnabled));
391	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrPending[0], sizeof(pGicDev->bmIntrPending));
392	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrActive[0], sizeof(pGicDev->bmIntrActive));
393	pHlp->pfnSSMGetMem(pSSM, &pGicDev->abIntrPriority[0], sizeof(pGicDev->abIntrPriority));
394	pHlp->pfnSSMGetMem(pSSM, &pGicDev->au32IntrRouting[0], sizeof(pGicDev->au32IntrRouting));
395	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrRoutingMode[0], sizeof(pGicDev->bmIntrRoutingMode));
396
397	/*
398	* Load per-VCPU data.
399	*/
400	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
401	{
402	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
403	Assert(pGicCpu);
404
405	/* Redistributor state. */
406	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrGroup[0], sizeof(pGicCpu->bmIntrGroup));
407	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrConfig[0], sizeof(pGicCpu->bmIntrConfig));
408	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrEnabled[0], sizeof(pGicCpu->bmIntrEnabled));
409	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrPending[0], sizeof(pGicCpu->bmIntrPending));
410	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrActive[0], sizeof(pGicCpu->bmIntrActive));
411	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->abIntrPriority[0], sizeof(pGicCpu->abIntrPriority));
412
413	/* ICC system register state. */
414	pHlp->pfnSSMGetU64(pSSM, &pGicCpu->uIccCtlr);
415	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bIntrPriorityMask);
416	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->idxRunningPriority);
417	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->abRunningPriorities[0], sizeof(pGicCpu->abRunningPriorities));
418	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmActivePriorityGroup0[0], sizeof(pGicCpu->bmActivePriorityGroup0));
419	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmActivePriorityGroup1[0], sizeof(pGicCpu->bmActivePriorityGroup1));
420	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPtGroup0);
421	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPtGroup1);
422	pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup0Enabled);
423	pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup1Enabled);
424	}
425
426	/*
427	* Check that we're still good wrt restored data.
428	*/
429	int rc = pHlp->pfnSSMHandleGetStatus(pSSM);
430	AssertRCReturn(rc, rc);
431
432	uint32_t uMarker = 0;
433	rc = pHlp->pfnSSMGetU32(pSSM, &uMarker);
434	AssertRCReturn(rc, rc);
435	if (uMarker == UINT32_MAX)
436	{ /* likely */ }
437	else
438	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Marker: got=%u expected=%u"), uMarker, UINT32_MAX);
439
440	/*
441	* Finally, perform sanity checks.
442	*/
443	if (pGicDev->uArchRev <= GIC_DIST_REG_PIDR2_ARCH_REV_GICV4)
444	{ /* likely */ }
445	else
446	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid uArchRev, got %u expected range [1,31]"), pGicDev->uArchRev,
447	GIC_DIST_REG_PIDR2_ARCH_REV_GICV1, GIC_DIST_REG_PIDR2_ARCH_REV_GICV4);
448	if (pGicDev->uMaxSpi - 1 < 31)
449	{ /* likely */ }
450	else
451	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxSpi, got %u expected range [1,31]"), pGicDev->uMaxSpi);
452	if (pGicDev->uMaxExtSpi <= 31)
453	{ /* likely */ }
454	else
455	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxExtSpi, got %u expected range [0,31]"), pGicDev->uMaxExtSpi);
456	if ( pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087
457	\|\| pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
458	{ /* likely */ }
459	else
460	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxExtPpi, got %u expected range [1,2]"), pGicDev->uMaxExtPpi);
461	return rc;
462	}
463
464
465	/**
466	* @interface_method_impl{PDMDEVREG,pfnReset}
467	*/
468	DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
469	{
470	PVM pVM = PDMDevHlpGetVM(pDevIns);
471	VM_ASSERT_EMT0(pVM);
472	VM_ASSERT_IS_NOT_RUNNING(pVM);
473
474	LogFlow(("GIC: gicR3Reset\n"));
475
476	gicReset(pDevIns);
477	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
478	{
479	PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
480	gicResetCpu(pDevIns, pVCpuDest);
481	}
482	}
483
484
485	/**
486	* @interface_method_impl{PDMDEVREG,pfnRelocate}
487	*/
488	DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
489	{
490	RT_NOREF(pDevIns, offDelta);
491	}
492
493
494	/**
495	* @interface_method_impl{PDMDEVREG,pfnDestruct}
496	*/
497	DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
498	{
499	LogFlowFunc(("pDevIns=%p\n", pDevIns));
500	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
501
502	return VINF_SUCCESS;
503	}
504
505
506	/**
507	* @interface_method_impl{PDMDEVREG,pfnConstruct}
508	*/
509	DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
510	{
511	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
512	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
513	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
514	PVM pVM = PDMDevHlpGetVM(pDevIns);
515	PGIC pGic = VM_TO_GIC(pVM);
516	Assert(iInstance == 0); NOREF(iInstance);
517
518	/*
519	* Init the data.
520	*/
521	pGic->pDevInsR3 = pDevIns;
522
523	/*
524	* Validate GIC settings.
525	*/
526	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase\|RedistributorMmioBase\|ItsMmioBase"
527	"\|ArchRev"
528	"\|MaxSpi"
529	"\|ExtSpi"
530	"\|MaxExtSpi"
531	"\|ExtPpi"
532	"\|MaxExtPpi"
533	"\|RangeSel"
534	"\|Nmi"
535	"\|Mbi"
536	"\|Aff3Levels", "");
537
538	#if 0
539	/*
540	* Disable automatic PDM locking for this device.
541	*/
542	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
543	AssertRCReturn(rc, rc);
544	#endif
545
546	/** @devcfgm{gic, ArchRev, uint8_t, 3}
547	* Configures the GIC architecture revision (GICD_PIDR2.ArchRev and
548	* GICR_PIDR2.ArchRev).
549	*
550	* Currently we only support GICv3. */
551	int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRev", &pGicDev->uArchRev, 3);
552	AssertLogRelRCReturn(rc, rc);
553	if (pGicDev->uArchRev == 3)
554	{ /* likely */ }
555	else
556	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
557	N_("Configuration error: \"ArchRev\" value %u is not supported"), pGicDev->uArchRev);
558
559	/** @devcfgm{gic, MaxSpi, uint8_t, 31}
560	* Configures GICD_TYPER.ItLinesNumber.
561	*
562	* For the IntId range [32,1023], configures the maximum SPI supported. Valid values
563	* are [1,31] which equates to interrupt IDs [63,1023]. A value of 0 implies SPIs
564	* are not supported. We don't allow configuring this value as it's expected that
565	* most guests would assume support for SPIs. */
566	AssertCompile(GIC_DIST_REG_TYPER_NUM_ITLINES == 31);
567	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxSpi", &pGicDev->uMaxSpi, 31 /* Upto and incl. IntId 1023 */);
568	AssertLogRelRCReturn(rc, rc);
569	if (pGicDev->uMaxSpi - 1 < 31)
570	{ /* likely */ }
571	else
572	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
573	N_("Configuration error: \"MaxSpi\" must be in the range [1,%u]"),
574	GIC_DIST_REG_TYPER_NUM_ITLINES);
575
576	/** @devcfgm{gic, ExtSpi, bool, false}
577	* Configures whether extended SPIs supported is enabled (GICD_TYPER.ESPI). */
578	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtSpi", &pGicDev->fExtSpi, true);
579	AssertLogRelRCReturn(rc, rc);
580
581	/** @devcfgm{gic, MaxExtSpi, uint8_t, 31}
582	* Configures GICD_TYPER.ESPI_range.
583	*
584	* For the extended SPI range [4096,5119], configures the maximum extended SPI
585	* supported. Valid values are [0,31] which equates to extended SPI IntIds
586	* [4127,5119]. This is ignored (set to 0 in the register) when extended SPIs are
587	* disabled. */
588	AssertCompile(GIC_DIST_REG_TYPER_ESPI_RANGE >> GIC_DIST_REG_TYPER_ESPI_RANGE_BIT == 31);
589	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxExtSpi", &pGicDev->uMaxExtSpi, 31);
590	AssertLogRelRCReturn(rc, rc);
591	if (pGicDev->uMaxExtSpi <= 31)
592	{ /* likely */ }
593	else
594	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
595	N_("Configuration error: \"MaxExtSpi\" must be in the range [0,31]"));
596
597	/** @devcfgm{gic, ExtPpi, bool, true}
598	* Configures whether extended PPIs support is enabled. */
599	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtPpi", &pGicDev->fExtPpi, true);
600	AssertLogRelRCReturn(rc, rc);
601
602	/** @devcfgm{gic, MaxExtPpi, uint8_t, 2}
603	* Configures GICR_TYPER.PPInum.
604	*
605	* For the extended PPI range [1056,5119], configures the maximum extended PPI
606	* supported. Valid values are [1,2] which equates to extended PPI IntIds
607	* [1087,1119]. This is unused when extended PPIs are disabled. */
608	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxExtPpi", &pGicDev->uMaxExtPpi, 2);
609	AssertLogRelRCReturn(rc, rc);
610	if ( pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087
611	\|\| pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
612	{ /* likely */ }
613	else
614	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
615	N_("Configuration error: \"MaxExtPpi\" must be in the range [0,2]"));
616
617	/** @devcfgm{gic, RangeSelSupport, bool, true}
618	* Configures whether range-selector support is enabled (GICD_TYPER.RSS and
619	* ICC_CTLR_EL1.RSS). */
620	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RangeSel", &pGicDev->fRangeSel, true);
621	AssertLogRelRCReturn(rc, rc);
622
623	/** @devcfgm{gic, Nmi, bool, false}
624	* Configures whether non-maskable interrupts (NMIs) are supported
625	* (GICD_TYPER.NMI). */
626	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Nmi", &pGicDev->fNmi, false);
627	AssertLogRelRCReturn(rc, rc);
628
629	/** @devcfgm{gic, Mbi, bool, true}
630	* Configures whether message-based interrupts (MBIs) are supported
631	* (GICD_TYPER.MBIS). */
632	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Mbi", &pGicDev->fMbi, true);
633	AssertLogRelRCReturn(rc, rc);
634
635	/** @devcfgm{gic, Aff3Levels, bool, true}
636	* Configures whether non-zero affinity 3 levels (A3V) are supported
637	* (GICD_TYPER.A3V) and (ICC_CTLR.A3V). */
638	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Aff3Levels", &pGicDev->fAff3Levels, true);
639	AssertLogRelRCReturn(rc, rc);
640
641	/*
642	* Register the GIC with PDM.
643	*/
644	rc = PDMDevHlpIcRegister(pDevIns);
645	AssertLogRelRCReturn(rc, rc);
646
647	rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
648	AssertLogRelRCReturn(rc, rc);
649
650	/*
651	* Insert the GIC system registers.
652	*/
653	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GIC); i++)
654	{
655	rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GIC[i]);
656	AssertLogRelRCReturn(rc, rc);
657	}
658
659	/*
660	* Register the MMIO ranges.
661	*/
662	RTGCPHYS GCPhysMmioBase = 0;
663	rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
664	if (RT_FAILURE(rc))
665	return PDMDEV_SET_ERROR(pDevIns, rc,
666	N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
667
668	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
669	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC_Dist", &pGicDev->hMmioDist);
670	AssertRCReturn(rc, rc);
671
672	rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
673	if (RT_FAILURE(rc))
674	return PDMDEV_SET_ERROR(pDevIns, rc,
675	N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
676
677	RTGCPHYS const cbRegion = (RTGCPHYS)pVM->cCpus
678	* (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
679	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
680	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC_ReDist", &pGicDev->hMmioReDist);
681	AssertRCReturn(rc, rc);
682
683	/*
684	* Register saved state callbacks.
685	*/
686	rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
687	AssertRCReturn(rc, rc);
688
689	/*
690	* Register debugger info callbacks.
691	*
692	* We use separate callbacks rather than arguments so they can also be
693	* dumped in an automated fashion while collecting crash diagnostics and
694	* not just used during live debugging via the VM debugger.
695	*/
696	DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3Info, DBGFINFO_FLAGS_ALL_EMTS);
697	DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC distributor information.", gicR3InfoDist, DBGFINFO_FLAGS_ALL_EMTS);
698	DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC redistributor information.", gicR3InfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
699
700	/*
701	* Statistics.
702	*/
703	#ifdef VBOX_WITH_STATISTICS
704	# define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
705	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, \
706	a_pszDesc, a_pszNameFmt, idCpu)
707	# define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
708	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, \
709	a_pszDesc, a_pszNameFmt, idCpu)
710
711	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
712	{
713	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
714	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
715
716	GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/MmioRead", "Number of MMIO reads in R3.");
717	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/MmioWrite", "Number of MMIO writes in R3.");
718	GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/SysRegRead", "Number of system register reads in R3.");
719	GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/SysRegWrite", "Number of system register writes in R3.");
720	GIC_REG_COUNTER(&pGicCpu->StatSetSpiR3, "%u/SetSpi", "Number of set SPI callbacks in R3.");
721	GIC_REG_COUNTER(&pGicCpu->StatSetPpiR3, "%u/SetPpi", "Number of set PPI callbacks in R3.");
722	GIC_REG_COUNTER(&pGicCpu->StatSetSgiR3, "%u/SetSgi", "Number of SGIs generated in R3.");
723
724	GIC_PROF_COUNTER(&pGicCpu->StatProfIntrAckR3, "%u/Prof/IntrAck", "Profiling of interrupt acknowledge (IAR) in R3.");
725	GIC_PROF_COUNTER(&pGicCpu->StatProfSetSpiR3, "%u/Prof/SetSpi", "Profiling of set SPI callback in R3.");
726	GIC_PROF_COUNTER(&pGicCpu->StatProfSetPpiR3, "%u/Prof/SetPpi", "Profiling of set PPI callback in R3.");
727	GIC_PROF_COUNTER(&pGicCpu->StatProfSetSgiR3, "%u/Prof/SetSgi", "Profiling of SGIs generated in R3.");
728	}
729	# undef GIC_REG_COUNTER
730	# undef GIC_PROF_COUNTER
731	#endif
732
733	gicR3Reset(pDevIns);
734
735	/*
736	* Log features/config.
737	*/
738	uint8_t const uArchRev = pGicDev->uArchRev;
739	uint8_t const uMaxSpi = pGicDev->uMaxSpi;
740	bool const fExtSpi = pGicDev->fExtSpi;
741	uint8_t const uMaxExtSpi = pGicDev->uMaxExtSpi;
742	bool const fExtPpi = pGicDev->fExtPpi;
743	uint8_t const uMaxExtPpi = pGicDev->uMaxExtPpi;
744	bool const fRangeSel = pGicDev->fRangeSel;
745	bool const fNmi = pGicDev->fNmi;
746	bool const fMbi = pGicDev->fMbi;
747	bool const fAff3Levels = pGicDev->fAff3Levels;
748	uint16_t const uExtPpiLast = uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 ? 1087 : GIC_INTID_RANGE_EXT_PPI_LAST;
749	LogRel(("GIC: ArchRev=%u RangeSel=%RTbool Nmi=%RTbool Mbi=%RTbool Aff3Levels=%RTbool\n",
750	uArchRev, fRangeSel, fNmi, fMbi, fAff3Levels));
751	LogRel(("GIC: SPIs=true (%u:32..%u) ExtSPIs=%RTbool (%u:4095..%u) ExtPPIs=%RTbool (%u:1056..%u)\n",
752	uMaxSpi, 32 * (uMaxSpi + 1),
753	fExtSpi, uMaxExtSpi, GIC_INTID_RANGE_EXT_SPI_START - 1 + 32 * (uMaxExtSpi + 1),
754	fExtPpi, uMaxExtPpi, uExtPpiLast));
755	return VINF_SUCCESS;
756	}
757
758	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
759

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source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 108531

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