GICR3.cpp@ 108779

Last change on this file since 108779 was 108779, checked in by vboxsync, 3 weeks ago
VMM/GIC: bugref:10877 Make GITS MMIO handlers deal directly with 64-bit wide accesses.
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File size: 43.7 KB

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1	/* $Id: GICR3.cpp 108779 2025-03-28 10:09:33Z vboxsync $ */
2	/** @file
3	* GIC - Generic Interrupt Controller Architecture (GIC).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_GIC
33	#include <VBox/log.h>
34	#include "GICInternal.h"
35	#include <VBox/vmm/pdmgic.h>
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/pdmdev.h>
40	#include <VBox/vmm/ssm.h>
41	#include <VBox/vmm/vm.h>
42
43	#include <iprt/armv8.h>
44
45
46	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
47
48
49	/*********************************************************************************************************************************
50	* Defined Constants And Macros *
51	*********************************************************************************************************************************/
52	/** GIC saved state version. */
53	#define GIC_SAVED_STATE_VERSION 7
54
55	# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
56	{ (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicIcc, kCpumSysRegWrFn_GicIcc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
57
58
59	/*********************************************************************************************************************************
60	* Global Variables *
61	*********************************************************************************************************************************/
62	/**
63	* System register ranges for the GIC.
64	*/
65	static CPUMSYSREGRANGE const g_aSysRegRanges_GIC[] =
66	{
67	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
68	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
69	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
70	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
71	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
72	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2"),
73	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, "ICC_SRE_EL3")
74	};
75
76
77	/**
78	* Dumps basic GIC state.
79	*
80	* @param pVM The cross context VM structure.
81	* @param pHlp The info helpers.
82	* @param pszArgs Arguments, ignored.
83	*/
84	static DECLCALLBACK(void) gicR3DbgInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
85	{
86	RT_NOREF(pszArgs);
87	PCGIC pGic = VM_TO_GIC(pVM);
88	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
89	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
90
91	pHlp->pfnPrintf(pHlp, "GIC:\n");
92	pHlp->pfnPrintf(pHlp, " uArchRev = %u\n", pGicDev->uArchRev);
93	pHlp->pfnPrintf(pHlp, " uMaxSpi = %u (upto IntId %u)\n", pGicDev->uMaxSpi, 32 * (pGicDev->uMaxSpi + 1));
94	pHlp->pfnPrintf(pHlp, " fExtSpi = %RTbool\n", pGicDev->fExtSpi);
95	pHlp->pfnPrintf(pHlp, " uMaxExtSpi = %u (upto IntId %u)\n", pGicDev->uMaxExtSpi,
96	GIC_INTID_RANGE_EXT_SPI_START - 1 + 32 * (pGicDev->uMaxExtSpi + 1));
97	pHlp->pfnPrintf(pHlp, " fExtPpi = %RTbool\n", pGicDev->fExtPpi);
98	pHlp->pfnPrintf(pHlp, " uMaxExtPpi = %u (upto IntId %u)\n", pGicDev->uMaxExtPpi,
99	pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 ? 1087 : GIC_INTID_RANGE_EXT_PPI_LAST);
100	pHlp->pfnPrintf(pHlp, " fRangeSelSupport = %RTbool\n", pGicDev->fRangeSel);
101	pHlp->pfnPrintf(pHlp, " fNmi = %RTbool\n", pGicDev->fNmi);
102	pHlp->pfnPrintf(pHlp, " fMbi = %RTbool\n", pGicDev->fMbi);
103	pHlp->pfnPrintf(pHlp, " fAff3Levels = %RTbool\n", pGicDev->fAff3Levels);
104	pHlp->pfnPrintf(pHlp, " fLpi = %RTbool\n", pGicDev->fLpi);
105	}
106
107
108	/**
109	* Dumps GIC Distributor information.
110	*
111	* @param pVM The cross context VM structure.
112	* @param pHlp The info helpers.
113	* @param pszArgs Arguments, ignored.
114	*/
115	static DECLCALLBACK(void) gicR3DbgInfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
116	{
117	RT_NOREF(pszArgs);
118
119	PGIC pGic = VM_TO_GIC(pVM);
120	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
121	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
122
123	#define GIC_DBGFINFO_DIST_INTR_BITMAP(a_Name, a_bmIntr) \
124	do \
125	{ \
126	pHlp->pfnPrintf(pHlp, " " a_Name " =\n"); \
127	for (uint32_t i = 0; i < RT_ELEMENTS(a_bmIntr); i += 8) \
128	pHlp->pfnPrintf(pHlp, " [%2u..%-2u] %#010x %#010x %#010x %#010x %#010x %#010x %#010x %#010x\n", i, i + 7, \
129	(a_bmIntr)[i], (a_bmIntr)[i+1], (a_bmIntr)[i+2], (a_bmIntr)[i+3], \
130	(a_bmIntr)[i+4], (a_bmIntr)[i+5], (a_bmIntr)[i+6], (a_bmIntr)[i+7]); \
131	} while (0)
132
133	pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
134	pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicDev->fIntrGroup0Enabled);
135	pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicDev->fIntrGroup1Enabled);
136	pHlp->pfnPrintf(pHlp, " fAffRoutingEnabled = %RTbool\n", pGicDev->fAffRoutingEnabled);
137	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrGroup", pGicDev->bmIntrGroup);
138	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrEnabled", pGicDev->bmIntrEnabled);
139	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrPending", pGicDev->bmIntrPending);
140	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrActive", pGicDev->bmIntrActive);
141
142	/* Interrupt priorities.*/
143	{
144	uint32_t const cPriorities = RT_ELEMENTS(pGicDev->abIntrPriority);
145	AssertCompile(!(cPriorities % 16));
146	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
147	for (uint32_t i = 0; i < cPriorities; i += 16)
148	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
149	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
150	gicDistGetIntIdFromIndex(i), gicDistGetIntIdFromIndex(i + 7),
151	pGicDev->abIntrPriority[i], pGicDev->abIntrPriority[i + 1],
152	pGicDev->abIntrPriority[i + 2], pGicDev->abIntrPriority[i + 3],
153	pGicDev->abIntrPriority[i + 4], pGicDev->abIntrPriority[i + 5],
154	pGicDev->abIntrPriority[i + 6], pGicDev->abIntrPriority[i + 7],
155	gicDistGetIntIdFromIndex(i + 8), gicDistGetIntIdFromIndex(i + 15),
156	pGicDev->abIntrPriority[i + 8], pGicDev->abIntrPriority[i + 9],
157	pGicDev->abIntrPriority[i + 10], pGicDev->abIntrPriority[i + 11],
158	pGicDev->abIntrPriority[i + 12], pGicDev->abIntrPriority[i + 13],
159	pGicDev->abIntrPriority[i + 14], pGicDev->abIntrPriority[i + 15]);
160	}
161
162	/* Interrupt routing.*/
163	{
164	/** @todo Interrupt rounting mode. */
165	uint32_t const cRouting = RT_ELEMENTS(pGicDev->au32IntrRouting);
166	AssertCompile(!(cRouting % 16));
167	pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
168	for (uint32_t i = 0; i < cRouting; i += 16)
169	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
170	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
171	gicDistGetIntIdFromIndex(i), gicDistGetIntIdFromIndex(i + 7),
172	pGicDev->au32IntrRouting[i], pGicDev->au32IntrRouting[i + 1],
173	pGicDev->au32IntrRouting[i + 2], pGicDev->au32IntrRouting[i + 3],
174	pGicDev->au32IntrRouting[i + 4], pGicDev->au32IntrRouting[i + 5],
175	pGicDev->au32IntrRouting[i + 6], pGicDev->au32IntrRouting[i + 7],
176	gicDistGetIntIdFromIndex(i + 8), gicDistGetIntIdFromIndex(i + 15),
177	pGicDev->au32IntrRouting[i + 8], pGicDev->au32IntrRouting[i + 9],
178	pGicDev->au32IntrRouting[i + 10], pGicDev->au32IntrRouting[i + 11],
179	pGicDev->au32IntrRouting[i + 12], pGicDev->au32IntrRouting[i + 13],
180	pGicDev->au32IntrRouting[i + 14], pGicDev->au32IntrRouting[i + 15]);
181	}
182
183	#undef GIC_DBGFINFO_DIST_INTR_BITMAP
184	}
185
186
187	/**
188	* Dumps the GIC Redistributor information.
189	*
190	* @param pVM The cross context VM structure.
191	* @param pHlp The info helpers.
192	* @param pszArgs Arguments, ignored.
193	*/
194	static DECLCALLBACK(void) gicR3DbgInfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
195	{
196	NOREF(pszArgs);
197	PVMCPU pVCpu = VMMGetCpu(pVM);
198	if (!pVCpu)
199	pVCpu = pVM->apCpusR3[0];
200
201	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
202
203	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
204	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrGroup) >= 3);
205	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrEnabled) >= 3);
206	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrPending) >= 3);
207	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrActive) >= 3);
208	pHlp->pfnPrintf(pHlp, " bmIntrGroup[0..2] = %#010x %#010x %#010x\n", pGicCpu->bmIntrGroup[0], pGicCpu->bmIntrGroup[1], pGicCpu->bmIntrGroup[2]);
209	pHlp->pfnPrintf(pHlp, " bmIntrEnabled[0..2] = %#010x %#010x %#010x\n", pGicCpu->bmIntrEnabled[0], pGicCpu->bmIntrEnabled[1], pGicCpu->bmIntrEnabled[2]);
210	pHlp->pfnPrintf(pHlp, " bmIntrPending[0..2] = %#010x %#010x %#010x\n", pGicCpu->bmIntrPending[0], pGicCpu->bmIntrPending[1], pGicCpu->bmIntrPending[2]);
211	pHlp->pfnPrintf(pHlp, " bmIntrActive[0..2] = %#010x %#010x %#010x\n", pGicCpu->bmIntrActive[0], pGicCpu->bmIntrActive[1], pGicCpu->bmIntrActive[2]);
212
213	/* Interrupt priorities. */
214	{
215	uint32_t const cPriorities = RT_ELEMENTS(pGicCpu->abIntrPriority);
216	AssertCompile(!(cPriorities % 16));
217	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
218	for (uint32_t i = 0; i < cPriorities; i += 16)
219	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
220	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
221	gicReDistGetIntIdFromIndex(i), gicReDistGetIntIdFromIndex(i + 7),
222	pGicCpu->abIntrPriority[i], pGicCpu->abIntrPriority[i + 1],
223	pGicCpu->abIntrPriority[i + 2], pGicCpu->abIntrPriority[i + 3],
224	pGicCpu->abIntrPriority[i + 4], pGicCpu->abIntrPriority[i + 5],
225	pGicCpu->abIntrPriority[i + 6], pGicCpu->abIntrPriority[i + 7],
226	gicReDistGetIntIdFromIndex(i + 8), gicReDistGetIntIdFromIndex(i + 15),
227	pGicCpu->abIntrPriority[i + 8], pGicCpu->abIntrPriority[i + 9],
228	pGicCpu->abIntrPriority[i + 10], pGicCpu->abIntrPriority[i + 11],
229	pGicCpu->abIntrPriority[i + 12], pGicCpu->abIntrPriority[i + 13],
230	pGicCpu->abIntrPriority[i + 14], pGicCpu->abIntrPriority[i + 15]);
231	}
232
233	pHlp->pfnPrintf(pHlp, "\nVCPU[%u] ICC system register state:\n", pVCpu->idCpu);
234	pHlp->pfnPrintf(pHlp, " uIccCtlr = %#RX64\n", pGicCpu->uIccCtlr);
235	pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicCpu->fIntrGroup0Enabled);
236	pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicCpu->fIntrGroup1Enabled);
237	pHlp->pfnPrintf(pHlp, " bBinaryPtGroup0 = %#x\n", pGicCpu->bBinaryPtGroup0);
238	pHlp->pfnPrintf(pHlp, " bBinaryPtGroup1 = %#x\n", pGicCpu->bBinaryPtGroup1);
239	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %#x\n", pGicCpu->idxRunningPriority);
240	pHlp->pfnPrintf(pHlp, " Running priority = %#x\n", pGicCpu->abRunningPriorities[pGicCpu->idxRunningPriority]);
241
242	/* Running interrupt priorities. */
243	{
244	uint32_t const cPriorities = RT_ELEMENTS(pGicCpu->abRunningPriorities);
245	AssertCompile(!(cPriorities % 16));
246	pHlp->pfnPrintf(pHlp, " Running-interrupt priorities:\n");
247	for (uint32_t i = 0; i < cPriorities; i += 16)
248	pHlp->pfnPrintf(pHlp, " [%3u..%-3u] = %3u %3u %3u %3u %3u %3u %3u %3u"
249	" [%3u..%-3u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
250	i, i + 7,
251	pGicCpu->abRunningPriorities[i], pGicCpu->abRunningPriorities[i + 1],
252	pGicCpu->abRunningPriorities[i + 2], pGicCpu->abRunningPriorities[i + 3],
253	pGicCpu->abRunningPriorities[i + 4], pGicCpu->abRunningPriorities[i + 5],
254	pGicCpu->abRunningPriorities[i + 6], pGicCpu->abRunningPriorities[i + 7],
255	i + 8, i + 15,
256	pGicCpu->abRunningPriorities[i + 8], pGicCpu->abRunningPriorities[i + 9],
257	pGicCpu->abRunningPriorities[i + 10], pGicCpu->abRunningPriorities[i + 11],
258	pGicCpu->abRunningPriorities[i + 12], pGicCpu->abRunningPriorities[i + 13],
259	pGicCpu->abRunningPriorities[i + 14], pGicCpu->abRunningPriorities[i + 15]);
260	}
261
262	AssertCompile(RT_ELEMENTS(pGicCpu->bmActivePriorityGroup0) >= 4);
263	pHlp->pfnPrintf(pHlp, " Active-interrupt priorities Group 0:\n");
264	pHlp->pfnPrintf(pHlp, " [0..3] = %#010x %#010x %#010x %#010x\n",
265	pGicCpu->bmActivePriorityGroup0[0], pGicCpu->bmActivePriorityGroup0[1],
266	pGicCpu->bmActivePriorityGroup0[2], pGicCpu->bmActivePriorityGroup0[3]);
267	AssertCompile(RT_ELEMENTS(pGicCpu->bmActivePriorityGroup1) >= 4);
268	pHlp->pfnPrintf(pHlp, " Active-interrupt priorities Group 1:\n");
269	pHlp->pfnPrintf(pHlp, " [0..3] = %#010x %#010x %#010x %#010x\n",
270	pGicCpu->bmActivePriorityGroup1[0], pGicCpu->bmActivePriorityGroup1[1],
271	pGicCpu->bmActivePriorityGroup1[2], pGicCpu->bmActivePriorityGroup1[3]);
272	}
273
274
275	/**
276	* Dumps the GIC ITS information.
277	*
278	* @param pVM The cross context VM structure.
279	* @param pHlp The info helpers.
280	* @param pszArgs Arguments, ignored.
281	*/
282	static DECLCALLBACK(void) gicR3DbgInfoIts(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
283	{
284	PGIC pGic = VM_TO_GIC(pVM);
285	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
286	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
287	if (pGicDev->hMmioGits != NIL_IOMMMIOHANDLE)
288	{
289	PCGITSDEV pGitsDev = &pGicDev->Gits;
290	gitsR3DbgInfo(pGitsDev, pHlp, pszArgs);
291	}
292	else
293	pHlp->pfnPrintf(pHlp, "GIC ITS is not mapped/configured for the VM\n");
294	}
295
296
297	/**
298	* @copydoc FNSSMDEVSAVEEXEC
299	*/
300	static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
301	{
302	PCVM pVM = PDMDevHlpGetVM(pDevIns);
303	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
304	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
305	AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
306	LogFlowFunc(("\n"));
307
308	/*
309	* Save per-VM data.
310	*/
311	pHlp->pfnSSMPutU32(pSSM, pVM->cCpus);
312	pHlp->pfnSSMPutU8(pSSM, pGicDev->uArchRev);
313	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxSpi);
314	pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtSpi);
315	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxExtSpi);
316	pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtPpi);
317	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxExtPpi);
318	pHlp->pfnSSMPutBool(pSSM, pGicDev->fRangeSel);
319	pHlp->pfnSSMPutBool(pSSM, pGicDev->fNmi);
320	pHlp->pfnSSMPutBool(pSSM, pGicDev->fMbi);
321	pHlp->pfnSSMPutBool(pSSM, pGicDev->fAff3Levels);
322	pHlp->pfnSSMPutBool(pSSM, pGicDev->fLpi);
323
324	/* Distributor state. */
325	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup0Enabled);
326	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup1Enabled);
327	pHlp->pfnSSMPutBool(pSSM, pGicDev->fAffRoutingEnabled);
328	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrGroup[0], sizeof(pGicDev->bmIntrGroup));
329	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrConfig[0], sizeof(pGicDev->bmIntrConfig));
330	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrEnabled[0], sizeof(pGicDev->bmIntrEnabled));
331	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrPending[0], sizeof(pGicDev->bmIntrPending));
332	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrActive[0], sizeof(pGicDev->bmIntrActive));
333	pHlp->pfnSSMPutMem(pSSM, &pGicDev->abIntrPriority[0], sizeof(pGicDev->abIntrPriority));
334	pHlp->pfnSSMPutMem(pSSM, &pGicDev->au32IntrRouting[0], sizeof(pGicDev->au32IntrRouting));
335	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrRoutingMode[0], sizeof(pGicDev->bmIntrRoutingMode));
336
337	/* We store the size followed by the data because we currently do not support the full LPI range. */
338	pHlp->pfnSSMPutU32(pSSM, sizeof(pGicDev->abLpiConfig));
339	pHlp->pfnSSMPutMem(pSSM, &pGicDev->abLpiConfig[0], sizeof(pGicDev->abLpiConfig));
340	pHlp->pfnSSMPutU32(pSSM, sizeof(pGicDev->bmLpiPending));
341	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmLpiPending[0], sizeof(pGicDev->bmLpiPending));
342
343	/** @todo GITS data. */
344
345	/*
346	* Save per-VCPU data.
347	*/
348	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
349	{
350	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
351	Assert(pGicCpu);
352
353	/* Redistributor state. */
354	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrGroup[0], sizeof(pGicCpu->bmIntrGroup));
355	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrConfig[0], sizeof(pGicCpu->bmIntrConfig));
356	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrEnabled[0], sizeof(pGicCpu->bmIntrEnabled));
357	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrPending[0], sizeof(pGicCpu->bmIntrPending));
358	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrActive[0], sizeof(pGicCpu->bmIntrActive));
359	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->abIntrPriority[0], sizeof(pGicCpu->abIntrPriority));
360
361	/* ICC system register state. */
362	pHlp->pfnSSMPutU64(pSSM, pGicCpu->uIccCtlr);
363	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bIntrPriorityMask);
364	pHlp->pfnSSMPutU8(pSSM, pGicCpu->idxRunningPriority);
365	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->abRunningPriorities[0], sizeof(pGicCpu->abRunningPriorities));
366	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmActivePriorityGroup0[0], sizeof(pGicCpu->bmActivePriorityGroup0));
367	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmActivePriorityGroup1[0], sizeof(pGicCpu->bmActivePriorityGroup1));
368	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPtGroup0);
369	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPtGroup1);
370	pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup0Enabled);
371	pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup1Enabled);
372	}
373
374	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
375	}
376
377
378	/**
379	* @copydoc FNSSMDEVLOADEXEC
380	*/
381	static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
382	{
383	PVM pVM = PDMDevHlpGetVM(pDevIns);
384	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
385
386	AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
387	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
388	LogFlowFunc(("uVersion=%u uPass=%#x\n", uVersion, uPass));
389
390	/*
391	* Validate supported saved-state versions.
392	*/
393	if (uVersion != GIC_SAVED_STATE_VERSION)
394	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid saved-state version %u"), uVersion);
395
396	/*
397	* Load per-VM data.
398	*/
399	uint32_t cCpus;
400	pHlp->pfnSSMGetU32(pSSM, &cCpus);
401	if (cCpus != pVM->cCpus)
402	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cCpus: got=%u expected=%u"), cCpus, pVM->cCpus);
403
404	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
405	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uArchRev);
406	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxSpi);
407	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtSpi);
408	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxExtSpi);
409	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtPpi);
410	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxExtPpi);
411	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fRangeSel);
412	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fNmi);
413	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fMbi);
414	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAff3Levels);
415	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fLpi);
416
417	/* Distributor state. */
418	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup0Enabled);
419	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup1Enabled);
420	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAffRoutingEnabled);
421	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrGroup[0], sizeof(pGicDev->bmIntrGroup));
422	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrConfig[0], sizeof(pGicDev->bmIntrConfig));
423	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrEnabled[0], sizeof(pGicDev->bmIntrEnabled));
424	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrPending[0], sizeof(pGicDev->bmIntrPending));
425	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrActive[0], sizeof(pGicDev->bmIntrActive));
426	pHlp->pfnSSMGetMem(pSSM, &pGicDev->abIntrPriority[0], sizeof(pGicDev->abIntrPriority));
427	pHlp->pfnSSMGetMem(pSSM, &pGicDev->au32IntrRouting[0], sizeof(pGicDev->au32IntrRouting));
428	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrRoutingMode[0], sizeof(pGicDev->bmIntrRoutingMode));
429
430	/* LPI config. */
431	{
432	uint32_t cbData = 0;
433	int const rc = pHlp->pfnSSMGetU32(pSSM, &cbData);
434	AssertRCReturn(rc, rc);
435	if (cbData <= sizeof(pGicDev->abLpiConfig))
436	pHlp->pfnSSMGetMem(pSSM, &pGicDev->abLpiConfig[0], cbData);
437	else
438	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPI config table size: got=%u expected=%u"),
439	cbData, sizeof(pGicDev->abLpiConfig));
440	}
441	/* LPI pending. */
442	{
443	uint32_t cbData = 0;
444	int const rc = pHlp->pfnSSMGetU32(pSSM, &cbData);
445	AssertRCReturn(rc, rc);
446	if (cbData <= sizeof(pGicDev->bmLpiPending))
447	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmLpiPending[0], cbData);
448	else
449	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPI pending bitmap size: got=%u expected=%u"),
450	cbData, sizeof(pGicDev->bmLpiPending));
451	}
452
453	/** @todo GITS data. */
454
455	/*
456	* Load per-VCPU data.
457	*/
458	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
459	{
460	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
461	Assert(pGicCpu);
462
463	/* Redistributor state. */
464	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrGroup[0], sizeof(pGicCpu->bmIntrGroup));
465	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrConfig[0], sizeof(pGicCpu->bmIntrConfig));
466	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrEnabled[0], sizeof(pGicCpu->bmIntrEnabled));
467	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrPending[0], sizeof(pGicCpu->bmIntrPending));
468	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrActive[0], sizeof(pGicCpu->bmIntrActive));
469	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->abIntrPriority[0], sizeof(pGicCpu->abIntrPriority));
470
471	/* ICC system register state. */
472	pHlp->pfnSSMGetU64(pSSM, &pGicCpu->uIccCtlr);
473	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bIntrPriorityMask);
474	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->idxRunningPriority);
475	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->abRunningPriorities[0], sizeof(pGicCpu->abRunningPriorities));
476	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmActivePriorityGroup0[0], sizeof(pGicCpu->bmActivePriorityGroup0));
477	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmActivePriorityGroup1[0], sizeof(pGicCpu->bmActivePriorityGroup1));
478	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPtGroup0);
479	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPtGroup1);
480	pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup0Enabled);
481	pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup1Enabled);
482	}
483
484	/*
485	* Check that we're still good wrt restored data.
486	*/
487	int rc = pHlp->pfnSSMHandleGetStatus(pSSM);
488	AssertRCReturn(rc, rc);
489
490	uint32_t uMarker = 0;
491	rc = pHlp->pfnSSMGetU32(pSSM, &uMarker);
492	AssertRCReturn(rc, rc);
493	if (uMarker == UINT32_MAX)
494	{ /* likely */ }
495	else
496	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Marker: got=%u expected=%u"), uMarker, UINT32_MAX);
497
498	/*
499	* Finally, perform sanity checks.
500	*/
501	if (pGicDev->uArchRev <= GIC_DIST_REG_PIDR2_ARCHREV_GICV4)
502	{ /* likely */ }
503	else
504	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid uArchRev, got %u expected range [1,31]"), pGicDev->uArchRev,
505	GIC_DIST_REG_PIDR2_ARCHREV_GICV1, GIC_DIST_REG_PIDR2_ARCHREV_GICV4);
506	if (pGicDev->uMaxSpi - 1 < 31)
507	{ /* likely */ }
508	else
509	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxSpi, got %u expected range [1,31]"), pGicDev->uMaxSpi);
510	if (pGicDev->uMaxExtSpi <= 31)
511	{ /* likely */ }
512	else
513	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxExtSpi, got %u expected range [0,31]"), pGicDev->uMaxExtSpi);
514	if ( pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087
515	\|\| pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
516	{ /* likely */ }
517	else
518	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxExtPpi, got %u expected range [1,2]"), pGicDev->uMaxExtPpi);
519	bool const fIsGitsEnabled = RT_BOOL(pGicDev->hMmioGits != NIL_IOMMMIOHANDLE);
520	if (fIsGitsEnabled == pGicDev->fLpi)
521	{ /* likely */ }
522	else
523	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPIs are %s when ITS is %s"),
524	fIsGitsEnabled ? "enabled" : "disabled", pGicDev->fLpi ? "enabled" : "disabled");
525	return rc;
526	}
527
528
529	/**
530	* @interface_method_impl{PDMDEVREG,pfnReset}
531	*/
532	DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
533	{
534	PVM pVM = PDMDevHlpGetVM(pDevIns);
535	VM_ASSERT_EMT0(pVM);
536	VM_ASSERT_IS_NOT_RUNNING(pVM);
537
538	LogFlow(("GIC: gicR3Reset\n"));
539
540	gicReset(pDevIns);
541	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
542	{
543	PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
544	gicResetCpu(pDevIns, pVCpuDest);
545	}
546	}
547
548
549	/**
550	* @interface_method_impl{PDMDEVREG,pfnRelocate}
551	*/
552	DECLCALLBACK(void) gicR3Relocate(PPDMDEVINS pDevIns, RTGCINTPTR offDelta)
553	{
554	RT_NOREF(pDevIns, offDelta);
555	}
556
557
558	/**
559	* @interface_method_impl{PDMDEVREG,pfnDestruct}
560	*/
561	DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
562	{
563	LogFlowFunc(("pDevIns=%p\n", pDevIns));
564	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
565
566	return VINF_SUCCESS;
567	}
568
569
570	/**
571	* @interface_method_impl{PDMDEVREG,pfnConstruct}
572	*/
573	DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
574	{
575	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
576	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
577	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
578	PVM pVM = PDMDevHlpGetVM(pDevIns);
579	PGIC pGic = VM_TO_GIC(pVM);
580	Assert(iInstance == 0); NOREF(iInstance);
581
582	/*
583	* Init the data.
584	*/
585	pGic->pDevInsR3 = pDevIns;
586
587	/*
588	* Validate GIC settings.
589	*/
590	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase\|RedistributorMmioBase\|ItsMmioBase"
591	"\|ArchRev"
592	"\|MaxSpi"
593	"\|ExtSpi"
594	"\|MaxExtSpi"
595	"\|ExtPpi"
596	"\|MaxExtPpi"
597	"\|RangeSel"
598	"\|Nmi"
599	"\|Mbi"
600	"\|Aff3Levels"
601	"\|Lpi"
602	"\|MaxLpi", "");
603
604	#if 0
605	/*
606	* Disable automatic PDM locking for this device.
607	*/
608	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
609	AssertRCReturn(rc, rc);
610	#endif
611
612	/** @devcfgm{gic, ArchRev, uint8_t, 3}
613	* Configures the GIC architecture revision (GICD_PIDR2.ArchRev, GICR_PIDR2.ArchRev
614	* and GITS_PIDR2.ArchRev).
615	*
616	* Currently we only support GICv3 and the architecture revision reported is the
617	* same for both the GIC and the ITS. */
618	int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRev", &pGicDev->uArchRev, 3);
619	AssertLogRelRCReturn(rc, rc);
620	if (pGicDev->uArchRev == 3)
621	pGicDev->Gits.uArchRev = pGicDev->uArchRev;
622	else
623	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
624	N_("Configuration error: \"ArchRev\" value %u is not supported"), pGicDev->uArchRev);
625
626	/** @devcfgm{gic, MaxSpi, uint8_t, 31}
627	* Configures GICD_TYPER.ItLinesNumber.
628	*
629	* For the IntId range [32,1023], configures the maximum SPI supported. Valid values
630	* are [1,31] which equates to interrupt IDs [63,1023]. A value of 0 implies SPIs
631	* are not supported. We don't allow configuring this value as it's expected that
632	* most guests would assume support for SPIs. */
633	AssertCompile(GIC_DIST_REG_TYPER_NUM_ITLINES == 31);
634	/** @todo This currently isn't implemented and the full range is always
635	* reported to the guest. */
636	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxSpi", &pGicDev->uMaxSpi, 31 /* Upto and incl. IntId 1023 */);
637	AssertLogRelRCReturn(rc, rc);
638	if (pGicDev->uMaxSpi - 1 < 31)
639	{ /* likely */ }
640	else
641	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
642	N_("Configuration error: \"MaxSpi\" must be in the range [1,%u]"),
643	GIC_DIST_REG_TYPER_NUM_ITLINES);
644
645	/** @devcfgm{gic, ExtSpi, bool, false}
646	* Configures whether extended SPIs supported is enabled (GICD_TYPER.ESPI). */
647	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtSpi", &pGicDev->fExtSpi, true);
648	AssertLogRelRCReturn(rc, rc);
649
650	/** @devcfgm{gic, MaxExtSpi, uint8_t, 31}
651	* Configures GICD_TYPER.ESPI_range.
652	*
653	* For the extended SPI range [4096,5119], configures the maximum extended SPI
654	* supported. Valid values are [0,31] which equates to extended SPI IntIds
655	* [4127,5119]. This is ignored (set to 0 in the register) when extended SPIs are
656	* disabled. */
657	AssertCompile(GIC_DIST_REG_TYPER_ESPI_RANGE >> GIC_DIST_REG_TYPER_ESPI_RANGE_BIT == 31);
658	/** @todo This currently isn't implemented and the full range is always
659	* reported to the guest. */
660	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxExtSpi", &pGicDev->uMaxExtSpi, 31);
661	AssertLogRelRCReturn(rc, rc);
662	if (pGicDev->uMaxExtSpi <= 31)
663	{ /* likely */ }
664	else
665	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
666	N_("Configuration error: \"MaxExtSpi\" must be in the range [0,31]"));
667
668	/** @devcfgm{gic, ExtPpi, bool, true}
669	* Configures whether extended PPIs support is enabled. */
670	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtPpi", &pGicDev->fExtPpi, true);
671	AssertLogRelRCReturn(rc, rc);
672
673	/** @devcfgm{gic, MaxExtPpi, uint8_t, 2}
674	* Configures GICR_TYPER.PPInum.
675	*
676	* For the extended PPI range [1056,5119], configures the maximum extended PPI
677	* supported. Valid values are [1,2] which equates to extended PPI IntIds
678	* [1087,1119]. This is unused when extended PPIs are disabled. */
679	/** @todo This currently isn't implemented and the full range is always
680	* reported to the guest. */
681	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxExtPpi", &pGicDev->uMaxExtPpi, 2);
682	AssertLogRelRCReturn(rc, rc);
683	if ( pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087
684	\|\| pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
685	{ /* likely */ }
686	else
687	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
688	N_("Configuration error: \"MaxExtPpi\" must be in the range [0,2]"));
689
690	/** @devcfgm{gic, RangeSelSupport, bool, true}
691	* Configures whether range-selector support is enabled (GICD_TYPER.RSS and
692	* ICC_CTLR_EL1.RSS). */
693	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RangeSel", &pGicDev->fRangeSel, true);
694	AssertLogRelRCReturn(rc, rc);
695
696	/** @devcfgm{gic, Nmi, bool, false}
697	* Configures whether non-maskable interrupts (NMIs) are supported
698	* (GICD_TYPER.NMI). */
699	/** @todo NMIs are currently not implemented. */
700	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Nmi", &pGicDev->fNmi, false);
701	AssertLogRelRCReturn(rc, rc);
702
703	/** @devcfgm{gic, Mbi, bool, false}
704	* Configures whether message-based interrupts (MBIs) are supported
705	* (GICD_TYPER.MBIS).
706	*
707	* Guests typically can't use MBIs without an ITS. */
708	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Mbi", &pGicDev->fMbi, false);
709	AssertLogRelRCReturn(rc, rc);
710
711	/** @devcfgm{gic, Aff3Levels, bool, true}
712	* Configures whether non-zero affinity 3 levels (A3V) are supported
713	* (GICD_TYPER.A3V and ICC_CTLR.A3V). */
714	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Aff3Levels", &pGicDev->fAff3Levels, true);
715	AssertLogRelRCReturn(rc, rc);
716
717	/** @devcfgm{gic, Lpi, bool, false}
718	* Configures whether physical LPIs are supported (GICD_TYPER.LPIS and
719	* GICR_TYPER.PLPIS).
720	*
721	* This currently requires an ITS as we do not support direction injection of
722	* LPIs as most guests do not use them anyway. */
723	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Lpi", &pGicDev->fLpi, false);
724	AssertLogRelRCReturn(rc, rc);
725
726	/** @devcfgm{gic, MaxLpi, uint8_t, 14}
727	* Configures GICD_TYPER.num_LPIs.
728	*
729	* For the physical LPI range [8192,65535], configures the number of physical LPI
730	* supported. Valid values are [3,14] which equates to LPI IntIds 8192 to
731	* [8207,40959]. A value of 15 or higher would exceed the maximum INTID size of
732	* 16-bits since 8192 + 2^(NumLpi+1) is >= 73727. A value of 2 or lower support
733	* fewer than 15 LPIs which seem pointless and is hence disallowed. This value is
734	* ignored (set to 0 in the register) when LPIs are disabled. */
735	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxLpi", &pGicDev->uMaxLpi, 10);
736	AssertLogRelRCReturn(rc, rc);
737
738	/* We currently support 2048 LPIs until we need to support more. */
739	if (pGicDev->uMaxLpi == 10)
740	{ /* likely */ }
741	else
742	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
743	N_("Configuration error: \"MaxLpi\" must be in the range [3,14]"));
744	AssertRelease(UINT32_C(2) << pGicDev->uMaxLpi <= RT_ELEMENTS(pGicDev->abLpiConfig));
745
746	/*
747	* Register the GIC with PDM.
748	*/
749	rc = PDMDevHlpIcRegister(pDevIns);
750	AssertLogRelRCReturn(rc, rc);
751
752	rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
753	AssertLogRelRCReturn(rc, rc);
754
755	/*
756	* Insert the GIC system registers.
757	*/
758	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GIC); i++)
759	{
760	rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GIC[i]);
761	AssertLogRelRCReturn(rc, rc);
762	}
763
764	/*
765	* Register the MMIO ranges.
766	*/
767	/* Distributor. */
768	{
769	RTGCPHYS GCPhysMmioBase = 0;
770	rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
771	if (RT_FAILURE(rc))
772	return PDMDEV_SET_ERROR(pDevIns, rc,
773	N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
774
775	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
776	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC Distributor",
777	&pGicDev->hMmioDist);
778	AssertRCReturn(rc, rc);
779	}
780
781	/* Redistributor. */
782	{
783	RTGCPHYS GCPhysMmioBase = 0;
784	rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
785	if (RT_FAILURE(rc))
786	return PDMDEV_SET_ERROR(pDevIns, rc,
787	N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
788
789	RTGCPHYS const cbRegion = (RTGCPHYS)pVM->cCpus
790	* (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
791	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
792	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC Redistributor",
793	&pGicDev->hMmioReDist);
794	AssertRCReturn(rc, rc);
795	}
796
797	/* ITS. */
798	{
799	RTGCPHYS GCPhysMmioBase = 0;
800	rc = pHlp->pfnCFGMQueryU64(pCfg, "ItsMmioBase", &GCPhysMmioBase);
801	if (RT_SUCCESS(rc))
802	{
803	RTGCPHYS const cbRegion = 2 * GITS_REG_FRAME_SIZE; /* 2 frames for GICv3. */
804	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicItsMmioWrite, gicItsMmioRead,
805	IOMMMIO_FLAGS_READ_DWORD_QWORD
806	\| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED
807	\| IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
808	\| IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
809	"GIC ITS", &pGicDev->hMmioGits);
810	AssertRCReturn(rc, rc);
811
812	/* When the ITS is enabled we must support LPIs. */
813	if (!pGicDev->fLpi)
814	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
815	N_("Configuration error: \"Lpi\" must be enabled when ITS is enabled\n"));
816	}
817	else
818	{
819	pGicDev->hMmioGits = NIL_IOMMMIOHANDLE;
820
821	/* When the ITS is disabled we don't support LPIs as we do not support direct LPI injection (guests don't use it). */
822	if (pGicDev->fLpi)
823	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
824	N_("Configuration error: \"Lpi\" must be disabled when ITS is disabled\n"));
825	}
826	}
827
828	/*
829	* Register saved state callbacks.
830	*/
831	rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
832	AssertRCReturn(rc, rc);
833
834	/*
835	* Register debugger info callbacks.
836	*
837	* We use separate callbacks rather than arguments so they can also be
838	* dumped in an automated fashion while collecting crash diagnostics and
839	* not just used during live debugging via the VM debugger.
840	*/
841	DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3DbgInfo, DBGFINFO_FLAGS_ALL_EMTS);
842	DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC distributor information.", gicR3DbgInfoDist, DBGFINFO_FLAGS_ALL_EMTS);
843	DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC redistributor information.", gicR3DbgInfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
844	DBGFR3InfoRegisterInternalEx(pVM, "gicits", "Dumps GIC ITS information.", gicR3DbgInfoIts, DBGFINFO_FLAGS_ALL_EMTS);
845
846	/*
847	* Statistics.
848	*/
849	#ifdef VBOX_WITH_STATISTICS
850	# define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
851	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, \
852	a_pszDesc, a_pszNameFmt, idCpu)
853	# define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
854	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, \
855	a_pszDesc, a_pszNameFmt, idCpu)
856
857	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
858	{
859	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
860	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
861
862	GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/MmioRead", "Number of MMIO reads in R3.");
863	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/MmioWrite", "Number of MMIO writes in R3.");
864	GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/SysRegRead", "Number of system register reads in R3.");
865	GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/SysRegWrite", "Number of system register writes in R3.");
866	GIC_REG_COUNTER(&pGicCpu->StatSetSpiR3, "%u/SetSpi", "Number of set SPI callbacks in R3.");
867	GIC_REG_COUNTER(&pGicCpu->StatSetPpiR3, "%u/SetPpi", "Number of set PPI callbacks in R3.");
868	GIC_REG_COUNTER(&pGicCpu->StatSetSgiR3, "%u/SetSgi", "Number of SGIs generated in R3.");
869
870	GIC_PROF_COUNTER(&pGicCpu->StatProfIntrAckR3, "%u/Prof/IntrAck", "Profiling of interrupt acknowledge (IAR) in R3.");
871	GIC_PROF_COUNTER(&pGicCpu->StatProfSetSpiR3, "%u/Prof/SetSpi", "Profiling of set SPI callback in R3.");
872	GIC_PROF_COUNTER(&pGicCpu->StatProfSetPpiR3, "%u/Prof/SetPpi", "Profiling of set PPI callback in R3.");
873	GIC_PROF_COUNTER(&pGicCpu->StatProfSetSgiR3, "%u/Prof/SetSgi", "Profiling of SGIs generated in R3.");
874	}
875	# undef GIC_REG_COUNTER
876	# undef GIC_PROF_COUNTER
877	#endif
878
879	gicR3Reset(pDevIns);
880
881	/*
882	* Log features/config.
883	*/
884	uint8_t const uArchRev = pGicDev->uArchRev;
885	uint8_t const uMaxSpi = pGicDev->uMaxSpi;
886	bool const fExtSpi = pGicDev->fExtSpi;
887	uint8_t const uMaxExtSpi = pGicDev->uMaxExtSpi;
888	bool const fExtPpi = pGicDev->fExtPpi;
889	uint8_t const uMaxExtPpi = pGicDev->uMaxExtPpi;
890	bool const fRangeSel = pGicDev->fRangeSel;
891	bool const fNmi = pGicDev->fNmi;
892	bool const fMbi = pGicDev->fMbi;
893	bool const fAff3Levels = pGicDev->fAff3Levels;
894	bool const fLpi = pGicDev->fLpi;
895	uint16_t const uExtPpiLast = uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 ? 1087 : GIC_INTID_RANGE_EXT_PPI_LAST;
896	LogRel(("GIC: ArchRev=%u RangeSel=%RTbool Nmi=%RTbool Mbi=%RTbool Aff3Levels=%RTbool Lpi=%RTbool\n",
897	uArchRev, fRangeSel, fNmi, fMbi, fAff3Levels, fLpi));
898	LogRel(("GIC: SPIs=true (%u:32..%u) ExtSPIs=%RTbool (%u:4095..%u) ExtPPIs=%RTbool (%u:1056..%u)\n",
899	uMaxSpi, 32 * (uMaxSpi + 1),
900	fExtSpi, uMaxExtSpi, GIC_INTID_RANGE_EXT_SPI_START - 1 + 32 * (uMaxExtSpi + 1),
901	fExtPpi, uMaxExtPpi, uExtPpiLast));
902	return VINF_SUCCESS;
903	}
904
905	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
906

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source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 108779

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