GICR3.cpp@ 108864

Last change on this file since 108864 was 108864, checked in by vboxsync, 2 weeks ago
VMM/GIC: bugref:10877 GIC ITS command-queue, work-in-progress.
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1	/* $Id: GICR3.cpp 108864 2025-04-07 09:10:44Z vboxsync $ */
2	/** @file
3	* GIC - Generic Interrupt Controller Architecture (GIC).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_GIC
33	#include <VBox/log.h>
34	#include "GICInternal.h"
35	#include <VBox/vmm/pdmgic.h>
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/pdmdev.h>
40	#include <VBox/vmm/ssm.h>
41	#include <VBox/vmm/vm.h>
42
43	#include <iprt/armv8.h>
44	#include <iprt/mem.h>
45
46
47	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
48
49
50	/*********************************************************************************************************************************
51	* Defined Constants And Macros *
52	*********************************************************************************************************************************/
53	/** GIC saved state version. */
54	#define GIC_SAVED_STATE_VERSION 8
55
56	# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
57	{ (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicIcc, kCpumSysRegWrFn_GicIcc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
58
59
60	/*********************************************************************************************************************************
61	* Global Variables *
62	*********************************************************************************************************************************/
63	/**
64	* System register ranges for the GIC.
65	*/
66	static CPUMSYSREGRANGE const g_aSysRegRanges_GIC[] =
67	{
68	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
69	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
70	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
71	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
72	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
73	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2"),
74	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, "ICC_SRE_EL3")
75	};
76
77
78	/**
79	* Dumps basic GIC state.
80	*
81	* @param pVM The cross context VM structure.
82	* @param pHlp The info helpers.
83	* @param pszArgs Arguments, ignored.
84	*/
85	static DECLCALLBACK(void) gicR3DbgInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
86	{
87	RT_NOREF(pszArgs);
88	PCGIC pGic = VM_TO_GIC(pVM);
89	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
90	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
91
92	pHlp->pfnPrintf(pHlp, "GIC:\n");
93	pHlp->pfnPrintf(pHlp, " uArchRev = %u\n", pGicDev->uArchRev);
94	pHlp->pfnPrintf(pHlp, " uArchRevMinor = %u\n", pGicDev->uArchRevMinor);
95	pHlp->pfnPrintf(pHlp, " uMaxSpi = %u (upto IntId %u)\n", pGicDev->uMaxSpi, 32 * (pGicDev->uMaxSpi + 1));
96	pHlp->pfnPrintf(pHlp, " fExtSpi = %RTbool\n", pGicDev->fExtSpi);
97	pHlp->pfnPrintf(pHlp, " uMaxExtSpi = %u (upto IntId %u)\n", pGicDev->uMaxExtSpi,
98	GIC_INTID_RANGE_EXT_SPI_START - 1 + 32 * (pGicDev->uMaxExtSpi + 1));
99	pHlp->pfnPrintf(pHlp, " fExtPpi = %RTbool\n", pGicDev->fExtPpi);
100	pHlp->pfnPrintf(pHlp, " uMaxExtPpi = %u (upto IntId %u)\n", pGicDev->uMaxExtPpi,
101	pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 ? 1087 : GIC_INTID_RANGE_EXT_PPI_LAST);
102	pHlp->pfnPrintf(pHlp, " fRangeSelSupport = %RTbool\n", pGicDev->fRangeSel);
103	pHlp->pfnPrintf(pHlp, " fNmi = %RTbool\n", pGicDev->fNmi);
104	pHlp->pfnPrintf(pHlp, " fMbi = %RTbool\n", pGicDev->fMbi);
105	pHlp->pfnPrintf(pHlp, " fAff3Levels = %RTbool\n", pGicDev->fAff3Levels);
106	pHlp->pfnPrintf(pHlp, " fLpi = %RTbool\n", pGicDev->fLpi);
107	}
108
109
110	/**
111	* Dumps GIC Distributor information.
112	*
113	* @param pVM The cross context VM structure.
114	* @param pHlp The info helpers.
115	* @param pszArgs Arguments, ignored.
116	*/
117	static DECLCALLBACK(void) gicR3DbgInfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
118	{
119	RT_NOREF(pszArgs);
120
121	PGIC pGic = VM_TO_GIC(pVM);
122	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
123	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
124
125	#define GIC_DBGFINFO_DIST_INTR_BITMAP(a_Name, a_bmIntr) \
126	do \
127	{ \
128	pHlp->pfnPrintf(pHlp, " " a_Name " =\n"); \
129	for (uint32_t i = 0; i < RT_ELEMENTS(a_bmIntr); i += 8) \
130	pHlp->pfnPrintf(pHlp, " [%2u..%-2u] %#010x %#010x %#010x %#010x %#010x %#010x %#010x %#010x\n", i, i + 7, \
131	(a_bmIntr)[i], (a_bmIntr)[i+1], (a_bmIntr)[i+2], (a_bmIntr)[i+3], \
132	(a_bmIntr)[i+4], (a_bmIntr)[i+5], (a_bmIntr)[i+6], (a_bmIntr)[i+7]); \
133	} while (0)
134
135	pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
136	pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicDev->fIntrGroup0Enabled);
137	pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicDev->fIntrGroup1Enabled);
138	pHlp->pfnPrintf(pHlp, " fAffRoutingEnabled = %RTbool\n", pGicDev->fAffRoutingEnabled);
139	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrGroup", pGicDev->bmIntrGroup);
140	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrEnabled", pGicDev->bmIntrEnabled);
141	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrPending", pGicDev->bmIntrPending);
142	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrActive", pGicDev->bmIntrActive);
143
144	/* Interrupt priorities.*/
145	{
146	uint32_t const cPriorities = RT_ELEMENTS(pGicDev->abIntrPriority);
147	AssertCompile(!(cPriorities % 16));
148	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
149	for (uint32_t i = 0; i < cPriorities; i += 16)
150	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
151	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
152	gicDistGetIntIdFromIndex(i), gicDistGetIntIdFromIndex(i + 7),
153	pGicDev->abIntrPriority[i], pGicDev->abIntrPriority[i + 1],
154	pGicDev->abIntrPriority[i + 2], pGicDev->abIntrPriority[i + 3],
155	pGicDev->abIntrPriority[i + 4], pGicDev->abIntrPriority[i + 5],
156	pGicDev->abIntrPriority[i + 6], pGicDev->abIntrPriority[i + 7],
157	gicDistGetIntIdFromIndex(i + 8), gicDistGetIntIdFromIndex(i + 15),
158	pGicDev->abIntrPriority[i + 8], pGicDev->abIntrPriority[i + 9],
159	pGicDev->abIntrPriority[i + 10], pGicDev->abIntrPriority[i + 11],
160	pGicDev->abIntrPriority[i + 12], pGicDev->abIntrPriority[i + 13],
161	pGicDev->abIntrPriority[i + 14], pGicDev->abIntrPriority[i + 15]);
162	}
163
164	/* Interrupt routing.*/
165	{
166	/** @todo Interrupt rounting mode. */
167	uint32_t const cRouting = RT_ELEMENTS(pGicDev->au32IntrRouting);
168	AssertCompile(!(cRouting % 16));
169	pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
170	for (uint32_t i = 0; i < cRouting; i += 16)
171	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
172	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
173	gicDistGetIntIdFromIndex(i), gicDistGetIntIdFromIndex(i + 7),
174	pGicDev->au32IntrRouting[i], pGicDev->au32IntrRouting[i + 1],
175	pGicDev->au32IntrRouting[i + 2], pGicDev->au32IntrRouting[i + 3],
176	pGicDev->au32IntrRouting[i + 4], pGicDev->au32IntrRouting[i + 5],
177	pGicDev->au32IntrRouting[i + 6], pGicDev->au32IntrRouting[i + 7],
178	gicDistGetIntIdFromIndex(i + 8), gicDistGetIntIdFromIndex(i + 15),
179	pGicDev->au32IntrRouting[i + 8], pGicDev->au32IntrRouting[i + 9],
180	pGicDev->au32IntrRouting[i + 10], pGicDev->au32IntrRouting[i + 11],
181	pGicDev->au32IntrRouting[i + 12], pGicDev->au32IntrRouting[i + 13],
182	pGicDev->au32IntrRouting[i + 14], pGicDev->au32IntrRouting[i + 15]);
183	}
184
185	#undef GIC_DBGFINFO_DIST_INTR_BITMAP
186	}
187
188
189	/**
190	* Dumps the GIC Redistributor information.
191	*
192	* @param pVM The cross context VM structure.
193	* @param pHlp The info helpers.
194	* @param pszArgs Arguments, ignored.
195	*/
196	static DECLCALLBACK(void) gicR3DbgInfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
197	{
198	NOREF(pszArgs);
199	PVMCPU pVCpu = VMMGetCpu(pVM);
200	if (!pVCpu)
201	pVCpu = pVM->apCpusR3[0];
202
203	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
204
205	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
206	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrGroup) >= 3);
207	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrEnabled) >= 3);
208	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrPending) >= 3);
209	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrActive) >= 3);
210
211	#define GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(a_bmIntr) pGicCpu->a_bmIntr[0], pGicCpu->a_bmIntr[1], pGicCpu->a_bmIntr[2]
212	pHlp->pfnPrintf(pHlp, " bmIntrGroup[0..2] = %#010x %#010x %#010x\n", GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(bmIntrGroup));
213	pHlp->pfnPrintf(pHlp, " bmIntrEnabled[0..2] = %#010x %#010x %#010x\n", GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(bmIntrEnabled));
214	pHlp->pfnPrintf(pHlp, " bmIntrPending[0..2] = %#010x %#010x %#010x\n", GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(bmIntrPending));
215	pHlp->pfnPrintf(pHlp, " bmIntrActive[0..2] = %#010x %#010x %#010x\n", GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(bmIntrActive));
216	#undef GIC_DBGFINFO_REDIST_INTR_BITMAPS
217
218	/* Interrupt priorities. */
219	{
220	uint32_t const cPriorities = RT_ELEMENTS(pGicCpu->abIntrPriority);
221	AssertCompile(!(cPriorities % 16));
222	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
223	for (uint32_t i = 0; i < cPriorities; i += 16)
224	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
225	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
226	gicReDistGetIntIdFromIndex(i), gicReDistGetIntIdFromIndex(i + 7),
227	pGicCpu->abIntrPriority[i], pGicCpu->abIntrPriority[i + 1],
228	pGicCpu->abIntrPriority[i + 2], pGicCpu->abIntrPriority[i + 3],
229	pGicCpu->abIntrPriority[i + 4], pGicCpu->abIntrPriority[i + 5],
230	pGicCpu->abIntrPriority[i + 6], pGicCpu->abIntrPriority[i + 7],
231	gicReDistGetIntIdFromIndex(i + 8), gicReDistGetIntIdFromIndex(i + 15),
232	pGicCpu->abIntrPriority[i + 8], pGicCpu->abIntrPriority[i + 9],
233	pGicCpu->abIntrPriority[i + 10], pGicCpu->abIntrPriority[i + 11],
234	pGicCpu->abIntrPriority[i + 12], pGicCpu->abIntrPriority[i + 13],
235	pGicCpu->abIntrPriority[i + 14], pGicCpu->abIntrPriority[i + 15]);
236	}
237
238	pHlp->pfnPrintf(pHlp, "\nVCPU[%u] ICC system register state:\n", pVCpu->idCpu);
239	pHlp->pfnPrintf(pHlp, " uIccCtlr = %#RX64\n", pGicCpu->uIccCtlr);
240	pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicCpu->fIntrGroup0Enabled);
241	pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicCpu->fIntrGroup1Enabled);
242	pHlp->pfnPrintf(pHlp, " bBinaryPtGroup0 = %#x\n", pGicCpu->bBinaryPtGroup0);
243	pHlp->pfnPrintf(pHlp, " bBinaryPtGroup1 = %#x\n", pGicCpu->bBinaryPtGroup1);
244	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %#x\n", pGicCpu->idxRunningPriority);
245	pHlp->pfnPrintf(pHlp, " Running priority = %#x\n", pGicCpu->abRunningPriorities[pGicCpu->idxRunningPriority]);
246
247	/* Running interrupt priorities. */
248	{
249	uint32_t const cPriorities = RT_ELEMENTS(pGicCpu->abRunningPriorities);
250	AssertCompile(!(cPriorities % 16));
251	pHlp->pfnPrintf(pHlp, " Running-interrupt priorities:\n");
252	for (uint32_t i = 0; i < cPriorities; i += 16)
253	pHlp->pfnPrintf(pHlp, " [%3u..%-3u] = %3u %3u %3u %3u %3u %3u %3u %3u"
254	" [%3u..%-3u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
255	i, i + 7,
256	pGicCpu->abRunningPriorities[i], pGicCpu->abRunningPriorities[i + 1],
257	pGicCpu->abRunningPriorities[i + 2], pGicCpu->abRunningPriorities[i + 3],
258	pGicCpu->abRunningPriorities[i + 4], pGicCpu->abRunningPriorities[i + 5],
259	pGicCpu->abRunningPriorities[i + 6], pGicCpu->abRunningPriorities[i + 7],
260	i + 8, i + 15,
261	pGicCpu->abRunningPriorities[i + 8], pGicCpu->abRunningPriorities[i + 9],
262	pGicCpu->abRunningPriorities[i + 10], pGicCpu->abRunningPriorities[i + 11],
263	pGicCpu->abRunningPriorities[i + 12], pGicCpu->abRunningPriorities[i + 13],
264	pGicCpu->abRunningPriorities[i + 14], pGicCpu->abRunningPriorities[i + 15]);
265	}
266
267	AssertCompile(RT_ELEMENTS(pGicCpu->bmActivePriorityGroup0) >= 4);
268	pHlp->pfnPrintf(pHlp, " Active-interrupt priorities Group 0:\n");
269	pHlp->pfnPrintf(pHlp, " [0..3] = %#010x %#010x %#010x %#010x\n",
270	pGicCpu->bmActivePriorityGroup0[0], pGicCpu->bmActivePriorityGroup0[1],
271	pGicCpu->bmActivePriorityGroup0[2], pGicCpu->bmActivePriorityGroup0[3]);
272	AssertCompile(RT_ELEMENTS(pGicCpu->bmActivePriorityGroup1) >= 4);
273	pHlp->pfnPrintf(pHlp, " Active-interrupt priorities Group 1:\n");
274	pHlp->pfnPrintf(pHlp, " [0..3] = %#010x %#010x %#010x %#010x\n",
275	pGicCpu->bmActivePriorityGroup1[0], pGicCpu->bmActivePriorityGroup1[1],
276	pGicCpu->bmActivePriorityGroup1[2], pGicCpu->bmActivePriorityGroup1[3]);
277	}
278
279
280	/**
281	* Dumps the GIC ITS information.
282	*
283	* @param pVM The cross context VM structure.
284	* @param pHlp The info helpers.
285	* @param pszArgs Arguments, ignored.
286	*/
287	static DECLCALLBACK(void) gicR3DbgInfoIts(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
288	{
289	PGIC pGic = VM_TO_GIC(pVM);
290	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
291	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
292	if (pGicDev->hMmioGits != NIL_IOMMMIOHANDLE)
293	gitsR3DbgInfo(&pGicDev->Gits, pHlp, pszArgs);
294	else
295	pHlp->pfnPrintf(pHlp, "GIC ITS is not mapped/configured for the VM\n");
296	}
297
298
299	/**
300	* The GIC ITS command-queue thread.
301	*
302	* @returns VBox status code.
303	* @param pDevIns The device instance.
304	* @param pThread The command thread.
305	*/
306	static DECLCALLBACK(int) gicItsR3CmdQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
307	{
308	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
309	return VINF_SUCCESS;
310
311	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
312	PGITSDEV pGitsDev = &pGicDev->Gits;
313	AssertPtrReturn(pGicDev, VERR_INVALID_PARAMETER);
314	LogFlowFunc(("Command-queue thread spawned and initialized\n"));
315
316	/*
317	* Pre-allocate the maximum size of the command queue allowed by the ARM GIC spec.
318	* This prevents trashing the heap as well as dealing with out-of-memory situations
319	* up-front while starting the VM. It also simplifies the code from having to
320	* dynamically grow/shrink the allocation based on how software sizes the queue.
321	* Guests normally don't alter the queue size all the time, but that's not an
322	* assumption we can make. Another benefit is that we can avoid releasing and
323	* re-acquiring the device critical section if/when guests modifies the command
324	* queue size.
325	*/
326	uint16_t const cMaxPages = GITS_BF_CTRL_REG_CBASER_SIZE_MASK + 1;
327	size_t const cbCmds = cMaxPages << GITS_CMD_QUEUE_PAGE_SHIFT;
328	void *pvCmds = RTMemAllocZ(cbCmds);
329	AssertLogRelMsgReturn(pvCmds, ("Failed to alloc %.Rhcb (%zu bytes) for the GITS command queue\n", cbCmds, cbCmds),
330	VERR_NO_MEMORY);
331
332	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
333	{
334	/* Sleep until we are woken up. */
335	{
336	int const rcLock = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pGitsDev->hEvtCmdQueue, RT_INDEFINITE_WAIT);
337	AssertLogRelMsgReturnStmt(RT_SUCCESS(rcLock) \|\| rcLock == VERR_INTERRUPTED, ("%Rrc\n", rcLock),
338	RTMemFree(pvCmds), rcLock);
339	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
340	break;
341	}
342
343	/* Process the command queue. */
344	int const rc = gitsR3CmdQueueProcess(pDevIns, pGitsDev, pvCmds, cbCmds);
345	if (RT_FAILURE(rc))
346	break;
347	}
348
349	RTMemFree(pvCmds);
350
351	LogFlowFunc(("Command-queue thread terminating\n"));
352	return VINF_SUCCESS;
353	}
354
355
356	/**
357	* Wakes up the command-queue thread so it can respond to a state change.
358	*
359	* @return VBox status code.
360	* @param pDevIns The device instance.
361	* @param pThread The command-queue thread.
362	*
363	* @thread EMT.
364	*/
365	static DECLCALLBACK(int) gicItsR3CmdQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
366	{
367	RT_NOREF(pThread);
368	LogFlowFunc(("\n"));
369	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
370	PGITSDEV pGitsDev = &pGicDev->Gits;
371	return PDMDevHlpSUPSemEventSignal(pDevIns, pGitsDev->hEvtCmdQueue);
372	}
373
374
375	/**
376	* @copydoc FNSSMDEVSAVEEXEC
377	*/
378	static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
379	{
380	PCVM pVM = PDMDevHlpGetVM(pDevIns);
381	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
382	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
383	AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
384	LogFlowFunc(("\n"));
385
386	/*
387	* Save per-VM data.
388	*/
389	pHlp->pfnSSMPutU32(pSSM, pVM->cCpus);
390	pHlp->pfnSSMPutU8(pSSM, pGicDev->uArchRev);
391	pHlp->pfnSSMPutU8(pSSM, pGicDev->uArchRevMinor);
392	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxSpi);
393	pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtSpi);
394	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxExtSpi);
395	pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtPpi);
396	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxExtPpi);
397	pHlp->pfnSSMPutBool(pSSM, pGicDev->fRangeSel);
398	pHlp->pfnSSMPutBool(pSSM, pGicDev->fNmi);
399	pHlp->pfnSSMPutBool(pSSM, pGicDev->fMbi);
400	pHlp->pfnSSMPutBool(pSSM, pGicDev->fAff3Levels);
401	pHlp->pfnSSMPutBool(pSSM, pGicDev->fLpi);
402
403	/* Distributor state. */
404	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup0Enabled);
405	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup1Enabled);
406	pHlp->pfnSSMPutBool(pSSM, pGicDev->fAffRoutingEnabled);
407	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrGroup[0], sizeof(pGicDev->bmIntrGroup));
408	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrConfig[0], sizeof(pGicDev->bmIntrConfig));
409	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrEnabled[0], sizeof(pGicDev->bmIntrEnabled));
410	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrPending[0], sizeof(pGicDev->bmIntrPending));
411	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrActive[0], sizeof(pGicDev->bmIntrActive));
412	pHlp->pfnSSMPutMem(pSSM, &pGicDev->abIntrPriority[0], sizeof(pGicDev->abIntrPriority));
413	pHlp->pfnSSMPutMem(pSSM, &pGicDev->au32IntrRouting[0], sizeof(pGicDev->au32IntrRouting));
414	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrRoutingMode[0], sizeof(pGicDev->bmIntrRoutingMode));
415
416	/* We store the size followed by the data because we currently do not support the full LPI range. */
417	pHlp->pfnSSMPutU32(pSSM, sizeof(pGicDev->abLpiConfig));
418	pHlp->pfnSSMPutMem(pSSM, &pGicDev->abLpiConfig[0], sizeof(pGicDev->abLpiConfig));
419	pHlp->pfnSSMPutU32(pSSM, sizeof(pGicDev->bmLpiPending));
420	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmLpiPending[0], sizeof(pGicDev->bmLpiPending));
421
422	/** @todo GITS data. */
423
424	/*
425	* Save per-VCPU data.
426	*/
427	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
428	{
429	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
430	Assert(pGicCpu);
431
432	/* Redistributor state. */
433	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrGroup[0], sizeof(pGicCpu->bmIntrGroup));
434	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrConfig[0], sizeof(pGicCpu->bmIntrConfig));
435	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrEnabled[0], sizeof(pGicCpu->bmIntrEnabled));
436	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrPending[0], sizeof(pGicCpu->bmIntrPending));
437	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrActive[0], sizeof(pGicCpu->bmIntrActive));
438	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->abIntrPriority[0], sizeof(pGicCpu->abIntrPriority));
439
440	/* ICC system register state. */
441	pHlp->pfnSSMPutU64(pSSM, pGicCpu->uIccCtlr);
442	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bIntrPriorityMask);
443	pHlp->pfnSSMPutU8(pSSM, pGicCpu->idxRunningPriority);
444	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->abRunningPriorities[0], sizeof(pGicCpu->abRunningPriorities));
445	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmActivePriorityGroup0[0], sizeof(pGicCpu->bmActivePriorityGroup0));
446	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmActivePriorityGroup1[0], sizeof(pGicCpu->bmActivePriorityGroup1));
447	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPtGroup0);
448	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPtGroup1);
449	pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup0Enabled);
450	pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup1Enabled);
451	}
452
453	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
454	}
455
456
457	/**
458	* @copydoc FNSSMDEVLOADEXEC
459	*/
460	static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
461	{
462	PVM pVM = PDMDevHlpGetVM(pDevIns);
463	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
464
465	AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
466	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
467	LogFlowFunc(("uVersion=%u uPass=%#x\n", uVersion, uPass));
468
469	/*
470	* Validate supported saved-state versions.
471	*/
472	if (uVersion != GIC_SAVED_STATE_VERSION)
473	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid saved-state version %u"), uVersion);
474
475	/*
476	* Load per-VM data.
477	*/
478	uint32_t cCpus;
479	pHlp->pfnSSMGetU32(pSSM, &cCpus);
480	if (cCpus != pVM->cCpus)
481	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cCpus: got=%u expected=%u"), cCpus, pVM->cCpus);
482
483	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
484	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uArchRev);
485	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uArchRevMinor);
486	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxSpi);
487	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtSpi);
488	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxExtSpi);
489	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtPpi);
490	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxExtPpi);
491	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fRangeSel);
492	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fNmi);
493	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fMbi);
494	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAff3Levels);
495	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fLpi);
496
497	/* Distributor state. */
498	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup0Enabled);
499	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup1Enabled);
500	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAffRoutingEnabled);
501	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrGroup[0], sizeof(pGicDev->bmIntrGroup));
502	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrConfig[0], sizeof(pGicDev->bmIntrConfig));
503	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrEnabled[0], sizeof(pGicDev->bmIntrEnabled));
504	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrPending[0], sizeof(pGicDev->bmIntrPending));
505	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrActive[0], sizeof(pGicDev->bmIntrActive));
506	pHlp->pfnSSMGetMem(pSSM, &pGicDev->abIntrPriority[0], sizeof(pGicDev->abIntrPriority));
507	pHlp->pfnSSMGetMem(pSSM, &pGicDev->au32IntrRouting[0], sizeof(pGicDev->au32IntrRouting));
508	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrRoutingMode[0], sizeof(pGicDev->bmIntrRoutingMode));
509
510	/* LPI config. */
511	{
512	uint32_t cbData = 0;
513	int const rc = pHlp->pfnSSMGetU32(pSSM, &cbData);
514	AssertRCReturn(rc, rc);
515	if (cbData <= sizeof(pGicDev->abLpiConfig))
516	pHlp->pfnSSMGetMem(pSSM, &pGicDev->abLpiConfig[0], cbData);
517	else
518	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPI config table size: got=%u expected=%u"),
519	cbData, sizeof(pGicDev->abLpiConfig));
520	}
521	/* LPI pending. */
522	{
523	uint32_t cbData = 0;
524	int const rc = pHlp->pfnSSMGetU32(pSSM, &cbData);
525	AssertRCReturn(rc, rc);
526	if (cbData <= sizeof(pGicDev->bmLpiPending))
527	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmLpiPending[0], cbData);
528	else
529	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPI pending bitmap size: got=%u expected=%u"),
530	cbData, sizeof(pGicDev->bmLpiPending));
531	}
532
533	/** @todo GITS data. */
534
535	/*
536	* Load per-VCPU data.
537	*/
538	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
539	{
540	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
541	Assert(pGicCpu);
542
543	/* Redistributor state. */
544	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrGroup[0], sizeof(pGicCpu->bmIntrGroup));
545	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrConfig[0], sizeof(pGicCpu->bmIntrConfig));
546	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrEnabled[0], sizeof(pGicCpu->bmIntrEnabled));
547	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrPending[0], sizeof(pGicCpu->bmIntrPending));
548	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrActive[0], sizeof(pGicCpu->bmIntrActive));
549	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->abIntrPriority[0], sizeof(pGicCpu->abIntrPriority));
550
551	/* ICC system register state. */
552	pHlp->pfnSSMGetU64(pSSM, &pGicCpu->uIccCtlr);
553	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bIntrPriorityMask);
554	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->idxRunningPriority);
555	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->abRunningPriorities[0], sizeof(pGicCpu->abRunningPriorities));
556	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmActivePriorityGroup0[0], sizeof(pGicCpu->bmActivePriorityGroup0));
557	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmActivePriorityGroup1[0], sizeof(pGicCpu->bmActivePriorityGroup1));
558	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPtGroup0);
559	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPtGroup1);
560	pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup0Enabled);
561	pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup1Enabled);
562	}
563
564	/*
565	* Check that we're still good wrt restored data.
566	*/
567	int rc = pHlp->pfnSSMHandleGetStatus(pSSM);
568	AssertRCReturn(rc, rc);
569
570	uint32_t uMarker = 0;
571	rc = pHlp->pfnSSMGetU32(pSSM, &uMarker);
572	AssertRCReturn(rc, rc);
573	if (uMarker == UINT32_MAX)
574	{ /* likely */ }
575	else
576	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Marker: got=%u expected=%u"), uMarker, UINT32_MAX);
577
578	/*
579	* Finally, perform sanity checks.
580	*/
581	if (pGicDev->uArchRev <= GIC_DIST_REG_PIDR2_ARCHREV_GICV4)
582	{ /* likely */ }
583	else
584	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid uArchRev, got %u expected range [1,31]"), pGicDev->uArchRev,
585	GIC_DIST_REG_PIDR2_ARCHREV_GICV1, GIC_DIST_REG_PIDR2_ARCHREV_GICV4);
586	if (pGicDev->uArchRevMinor == 1)
587	{ /* likely */ }
588	else
589	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid uArchRevMinor, got %u expected 1"), pGicDev->uArchRevMinor);
590	if (pGicDev->uMaxSpi - 1 < 31)
591	{ /* likely */ }
592	else
593	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxSpi, got %u expected range [1,31]"), pGicDev->uMaxSpi);
594	if (pGicDev->uMaxExtSpi <= 31)
595	{ /* likely */ }
596	else
597	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxExtSpi, got %u expected range [0,31]"), pGicDev->uMaxExtSpi);
598	if ( pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087
599	\|\| pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
600	{ /* likely */ }
601	else
602	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxExtPpi, got %u expected range [1,2]"), pGicDev->uMaxExtPpi);
603	bool const fIsGitsEnabled = RT_BOOL(pGicDev->hMmioGits != NIL_IOMMMIOHANDLE);
604	if (fIsGitsEnabled == pGicDev->fLpi)
605	{ /* likely */ }
606	else
607	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPIs are %s when ITS is %s"),
608	fIsGitsEnabled ? "enabled" : "disabled", pGicDev->fLpi ? "enabled" : "disabled");
609	return rc;
610	}
611
612
613	/**
614	* @interface_method_impl{PDMDEVREG,pfnReset}
615	*/
616	DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
617	{
618	PVM pVM = PDMDevHlpGetVM(pDevIns);
619	VM_ASSERT_EMT0(pVM);
620	VM_ASSERT_IS_NOT_RUNNING(pVM);
621
622	LogFlow(("GIC: gicR3Reset\n"));
623
624	gicReset(pDevIns);
625	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
626	{
627	PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
628	gicResetCpu(pDevIns, pVCpuDest);
629	}
630	}
631
632
633	/**
634	* @interface_method_impl{PDMDEVREG,pfnDestruct}
635	*/
636	DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
637	{
638	LogFlowFunc(("pDevIns=%p\n", pDevIns));
639	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
640
641	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
642	PGITSDEV pGitsDev = &pGicDev->Gits;
643	if (pGitsDev->hEvtCmdQueue != NIL_SUPSEMEVENT)
644	{
645	PDMDevHlpSUPSemEventClose(pDevIns, pGitsDev->hEvtCmdQueue);
646	pGitsDev->hEvtCmdQueue = NIL_SUPSEMEVENT;
647	}
648
649	return VINF_SUCCESS;
650	}
651
652
653	/**
654	* @interface_method_impl{PDMDEVREG,pfnConstruct}
655	*/
656	DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
657	{
658	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
659	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
660	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
661	PVM pVM = PDMDevHlpGetVM(pDevIns);
662	PGIC pGic = VM_TO_GIC(pVM);
663	Assert(iInstance == 0);
664
665	/*
666	* Init the data.
667	*/
668	pGic->pDevInsR3 = pDevIns;
669
670	/*
671	* Validate GIC settings.
672	*/
673	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase\|RedistributorMmioBase\|ItsMmioBase"
674	"\|ArchRev"
675	"\|ArchRevMinor"
676	"\|MaxSpi"
677	"\|ExtSpi"
678	"\|MaxExtSpi"
679	"\|ExtPpi"
680	"\|MaxExtPpi"
681	"\|RangeSel"
682	"\|Nmi"
683	"\|Mbi"
684	"\|Aff3Levels"
685	"\|Lpi"
686	"\|MaxLpi", "");
687
688	#if 0
689	/*
690	* Disable automatic PDM locking for this device.
691	*/
692	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
693	AssertRCReturn(rc, rc);
694	#endif
695
696	/** @devcfgm{gic, ArchRev, uint8_t, 3}
697	* Configures the GIC architecture revision (GICD_PIDR2.ArchRev, GICR_PIDR2.ArchRev
698	* and GITS_PIDR2.ArchRev).
699	*
700	* Currently we only support GICv3 and the architecture revision reported is the
701	* same for both the GIC and the ITS. */
702	int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRev", &pGicDev->uArchRev, 3);
703	AssertLogRelRCReturn(rc, rc);
704	if (pGicDev->uArchRev == GIC_DIST_REG_PIDR2_ARCHREV_GICV3)
705	{
706	AssertCompile(GIC_DIST_REG_PIDR2_ARCHREV_GICV3 == GITS_CTRL_REG_PIDR2_ARCHREV_GICV3);
707	pGicDev->Gits.uArchRev = pGicDev->uArchRev;
708	}
709	else
710	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
711	N_("Configuration error: \"ArchRev\" must be %u, other revisions not supported"),
712	GIC_DIST_REG_PIDR2_ARCHREV_GICV3);
713
714	/** @devcfgm{gic, ArchRevMinor, uint8_t, 1}
715	* Configures the GIC architecture revision minor version.
716	*
717	* Currently we support GICv3.1 only. GICv3.1's only addition to GICv3 is supported
718	* for extended INTID ranges which we currently always support. */
719	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRevMinor", &pGicDev->uArchRevMinor, 1);
720	AssertLogRelRCReturn(rc, rc);
721	if (pGicDev->uArchRevMinor == 1)
722	{ /* likely */ }
723	else
724	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
725	N_("Configuration error: \"ArchRevMinor\" must be 1, other minor revisions not supported"));
726
727	/** @devcfgm{gic, MaxSpi, uint8_t, 31}
728	* Configures GICD_TYPER.ItLinesNumber.
729	*
730	* For the IntId range [32,1023], configures the maximum SPI supported. Valid values
731	* are [1,31] which equates to interrupt IDs [63,1023]. A value of 0 implies SPIs
732	* are not supported. We don't allow configuring this value as it's expected that
733	* most guests would assume support for SPIs. */
734	AssertCompile(GIC_DIST_REG_TYPER_NUM_ITLINES == 31);
735	/** @todo This currently isn't implemented and the full range is always
736	* reported to the guest. */
737	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxSpi", &pGicDev->uMaxSpi, 31 /* Upto and incl. IntId 1023 */);
738	AssertLogRelRCReturn(rc, rc);
739	if (pGicDev->uMaxSpi - 1 < 31)
740	{ /* likely */ }
741	else
742	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
743	N_("Configuration error: \"MaxSpi\" must be in the range [1,%u]"),
744	GIC_DIST_REG_TYPER_NUM_ITLINES);
745
746	/** @devcfgm{gic, ExtSpi, bool, false}
747	* Configures whether extended SPIs supported is enabled (GICD_TYPER.ESPI). */
748	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtSpi", &pGicDev->fExtSpi, true);
749	AssertLogRelRCReturn(rc, rc);
750
751	/** @devcfgm{gic, MaxExtSpi, uint8_t, 31}
752	* Configures GICD_TYPER.ESPI_range.
753	*
754	* For the extended SPI range [4096,5119], configures the maximum extended SPI
755	* supported. Valid values are [0,31] which equates to extended SPI IntIds
756	* [4127,5119]. This is ignored (set to 0 in the register) when extended SPIs are
757	* disabled. */
758	AssertCompile(GIC_DIST_REG_TYPER_ESPI_RANGE >> GIC_DIST_REG_TYPER_ESPI_RANGE_BIT == 31);
759	/** @todo This currently isn't implemented and the full range is always
760	* reported to the guest. */
761	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxExtSpi", &pGicDev->uMaxExtSpi, 31);
762	AssertLogRelRCReturn(rc, rc);
763	if (pGicDev->uMaxExtSpi <= 31)
764	{ /* likely */ }
765	else
766	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
767	N_("Configuration error: \"MaxExtSpi\" must be in the range [0,31]"));
768
769	/** @devcfgm{gic, ExtPpi, bool, true}
770	* Configures whether extended PPIs support is enabled. */
771	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtPpi", &pGicDev->fExtPpi, true);
772	AssertLogRelRCReturn(rc, rc);
773
774	/** @devcfgm{gic, MaxExtPpi, uint8_t, 2}
775	* Configures GICR_TYPER.PPInum.
776	*
777	* For the extended PPI range [1056,5119], configures the maximum extended PPI
778	* supported. Valid values are [1,2] which equates to extended PPI IntIds
779	* [1087,1119]. This is unused when extended PPIs are disabled. */
780	/** @todo This currently isn't implemented and the full range is always
781	* reported to the guest. */
782	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxExtPpi", &pGicDev->uMaxExtPpi, 2);
783	AssertLogRelRCReturn(rc, rc);
784	if ( pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087
785	\|\| pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
786	{ /* likely */ }
787	else
788	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
789	N_("Configuration error: \"MaxExtPpi\" must be in the range [0,2]"));
790
791	/** @devcfgm{gic, RangeSel, bool, true}
792	* Configures whether range-selector support is enabled (GICD_TYPER.RSS and
793	* ICC_CTLR_EL1.RSS). */
794	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RangeSel", &pGicDev->fRangeSel, true);
795	AssertLogRelRCReturn(rc, rc);
796
797	/** @devcfgm{gic, Nmi, bool, false}
798	* Configures whether non-maskable interrupts (NMIs) are supported
799	* (GICD_TYPER.NMI). */
800	/** @todo NMIs are currently not implemented. */
801	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Nmi", &pGicDev->fNmi, false);
802	AssertLogRelRCReturn(rc, rc);
803
804	/** @devcfgm{gic, Mbi, bool, false}
805	* Configures whether message-based interrupts (MBIs) are supported
806	* (GICD_TYPER.MBIS).
807	*
808	* Guests typically can't use MBIs without an ITS. */
809	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Mbi", &pGicDev->fMbi, false);
810	AssertLogRelRCReturn(rc, rc);
811
812	/** @devcfgm{gic, Aff3Levels, bool, true}
813	* Configures whether non-zero affinity 3 levels (A3V) are supported
814	* (GICD_TYPER.A3V and ICC_CTLR.A3V). */
815	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Aff3Levels", &pGicDev->fAff3Levels, true);
816	AssertLogRelRCReturn(rc, rc);
817
818	/** @devcfgm{gic, Lpi, bool, false}
819	* Configures whether physical LPIs are supported (GICD_TYPER.LPIS and
820	* GICR_TYPER.PLPIS).
821	*
822	* This currently requires an ITS as we do not support direction injection of
823	* LPIs as most guests do not use them anyway. */
824	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Lpi", &pGicDev->fLpi, false);
825	AssertLogRelRCReturn(rc, rc);
826
827	/** @devcfgm{gic, MaxLpi, uint8_t, 14}
828	* Configures GICD_TYPER.num_LPIs.
829	*
830	* For the physical LPI range [8192,65535], configures the number of physical LPI
831	* supported. Valid values are [3,14] which equates to LPI IntIds 8192 to
832	* [8207,40959]. A value of 15 or higher would exceed the maximum INTID size of
833	* 16-bits since 8192 + 2^(NumLpi+1) is >= 73727. A value of 2 or lower support
834	* fewer than 15 LPIs which seem pointless and is hence disallowed. This value is
835	* ignored (set to 0 in the register) when LPIs are disabled. */
836	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxLpi", &pGicDev->uMaxLpi, 10);
837	AssertLogRelRCReturn(rc, rc);
838
839	/* We currently support 2048 LPIs until we need to support more. */
840	if (pGicDev->uMaxLpi == 10)
841	{ /* likely */ }
842	else
843	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
844	N_("Configuration error: \"MaxLpi\" must be in the range [3,14]"));
845	AssertRelease(UINT32_C(2) << pGicDev->uMaxLpi <= RT_ELEMENTS(pGicDev->abLpiConfig));
846
847	/*
848	* Register the GIC with PDM.
849	*/
850	rc = PDMDevHlpIcRegister(pDevIns);
851	AssertLogRelRCReturn(rc, rc);
852
853	rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
854	AssertLogRelRCReturn(rc, rc);
855
856	/*
857	* Insert the GIC system registers.
858	*/
859	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GIC); i++)
860	{
861	rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GIC[i]);
862	AssertLogRelRCReturn(rc, rc);
863	}
864
865	/*
866	* Register the MMIO ranges.
867	*/
868	/* Distributor. */
869	{
870	RTGCPHYS GCPhysMmioBase = 0;
871	rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
872	if (RT_FAILURE(rc))
873	return PDMDEV_SET_ERROR(pDevIns, rc,
874	N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
875
876	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
877	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC Distributor",
878	&pGicDev->hMmioDist);
879	AssertRCReturn(rc, rc);
880	}
881
882	/* Redistributor. */
883	{
884	RTGCPHYS GCPhysMmioBase = 0;
885	rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
886	if (RT_FAILURE(rc))
887	return PDMDEV_SET_ERROR(pDevIns, rc,
888	N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
889
890	RTGCPHYS const cbRegion = (RTGCPHYS)pVM->cCpus
891	* (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
892	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
893	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC Redistributor",
894	&pGicDev->hMmioReDist);
895	AssertRCReturn(rc, rc);
896	}
897
898	/* ITS. */
899	{
900	RTGCPHYS GCPhysMmioBase = 0;
901	rc = pHlp->pfnCFGMQueryU64(pCfg, "ItsMmioBase", &GCPhysMmioBase);
902	if (RT_SUCCESS(rc))
903	{
904	Assert(pGicDev->hMmioGits != NIL_IOMMMIOHANDLE); /* paranoia */
905	RTGCPHYS const cbRegion = 2 * GITS_REG_FRAME_SIZE; /* 2 frames for GICv3. */
906	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicItsMmioWrite, gicItsMmioRead,
907	IOMMMIO_FLAGS_READ_DWORD_QWORD
908	\| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED
909	\| IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
910	\| IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
911	"GIC ITS", &pGicDev->hMmioGits);
912	AssertLogRelRCReturn(rc, rc);
913
914	/* When the ITS is enabled we must support LPIs. */
915	if (!pGicDev->fLpi)
916	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
917	N_("Configuration error: \"Lpi\" must be enabled when ITS is enabled\n"));
918
919	/* Create ITS command-queue thread and semaphore. */
920	PGITSDEV pGitsDev = &pGicDev->Gits;
921	char szCmdQueueThread[32];
922	RT_ZERO(szCmdQueueThread);
923	RTStrPrintf(szCmdQueueThread, sizeof(szCmdQueueThread), "Gits-CmdQ-%u", iInstance);
924	rc = PDMDevHlpThreadCreate(pDevIns, &pGitsDev->pCmdQueueThread, &pGicDev, gicItsR3CmdQueueThread,
925	gicItsR3CmdQueueThreadWakeUp, 0 /* cbStack */, RTTHREADTYPE_IO, szCmdQueueThread);
926	AssertLogRelRCReturn(rc, rc);
927
928	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pGitsDev->hEvtCmdQueue);
929	AssertLogRelRCReturn(rc, rc);
930	}
931	else
932	{
933	pGicDev->hMmioGits = NIL_IOMMMIOHANDLE;
934
935	/* When the ITS is disabled we don't support LPIs as we do not support direct LPI injection (guests don't use it). */
936	if (pGicDev->fLpi)
937	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
938	N_("Configuration error: \"Lpi\" must be disabled when ITS is disabled\n"));
939	}
940	}
941
942	/*
943	* Register saved state callbacks.
944	*/
945	rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
946	AssertRCReturn(rc, rc);
947
948	/*
949	* Register debugger info callbacks.
950	*
951	* We use separate callbacks rather than arguments so they can also be
952	* dumped in an automated fashion while collecting crash diagnostics and
953	* not just used during live debugging via the VM debugger.
954	*/
955	DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3DbgInfo, DBGFINFO_FLAGS_ALL_EMTS);
956	DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC distributor information.", gicR3DbgInfoDist, DBGFINFO_FLAGS_ALL_EMTS);
957	DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC redistributor information.", gicR3DbgInfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
958	DBGFR3InfoRegisterInternalEx(pVM, "gicits", "Dumps GIC ITS information.", gicR3DbgInfoIts, DBGFINFO_FLAGS_ALL_EMTS);
959
960	/*
961	* Statistics.
962	*/
963	#ifdef VBOX_WITH_STATISTICS
964	# define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
965	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, \
966	a_pszDesc, a_pszNameFmt, idCpu)
967	# define GIC_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
968	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, \
969	a_pszDesc, a_pszNameFmt, idCpu)
970
971	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
972	{
973	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
974	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
975
976	GIC_REG_COUNTER(&pGicCpu->StatMmioReadR3, "%u/MmioRead", "Number of MMIO reads in R3.");
977	GIC_REG_COUNTER(&pGicCpu->StatMmioWriteR3, "%u/MmioWrite", "Number of MMIO writes in R3.");
978	GIC_REG_COUNTER(&pGicCpu->StatSysRegReadR3, "%u/SysRegRead", "Number of system register reads in R3.");
979	GIC_REG_COUNTER(&pGicCpu->StatSysRegWriteR3, "%u/SysRegWrite", "Number of system register writes in R3.");
980	GIC_REG_COUNTER(&pGicCpu->StatSetSpiR3, "%u/SetSpi", "Number of set SPI callbacks in R3.");
981	GIC_REG_COUNTER(&pGicCpu->StatSetPpiR3, "%u/SetPpi", "Number of set PPI callbacks in R3.");
982	GIC_REG_COUNTER(&pGicCpu->StatSetSgiR3, "%u/SetSgi", "Number of SGIs generated in R3.");
983
984	GIC_PROF_COUNTER(&pGicCpu->StatProfIntrAckR3, "%u/Prof/IntrAck", "Profiling of interrupt acknowledge (IAR) in R3.");
985	GIC_PROF_COUNTER(&pGicCpu->StatProfSetSpiR3, "%u/Prof/SetSpi", "Profiling of set SPI callback in R3.");
986	GIC_PROF_COUNTER(&pGicCpu->StatProfSetPpiR3, "%u/Prof/SetPpi", "Profiling of set PPI callback in R3.");
987	GIC_PROF_COUNTER(&pGicCpu->StatProfSetSgiR3, "%u/Prof/SetSgi", "Profiling of SGIs generated in R3.");
988	}
989	# undef GIC_REG_COUNTER
990	# undef GIC_PROF_COUNTER
991	#endif
992
993	gicR3Reset(pDevIns);
994
995	/*
996	* Log some of the features exposed to software.
997	*/
998	uint8_t const uArchRev = pGicDev->uArchRev;
999	uint8_t const uArchRevMinor = pGicDev->uArchRevMinor;
1000	uint8_t const uMaxSpi = pGicDev->uMaxSpi;
1001	bool const fExtSpi = pGicDev->fExtSpi;
1002	uint8_t const uMaxExtSpi = pGicDev->uMaxExtSpi;
1003	bool const fExtPpi = pGicDev->fExtPpi;
1004	uint8_t const uMaxExtPpi = pGicDev->uMaxExtPpi;
1005	bool const fRangeSel = pGicDev->fRangeSel;
1006	bool const fNmi = pGicDev->fNmi;
1007	bool const fMbi = pGicDev->fMbi;
1008	bool const fAff3Levels = pGicDev->fAff3Levels;
1009	bool const fLpi = pGicDev->fLpi;
1010	uint32_t const uMaxLpi = pGicDev->uMaxLpi;
1011	uint16_t const uExtPpiLast = uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 ? 1087 : GIC_INTID_RANGE_EXT_PPI_LAST;
1012	LogRel(("GIC: ArchRev=%u.%u RangeSel=%RTbool Nmi=%RTbool Mbi=%RTbool Aff3Levels=%RTbool\n",
1013	uArchRev, uArchRevMinor, fRangeSel, fNmi, fMbi, fAff3Levels));
1014	LogRel(("GIC: SPIs=true (%u:32..%u) ExtSPIs=%RTbool (%u:4095..%u) ExtPPIs=%RTbool (%u:1056..%u)\n",
1015	uMaxSpi, 32 * (uMaxSpi + 1),
1016	fExtSpi, uMaxExtSpi, GIC_INTID_RANGE_EXT_SPI_START - 1 + 32 * (uMaxExtSpi + 1),
1017	fExtPpi, uMaxExtPpi, uExtPpiLast));
1018	LogRel(("GIC: ITS=%s LPIs=%RTbool (%u:%u..%u)\n",
1019	pGicDev->hMmioGits != NIL_IOMMMIOHANDLE ? "enabled" : "disabled", fLpi,
1020	uMaxLpi, GIC_INTID_RANGE_LPI_START, GIC_INTID_RANGE_LPI_START - 1 + (UINT32_C(2) << uMaxLpi)));
1021	return VINF_SUCCESS;
1022	}
1023
1024	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1025

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source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 108864

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