GICR3.cpp@ 108946

Last change on this file since 108946 was 108946, checked in by vboxsync, 10 days ago
VMM/GIC: bugref:10877 LPI work-in-progress.
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1	/* $Id: GICR3.cpp 108946 2025-04-11 09:44:17Z vboxsync $ */
2	/** @file
3	* GIC - Generic Interrupt Controller Architecture (GIC).
4	*/
5
6	/*
7	* Copyright (C) 2023-2024 Oracle and/or its affiliates.
8	*
9	* This file is part of VirtualBox base platform packages, as
10	* available from https://www.virtualbox.org.
11	*
12	* This program is free software; you can redistribute it and/or
13	* modify it under the terms of the GNU General Public License
14	* as published by the Free Software Foundation, in version 3 of the
15	* License.
16	*
17	* This program is distributed in the hope that it will be useful, but
18	* WITHOUT ANY WARRANTY; without even the implied warranty of
19	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
20	* General Public License for more details.
21	*
22	* You should have received a copy of the GNU General Public License
23	* along with this program; if not, see <https://www.gnu.org/licenses>.
24	*
25	* SPDX-License-Identifier: GPL-3.0-only
26	*/
27
28
29	/*********************************************************************************************************************************
30	* Header Files *
31	*********************************************************************************************************************************/
32	#define LOG_GROUP LOG_GROUP_DEV_GIC
33	#include <VBox/log.h>
34	#include "GICInternal.h"
35	#include <VBox/vmm/pdmgic.h>
36	#include <VBox/vmm/cpum.h>
37	#include <VBox/vmm/hm.h>
38	#include <VBox/vmm/mm.h>
39	#include <VBox/vmm/pdmdev.h>
40	#include <VBox/vmm/ssm.h>
41	#include <VBox/vmm/vm.h>
42
43	#include <iprt/armv8.h>
44	#include <iprt/mem.h>
45
46
47	#ifndef VBOX_DEVICE_STRUCT_TESTCASE
48
49
50	/*********************************************************************************************************************************
51	* Defined Constants And Macros *
52	*********************************************************************************************************************************/
53	/** GIC saved state version. */
54	#define GIC_SAVED_STATE_VERSION 9
55
56	# define GIC_SYSREGRANGE(a_uFirst, a_uLast, a_szName) \
57	{ (a_uFirst), (a_uLast), kCpumSysRegRdFn_GicIcc, kCpumSysRegWrFn_GicIcc, 0, 0, 0, 0, 0, 0, a_szName, { 0 }, { 0 }, { 0 }, { 0 } }
58
59
60	/*********************************************************************************************************************************
61	* Global Variables *
62	*********************************************************************************************************************************/
63	/**
64	* System register ranges for the GIC.
65	*/
66	static CPUMSYSREGRANGE const g_aSysRegRanges_GIC[] =
67	{
68	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, ARMV8_AARCH64_SYSREG_ICC_PMR_EL1, "ICC_PMR_EL1"),
69	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR0_EL1, ARMV8_AARCH64_SYSREG_ICC_AP0R3_EL1, "ICC_IAR0_EL1 - ICC_AP0R3_EL1"),
70	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_AP1R0_EL1, ARMV8_AARCH64_SYSREG_ICC_NMIAR1_EL1, "ICC_AP1R0_EL1 - ICC_NMIAR1_EL1"),
71	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_DIR_EL1, ARMV8_AARCH64_SYSREG_ICC_SGI0R_EL1, "ICC_DIR_EL1 - ICC_SGI0R_EL1"),
72	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_IAR1_EL1, ARMV8_AARCH64_SYSREG_ICC_IGRPEN1_EL1, "ICC_IAR1_EL1 - ICC_IGRPEN1_EL1"),
73	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, ARMV8_AARCH64_SYSREG_ICC_SRE_EL2, "ICC_SRE_EL2"),
74	GIC_SYSREGRANGE(ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, ARMV8_AARCH64_SYSREG_ICC_SRE_EL3, "ICC_SRE_EL3")
75	};
76
77
78	/**
79	* Dumps basic GIC state.
80	*
81	* @param pVM The cross context VM structure.
82	* @param pHlp The info helpers.
83	* @param pszArgs Arguments, ignored.
84	*/
85	static DECLCALLBACK(void) gicR3DbgInfo(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
86	{
87	RT_NOREF(pszArgs);
88	PCGIC pGic = VM_TO_GIC(pVM);
89	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
90	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
91
92	pHlp->pfnPrintf(pHlp, "GIC:\n");
93	pHlp->pfnPrintf(pHlp, " uArchRev = %u\n", pGicDev->uArchRev);
94	pHlp->pfnPrintf(pHlp, " uArchRevMinor = %u\n", pGicDev->uArchRevMinor);
95	pHlp->pfnPrintf(pHlp, " uMaxSpi = %u (upto IntId %u)\n", pGicDev->uMaxSpi, 32 * (pGicDev->uMaxSpi + 1));
96	pHlp->pfnPrintf(pHlp, " fExtSpi = %RTbool\n", pGicDev->fExtSpi);
97	pHlp->pfnPrintf(pHlp, " uMaxExtSpi = %u (upto IntId %u)\n", pGicDev->uMaxExtSpi,
98	GIC_INTID_RANGE_EXT_SPI_START - 1 + 32 * (pGicDev->uMaxExtSpi + 1));
99	pHlp->pfnPrintf(pHlp, " fExtPpi = %RTbool\n", pGicDev->fExtPpi);
100	pHlp->pfnPrintf(pHlp, " uMaxExtPpi = %u (upto IntId %u)\n", pGicDev->uMaxExtPpi,
101	pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 ? 1087 : GIC_INTID_RANGE_EXT_PPI_LAST);
102	pHlp->pfnPrintf(pHlp, " fRangeSelSupport = %RTbool\n", pGicDev->fRangeSel);
103	pHlp->pfnPrintf(pHlp, " fNmi = %RTbool\n", pGicDev->fNmi);
104	pHlp->pfnPrintf(pHlp, " fMbi = %RTbool\n", pGicDev->fMbi);
105	pHlp->pfnPrintf(pHlp, " fAff3Levels = %RTbool\n", pGicDev->fAff3Levels);
106	pHlp->pfnPrintf(pHlp, " fLpi = %RTbool\n", pGicDev->fLpi);
107	}
108
109
110	/**
111	* Dumps GIC Distributor information.
112	*
113	* @param pVM The cross context VM structure.
114	* @param pHlp The info helpers.
115	* @param pszArgs Arguments, ignored.
116	*/
117	static DECLCALLBACK(void) gicR3DbgInfoDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
118	{
119	RT_NOREF(pszArgs);
120
121	PGIC pGic = VM_TO_GIC(pVM);
122	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
123	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
124
125	#define GIC_DBGFINFO_DIST_INTR_BITMAP(a_Name, a_bmIntr) \
126	do \
127	{ \
128	pHlp->pfnPrintf(pHlp, " " a_Name " =\n"); \
129	for (uint32_t i = 0; i < RT_ELEMENTS(a_bmIntr); i += 8) \
130	pHlp->pfnPrintf(pHlp, " [%2u..%-2u] %#010x %#010x %#010x %#010x %#010x %#010x %#010x %#010x\n", i, i + 7, \
131	(a_bmIntr)[i], (a_bmIntr)[i+1], (a_bmIntr)[i+2], (a_bmIntr)[i+3], \
132	(a_bmIntr)[i+4], (a_bmIntr)[i+5], (a_bmIntr)[i+6], (a_bmIntr)[i+7]); \
133	} while (0)
134
135	pHlp->pfnPrintf(pHlp, "GIC Distributor:\n");
136	pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicDev->fIntrGroup0Enabled);
137	pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicDev->fIntrGroup1Enabled);
138	pHlp->pfnPrintf(pHlp, " fAffRoutingEnabled = %RTbool\n", pGicDev->fAffRoutingEnabled);
139	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrGroup", pGicDev->bmIntrGroup);
140	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrEnabled", pGicDev->bmIntrEnabled);
141	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrPending", pGicDev->bmIntrPending);
142	GIC_DBGFINFO_DIST_INTR_BITMAP("bmIntrActive", pGicDev->bmIntrActive);
143
144	/* Interrupt priorities.*/
145	{
146	uint32_t const cPriorities = RT_ELEMENTS(pGicDev->abIntrPriority);
147	AssertCompile(!(cPriorities % 16));
148	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
149	for (uint32_t i = 0; i < cPriorities; i += 16)
150	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
151	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
152	gicDistGetIntIdFromIndex(i), gicDistGetIntIdFromIndex(i + 7),
153	pGicDev->abIntrPriority[i], pGicDev->abIntrPriority[i + 1],
154	pGicDev->abIntrPriority[i + 2], pGicDev->abIntrPriority[i + 3],
155	pGicDev->abIntrPriority[i + 4], pGicDev->abIntrPriority[i + 5],
156	pGicDev->abIntrPriority[i + 6], pGicDev->abIntrPriority[i + 7],
157	gicDistGetIntIdFromIndex(i + 8), gicDistGetIntIdFromIndex(i + 15),
158	pGicDev->abIntrPriority[i + 8], pGicDev->abIntrPriority[i + 9],
159	pGicDev->abIntrPriority[i + 10], pGicDev->abIntrPriority[i + 11],
160	pGicDev->abIntrPriority[i + 12], pGicDev->abIntrPriority[i + 13],
161	pGicDev->abIntrPriority[i + 14], pGicDev->abIntrPriority[i + 15]);
162	}
163
164	/* Interrupt routing.*/
165	{
166	/** @todo Interrupt rounting mode. */
167	uint32_t const cRouting = RT_ELEMENTS(pGicDev->au32IntrRouting);
168	AssertCompile(!(cRouting % 16));
169	pHlp->pfnPrintf(pHlp, " Interrupt routing:\n");
170	for (uint32_t i = 0; i < cRouting; i += 16)
171	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
172	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
173	gicDistGetIntIdFromIndex(i), gicDistGetIntIdFromIndex(i + 7),
174	pGicDev->au32IntrRouting[i], pGicDev->au32IntrRouting[i + 1],
175	pGicDev->au32IntrRouting[i + 2], pGicDev->au32IntrRouting[i + 3],
176	pGicDev->au32IntrRouting[i + 4], pGicDev->au32IntrRouting[i + 5],
177	pGicDev->au32IntrRouting[i + 6], pGicDev->au32IntrRouting[i + 7],
178	gicDistGetIntIdFromIndex(i + 8), gicDistGetIntIdFromIndex(i + 15),
179	pGicDev->au32IntrRouting[i + 8], pGicDev->au32IntrRouting[i + 9],
180	pGicDev->au32IntrRouting[i + 10], pGicDev->au32IntrRouting[i + 11],
181	pGicDev->au32IntrRouting[i + 12], pGicDev->au32IntrRouting[i + 13],
182	pGicDev->au32IntrRouting[i + 14], pGicDev->au32IntrRouting[i + 15]);
183	}
184
185	#undef GIC_DBGFINFO_DIST_INTR_BITMAP
186	}
187
188
189	/**
190	* Dumps the GIC Redistributor information.
191	*
192	* @param pVM The cross context VM structure.
193	* @param pHlp The info helpers.
194	* @param pszArgs Arguments, ignored.
195	*/
196	static DECLCALLBACK(void) gicR3DbgInfoReDist(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
197	{
198	NOREF(pszArgs);
199	PVMCPU pVCpu = VMMGetCpu(pVM);
200	if (!pVCpu)
201	pVCpu = pVM->apCpusR3[0];
202
203	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
204
205	pHlp->pfnPrintf(pHlp, "VCPU[%u] Redistributor:\n", pVCpu->idCpu);
206	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrGroup) >= 3);
207	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrEnabled) >= 3);
208	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrPending) >= 3);
209	AssertCompile(RT_ELEMENTS(pGicCpu->bmIntrActive) >= 3);
210
211	#define GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(a_bmIntr) pGicCpu->a_bmIntr[0], pGicCpu->a_bmIntr[1], pGicCpu->a_bmIntr[2]
212	pHlp->pfnPrintf(pHlp, " bmIntrGroup[0..2] = %#010x %#010x %#010x\n", GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(bmIntrGroup));
213	pHlp->pfnPrintf(pHlp, " bmIntrEnabled[0..2] = %#010x %#010x %#010x\n", GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(bmIntrEnabled));
214	pHlp->pfnPrintf(pHlp, " bmIntrPending[0..2] = %#010x %#010x %#010x\n", GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(bmIntrPending));
215	pHlp->pfnPrintf(pHlp, " bmIntrActive[0..2] = %#010x %#010x %#010x\n", GIC_DBGFINFO_REDIST_INTR_BITMAPS_3(bmIntrActive));
216	#undef GIC_DBGFINFO_REDIST_INTR_BITMAPS
217
218	/* Interrupt priorities. */
219	{
220	uint32_t const cPriorities = RT_ELEMENTS(pGicCpu->abIntrPriority);
221	AssertCompile(!(cPriorities % 16));
222	pHlp->pfnPrintf(pHlp, " Interrupt priorities:\n");
223	for (uint32_t i = 0; i < cPriorities; i += 16)
224	pHlp->pfnPrintf(pHlp, " IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u"
225	" IntId[%4u..%-4u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
226	gicReDistGetIntIdFromIndex(i), gicReDistGetIntIdFromIndex(i + 7),
227	pGicCpu->abIntrPriority[i], pGicCpu->abIntrPriority[i + 1],
228	pGicCpu->abIntrPriority[i + 2], pGicCpu->abIntrPriority[i + 3],
229	pGicCpu->abIntrPriority[i + 4], pGicCpu->abIntrPriority[i + 5],
230	pGicCpu->abIntrPriority[i + 6], pGicCpu->abIntrPriority[i + 7],
231	gicReDistGetIntIdFromIndex(i + 8), gicReDistGetIntIdFromIndex(i + 15),
232	pGicCpu->abIntrPriority[i + 8], pGicCpu->abIntrPriority[i + 9],
233	pGicCpu->abIntrPriority[i + 10], pGicCpu->abIntrPriority[i + 11],
234	pGicCpu->abIntrPriority[i + 12], pGicCpu->abIntrPriority[i + 13],
235	pGicCpu->abIntrPriority[i + 14], pGicCpu->abIntrPriority[i + 15]);
236	}
237
238	pHlp->pfnPrintf(pHlp, "\nVCPU[%u] ICC system register state:\n", pVCpu->idCpu);
239	pHlp->pfnPrintf(pHlp, " uIccCtlr = %#RX64\n", pGicCpu->uIccCtlr);
240	pHlp->pfnPrintf(pHlp, " fIntrGroup0Enabled = %RTbool\n", pGicCpu->fIntrGroup0Enabled);
241	pHlp->pfnPrintf(pHlp, " fIntrGroup1Enabled = %RTbool\n", pGicCpu->fIntrGroup1Enabled);
242	pHlp->pfnPrintf(pHlp, " bBinaryPtGroup0 = %#x\n", pGicCpu->bBinaryPtGroup0);
243	pHlp->pfnPrintf(pHlp, " bBinaryPtGroup1 = %#x\n", pGicCpu->bBinaryPtGroup1);
244	pHlp->pfnPrintf(pHlp, " idxRunningPriority = %#x\n", pGicCpu->idxRunningPriority);
245	pHlp->pfnPrintf(pHlp, " Running priority = %#x\n", pGicCpu->abRunningPriorities[pGicCpu->idxRunningPriority]);
246
247	/* Running interrupt priorities. */
248	{
249	uint32_t const cPriorities = RT_ELEMENTS(pGicCpu->abRunningPriorities);
250	AssertCompile(!(cPriorities % 16));
251	pHlp->pfnPrintf(pHlp, " Running-interrupt priorities:\n");
252	for (uint32_t i = 0; i < cPriorities; i += 16)
253	pHlp->pfnPrintf(pHlp, " [%3u..%-3u] = %3u %3u %3u %3u %3u %3u %3u %3u"
254	" [%3u..%-3u] = %3u %3u %3u %3u %3u %3u %3u %3u\n",
255	i, i + 7,
256	pGicCpu->abRunningPriorities[i], pGicCpu->abRunningPriorities[i + 1],
257	pGicCpu->abRunningPriorities[i + 2], pGicCpu->abRunningPriorities[i + 3],
258	pGicCpu->abRunningPriorities[i + 4], pGicCpu->abRunningPriorities[i + 5],
259	pGicCpu->abRunningPriorities[i + 6], pGicCpu->abRunningPriorities[i + 7],
260	i + 8, i + 15,
261	pGicCpu->abRunningPriorities[i + 8], pGicCpu->abRunningPriorities[i + 9],
262	pGicCpu->abRunningPriorities[i + 10], pGicCpu->abRunningPriorities[i + 11],
263	pGicCpu->abRunningPriorities[i + 12], pGicCpu->abRunningPriorities[i + 13],
264	pGicCpu->abRunningPriorities[i + 14], pGicCpu->abRunningPriorities[i + 15]);
265	}
266
267	AssertCompile(RT_ELEMENTS(pGicCpu->bmActivePriorityGroup0) >= 4);
268	pHlp->pfnPrintf(pHlp, " Active-interrupt priorities Group 0:\n");
269	pHlp->pfnPrintf(pHlp, " [0..3] = %#010x %#010x %#010x %#010x\n",
270	pGicCpu->bmActivePriorityGroup0[0], pGicCpu->bmActivePriorityGroup0[1],
271	pGicCpu->bmActivePriorityGroup0[2], pGicCpu->bmActivePriorityGroup0[3]);
272	AssertCompile(RT_ELEMENTS(pGicCpu->bmActivePriorityGroup1) >= 4);
273	pHlp->pfnPrintf(pHlp, " Active-interrupt priorities Group 1:\n");
274	pHlp->pfnPrintf(pHlp, " [0..3] = %#010x %#010x %#010x %#010x\n",
275	pGicCpu->bmActivePriorityGroup1[0], pGicCpu->bmActivePriorityGroup1[1],
276	pGicCpu->bmActivePriorityGroup1[2], pGicCpu->bmActivePriorityGroup1[3]);
277	}
278
279
280	/**
281	* Dumps the GIC ITS information.
282	*
283	* @param pVM The cross context VM structure.
284	* @param pHlp The info helpers.
285	* @param pszArgs Arguments, ignored.
286	*/
287	static DECLCALLBACK(void) gicR3DbgInfoIts(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
288	{
289	NOREF(pszArgs);
290	PGIC pGic = VM_TO_GIC(pVM);
291	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
292	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
293	if (pGicDev->hMmioGits != NIL_IOMMMIOHANDLE)
294	gitsR3DbgInfo(&pGicDev->Gits, pHlp);
295	else
296	pHlp->pfnPrintf(pHlp, "GIC ITS is not mapped/configured for the VM\n");
297	}
298
299
300	/**
301	* Dumps the GIC LPI information.
302	*
303	* @param pVM The cross context VM structure.
304	* @param pHlp The info helpers.
305	* @param pszArgs Arguments, ignored.
306	*/
307	static DECLCALLBACK(void) gicR3DbgInfoLpi(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
308	{
309	NOREF(pszArgs);
310	PGIC pGic = VM_TO_GIC(pVM);
311	PPDMDEVINS pDevIns = pGic->CTX_SUFF(pDevIns);
312	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
313	if (!pGicDev->fLpi)
314	{
315	pHlp->pfnPrintf(pHlp, "GIC LPI support is not enabled for the VM\n");
316	return;
317	}
318	pHlp->pfnPrintf(pHlp, "GIC LPIs:\n");
319	pHlp->pfnPrintf(pHlp, " Enabled = %RTbool\n", pGicDev->fEnableLpis);
320
321	/* GICR_PENDBASER. */
322	{
323	uint64_t const uReg = pGicDev->uLpiPendingBaseReg.u;
324	pHlp->pfnPrintf(pHlp, " uLpiPendingBaseReg = %#RX64\n", uReg);
325	pHlp->pfnPrintf(pHlp, " Inner cache = %#x\n", RT_BF_GET(uReg, GIC_BF_REDIST_REG_PENDBASER_INNER_CACHE));
326	pHlp->pfnPrintf(pHlp, " Shareability = %#x\n", RT_BF_GET(uReg, GIC_BF_REDIST_REG_PENDBASER_SHAREABILITY));
327	pHlp->pfnPrintf(pHlp, " Phys addr = %#RX64\n", uReg & GIC_BF_REDIST_REG_PENDBASER_PHYS_ADDR_MASK);
328	pHlp->pfnPrintf(pHlp, " Outer cache = %#x\n", RT_BF_GET(uReg, GIC_BF_REDIST_REG_PENDBASER_OUTER_CACHE));
329	pHlp->pfnPrintf(pHlp, " Pending Table Zero = %RTbool\n", RT_BF_GET(uReg, GIC_BF_REDIST_REG_PENDBASER_PTZ));
330	}
331
332	/* GICR_PROPBASER. */
333	{
334	uint64_t const uReg = pGicDev->uLpiConfigBaseReg.u;
335	uint8_t const cIdBits = RT_BF_GET(uReg, GIC_BF_REDIST_REG_PROPBASER_ID_BITS);
336	pHlp->pfnPrintf(pHlp, " uLpiConfigBaseReg = %#RX64\n", uReg);
337	pHlp->pfnPrintf(pHlp, " ID bits = %#x (%u bits)\n", cIdBits, cIdBits);
338	pHlp->pfnPrintf(pHlp, " Inner cache = %#x\n", RT_BF_GET(uReg, GIC_BF_REDIST_REG_PROPBASER_INNER_CACHE));
339	pHlp->pfnPrintf(pHlp, " Shareability = %#x\n", RT_BF_GET(uReg, GIC_BF_REDIST_REG_PROPBASER_SHAREABILITY));
340	pHlp->pfnPrintf(pHlp, " Phys addr = %#RX64\n", uReg & GIC_BF_REDIST_REG_PROPBASER_PHYS_ADDR_MASK);
341	pHlp->pfnPrintf(pHlp, " Outer cache = %#x\n", RT_BF_GET(uReg, GIC_BF_REDIST_REG_PROPBASER_OUTER_CACHE));
342	}
343
344	/* */
345	{
346
347	}
348	/** @todo Dump LPI config and LPI pending registers. */
349	}
350
351
352	/**
353	* The GIC ITS command-queue thread.
354	*
355	* @returns VBox status code.
356	* @param pDevIns The device instance.
357	* @param pThread The command thread.
358	*/
359	static DECLCALLBACK(int) gicItsR3CmdQueueThread(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
360	{
361	if (pThread->enmState == PDMTHREADSTATE_INITIALIZING)
362	return VINF_SUCCESS;
363
364	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
365	PGITSDEV pGitsDev = &pGicDev->Gits;
366	AssertPtrReturn(pGicDev, VERR_INVALID_PARAMETER);
367	LogFlowFunc(("Command-queue thread spawned and initialized\n"));
368
369	/*
370	* Pre-allocate the maximum size of the command queue allowed by the ARM GIC spec.
371	* This prevents trashing the heap as well as dealing with out-of-memory situations
372	* up-front while starting the VM. It also simplifies the code from having to
373	* dynamically grow/shrink the allocation based on how software sizes the queue.
374	* Guests normally don't alter the queue size all the time, but that's not an
375	* assumption we can make. Another benefit is that we can avoid releasing and
376	* re-acquiring the device critical section if/when guests modifies the command
377	* queue size.
378	*/
379	uint16_t const cMaxPages = GITS_BF_CTRL_REG_CBASER_SIZE_MASK + 1;
380	size_t const cbCmds = cMaxPages << GITS_CMD_QUEUE_PAGE_SHIFT;
381	void *pvCmds = RTMemAllocZ(cbCmds);
382	AssertLogRelMsgReturn(pvCmds, ("Failed to alloc %.Rhcb (%zu bytes) for the GITS command queue\n", cbCmds, cbCmds),
383	VERR_NO_MEMORY);
384
385	while (pThread->enmState == PDMTHREADSTATE_RUNNING)
386	{
387	/* Sleep until we are woken up. */
388	{
389	int const rcLock = PDMDevHlpSUPSemEventWaitNoResume(pDevIns, pGitsDev->hEvtCmdQueue, RT_INDEFINITE_WAIT);
390	AssertLogRelMsgReturnStmt(RT_SUCCESS(rcLock) \|\| rcLock == VERR_INTERRUPTED, ("%Rrc\n", rcLock),
391	RTMemFree(pvCmds), rcLock);
392	if (pThread->enmState != PDMTHREADSTATE_RUNNING)
393	break;
394	}
395
396	/* Process the command queue. */
397	int const rc = gitsR3CmdQueueProcess(pDevIns, pGitsDev, pvCmds, cbCmds);
398	if (RT_FAILURE(rc))
399	break;
400	}
401
402	RTMemFree(pvCmds);
403
404	LogFlowFunc(("Command-queue thread terminating\n"));
405	return VINF_SUCCESS;
406	}
407
408
409	/**
410	* Wakes up the command-queue thread so it can respond to a state change.
411	*
412	* @return VBox status code.
413	* @param pDevIns The device instance.
414	* @param pThread The command-queue thread.
415	*
416	* @thread EMT.
417	*/
418	static DECLCALLBACK(int) gicItsR3CmdQueueThreadWakeUp(PPDMDEVINS pDevIns, PPDMTHREAD pThread)
419	{
420	RT_NOREF(pThread);
421	LogFlowFunc(("\n"));
422	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
423	PGITSDEV pGitsDev = &pGicDev->Gits;
424	return PDMDevHlpSUPSemEventSignal(pDevIns, pGitsDev->hEvtCmdQueue);
425	}
426
427
428	/**
429	* @copydoc FNSSMDEVSAVEEXEC
430	*/
431	static DECLCALLBACK(int) gicR3SaveExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM)
432	{
433	PCVM pVM = PDMDevHlpGetVM(pDevIns);
434	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
435	PCGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PCGICDEV);
436	AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
437	LogFlowFunc(("\n"));
438
439	/*
440	* Save per-VM data.
441	*/
442	pHlp->pfnSSMPutU32(pSSM, pVM->cCpus);
443	pHlp->pfnSSMPutU8(pSSM, pGicDev->uArchRev);
444	pHlp->pfnSSMPutU8(pSSM, pGicDev->uArchRevMinor);
445	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxSpi);
446	pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtSpi);
447	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxExtSpi);
448	pHlp->pfnSSMPutBool(pSSM, pGicDev->fExtPpi);
449	pHlp->pfnSSMPutU8(pSSM, pGicDev->uMaxExtPpi);
450	pHlp->pfnSSMPutBool(pSSM, pGicDev->fRangeSel);
451	pHlp->pfnSSMPutBool(pSSM, pGicDev->fNmi);
452	pHlp->pfnSSMPutBool(pSSM, pGicDev->fMbi);
453	pHlp->pfnSSMPutBool(pSSM, pGicDev->fAff3Levels);
454	pHlp->pfnSSMPutBool(pSSM, pGicDev->fLpi);
455
456	/* Distributor state. */
457	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup0Enabled);
458	pHlp->pfnSSMPutBool(pSSM, pGicDev->fIntrGroup1Enabled);
459	pHlp->pfnSSMPutBool(pSSM, pGicDev->fAffRoutingEnabled);
460	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrGroup[0], sizeof(pGicDev->bmIntrGroup));
461	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrConfig[0], sizeof(pGicDev->bmIntrConfig));
462	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrEnabled[0], sizeof(pGicDev->bmIntrEnabled));
463	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrPending[0], sizeof(pGicDev->bmIntrPending));
464	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrActive[0], sizeof(pGicDev->bmIntrActive));
465	pHlp->pfnSSMPutMem(pSSM, &pGicDev->abIntrPriority[0], sizeof(pGicDev->abIntrPriority));
466	pHlp->pfnSSMPutMem(pSSM, &pGicDev->au32IntrRouting[0], sizeof(pGicDev->au32IntrRouting));
467	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmIntrRoutingMode[0], sizeof(pGicDev->bmIntrRoutingMode));
468
469	/* LPI state. */
470	/* We store the size followed by the data because we currently do not support the full LPI range. */
471	pHlp->pfnSSMPutU32(pSSM, sizeof(pGicDev->abLpiConfig));
472	pHlp->pfnSSMPutMem(pSSM, &pGicDev->abLpiConfig[0], sizeof(pGicDev->abLpiConfig));
473	pHlp->pfnSSMPutU32(pSSM, sizeof(pGicDev->bmLpiPending));
474	pHlp->pfnSSMPutMem(pSSM, &pGicDev->bmLpiPending[0], sizeof(pGicDev->bmLpiPending));
475	pHlp->pfnSSMPutU64(pSSM, pGicDev->uLpiConfigBaseReg.u);
476	pHlp->pfnSSMPutU64(pSSM, pGicDev->uLpiPendingBaseReg.u);
477	pHlp->pfnSSMPutBool(pSSM, pGicDev->fEnableLpis);
478
479	/** @todo GITS data. */
480
481	/*
482	* Save per-VCPU data.
483	*/
484	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
485	{
486	PCGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
487	Assert(pGicCpu);
488
489	/* Redistributor state. */
490	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrGroup[0], sizeof(pGicCpu->bmIntrGroup));
491	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrConfig[0], sizeof(pGicCpu->bmIntrConfig));
492	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrEnabled[0], sizeof(pGicCpu->bmIntrEnabled));
493	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrPending[0], sizeof(pGicCpu->bmIntrPending));
494	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmIntrActive[0], sizeof(pGicCpu->bmIntrActive));
495	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->abIntrPriority[0], sizeof(pGicCpu->abIntrPriority));
496
497	/* ICC system register state. */
498	pHlp->pfnSSMPutU64(pSSM, pGicCpu->uIccCtlr);
499	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bIntrPriorityMask);
500	pHlp->pfnSSMPutU8(pSSM, pGicCpu->idxRunningPriority);
501	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->abRunningPriorities[0], sizeof(pGicCpu->abRunningPriorities));
502	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmActivePriorityGroup0[0], sizeof(pGicCpu->bmActivePriorityGroup0));
503	pHlp->pfnSSMPutMem(pSSM, &pGicCpu->bmActivePriorityGroup1[0], sizeof(pGicCpu->bmActivePriorityGroup1));
504	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPtGroup0);
505	pHlp->pfnSSMPutU8(pSSM, pGicCpu->bBinaryPtGroup1);
506	pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup0Enabled);
507	pHlp->pfnSSMPutBool(pSSM, pGicCpu->fIntrGroup1Enabled);
508	}
509
510	return pHlp->pfnSSMPutU32(pSSM, UINT32_MAX);
511	}
512
513
514	/**
515	* @copydoc FNSSMDEVLOADEXEC
516	*/
517	static DECLCALLBACK(int) gicR3LoadExec(PPDMDEVINS pDevIns, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
518	{
519	PVM pVM = PDMDevHlpGetVM(pDevIns);
520	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
521
522	AssertPtrReturn(pVM, VERR_INVALID_VM_HANDLE);
523	AssertReturn(uPass == SSM_PASS_FINAL, VERR_WRONG_ORDER);
524	LogFlowFunc(("uVersion=%u uPass=%#x\n", uVersion, uPass));
525
526	/*
527	* Validate supported saved-state versions.
528	*/
529	if (uVersion != GIC_SAVED_STATE_VERSION)
530	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid saved-state version %u"), uVersion);
531
532	/*
533	* Load per-VM data.
534	*/
535	uint32_t cCpus;
536	pHlp->pfnSSMGetU32(pSSM, &cCpus);
537	if (cCpus != pVM->cCpus)
538	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: cCpus: got=%u expected=%u"), cCpus, pVM->cCpus);
539
540	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
541	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uArchRev);
542	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uArchRevMinor);
543	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxSpi);
544	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtSpi);
545	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxExtSpi);
546	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fExtPpi);
547	pHlp->pfnSSMGetU8(pSSM, &pGicDev->uMaxExtPpi);
548	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fRangeSel);
549	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fNmi);
550	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fMbi);
551	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAff3Levels);
552	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fLpi);
553
554	/* Distributor state. */
555	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup0Enabled);
556	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fIntrGroup1Enabled);
557	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fAffRoutingEnabled);
558	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrGroup[0], sizeof(pGicDev->bmIntrGroup));
559	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrConfig[0], sizeof(pGicDev->bmIntrConfig));
560	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrEnabled[0], sizeof(pGicDev->bmIntrEnabled));
561	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrPending[0], sizeof(pGicDev->bmIntrPending));
562	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrActive[0], sizeof(pGicDev->bmIntrActive));
563	pHlp->pfnSSMGetMem(pSSM, &pGicDev->abIntrPriority[0], sizeof(pGicDev->abIntrPriority));
564	pHlp->pfnSSMGetMem(pSSM, &pGicDev->au32IntrRouting[0], sizeof(pGicDev->au32IntrRouting));
565	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmIntrRoutingMode[0], sizeof(pGicDev->bmIntrRoutingMode));
566
567	/* LPI config. */
568	{
569	uint32_t cbData = 0;
570	int const rc = pHlp->pfnSSMGetU32(pSSM, &cbData);
571	AssertRCReturn(rc, rc);
572	if (cbData <= sizeof(pGicDev->abLpiConfig))
573	pHlp->pfnSSMGetMem(pSSM, &pGicDev->abLpiConfig[0], cbData);
574	else
575	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPI config table size: got=%u expected=%u"),
576	cbData, sizeof(pGicDev->abLpiConfig));
577	}
578	/* LPI pending. */
579	{
580	uint32_t cbData = 0;
581	int const rc = pHlp->pfnSSMGetU32(pSSM, &cbData);
582	AssertRCReturn(rc, rc);
583	if (cbData <= sizeof(pGicDev->bmLpiPending))
584	pHlp->pfnSSMGetMem(pSSM, &pGicDev->bmLpiPending[0], cbData);
585	else
586	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPI pending bitmap size: got=%u expected=%u"),
587	cbData, sizeof(pGicDev->bmLpiPending));
588	}
589	pHlp->pfnSSMGetU64(pSSM, &pGicDev->uLpiConfigBaseReg.u);
590	pHlp->pfnSSMGetU64(pSSM, &pGicDev->uLpiPendingBaseReg.u);
591	pHlp->pfnSSMGetBool(pSSM, &pGicDev->fEnableLpis);
592
593	/** @todo GITS data. */
594
595	/*
596	* Load per-VCPU data.
597	*/
598	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
599	{
600	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVM->apCpusR3[idCpu]);
601	Assert(pGicCpu);
602
603	/* Redistributor state. */
604	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrGroup[0], sizeof(pGicCpu->bmIntrGroup));
605	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrConfig[0], sizeof(pGicCpu->bmIntrConfig));
606	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrEnabled[0], sizeof(pGicCpu->bmIntrEnabled));
607	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrPending[0], sizeof(pGicCpu->bmIntrPending));
608	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmIntrActive[0], sizeof(pGicCpu->bmIntrActive));
609	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->abIntrPriority[0], sizeof(pGicCpu->abIntrPriority));
610
611	/* ICC system register state. */
612	pHlp->pfnSSMGetU64(pSSM, &pGicCpu->uIccCtlr);
613	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bIntrPriorityMask);
614	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->idxRunningPriority);
615	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->abRunningPriorities[0], sizeof(pGicCpu->abRunningPriorities));
616	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmActivePriorityGroup0[0], sizeof(pGicCpu->bmActivePriorityGroup0));
617	pHlp->pfnSSMGetMem(pSSM, &pGicCpu->bmActivePriorityGroup1[0], sizeof(pGicCpu->bmActivePriorityGroup1));
618	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPtGroup0);
619	pHlp->pfnSSMGetU8(pSSM, &pGicCpu->bBinaryPtGroup1);
620	pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup0Enabled);
621	pHlp->pfnSSMGetBool(pSSM, &pGicCpu->fIntrGroup1Enabled);
622	}
623
624	/*
625	* Check that we're still good wrt restored data.
626	*/
627	int rc = pHlp->pfnSSMHandleGetStatus(pSSM);
628	AssertRCReturn(rc, rc);
629
630	uint32_t uMarker = 0;
631	rc = pHlp->pfnSSMGetU32(pSSM, &uMarker);
632	AssertRCReturn(rc, rc);
633	if (uMarker == UINT32_MAX)
634	{ /* likely */ }
635	else
636	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: Marker: got=%u expected=%u"), uMarker, UINT32_MAX);
637
638	/*
639	* Finally, perform sanity checks.
640	*/
641	if (pGicDev->uArchRev <= GIC_DIST_REG_PIDR2_ARCHREV_GICV4)
642	{ /* likely */ }
643	else
644	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid uArchRev, got %u expected range [1,31]"), pGicDev->uArchRev,
645	GIC_DIST_REG_PIDR2_ARCHREV_GICV1, GIC_DIST_REG_PIDR2_ARCHREV_GICV4);
646	if (pGicDev->uArchRevMinor == 1)
647	{ /* likely */ }
648	else
649	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid uArchRevMinor, got %u expected 1"), pGicDev->uArchRevMinor);
650	if (pGicDev->uMaxSpi - 1 < 31)
651	{ /* likely */ }
652	else
653	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxSpi, got %u expected range [1,31]"), pGicDev->uMaxSpi);
654	if (pGicDev->uMaxExtSpi <= 31)
655	{ /* likely */ }
656	else
657	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxExtSpi, got %u expected range [0,31]"), pGicDev->uMaxExtSpi);
658	if ( pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087
659	\|\| pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
660	{ /* likely */ }
661	else
662	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Invalid MaxExtPpi, got %u expected range [1,2]"), pGicDev->uMaxExtPpi);
663	bool const fIsGitsEnabled = RT_BOOL(pGicDev->hMmioGits != NIL_IOMMMIOHANDLE);
664	if (fIsGitsEnabled == pGicDev->fLpi)
665	{ /* likely */ }
666	else
667	return pHlp->pfnSSMSetCfgError(pSSM, RT_SRC_POS, N_("Config mismatch: LPIs are %s when ITS is %s"),
668	fIsGitsEnabled ? "enabled" : "disabled", pGicDev->fLpi ? "enabled" : "disabled");
669	return rc;
670	}
671
672
673	/**
674	* @interface_method_impl{PDMDEVREG,pfnReset}
675	*/
676	DECLCALLBACK(void) gicR3Reset(PPDMDEVINS pDevIns)
677	{
678	PVM pVM = PDMDevHlpGetVM(pDevIns);
679	VM_ASSERT_EMT0(pVM);
680	VM_ASSERT_IS_NOT_RUNNING(pVM);
681
682	LogFlow(("GIC: gicR3Reset\n"));
683
684	gicReset(pDevIns);
685	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
686	{
687	PVMCPU pVCpuDest = pVM->apCpusR3[idCpu];
688	gicResetCpu(pDevIns, pVCpuDest);
689	}
690	}
691
692
693	/**
694	* @interface_method_impl{PDMDEVREG,pfnDestruct}
695	*/
696	DECLCALLBACK(int) gicR3Destruct(PPDMDEVINS pDevIns)
697	{
698	LogFlowFunc(("pDevIns=%p\n", pDevIns));
699	PDMDEV_CHECK_VERSIONS_RETURN_QUIET(pDevIns);
700
701	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
702	PGITSDEV pGitsDev = &pGicDev->Gits;
703	if (pGitsDev->hEvtCmdQueue != NIL_SUPSEMEVENT)
704	{
705	PDMDevHlpSUPSemEventClose(pDevIns, pGitsDev->hEvtCmdQueue);
706	pGitsDev->hEvtCmdQueue = NIL_SUPSEMEVENT;
707	}
708
709	return VINF_SUCCESS;
710	}
711
712
713	/**
714	* @interface_method_impl{PDMDEVREG,pfnConstruct}
715	*/
716	DECLCALLBACK(int) gicR3Construct(PPDMDEVINS pDevIns, int iInstance, PCFGMNODE pCfg)
717	{
718	PDMDEV_CHECK_VERSIONS_RETURN(pDevIns);
719	PGICDEV pGicDev = PDMDEVINS_2_DATA(pDevIns, PGICDEV);
720	PCPDMDEVHLPR3 pHlp = pDevIns->pHlpR3;
721	PVM pVM = PDMDevHlpGetVM(pDevIns);
722	PGIC pGic = VM_TO_GIC(pVM);
723	Assert(iInstance == 0);
724
725	/*
726	* Init the data.
727	*/
728	pGic->pDevInsR3 = pDevIns;
729
730	/*
731	* Validate GIC settings.
732	*/
733	PDMDEV_VALIDATE_CONFIG_RETURN(pDevIns, "DistributorMmioBase\|RedistributorMmioBase\|ItsMmioBase"
734	"\|ArchRev"
735	"\|ArchRevMinor"
736	"\|MaxSpi"
737	"\|ExtSpi"
738	"\|MaxExtSpi"
739	"\|ExtPpi"
740	"\|MaxExtPpi"
741	"\|RangeSel"
742	"\|Nmi"
743	"\|Mbi"
744	"\|Aff3Levels"
745	"\|Lpi"
746	"\|MaxLpi", "");
747
748	#if 0
749	/*
750	* Disable automatic PDM locking for this device.
751	*/
752	int rc = PDMDevHlpSetDeviceCritSect(pDevIns, PDMDevHlpCritSectGetNop(pDevIns));
753	AssertRCReturn(rc, rc);
754	#endif
755
756	/** @devcfgm{gic, ArchRev, uint8_t, 3}
757	* Configures the GIC architecture revision (GICD_PIDR2.ArchRev, GICR_PIDR2.ArchRev
758	* and GITS_PIDR2.ArchRev).
759	*
760	* Currently we only support GICv3 and the architecture revision reported is the
761	* same for both the GIC and the ITS. */
762	int rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRev", &pGicDev->uArchRev, 3);
763	AssertLogRelRCReturn(rc, rc);
764	if (pGicDev->uArchRev == GIC_DIST_REG_PIDR2_ARCHREV_GICV3)
765	{
766	AssertCompile(GIC_DIST_REG_PIDR2_ARCHREV_GICV3 == GITS_CTRL_REG_PIDR2_ARCHREV_GICV3);
767	pGicDev->Gits.uArchRev = pGicDev->uArchRev;
768	}
769	else
770	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
771	N_("Configuration error: \"ArchRev\" must be %u, other revisions not supported"),
772	GIC_DIST_REG_PIDR2_ARCHREV_GICV3);
773
774	/** @devcfgm{gic, ArchRevMinor, uint8_t, 1}
775	* Configures the GIC architecture revision minor version.
776	*
777	* Currently we support GICv3.1 only. GICv3.1's only addition to GICv3 is supported
778	* for extended INTID ranges which we currently always support. */
779	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "ArchRevMinor", &pGicDev->uArchRevMinor, 1);
780	AssertLogRelRCReturn(rc, rc);
781	if (pGicDev->uArchRevMinor == 1)
782	{ /* likely */ }
783	else
784	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
785	N_("Configuration error: \"ArchRevMinor\" must be 1, other minor revisions not supported"));
786
787	/** @devcfgm{gic, MaxSpi, uint8_t, 31}
788	* Configures GICD_TYPER.ItLinesNumber.
789	*
790	* For the IntId range [32,1023], configures the maximum SPI supported. Valid values
791	* are [1,31] which equates to interrupt IDs [63,1023]. A value of 0 implies SPIs
792	* are not supported. We don't allow configuring this value as it's expected that
793	* most guests would assume support for SPIs. */
794	AssertCompile(GIC_DIST_REG_TYPER_NUM_ITLINES == 31);
795	/** @todo This currently isn't implemented and the full range is always
796	* reported to the guest. */
797	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxSpi", &pGicDev->uMaxSpi, 31 /* Upto and incl. IntId 1023 */);
798	AssertLogRelRCReturn(rc, rc);
799	if (pGicDev->uMaxSpi - 1 < 31)
800	{ /* likely */ }
801	else
802	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
803	N_("Configuration error: \"MaxSpi\" must be in the range [1,%u]"),
804	GIC_DIST_REG_TYPER_NUM_ITLINES);
805
806	/** @devcfgm{gic, ExtSpi, bool, false}
807	* Configures whether extended SPIs supported is enabled (GICD_TYPER.ESPI). */
808	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtSpi", &pGicDev->fExtSpi, true);
809	AssertLogRelRCReturn(rc, rc);
810
811	/** @devcfgm{gic, MaxExtSpi, uint8_t, 31}
812	* Configures GICD_TYPER.ESPI_range.
813	*
814	* For the extended SPI range [4096,5119], configures the maximum extended SPI
815	* supported. Valid values are [0,31] which equates to extended SPI IntIds
816	* [4127,5119]. This is ignored (set to 0 in the register) when extended SPIs are
817	* disabled. */
818	AssertCompile(GIC_DIST_REG_TYPER_ESPI_RANGE >> GIC_DIST_REG_TYPER_ESPI_RANGE_BIT == 31);
819	/** @todo This currently isn't implemented and the full range is always
820	* reported to the guest. */
821	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxExtSpi", &pGicDev->uMaxExtSpi, 31);
822	AssertLogRelRCReturn(rc, rc);
823	if (pGicDev->uMaxExtSpi <= 31)
824	{ /* likely */ }
825	else
826	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
827	N_("Configuration error: \"MaxExtSpi\" must be in the range [0,31]"));
828
829	/** @devcfgm{gic, ExtPpi, bool, true}
830	* Configures whether extended PPIs support is enabled. */
831	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "ExtPpi", &pGicDev->fExtPpi, true);
832	AssertLogRelRCReturn(rc, rc);
833
834	/** @devcfgm{gic, MaxExtPpi, uint8_t, 2}
835	* Configures GICR_TYPER.PPInum.
836	*
837	* For the extended PPI range [1056,5119], configures the maximum extended PPI
838	* supported. Valid values are [1,2] which equates to extended PPI IntIds
839	* [1087,1119]. This is unused when extended PPIs are disabled. */
840	/** @todo This currently isn't implemented and the full range is always
841	* reported to the guest. */
842	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxExtPpi", &pGicDev->uMaxExtPpi, 2);
843	AssertLogRelRCReturn(rc, rc);
844	if ( pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087
845	\|\| pGicDev->uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1119)
846	{ /* likely */ }
847	else
848	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
849	N_("Configuration error: \"MaxExtPpi\" must be in the range [0,2]"));
850
851	/** @devcfgm{gic, RangeSel, bool, true}
852	* Configures whether range-selector support is enabled (GICD_TYPER.RSS and
853	* ICC_CTLR_EL1.RSS). */
854	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "RangeSel", &pGicDev->fRangeSel, true);
855	AssertLogRelRCReturn(rc, rc);
856
857	/** @devcfgm{gic, Nmi, bool, false}
858	* Configures whether non-maskable interrupts (NMIs) are supported
859	* (GICD_TYPER.NMI). */
860	/** @todo NMIs are currently not implemented. */
861	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Nmi", &pGicDev->fNmi, false);
862	AssertLogRelRCReturn(rc, rc);
863
864	/** @devcfgm{gic, Mbi, bool, false}
865	* Configures whether message-based interrupts (MBIs) are supported
866	* (GICD_TYPER.MBIS).
867	*
868	* Guests typically can't use MBIs without an ITS. */
869	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Mbi", &pGicDev->fMbi, false);
870	AssertLogRelRCReturn(rc, rc);
871
872	/** @devcfgm{gic, Aff3Levels, bool, true}
873	* Configures whether non-zero affinity 3 levels (A3V) are supported
874	* (GICD_TYPER.A3V and ICC_CTLR.A3V). */
875	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Aff3Levels", &pGicDev->fAff3Levels, true);
876	AssertLogRelRCReturn(rc, rc);
877
878	/** @devcfgm{gic, Lpi, bool, false}
879	* Configures whether physical LPIs are supported (GICD_TYPER.LPIS and
880	* GICR_TYPER.PLPIS).
881	*
882	* This currently requires an ITS as we do not support direction injection of
883	* LPIs as most guests do not use them anyway. */
884	rc = pHlp->pfnCFGMQueryBoolDef(pCfg, "Lpi", &pGicDev->fLpi, false);
885	AssertLogRelRCReturn(rc, rc);
886
887	/** @devcfgm{gic, MaxLpi, uint8_t, 14}
888	* Configures GICD_TYPER.num_LPIs.
889	*
890	* For the physical LPI range [8192,65535], configures the number of physical LPI
891	* supported. Valid values are [3,14] which equates to LPI IntIds 8192 to
892	* [8207,40959]. A value of 15 or higher would exceed the maximum INTID size of
893	* 16-bits since 8192 + 2^(NumLpi+1) is >= 73727. A value of 2 or lower support
894	* fewer than 15 LPIs which seem pointless and is hence disallowed. This value is
895	* ignored (set to 0 in the register) when LPIs are disabled. */
896	rc = pHlp->pfnCFGMQueryU8Def(pCfg, "MaxLpi", &pGicDev->uMaxLpi, 10);
897	AssertLogRelRCReturn(rc, rc);
898
899	/* We currently support 2048 LPIs until we need to support more. */
900	if (pGicDev->uMaxLpi == 10)
901	{ /* likely */ }
902	else
903	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
904	N_("Configuration error: \"MaxLpi\" must be in the range [3,14]"));
905	AssertRelease(UINT32_C(2) << pGicDev->uMaxLpi <= RT_ELEMENTS(pGicDev->abLpiConfig));
906
907	/*
908	* Register the GIC with PDM.
909	*/
910	rc = PDMDevHlpIcRegister(pDevIns);
911	AssertLogRelRCReturn(rc, rc);
912
913	rc = PDMGicRegisterBackend(pVM, PDMGICBACKENDTYPE_VBOX, &g_GicBackend);
914	AssertLogRelRCReturn(rc, rc);
915
916	/*
917	* Insert the GIC system registers.
918	*/
919	for (uint32_t i = 0; i < RT_ELEMENTS(g_aSysRegRanges_GIC); i++)
920	{
921	rc = CPUMR3SysRegRangesInsert(pVM, &g_aSysRegRanges_GIC[i]);
922	AssertLogRelRCReturn(rc, rc);
923	}
924
925	/*
926	* Register the MMIO ranges.
927	*/
928	/* Distributor. */
929	{
930	RTGCPHYS GCPhysMmioBase = 0;
931	rc = pHlp->pfnCFGMQueryU64(pCfg, "DistributorMmioBase", &GCPhysMmioBase);
932	if (RT_FAILURE(rc))
933	return PDMDEV_SET_ERROR(pDevIns, rc,
934	N_("Configuration error: Failed to get the \"DistributorMmioBase\" value"));
935
936	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, GIC_DIST_REG_FRAME_SIZE, gicDistMmioWrite, gicDistMmioRead,
937	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC Distributor",
938	&pGicDev->hMmioDist);
939	AssertRCReturn(rc, rc);
940	}
941
942	/* Redistributor. */
943	{
944	RTGCPHYS GCPhysMmioBase = 0;
945	rc = pHlp->pfnCFGMQueryU64(pCfg, "RedistributorMmioBase", &GCPhysMmioBase);
946	if (RT_FAILURE(rc))
947	return PDMDEV_SET_ERROR(pDevIns, rc,
948	N_("Configuration error: Failed to get the \"RedistributorMmioBase\" value"));
949
950	RTGCPHYS const cbRegion = (RTGCPHYS)pVM->cCpus
951	* (GIC_REDIST_REG_FRAME_SIZE + GIC_REDIST_SGI_PPI_REG_FRAME_SIZE); /* Adjacent and per vCPU. */
952	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicReDistMmioWrite, gicReDistMmioRead,
953	IOMMMIO_FLAGS_READ_DWORD \| IOMMMIO_FLAGS_WRITE_DWORD_ZEROED, "GIC Redistributor",
954	&pGicDev->hMmioReDist);
955	AssertRCReturn(rc, rc);
956	}
957
958	/* ITS. */
959	{
960	RTGCPHYS GCPhysMmioBase = 0;
961	rc = pHlp->pfnCFGMQueryU64(pCfg, "ItsMmioBase", &GCPhysMmioBase);
962	if (RT_SUCCESS(rc))
963	{
964	Assert(pGicDev->hMmioGits != NIL_IOMMMIOHANDLE); /* paranoia */
965	RTGCPHYS const cbRegion = 2 * GITS_REG_FRAME_SIZE; /* 2 frames for GICv3. */
966	rc = PDMDevHlpMmioCreateAndMap(pDevIns, GCPhysMmioBase, cbRegion, gicItsMmioWrite, gicItsMmioRead,
967	IOMMMIO_FLAGS_READ_DWORD_QWORD
968	\| IOMMMIO_FLAGS_WRITE_DWORD_QWORD_ZEROED
969	\| IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_READ
970	\| IOMMMIO_FLAGS_DBGSTOP_ON_COMPLICATED_WRITE,
971	"GIC ITS", &pGicDev->hMmioGits);
972	AssertLogRelRCReturn(rc, rc);
973
974	/* When the ITS is enabled we must support LPIs. */
975	if (!pGicDev->fLpi)
976	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
977	N_("Configuration error: \"Lpi\" must be enabled when ITS is enabled\n"));
978
979	/* Create ITS command-queue thread and semaphore. */
980	PGITSDEV pGitsDev = &pGicDev->Gits;
981	char szCmdQueueThread[32];
982	RT_ZERO(szCmdQueueThread);
983	RTStrPrintf(szCmdQueueThread, sizeof(szCmdQueueThread), "Gits-CmdQ-%u", iInstance);
984	rc = PDMDevHlpThreadCreate(pDevIns, &pGitsDev->pCmdQueueThread, &pGicDev, gicItsR3CmdQueueThread,
985	gicItsR3CmdQueueThreadWakeUp, 0 /* cbStack */, RTTHREADTYPE_IO, szCmdQueueThread);
986	AssertLogRelRCReturn(rc, rc);
987
988	rc = PDMDevHlpSUPSemEventCreate(pDevIns, &pGitsDev->hEvtCmdQueue);
989	AssertLogRelRCReturn(rc, rc);
990	}
991	else
992	{
993	pGicDev->hMmioGits = NIL_IOMMMIOHANDLE;
994
995	/* When the ITS is disabled we don't support LPIs as we do not support direct LPI injection (guests don't use it). */
996	if (pGicDev->fLpi)
997	return PDMDevHlpVMSetError(pDevIns, VERR_INVALID_PARAMETER, RT_SRC_POS,
998	N_("Configuration error: \"Lpi\" must be disabled when ITS is disabled\n"));
999	}
1000	}
1001
1002	/*
1003	* Register saved state callbacks.
1004	*/
1005	rc = PDMDevHlpSSMRegister(pDevIns, GIC_SAVED_STATE_VERSION, 0, gicR3SaveExec, gicR3LoadExec);
1006	AssertRCReturn(rc, rc);
1007
1008	/*
1009	* Register debugger info callbacks.
1010	*
1011	* We use separate callbacks rather than arguments so they can also be
1012	* dumped in an automated fashion while collecting crash diagnostics and
1013	* not just used during live debugging via the VM debugger.
1014	*/
1015	DBGFR3InfoRegisterInternalEx(pVM, "gic", "Dumps GIC basic information.", gicR3DbgInfo, DBGFINFO_FLAGS_ALL_EMTS);
1016	DBGFR3InfoRegisterInternalEx(pVM, "gicdist", "Dumps GIC distributor information.", gicR3DbgInfoDist, DBGFINFO_FLAGS_ALL_EMTS);
1017	DBGFR3InfoRegisterInternalEx(pVM, "gicredist", "Dumps GIC redistributor information.", gicR3DbgInfoReDist, DBGFINFO_FLAGS_ALL_EMTS);
1018	DBGFR3InfoRegisterInternalEx(pVM, "gicits", "Dumps GIC ITS information.", gicR3DbgInfoIts, DBGFINFO_FLAGS_ALL_EMTS);
1019	DBGFR3InfoRegisterInternalEx(pVM, "giclpi", "Dumps GIC LPI information.", gicR3DbgInfoLpi, DBGFINFO_FLAGS_ALL_EMTS);
1020
1021	/*
1022	* Statistics.
1023	*/
1024	#ifdef VBOX_WITH_STATISTICS
1025	# define GICCPU_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
1026	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, \
1027	a_pszDesc, a_pszNameFmt, idCpu)
1028	# define GICCPU_PROF_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
1029	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_PROFILE, STAMVISIBILITY_ALWAYS, STAMUNIT_TICKS_PER_CALL, \
1030	a_pszDesc, a_pszNameFmt, idCpu)
1031	# define GIC_REG_COUNTER(a_pvReg, a_pszNameFmt, a_pszDesc) \
1032	PDMDevHlpSTAMRegisterF(pDevIns, a_pvReg, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, \
1033	a_pszDesc, a_pszNameFmt)
1034
1035	/* Redistributor. */
1036	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1037	{
1038	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1039	PGICCPU pGicCpu = VMCPU_TO_GICCPU(pVCpu);
1040
1041	GICCPU_REG_COUNTER(&pGicCpu->StatMmioRead, "%u/MmioRead", "Number of MMIO reads.");
1042	GICCPU_REG_COUNTER(&pGicCpu->StatMmioWrite, "%u/MmioWrite", "Number of MMIO writes.");
1043	GICCPU_REG_COUNTER(&pGicCpu->StatSysRegRead, "%u/SysRegRead", "Number of system register reads.");
1044	GICCPU_REG_COUNTER(&pGicCpu->StatSysRegWrite, "%u/SysRegWrite", "Number of system register writes.");
1045	GICCPU_REG_COUNTER(&pGicCpu->StatSetSpi, "%u/SetSpi", "Number of set SPI callbacks.");
1046	GICCPU_REG_COUNTER(&pGicCpu->StatSetPpi, "%u/SetPpi", "Number of set PPI callbacks.");
1047	GICCPU_REG_COUNTER(&pGicCpu->StatSetSgi, "%u/SetSgi", "Number of SGIs generated.");
1048
1049	GICCPU_PROF_COUNTER(&pGicCpu->StatProfIntrAck, "%u/Prof/IntrAck", "Profiling of interrupt acknowledge (IAR).");
1050	GICCPU_PROF_COUNTER(&pGicCpu->StatProfSetSpi, "%u/Prof/SetSpi", "Profiling of set SPI callback.");
1051	GICCPU_PROF_COUNTER(&pGicCpu->StatProfSetPpi, "%u/Prof/SetPpi", "Profiling of set PPI callback.");
1052	GICCPU_PROF_COUNTER(&pGicCpu->StatProfSetSgi, "%u/Prof/SetSgi", "Profiling of SGIs generated.");
1053	}
1054
1055	/* ITS. */
1056	PGITSDEV pGitsDev = &pGicDev->Gits;
1057	GIC_REG_COUNTER(&pGitsDev->StatCmdMapc, "ITS/Commands/MAPC", "Number of MAPC commands executed.");
1058	GIC_REG_COUNTER(&pGitsDev->StatCmdSync, "ITS/Commands/SYNC", "Number of SYNC commands executed.");
1059	GIC_REG_COUNTER(&pGitsDev->StatCmdInvall, "ITS/Commands/INVALL", "Number of INVALL commands executed.");
1060
1061	# undef GICCPU_REG_COUNTER
1062	# undef GICCPU_PROF_COUNTER
1063	# undef GIC_REG_COUNTER
1064	#endif /* VBOX_WITH_STATISTICS */
1065
1066	gicR3Reset(pDevIns);
1067
1068	/*
1069	* Log some of the features exposed to software.
1070	*/
1071	uint8_t const uArchRev = pGicDev->uArchRev;
1072	uint8_t const uArchRevMinor = pGicDev->uArchRevMinor;
1073	uint8_t const uMaxSpi = pGicDev->uMaxSpi;
1074	bool const fExtSpi = pGicDev->fExtSpi;
1075	uint8_t const uMaxExtSpi = pGicDev->uMaxExtSpi;
1076	bool const fExtPpi = pGicDev->fExtPpi;
1077	uint8_t const uMaxExtPpi = pGicDev->uMaxExtPpi;
1078	bool const fRangeSel = pGicDev->fRangeSel;
1079	bool const fNmi = pGicDev->fNmi;
1080	bool const fMbi = pGicDev->fMbi;
1081	bool const fAff3Levels = pGicDev->fAff3Levels;
1082	bool const fLpi = pGicDev->fLpi;
1083	uint32_t const uMaxLpi = pGicDev->uMaxLpi;
1084	uint16_t const uExtPpiLast = uMaxExtPpi == GIC_REDIST_REG_TYPER_PPI_NUM_MAX_1087 ? 1087 : GIC_INTID_RANGE_EXT_PPI_LAST;
1085	LogRel(("GIC: ArchRev=%u.%u RangeSel=%RTbool Nmi=%RTbool Mbi=%RTbool Aff3Levels=%RTbool\n",
1086	uArchRev, uArchRevMinor, fRangeSel, fNmi, fMbi, fAff3Levels));
1087	LogRel(("GIC: SPIs=true (%u:32..%u) ExtSPIs=%RTbool (%u:4095..%u) ExtPPIs=%RTbool (%u:1056..%u)\n",
1088	uMaxSpi, 32 * (uMaxSpi + 1),
1089	fExtSpi, uMaxExtSpi, GIC_INTID_RANGE_EXT_SPI_START - 1 + 32 * (uMaxExtSpi + 1),
1090	fExtPpi, uMaxExtPpi, uExtPpiLast));
1091	LogRel(("GIC: ITS=%s LPIs=%RTbool (%u:%u..%u)\n",
1092	pGicDev->hMmioGits != NIL_IOMMMIOHANDLE ? "enabled" : "disabled", fLpi,
1093	uMaxLpi, GIC_INTID_RANGE_LPI_START, GIC_INTID_RANGE_LPI_START - 1 + (UINT32_C(2) << uMaxLpi)));
1094	return VINF_SUCCESS;
1095	}
1096
1097	#endif /* !VBOX_DEVICE_STRUCT_TESTCASE */
1098

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source: vbox/trunk/src/VBox/VMM/VMMR3/GICR3.cpp@ 108946

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