VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 60682

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1/* $Id: HM.cpp 60406 2016-04-10 02:05:03Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2015 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assited virtualization manager was origianlly abriviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shorted to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35/*********************************************************************************************************************************
36* Header Files *
37*********************************************************************************************************************************/
38#define LOG_GROUP LOG_GROUP_HM
39#include <VBox/vmm/cpum.h>
40#include <VBox/vmm/stam.h>
41#include <VBox/vmm/mm.h>
42#include <VBox/vmm/pdmapi.h>
43#include <VBox/vmm/pgm.h>
44#include <VBox/vmm/ssm.h>
45#include <VBox/vmm/trpm.h>
46#include <VBox/vmm/dbgf.h>
47#include <VBox/vmm/iom.h>
48#include <VBox/vmm/patm.h>
49#include <VBox/vmm/csam.h>
50#include <VBox/vmm/selm.h>
51#ifdef VBOX_WITH_REM
52# include <VBox/vmm/rem.h>
53#endif
54#include <VBox/vmm/hm_vmx.h>
55#include <VBox/vmm/hm_svm.h>
56#include "HMInternal.h"
57#include <VBox/vmm/vm.h>
58#include <VBox/vmm/uvm.h>
59#include <VBox/err.h>
60#include <VBox/param.h>
61
62#include <iprt/assert.h>
63#include <VBox/log.h>
64#include <iprt/asm.h>
65#include <iprt/asm-amd64-x86.h>
66#include <iprt/env.h>
67#include <iprt/thread.h>
68
69
70/*********************************************************************************************************************************
71* Global Variables *
72*********************************************************************************************************************************/
73#ifdef VBOX_WITH_STATISTICS
74# define EXIT_REASON(def, val, str) #def " - " #val " - " str
75# define EXIT_REASON_NIL() NULL
76/** Exit reason descriptions for VT-x, used to describe statistics. */
77static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
78{
79 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
80 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
81 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
82 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
83 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
84 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
85 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
86 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
87 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
88 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
89 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
90 EXIT_REASON_NIL(),
91 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
92 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
93 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
94 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
95 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
96 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
97 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
98 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
99 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
100 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
101 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
102 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
103 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
104 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
105 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
106 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
107 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
108 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
109 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
110 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
111 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
112 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
113 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
114 EXIT_REASON_NIL(),
115 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
116 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
117 EXIT_REASON_NIL(),
118 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
119 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
120 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
121 EXIT_REASON_NIL(),
122 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold (MOV to CR8)."),
123 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
124 EXIT_REASON_NIL(),
125 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR using LGDT, LIDT, SGDT, or SIDT."),
126 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR using LLDT, LTR, SLDT, or STR."),
127 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
128 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
129 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
130 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
131 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
132 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
133 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
134 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
135 EXIT_REASON_NIL(),
136 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
137 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
138 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
139 EXIT_REASON_NIL(),
140 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
141 EXIT_REASON_NIL(),
142 EXIT_REASON(VMX_EXIT_XSAVES , 61, "XSAVES instruction."),
143 EXIT_REASON(VMX_EXIT_XRSTORS , 62, "XRSTORS instruction.")
144};
145/** Exit reason descriptions for AMD-V, used to describe statistics. */
146static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
147{
148 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
149 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
150 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
151 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
152 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
153 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
154 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
155 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
156 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
157 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
158 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
159 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
160 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
161 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
162 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
163 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
164 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
165 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
166 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
167 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
168 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
169 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
170 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
171 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
172 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
173 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
174 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
180 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
181 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
182 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
183 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
184 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
185 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
186 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
187 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
188 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
189 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
190 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
191 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
192 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
193 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
194 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
195 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
196 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
197 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
198 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
199 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
200 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
201 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
202 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
203 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
204 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
205 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
206 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
233 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
234 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
235 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
236 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
237 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
238 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
239 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
240 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
241 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
242 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
243 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
244 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
245 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
246 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
247 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
248 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
249 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
250 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
251 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
252 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
253 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
254 EXIT_REASON(SVM_EXIT_IDTR_WRITE ,106, "Write IDTR."),
255 EXIT_REASON(SVM_EXIT_GDTR_WRITE ,107, "Write GDTR."),
256 EXIT_REASON(SVM_EXIT_LDTR_WRITE ,108, "Write LDTR."),
257 EXIT_REASON(SVM_EXIT_TR_WRITE ,109, "Write TR."),
258 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
259 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
260 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
261 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
262 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
263 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
264 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
265 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
266 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
267 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
268 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
269 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
270 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
271 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
272 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
273 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
274 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
275 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
276 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
277 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
278 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
279 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
280 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
281 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
282 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
283 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
284 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
285 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
286 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
287 EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
288 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
289 EXIT_REASON(SVM_EXIT_XSETBV ,141, "XSETBV instruction."),
290 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
291 EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI,1025, "AVIC incomplete IPI delivery."),
292 EXIT_REASON(SVM_EXIT_AVIC_NOACCEL ,1026, "AVIC unaccelerated register."),
293 EXIT_REASON_NIL()
294};
295# undef EXIT_REASON
296# undef EXIT_REASON_NIL
297#endif /* VBOX_WITH_STATISTICS */
298
299#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
300 do { \
301 if ((allowed1) & (featflag)) \
302 { \
303 if ((disallowed0) & (featflag)) \
304 LogRel(("HM: " #featflag " (must be set)\n")); \
305 else \
306 LogRel(("HM: " #featflag "\n")); \
307 } \
308 else \
309 LogRel(("HM: " #featflag " (must be cleared)\n")); \
310 } while (0)
311
312#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, featflag) \
313 do { \
314 if ((allowed1) & (featflag)) \
315 LogRel(("HM: " #featflag "\n")); \
316 else \
317 LogRel(("HM: " #featflag " not supported\n")); \
318 } while (0)
319
320#define HMVMX_REPORT_CAPABILITY(msrcaps, cap) \
321 do { \
322 if ((msrcaps) & (cap)) \
323 LogRel(("HM: " #cap "\n")); \
324 } while (0)
325
326
327/*********************************************************************************************************************************
328* Internal Functions *
329*********************************************************************************************************************************/
330static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
331static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
332static int hmR3InitCPU(PVM pVM);
333static int hmR3InitFinalizeR0(PVM pVM);
334static int hmR3InitFinalizeR0Intel(PVM pVM);
335static int hmR3InitFinalizeR0Amd(PVM pVM);
336static int hmR3TermCPU(PVM pVM);
337
338
339
340/**
341 * Initializes the HM.
342 *
343 * This reads the config and check whether VT-x or AMD-V hardware is available
344 * if configured to use it. This is one of the very first components to be
345 * initialized after CFGM, so that we can fall back to raw-mode early in the
346 * initialization process.
347 *
348 * Note that a lot of the set up work is done in ring-0 and thus postponed till
349 * the ring-3 and ring-0 callback to HMR3InitCompleted.
350 *
351 * @returns VBox status code.
352 * @param pVM The cross context VM structure.
353 *
354 * @remarks Be careful with what we call here, since most of the VMM components
355 * are uninitialized.
356 */
357VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
358{
359 LogFlow(("HMR3Init\n"));
360
361 /*
362 * Assert alignment and sizes.
363 */
364 AssertCompileMemberAlignment(VM, hm.s, 32);
365 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
366
367 /*
368 * Register the saved state data unit.
369 */
370 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
371 NULL, NULL, NULL,
372 NULL, hmR3Save, NULL,
373 NULL, hmR3Load, NULL);
374 if (RT_FAILURE(rc))
375 return rc;
376
377 /*
378 * Read configuration.
379 */
380 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
381
382 /*
383 * Validate the HM settings.
384 */
385 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
386 "HMForced"
387 "|EnableNestedPaging"
388 "|EnableUX"
389 "|EnableLargePages"
390 "|EnableVPID"
391 "|TPRPatchingEnabled"
392 "|64bitEnabled"
393 "|VmxPleGap"
394 "|VmxPleWindow"
395 "|SvmPauseFilter"
396 "|SvmPauseFilterThreshold"
397 "|Exclusive"
398 "|MaxResumeLoops"
399 "|UseVmxPreemptTimer",
400 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
401 if (RT_FAILURE(rc))
402 return rc;
403
404 /** @cfgm{/HM/HMForced, bool, false}
405 * Forces hardware virtualization, no falling back on raw-mode. HM must be
406 * enabled, i.e. /HMEnabled must be true. */
407 bool fHMForced;
408#ifdef VBOX_WITH_RAW_MODE
409 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
410 AssertRCReturn(rc, rc);
411 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
412 VERR_INVALID_PARAMETER);
413# if defined(RT_OS_DARWIN)
414 if (pVM->fHMEnabled)
415 fHMForced = true;
416# endif
417 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
418 VERR_INVALID_PARAMETER);
419 if (pVM->cCpus > 1)
420 fHMForced = true;
421#else /* !VBOX_WITH_RAW_MODE */
422 AssertRelease(pVM->fHMEnabled);
423 fHMForced = true;
424#endif /* !VBOX_WITH_RAW_MODE */
425
426 /** @cfgm{/HM/EnableNestedPaging, bool, false}
427 * Enables nested paging (aka extended page tables). */
428 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
429 AssertRCReturn(rc, rc);
430
431 /** @cfgm{/HM/EnableUX, bool, true}
432 * Enables the VT-x unrestricted execution feature. */
433 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
434 AssertRCReturn(rc, rc);
435
436 /** @cfgm{/HM/EnableLargePages, bool, false}
437 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
438 * page table walking and maybe better TLB hit rate in some cases. */
439 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
440 AssertRCReturn(rc, rc);
441
442 /** @cfgm{/HM/EnableVPID, bool, false}
443 * Enables the VT-x VPID feature. */
444 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
445 AssertRCReturn(rc, rc);
446
447 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
448 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
449 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
450 AssertRCReturn(rc, rc);
451
452 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
453 * Enables AMD64 cpu features.
454 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
455 * already have the support. */
456#ifdef VBOX_ENABLE_64_BITS_GUESTS
457 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
458 AssertLogRelRCReturn(rc, rc);
459#else
460 pVM->hm.s.fAllow64BitGuests = false;
461#endif
462
463 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
464 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
465 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
466 * latest PAUSE instruction to be start of a new PAUSE loop.
467 */
468 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
469 AssertRCReturn(rc, rc);
470
471 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
472 * The pause-filter exiting window in TSC ticks. When the number of ticks
473 * between the current PAUSE instruction and first PAUSE of a loop exceeds
474 * VmxPleWindow, a VM-exit is triggered.
475 *
476 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
477 */
478 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
479 AssertRCReturn(rc, rc);
480
481 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
482 * A counter that is decrement each time a PAUSE instruction is executed by the
483 * guest. When the counter is 0, a \#VMEXIT is triggered.
484 */
485 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
486 AssertRCReturn(rc, rc);
487
488 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
489 * The pause filter threshold in ticks. When the elapsed time between two
490 * successive PAUSE instructions exceeds SvmPauseFilterThreshold, the PauseFilter
491 * count is reset to its initial value. However, if PAUSE is executed PauseFilter
492 * times within PauseFilterThreshold ticks, a VM-exit will be triggered.
493 *
494 * Setting both SvmPauseFilterCount and SvmPauseFilterCount to 0 disables
495 * pause-filter exiting.
496 */
497 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
498 AssertRCReturn(rc, rc);
499
500 /** @cfgm{/HM/Exclusive, bool}
501 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
502 * global init for each host CPU. If false, we do local init each time we wish
503 * to execute guest code.
504 *
505 * On Windows, default is false due to the higher risk of conflicts with other
506 * hypervisors.
507 *
508 * On Mac OS X, this setting is ignored since the code does not handle local
509 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
510 */
511#if defined(RT_OS_DARWIN)
512 pVM->hm.s.fGlobalInit = true;
513#else
514 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
515# if defined(RT_OS_WINDOWS)
516 false
517# else
518 true
519# endif
520 );
521 AssertLogRelRCReturn(rc, rc);
522#endif
523
524 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
525 * The number of times to resume guest execution before we forcibly return to
526 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
527 * determines the default value. */
528 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
529 AssertLogRelRCReturn(rc, rc);
530
531 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
532 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
533 * available. */
534 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
535 AssertLogRelRCReturn(rc, rc);
536
537 /*
538 * Check if VT-x or AMD-v support according to the users wishes.
539 */
540 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
541 * VERR_SVM_IN_USE. */
542 if (pVM->fHMEnabled)
543 {
544 uint32_t fCaps;
545 rc = SUPR3QueryVTCaps(&fCaps);
546 if (RT_SUCCESS(rc))
547 {
548 if (fCaps & SUPVTCAPS_AMD_V)
549 {
550 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
551 pVM->hm.s.svm.fSupported = true;
552 }
553 else if (fCaps & SUPVTCAPS_VT_X)
554 {
555 rc = SUPR3QueryVTxSupported();
556 if (RT_SUCCESS(rc))
557 {
558 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
559 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
560 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
561 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
562 pVM->hm.s.vmx.fSupported = true;
563 }
564 else
565 {
566#ifdef RT_OS_LINUX
567 const char *pszMinReq = " Linux 2.6.13 or newer required!";
568#else
569 const char *pszMinReq = "";
570#endif
571 if (fHMForced)
572 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
573
574 /* Fall back to raw-mode. */
575 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
576 pVM->fHMEnabled = false;
577 }
578 }
579 else
580 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
581 VERR_INTERNAL_ERROR_5);
582
583 /*
584 * Do we require a little bit or raw-mode for 64-bit guest execution?
585 */
586 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
587 && pVM->fHMEnabled
588 && pVM->hm.s.fAllow64BitGuests;
589
590 /*
591 * Disable nested paging and unrestricted guest execution now if they're
592 * configured so that CPUM can make decisions based on our configuration.
593 */
594 Assert(!pVM->hm.s.fNestedPaging);
595 if (pVM->hm.s.fAllowNestedPaging)
596 {
597 if (fCaps & SUPVTCAPS_NESTED_PAGING)
598 pVM->hm.s.fNestedPaging = true;
599 else
600 pVM->hm.s.fAllowNestedPaging = false;
601 }
602
603 if (fCaps & SUPVTCAPS_VT_X)
604 {
605 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
606 if (pVM->hm.s.vmx.fAllowUnrestricted)
607 {
608 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
609 && pVM->hm.s.fNestedPaging)
610 pVM->hm.s.vmx.fUnrestrictedGuest = true;
611 else
612 pVM->hm.s.vmx.fAllowUnrestricted = false;
613 }
614 }
615 }
616 else
617 {
618 const char *pszMsg;
619 switch (rc)
620 {
621 case VERR_UNSUPPORTED_CPU:
622 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained";
623 break;
624
625 case VERR_VMX_NO_VMX:
626 pszMsg = "VT-x is not available";
627 break;
628
629 case VERR_VMX_MSR_VMX_DISABLED:
630 pszMsg = "VT-x is disabled in the BIOS";
631 break;
632
633 case VERR_VMX_MSR_ALL_VMX_DISABLED:
634 pszMsg = "VT-x is disabled in the BIOS for all CPU modes";
635 break;
636
637 case VERR_VMX_MSR_LOCKING_FAILED:
638 pszMsg = "Failed to enable and lock VT-x features";
639 break;
640
641 case VERR_SVM_NO_SVM:
642 pszMsg = "AMD-V is not available";
643 break;
644
645 case VERR_SVM_DISABLED:
646 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)";
647 break;
648
649 default:
650 pszMsg = NULL;
651 break;
652 }
653 if (fHMForced && pszMsg)
654 return VM_SET_ERROR(pVM, rc, pszMsg);
655 if (!pszMsg)
656 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
657
658 /* Fall back to raw-mode. */
659 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
660 pVM->fHMEnabled = false;
661 }
662 }
663
664 /* It's now OK to use the predicate function. */
665 pVM->fHMEnabledFixed = true;
666 return VINF_SUCCESS;
667}
668
669
670/**
671 * Initializes the per-VCPU HM.
672 *
673 * @returns VBox status code.
674 * @param pVM The cross context VM structure.
675 */
676static int hmR3InitCPU(PVM pVM)
677{
678 LogFlow(("HMR3InitCPU\n"));
679
680 if (!HMIsEnabled(pVM))
681 return VINF_SUCCESS;
682
683 for (VMCPUID i = 0; i < pVM->cCpus; i++)
684 {
685 PVMCPU pVCpu = &pVM->aCpus[i];
686 pVCpu->hm.s.fActive = false;
687 }
688
689#ifdef VBOX_WITH_STATISTICS
690 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
691 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
692 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
693 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
694 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
695#endif
696
697 /*
698 * Statistics.
699 */
700 for (VMCPUID i = 0; i < pVM->cCpus; i++)
701 {
702 PVMCPU pVCpu = &pVM->aCpus[i];
703 int rc;
704
705#ifdef VBOX_WITH_STATISTICS
706 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
707 "Profiling of RTMpPokeCpu",
708 "/PROF/CPU%d/HM/Poke", i);
709 AssertRC(rc);
710 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
711 "Profiling of poke wait",
712 "/PROF/CPU%d/HM/PokeWait", i);
713 AssertRC(rc);
714 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
715 "Profiling of poke wait when RTMpPokeCpu fails",
716 "/PROF/CPU%d/HM/PokeWaitFailed", i);
717 AssertRC(rc);
718 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
719 "Profiling of VMXR0RunGuestCode entry",
720 "/PROF/CPU%d/HM/StatEntry", i);
721 AssertRC(rc);
722 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
723 "Profiling of VMXR0RunGuestCode exit part 1",
724 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
725 AssertRC(rc);
726 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
727 "Profiling of VMXR0RunGuestCode exit part 2",
728 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
729 AssertRC(rc);
730
731 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
732 "I/O",
733 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
734 AssertRC(rc);
735 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
736 "MOV CRx",
737 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
738 AssertRC(rc);
739 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
740 "Exceptions, NMIs",
741 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
742 AssertRC(rc);
743
744 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
745 "Profiling of VMXR0LoadGuestState",
746 "/PROF/CPU%d/HM/StatLoadGuestState", i);
747 AssertRC(rc);
748 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
749 "Profiling of VMLAUNCH/VMRESUME.",
750 "/PROF/CPU%d/HM/InGC", i);
751 AssertRC(rc);
752
753# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
754 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
755 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
756 "/PROF/CPU%d/HM/Switcher3264", i);
757 AssertRC(rc);
758# endif
759
760# ifdef HM_PROFILE_EXIT_DISPATCH
761 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
762 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
763 "/PROF/CPU%d/HM/ExitDispatch", i);
764 AssertRC(rc);
765# endif
766
767#endif
768# define HM_REG_COUNTER(a, b, desc) \
769 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
770 AssertRC(rc);
771
772#ifdef VBOX_WITH_STATISTICS
773 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
774 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
775 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
776 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
777 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
778 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
779 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
780 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
781 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
782 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
783 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
784 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
785 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
786 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
787 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
788 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
789 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
790 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
791 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
792 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
793 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
794 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
795 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
796 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
797 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
798 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
799 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
800 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
801 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
802 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
803 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
804 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
805 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
806 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
807 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
808 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
809 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
810 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
811 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
812 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
813 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
814 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
815 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
816 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
817 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
818 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
819 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
820#endif
821 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
822#ifdef VBOX_WITH_STATISTICS
823 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
824 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
825 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
826 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
827 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
828
829 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
830 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
831 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
832 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
833 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
834 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
835 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
836 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
837 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
838 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
839
840 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
841 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
842 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
843
844 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
845 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
846 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
847 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
848 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
849 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
850 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
851 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
852 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
853 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
854 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
855 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
856 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
857 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
858
859 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
860 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
861 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
862
863 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
864 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
865 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
866
867 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
868 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
869
870 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
871 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
872 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
873 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
874 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
875 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
876 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
877 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
878
879#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
880 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
881 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
882#endif
883
884 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
885 {
886 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
887 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
888 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
889 AssertRC(rc);
890 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
891 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
892 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
893 AssertRC(rc);
894 }
895
896#undef HM_REG_COUNTER
897
898 pVCpu->hm.s.paStatExitReason = NULL;
899
900 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
901 (void **)&pVCpu->hm.s.paStatExitReason);
902 AssertRC(rc);
903 if (RT_SUCCESS(rc))
904 {
905 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
906 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
907 {
908 if (papszDesc[j])
909 {
910 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
911 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
912 AssertRC(rc);
913 }
914 }
915 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
916 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
917 AssertRC(rc);
918 }
919 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
920# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
921 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
922# else
923 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
924# endif
925
926 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
927 AssertRCReturn(rc, rc);
928 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
929# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
930 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
931# else
932 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
933# endif
934 for (unsigned j = 0; j < 255; j++)
935 {
936 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
937 "Injected event.",
938 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
939 }
940
941#endif /* VBOX_WITH_STATISTICS */
942 }
943
944#ifdef VBOX_WITH_CRASHDUMP_MAGIC
945 /*
946 * Magic marker for searching in crash dumps.
947 */
948 for (VMCPUID i = 0; i < pVM->cCpus; i++)
949 {
950 PVMCPU pVCpu = &pVM->aCpus[i];
951
952 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
953 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
954 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
955 }
956#endif
957
958 return VINF_SUCCESS;
959}
960
961
962/**
963 * Called when a init phase has completed.
964 *
965 * @returns VBox status code.
966 * @param pVM The cross context VM structure.
967 * @param enmWhat The phase that completed.
968 */
969VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
970{
971 switch (enmWhat)
972 {
973 case VMINITCOMPLETED_RING3:
974 return hmR3InitCPU(pVM);
975 case VMINITCOMPLETED_RING0:
976 return hmR3InitFinalizeR0(pVM);
977 default:
978 return VINF_SUCCESS;
979 }
980}
981
982
983/**
984 * Turns off normal raw mode features.
985 *
986 * @param pVM The cross context VM structure.
987 */
988static void hmR3DisableRawMode(PVM pVM)
989{
990 /* Reinit the paging mode to force the new shadow mode. */
991 for (VMCPUID i = 0; i < pVM->cCpus; i++)
992 {
993 PVMCPU pVCpu = &pVM->aCpus[i];
994
995 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
996 }
997}
998
999
1000/**
1001 * Initialize VT-x or AMD-V.
1002 *
1003 * @returns VBox status code.
1004 * @param pVM The cross context VM structure.
1005 */
1006static int hmR3InitFinalizeR0(PVM pVM)
1007{
1008 int rc;
1009
1010 if (!HMIsEnabled(pVM))
1011 return VINF_SUCCESS;
1012
1013 /*
1014 * Hack to allow users to work around broken BIOSes that incorrectly set
1015 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1016 */
1017 if ( !pVM->hm.s.vmx.fSupported
1018 && !pVM->hm.s.svm.fSupported
1019 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
1020 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1021 {
1022 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1023 pVM->hm.s.svm.fSupported = true;
1024 pVM->hm.s.svm.fIgnoreInUseError = true;
1025 pVM->hm.s.lLastError = VINF_SUCCESS;
1026 }
1027
1028 /*
1029 * Report ring-0 init errors.
1030 */
1031 if ( !pVM->hm.s.vmx.fSupported
1032 && !pVM->hm.s.svm.fSupported)
1033 {
1034 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
1035 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1036 switch (pVM->hm.s.lLastError)
1037 {
1038 case VERR_VMX_IN_VMX_ROOT_MODE:
1039 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1040 case VERR_VMX_NO_VMX:
1041 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1042 case VERR_VMX_MSR_VMX_DISABLED:
1043 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1044 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1045 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1046 case VERR_VMX_MSR_LOCKING_FAILED:
1047 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1048 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1049 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1050 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1051 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1052
1053 case VERR_SVM_IN_USE:
1054 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1055 case VERR_SVM_NO_SVM:
1056 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1057 case VERR_SVM_DISABLED:
1058 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1059 }
1060 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
1061 }
1062
1063 /*
1064 * Enable VT-x or AMD-V on all host CPUs.
1065 */
1066 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1067 if (RT_FAILURE(rc))
1068 {
1069 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1070 HMR3CheckError(pVM, rc);
1071 return rc;
1072 }
1073
1074 /*
1075 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1076 * (Main should have taken care of this already)
1077 */
1078 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
1079 if (!pVM->hm.s.fHasIoApic)
1080 {
1081 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1082 pVM->hm.s.fTprPatchingAllowed = false;
1083 }
1084
1085 /*
1086 * Do the vendor specific initialization .
1087 * .
1088 * Note! We disable release log buffering here since we're doing relatively .
1089 * lot of logging and doesn't want to hit the disk with each LogRel .
1090 * statement.
1091 */
1092 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1093 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1094 if (pVM->hm.s.vmx.fSupported)
1095 rc = hmR3InitFinalizeR0Intel(pVM);
1096 else
1097 rc = hmR3InitFinalizeR0Amd(pVM);
1098 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1099 RTLogRelSetBuffering(fOldBuffered);
1100 pVM->hm.s.fInitialized = true;
1101
1102 return rc;
1103}
1104
1105
1106/**
1107 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1108 */
1109static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1110{
1111 NOREF(pVM);
1112 NOREF(pvAllocation);
1113 NOREF(GCPhysAllocation);
1114}
1115
1116
1117/**
1118 * Finish VT-x initialization (after ring-0 init).
1119 *
1120 * @returns VBox status code.
1121 * @param pVM The cross context VM structure.
1122 */
1123static int hmR3InitFinalizeR0Intel(PVM pVM)
1124{
1125 int rc;
1126
1127 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1128 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1129
1130 uint64_t val;
1131 uint64_t zap;
1132 RTGCPHYS GCPhys = 0;
1133
1134 LogRel(("HM: Using VT-x implementation 2.0\n"));
1135 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1136 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1137 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1138 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1139 if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1140 LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1141 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1142 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1143 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1144 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1145 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1146 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1147 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1148 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1149
1150 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1151 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1152 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1153 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1154 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1155 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1156 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1157 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1158
1159 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1160 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1161 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1162 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1163 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1164 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1165 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1166 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1167 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1168 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1169 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1170 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1171 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1172 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1173 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1174 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1175 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1176 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1177 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1178 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1179 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1180 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1181 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1182 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1183 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1184 {
1185 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1186 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1187 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1188 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1189 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1190 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1191 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1192 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1193 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1194 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1195 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1196 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1197 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1198 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1199 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1200 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1201 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1202 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1203 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1204 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1205 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_XSAVES);
1206 }
1207
1208 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1209 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1210 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1211 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1212 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1213 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1214 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1215 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1216 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1217 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1218
1219 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1220 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1221 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1222 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1223 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1224 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1225 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1226 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1227 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1228 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1229 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1230 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1231
1232 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1233 {
1234 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1235 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1236 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1237 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1238 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1239 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1240 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1241 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1242 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1243 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1244 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1245 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1246 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1247 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1248 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1249 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1250 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1251 }
1252
1253 val = pVM->hm.s.vmx.Msrs.u64Misc;
1254 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1255 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1256 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1257 else
1258 {
1259 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1260 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1261 }
1262
1263 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1264 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1265 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1266 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1267 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1268 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1269 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1270 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1271
1272 /* Paranoia */
1273 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1274
1275 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1276 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1277 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1278 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1279
1280 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1281 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1282 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1283
1284 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1285 if (val)
1286 {
1287 LogRel(("HM: MSR_A32_VMX_VMFUNC = %#RX64\n", val));
1288 HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1289 }
1290
1291 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1292
1293 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1294 {
1295 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1296 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1297 }
1298
1299 /*
1300 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1301 */
1302 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1303 || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1304 VERR_HM_IPE_1);
1305 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1306 || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1307 && pVM->hm.s.fNestedPaging),
1308 VERR_HM_IPE_1);
1309
1310 /*
1311 * Enable VPID if configured and supported.
1312 */
1313 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1314 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1315
1316#ifdef VBOX_WITH_NEW_APIC
1317 /*
1318 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1319 */
1320 if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1321 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1322 pVM->hm.s.fVirtApicRegs = true;
1323
1324 /*
1325 * Enable posted-interrupt processing if supported.
1326 */
1327 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1328 * here. */
1329 if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1330 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1331 pVM->hm.s.fPostedIntrs = true;
1332#endif
1333
1334 /*
1335 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1336 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1337 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1338 */
1339 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1340 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1341 {
1342 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1343 LogRel(("HM: Disabled RDTSCP\n"));
1344 }
1345
1346 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1347 {
1348 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1349 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1350 if (RT_SUCCESS(rc))
1351 {
1352 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1353 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1354 esp. Figure 20-5.*/
1355 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1356 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1357
1358 /* Bit set to 0 means software interrupts are redirected to the
1359 8086 program interrupt handler rather than switching to
1360 protected-mode handler. */
1361 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1362
1363 /* Allow all port IO, so that port IO instructions do not cause
1364 exceptions and would instead cause a VM-exit (based on VT-x's
1365 IO bitmap which we currently configure to always cause an exit). */
1366 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1367 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1368
1369 /*
1370 * Construct a 1024 element page directory with 4 MB pages for
1371 * the identity mapped page table used in real and protected mode
1372 * without paging with EPT.
1373 */
1374 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1375 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1376 {
1377 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1378 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1379 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1380 | X86_PDE4M_G;
1381 }
1382
1383 /* We convert it here every time as pci regions could be reconfigured. */
1384 if (PDMVmmDevHeapIsEnabled(pVM))
1385 {
1386 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1387 AssertRCReturn(rc, rc);
1388 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1389
1390 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1391 AssertRCReturn(rc, rc);
1392 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1393 }
1394 }
1395 else
1396 {
1397 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1398 pVM->hm.s.vmx.pRealModeTSS = NULL;
1399 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1400 return VMSetError(pVM, rc, RT_SRC_POS,
1401 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1402 }
1403 }
1404
1405 LogRel((pVM->hm.s.fAllow64BitGuests
1406 ? "HM: Guest support: 32-bit and 64-bit\n"
1407 : "HM: Guest support: 32-bit only\n"));
1408
1409 /*
1410 * Call ring-0 to set up the VM.
1411 */
1412 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1413 if (rc != VINF_SUCCESS)
1414 {
1415 AssertMsgFailed(("%Rrc\n", rc));
1416 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1417 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1418 {
1419 PVMCPU pVCpu = &pVM->aCpus[i];
1420 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1421 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1422 }
1423 HMR3CheckError(pVM, rc);
1424 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1425 }
1426
1427 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1428 LogRel(("HM: Enabled VMX\n"));
1429 pVM->hm.s.vmx.fEnabled = true;
1430
1431 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1432
1433 /*
1434 * Change the CPU features.
1435 */
1436 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1437 if (pVM->hm.s.fAllow64BitGuests)
1438 {
1439 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1440 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1441 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1442 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1443 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1444 }
1445 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1446 (we reuse the host EFER in the switcher). */
1447 /** @todo this needs to be fixed properly!! */
1448 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1449 {
1450 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1451 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1452 else
1453 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1454 }
1455
1456 /*
1457 * Log configuration details.
1458 */
1459 if (pVM->hm.s.fNestedPaging)
1460 {
1461 LogRel(("HM: Enabled nested paging\n"));
1462 if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1463 LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1464 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1465 LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1466 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1467 LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1468 else
1469 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1470
1471 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1472 LogRel(("HM: Enabled unrestricted guest execution\n"));
1473
1474#if HC_ARCH_BITS == 64
1475 if (pVM->hm.s.fLargePages)
1476 {
1477 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1478 PGMSetLargePageUsage(pVM, true);
1479 LogRel(("HM: Enabled large page support\n"));
1480 }
1481#endif
1482 }
1483 else
1484 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1485
1486 if (pVM->hm.s.fVirtApicRegs)
1487 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1488
1489 if (pVM->hm.s.fPostedIntrs)
1490 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1491
1492 if (pVM->hm.s.vmx.fVpid)
1493 {
1494 LogRel(("HM: Enabled VPID\n"));
1495 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1496 LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1497 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1498 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1499 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1500 LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1501 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1502 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1503 else
1504 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1505 }
1506 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1507 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1508
1509 if (pVM->hm.s.vmx.fUsePreemptTimer)
1510 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1511 else
1512 LogRel(("HM: Disabled VMX-preemption timer\n"));
1513
1514 return VINF_SUCCESS;
1515}
1516
1517
1518/**
1519 * Finish AMD-V initialization (after ring-0 init).
1520 *
1521 * @returns VBox status code.
1522 * @param pVM The cross context VM structure.
1523 */
1524static int hmR3InitFinalizeR0Amd(PVM pVM)
1525{
1526 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1527
1528 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1529
1530 uint32_t u32Family;
1531 uint32_t u32Model;
1532 uint32_t u32Stepping;
1533 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1534 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1535 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1536 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1537 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1538 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1539 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1540 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1541 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1542
1543 /*
1544 * Enumerate AMD-V features.
1545 */
1546 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1547 {
1548#define HMSVM_REPORT_FEATURE(a_Define) { a_Define, #a_Define }
1549 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1550 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1551 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1552 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1553 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1554 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1555 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1556 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1557 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1558 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1559 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1560#undef HMSVM_REPORT_FEATURE
1561 };
1562
1563 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1564 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1565 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1566 {
1567 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1568 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1569 }
1570 if (fSvmFeatures)
1571 for (unsigned iBit = 0; iBit < 32; iBit++)
1572 if (RT_BIT_32(iBit) & fSvmFeatures)
1573 LogRel(("HM: Reserved bit %u\n", iBit));
1574
1575 /*
1576 * Nested paging is determined in HMR3Init, verify the sanity of that.
1577 */
1578 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1579 || (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1580 VERR_HM_IPE_1);
1581
1582#if 0
1583 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1584 * here. */
1585 if (RTR0IsPostIpiSupport())
1586 pVM->hm.s.fPostedIntrs = true;
1587#endif
1588
1589 /*
1590 * Call ring-0 to set up the VM.
1591 */
1592 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1593 if (rc != VINF_SUCCESS)
1594 {
1595 AssertMsgFailed(("%Rrc\n", rc));
1596 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1597 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1598 }
1599
1600 LogRel(("HM: Enabled SVM\n"));
1601 pVM->hm.s.svm.fEnabled = true;
1602
1603 if (pVM->hm.s.fNestedPaging)
1604 {
1605 LogRel(("HM: Enabled nested paging\n"));
1606
1607 /*
1608 * Enable large pages (2 MB) if applicable.
1609 */
1610#if HC_ARCH_BITS == 64
1611 if (pVM->hm.s.fLargePages)
1612 {
1613 PGMSetLargePageUsage(pVM, true);
1614 LogRel(("HM: Enabled large page support\n"));
1615 }
1616#endif
1617 }
1618
1619 if (pVM->hm.s.fVirtApicRegs)
1620 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1621
1622 if (pVM->hm.s.fPostedIntrs)
1623 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1624
1625 hmR3DisableRawMode(pVM);
1626
1627 /*
1628 * Change the CPU features.
1629 */
1630 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1631 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1632 if (pVM->hm.s.fAllow64BitGuests)
1633 {
1634 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1635 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1636 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1637 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1638 }
1639 /* Turn on NXE if PAE has been enabled. */
1640 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1641 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1642
1643 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1644
1645 LogRel((pVM->hm.s.fAllow64BitGuests
1646 ? "HM: Guest support: 32-bit and 64-bit\n"
1647 : "HM: Guest support: 32-bit only\n"));
1648
1649 return VINF_SUCCESS;
1650}
1651
1652
1653/**
1654 * Applies relocations to data and code managed by this
1655 * component. This function will be called at init and
1656 * whenever the VMM need to relocate it self inside the GC.
1657 *
1658 * @param pVM The cross context VM structure.
1659 */
1660VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1661{
1662 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1663
1664 /* Fetch the current paging mode during the relocate callback during state loading. */
1665 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1666 {
1667 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1668 {
1669 PVMCPU pVCpu = &pVM->aCpus[i];
1670 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1671 }
1672 }
1673#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1674 if (HMIsEnabled(pVM))
1675 {
1676 switch (PGMGetHostMode(pVM))
1677 {
1678 case PGMMODE_32_BIT:
1679 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1680 break;
1681
1682 case PGMMODE_PAE:
1683 case PGMMODE_PAE_NX:
1684 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1685 break;
1686
1687 default:
1688 AssertFailed();
1689 break;
1690 }
1691 }
1692#endif
1693 return;
1694}
1695
1696
1697/**
1698 * Notification callback which is called whenever there is a chance that a CR3
1699 * value might have changed.
1700 *
1701 * This is called by PGM.
1702 *
1703 * @param pVM The cross context VM structure.
1704 * @param pVCpu The cross context virtual CPU structure.
1705 * @param enmShadowMode New shadow paging mode.
1706 * @param enmGuestMode New guest paging mode.
1707 */
1708VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1709{
1710 /* Ignore page mode changes during state loading. */
1711 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1712 return;
1713
1714 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1715
1716 /*
1717 * If the guest left protected mode VMX execution, we'll have to be
1718 * extra careful if/when the guest switches back to protected mode.
1719 */
1720 if (enmGuestMode == PGMMODE_REAL)
1721 {
1722 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1723 pVCpu->hm.s.vmx.fWasInRealMode = true;
1724 }
1725}
1726
1727
1728/**
1729 * Terminates the HM.
1730 *
1731 * Termination means cleaning up and freeing all resources,
1732 * the VM itself is, at this point, powered off or suspended.
1733 *
1734 * @returns VBox status code.
1735 * @param pVM The cross context VM structure.
1736 */
1737VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1738{
1739 if (pVM->hm.s.vmx.pRealModeTSS)
1740 {
1741 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1742 pVM->hm.s.vmx.pRealModeTSS = 0;
1743 }
1744 hmR3TermCPU(pVM);
1745 return 0;
1746}
1747
1748
1749/**
1750 * Terminates the per-VCPU HM.
1751 *
1752 * @returns VBox status code.
1753 * @param pVM The cross context VM structure.
1754 */
1755static int hmR3TermCPU(PVM pVM)
1756{
1757 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1758 {
1759 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1760
1761#ifdef VBOX_WITH_STATISTICS
1762 if (pVCpu->hm.s.paStatExitReason)
1763 {
1764 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1765 pVCpu->hm.s.paStatExitReason = NULL;
1766 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1767 }
1768 if (pVCpu->hm.s.paStatInjectedIrqs)
1769 {
1770 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1771 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1772 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1773 }
1774#endif
1775
1776#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1777 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1778 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1779 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1780#endif
1781 }
1782 return 0;
1783}
1784
1785
1786/**
1787 * Resets a virtual CPU.
1788 *
1789 * Used by HMR3Reset and CPU hot plugging.
1790 *
1791 * @param pVCpu The cross context virtual CPU structure to reset.
1792 */
1793VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1794{
1795 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
1796 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1797 HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1798
1799 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1800 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1801 pVCpu->hm.s.fActive = false;
1802 pVCpu->hm.s.Event.fPending = false;
1803 pVCpu->hm.s.vmx.fWasInRealMode = true;
1804 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
1805
1806 /* Reset the contents of the read cache. */
1807 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1808 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1809 pCache->Read.aFieldVal[j] = 0;
1810
1811#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1812 /* Magic marker for searching in crash dumps. */
1813 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1814 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1815#endif
1816}
1817
1818
1819/**
1820 * The VM is being reset.
1821 *
1822 * For the HM component this means that any GDT/LDT/TSS monitors
1823 * needs to be removed.
1824 *
1825 * @param pVM The cross context VM structure.
1826 */
1827VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1828{
1829 LogFlow(("HMR3Reset:\n"));
1830
1831 if (HMIsEnabled(pVM))
1832 hmR3DisableRawMode(pVM);
1833
1834 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1835 {
1836 PVMCPU pVCpu = &pVM->aCpus[i];
1837
1838 HMR3ResetCpu(pVCpu);
1839 }
1840
1841 /* Clear all patch information. */
1842 pVM->hm.s.pGuestPatchMem = 0;
1843 pVM->hm.s.pFreeGuestPatchMem = 0;
1844 pVM->hm.s.cbGuestPatchMem = 0;
1845 pVM->hm.s.cPatches = 0;
1846 pVM->hm.s.PatchTree = 0;
1847 pVM->hm.s.fTPRPatchingActive = false;
1848 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1849}
1850
1851
1852/**
1853 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1854 *
1855 * @returns VBox strict status code.
1856 * @param pVM The cross context VM structure.
1857 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1858 * @param pvUser Unused.
1859 */
1860static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1861{
1862 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1863
1864 /* Only execute the handler on the VCPU the original patch request was issued. */
1865 if (pVCpu->idCpu != idCpu)
1866 return VINF_SUCCESS;
1867
1868 Log(("hmR3RemovePatches\n"));
1869 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1870 {
1871 uint8_t abInstr[15];
1872 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1873 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1874 int rc;
1875
1876#ifdef LOG_ENABLED
1877 char szOutput[256];
1878
1879 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1880 szOutput, sizeof(szOutput), NULL);
1881 if (RT_SUCCESS(rc))
1882 Log(("Patched instr: %s\n", szOutput));
1883#endif
1884
1885 /* Check if the instruction is still the same. */
1886 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1887 if (rc != VINF_SUCCESS)
1888 {
1889 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1890 continue; /* swapped out or otherwise removed; skip it. */
1891 }
1892
1893 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1894 {
1895 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1896 continue; /* skip it. */
1897 }
1898
1899 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1900 AssertRC(rc);
1901
1902#ifdef LOG_ENABLED
1903 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1904 szOutput, sizeof(szOutput), NULL);
1905 if (RT_SUCCESS(rc))
1906 Log(("Original instr: %s\n", szOutput));
1907#endif
1908 }
1909 pVM->hm.s.cPatches = 0;
1910 pVM->hm.s.PatchTree = 0;
1911 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1912 pVM->hm.s.fTPRPatchingActive = false;
1913 return VINF_SUCCESS;
1914}
1915
1916
1917/**
1918 * Worker for enabling patching in a VT-x/AMD-V guest.
1919 *
1920 * @returns VBox status code.
1921 * @param pVM The cross context VM structure.
1922 * @param idCpu VCPU to execute hmR3RemovePatches on.
1923 * @param pPatchMem Patch memory range.
1924 * @param cbPatchMem Size of the memory range.
1925 */
1926static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1927{
1928 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1929 AssertRC(rc);
1930
1931 pVM->hm.s.pGuestPatchMem = pPatchMem;
1932 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1933 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1934 return VINF_SUCCESS;
1935}
1936
1937
1938/**
1939 * Enable patching in a VT-x/AMD-V guest
1940 *
1941 * @returns VBox status code.
1942 * @param pVM The cross context VM structure.
1943 * @param pPatchMem Patch memory range.
1944 * @param cbPatchMem Size of the memory range.
1945 */
1946VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1947{
1948 VM_ASSERT_EMT(pVM);
1949 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1950 if (pVM->cCpus > 1)
1951 {
1952 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1953 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1954 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1955 AssertRC(rc);
1956 return rc;
1957 }
1958 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1959}
1960
1961
1962/**
1963 * Disable patching in a VT-x/AMD-V guest.
1964 *
1965 * @returns VBox status code.
1966 * @param pVM The cross context VM structure.
1967 * @param pPatchMem Patch memory range.
1968 * @param cbPatchMem Size of the memory range.
1969 */
1970VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1971{
1972 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1973
1974 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1975 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1976
1977 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1978 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1979 (void *)(uintptr_t)VMMGetCpuId(pVM));
1980 AssertRC(rc);
1981
1982 pVM->hm.s.pGuestPatchMem = 0;
1983 pVM->hm.s.pFreeGuestPatchMem = 0;
1984 pVM->hm.s.cbGuestPatchMem = 0;
1985 pVM->hm.s.fTPRPatchingActive = false;
1986 return VINF_SUCCESS;
1987}
1988
1989
1990/**
1991 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1992 *
1993 * @returns VBox strict status code.
1994 * @param pVM The cross context VM structure.
1995 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1996 * @param pvUser User specified CPU context.
1997 *
1998 */
1999static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2000{
2001 /*
2002 * Only execute the handler on the VCPU the original patch request was
2003 * issued. (The other CPU(s) might not yet have switched to protected
2004 * mode, nor have the correct memory context.)
2005 */
2006 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2007 if (pVCpu->idCpu != idCpu)
2008 return VINF_SUCCESS;
2009
2010 /*
2011 * We're racing other VCPUs here, so don't try patch the instruction twice
2012 * and make sure there is still room for our patch record.
2013 */
2014 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2015 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2016 if (pPatch)
2017 {
2018 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2019 return VINF_SUCCESS;
2020 }
2021 uint32_t const idx = pVM->hm.s.cPatches;
2022 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2023 {
2024 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2025 return VINF_SUCCESS;
2026 }
2027 pPatch = &pVM->hm.s.aPatches[idx];
2028
2029 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2030
2031 /*
2032 * Disassembler the instruction and get cracking.
2033 */
2034 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2035 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2036 uint32_t cbOp;
2037 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2038 AssertRC(rc);
2039 if ( rc == VINF_SUCCESS
2040 && pDis->pCurInstr->uOpcode == OP_MOV
2041 && cbOp >= 3)
2042 {
2043 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2044
2045 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2046 AssertRC(rc);
2047
2048 pPatch->cbOp = cbOp;
2049
2050 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2051 {
2052 /* write. */
2053 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2054 {
2055 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2056 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2057 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2058 }
2059 else
2060 {
2061 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2062 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2063 pPatch->uSrcOperand = pDis->Param2.uValue;
2064 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2065 }
2066 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2067 AssertRC(rc);
2068
2069 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2070 pPatch->cbNewOp = sizeof(s_abVMMCall);
2071 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2072 }
2073 else
2074 {
2075 /*
2076 * TPR Read.
2077 *
2078 * Found:
2079 * mov eax, dword [fffe0080] (5 bytes)
2080 * Check if next instruction is:
2081 * shr eax, 4
2082 */
2083 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2084
2085 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2086 uint8_t const cbOpMmio = cbOp;
2087 uint64_t const uSavedRip = pCtx->rip;
2088
2089 pCtx->rip += cbOp;
2090 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2091 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2092 pCtx->rip = uSavedRip;
2093
2094 if ( rc == VINF_SUCCESS
2095 && pDis->pCurInstr->uOpcode == OP_SHR
2096 && pDis->Param1.fUse == DISUSE_REG_GEN32
2097 && pDis->Param1.Base.idxGenReg == idxMmioReg
2098 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2099 && pDis->Param2.uValue == 4
2100 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2101 {
2102 uint8_t abInstr[15];
2103
2104 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2105 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2106 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2107 AssertRC(rc);
2108
2109 pPatch->cbOp = cbOpMmio + cbOp;
2110
2111 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2112 abInstr[0] = 0xF0;
2113 abInstr[1] = 0x0F;
2114 abInstr[2] = 0x20;
2115 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2116 for (unsigned i = 4; i < pPatch->cbOp; i++)
2117 abInstr[i] = 0x90; /* nop */
2118
2119 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2120 AssertRC(rc);
2121
2122 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2123 pPatch->cbNewOp = pPatch->cbOp;
2124 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2125
2126 Log(("Acceptable read/shr candidate!\n"));
2127 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2128 }
2129 else
2130 {
2131 pPatch->enmType = HMTPRINSTR_READ;
2132 pPatch->uDstOperand = idxMmioReg;
2133
2134 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2135 AssertRC(rc);
2136
2137 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2138 pPatch->cbNewOp = sizeof(s_abVMMCall);
2139 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2140 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2141 }
2142 }
2143
2144 pPatch->Core.Key = pCtx->eip;
2145 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2146 AssertRC(rc);
2147
2148 pVM->hm.s.cPatches++;
2149 return VINF_SUCCESS;
2150 }
2151
2152 /*
2153 * Save invalid patch, so we will not try again.
2154 */
2155 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2156 pPatch->Core.Key = pCtx->eip;
2157 pPatch->enmType = HMTPRINSTR_INVALID;
2158 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2159 AssertRC(rc);
2160 pVM->hm.s.cPatches++;
2161 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2162 return VINF_SUCCESS;
2163}
2164
2165
2166/**
2167 * Callback to patch a TPR instruction (jump to generated code).
2168 *
2169 * @returns VBox strict status code.
2170 * @param pVM The cross context VM structure.
2171 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2172 * @param pvUser User specified CPU context.
2173 *
2174 */
2175static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2176{
2177 /*
2178 * Only execute the handler on the VCPU the original patch request was
2179 * issued. (The other CPU(s) might not yet have switched to protected
2180 * mode, nor have the correct memory context.)
2181 */
2182 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2183 if (pVCpu->idCpu != idCpu)
2184 return VINF_SUCCESS;
2185
2186 /*
2187 * We're racing other VCPUs here, so don't try patch the instruction twice
2188 * and make sure there is still room for our patch record.
2189 */
2190 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2191 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2192 if (pPatch)
2193 {
2194 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2195 return VINF_SUCCESS;
2196 }
2197 uint32_t const idx = pVM->hm.s.cPatches;
2198 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2199 {
2200 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2201 return VINF_SUCCESS;
2202 }
2203 pPatch = &pVM->hm.s.aPatches[idx];
2204
2205 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2206 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2207
2208 /*
2209 * Disassemble the instruction and get cracking.
2210 */
2211 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2212 uint32_t cbOp;
2213 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2214 AssertRC(rc);
2215 if ( rc == VINF_SUCCESS
2216 && pDis->pCurInstr->uOpcode == OP_MOV
2217 && cbOp >= 5)
2218 {
2219 uint8_t aPatch[64];
2220 uint32_t off = 0;
2221
2222 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2223 AssertRC(rc);
2224
2225 pPatch->cbOp = cbOp;
2226 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2227
2228 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2229 {
2230 /*
2231 * TPR write:
2232 *
2233 * push ECX [51]
2234 * push EDX [52]
2235 * push EAX [50]
2236 * xor EDX,EDX [31 D2]
2237 * mov EAX,EAX [89 C0]
2238 * or
2239 * mov EAX,0000000CCh [B8 CC 00 00 00]
2240 * mov ECX,0C0000082h [B9 82 00 00 C0]
2241 * wrmsr [0F 30]
2242 * pop EAX [58]
2243 * pop EDX [5A]
2244 * pop ECX [59]
2245 * jmp return_address [E9 return_address]
2246 *
2247 */
2248 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2249
2250 aPatch[off++] = 0x51; /* push ecx */
2251 aPatch[off++] = 0x52; /* push edx */
2252 if (!fUsesEax)
2253 aPatch[off++] = 0x50; /* push eax */
2254 aPatch[off++] = 0x31; /* xor edx, edx */
2255 aPatch[off++] = 0xD2;
2256 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2257 {
2258 if (!fUsesEax)
2259 {
2260 aPatch[off++] = 0x89; /* mov eax, src_reg */
2261 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2262 }
2263 }
2264 else
2265 {
2266 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2267 aPatch[off++] = 0xB8; /* mov eax, immediate */
2268 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2269 off += sizeof(uint32_t);
2270 }
2271 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2272 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2273 off += sizeof(uint32_t);
2274
2275 aPatch[off++] = 0x0F; /* wrmsr */
2276 aPatch[off++] = 0x30;
2277 if (!fUsesEax)
2278 aPatch[off++] = 0x58; /* pop eax */
2279 aPatch[off++] = 0x5A; /* pop edx */
2280 aPatch[off++] = 0x59; /* pop ecx */
2281 }
2282 else
2283 {
2284 /*
2285 * TPR read:
2286 *
2287 * push ECX [51]
2288 * push EDX [52]
2289 * push EAX [50]
2290 * mov ECX,0C0000082h [B9 82 00 00 C0]
2291 * rdmsr [0F 32]
2292 * mov EAX,EAX [89 C0]
2293 * pop EAX [58]
2294 * pop EDX [5A]
2295 * pop ECX [59]
2296 * jmp return_address [E9 return_address]
2297 *
2298 */
2299 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2300
2301 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2302 aPatch[off++] = 0x51; /* push ecx */
2303 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2304 aPatch[off++] = 0x52; /* push edx */
2305 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2306 aPatch[off++] = 0x50; /* push eax */
2307
2308 aPatch[off++] = 0x31; /* xor edx, edx */
2309 aPatch[off++] = 0xD2;
2310
2311 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2312 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2313 off += sizeof(uint32_t);
2314
2315 aPatch[off++] = 0x0F; /* rdmsr */
2316 aPatch[off++] = 0x32;
2317
2318 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2319 {
2320 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2321 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2322 }
2323
2324 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2325 aPatch[off++] = 0x58; /* pop eax */
2326 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2327 aPatch[off++] = 0x5A; /* pop edx */
2328 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2329 aPatch[off++] = 0x59; /* pop ecx */
2330 }
2331 aPatch[off++] = 0xE9; /* jmp return_address */
2332 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2333 off += sizeof(RTRCUINTPTR);
2334
2335 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2336 {
2337 /* Write new code to the patch buffer. */
2338 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2339 AssertRC(rc);
2340
2341#ifdef LOG_ENABLED
2342 uint32_t cbCurInstr;
2343 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2344 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2345 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2346 {
2347 char szOutput[256];
2348 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2349 szOutput, sizeof(szOutput), &cbCurInstr);
2350 if (RT_SUCCESS(rc))
2351 Log(("Patch instr %s\n", szOutput));
2352 else
2353 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2354 }
2355#endif
2356
2357 pPatch->aNewOpcode[0] = 0xE9;
2358 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2359
2360 /* Overwrite the TPR instruction with a jump. */
2361 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2362 AssertRC(rc);
2363
2364 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2365
2366 pVM->hm.s.pFreeGuestPatchMem += off;
2367 pPatch->cbNewOp = 5;
2368
2369 pPatch->Core.Key = pCtx->eip;
2370 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2371 AssertRC(rc);
2372
2373 pVM->hm.s.cPatches++;
2374 pVM->hm.s.fTPRPatchingActive = true;
2375 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2376 return VINF_SUCCESS;
2377 }
2378
2379 Log(("Ran out of space in our patch buffer!\n"));
2380 }
2381 else
2382 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2383
2384
2385 /*
2386 * Save invalid patch, so we will not try again.
2387 */
2388 pPatch = &pVM->hm.s.aPatches[idx];
2389 pPatch->Core.Key = pCtx->eip;
2390 pPatch->enmType = HMTPRINSTR_INVALID;
2391 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2392 AssertRC(rc);
2393 pVM->hm.s.cPatches++;
2394 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2395 return VINF_SUCCESS;
2396}
2397
2398
2399/**
2400 * Attempt to patch TPR mmio instructions.
2401 *
2402 * @returns VBox status code.
2403 * @param pVM The cross context VM structure.
2404 * @param pVCpu The cross context virtual CPU structure.
2405 * @param pCtx Pointer to the guest CPU context.
2406 */
2407VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2408{
2409 NOREF(pCtx);
2410 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2411 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2412 (void *)(uintptr_t)pVCpu->idCpu);
2413 AssertRC(rc);
2414 return rc;
2415}
2416
2417
2418/**
2419 * Checks if a code selector (CS) is suitable for execution
2420 * within VMX when unrestricted execution isn't available.
2421 *
2422 * @returns true if selector is suitable for VMX, otherwise
2423 * false.
2424 * @param pSel Pointer to the selector to check (CS).
2425 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2426 */
2427static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2428{
2429 /*
2430 * Segment must be an accessed code segment, it must be present and it must
2431 * be usable.
2432 * Note! These are all standard requirements and if CS holds anything else
2433 * we've got buggy code somewhere!
2434 */
2435 AssertCompile(X86DESCATTR_TYPE == 0xf);
2436 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2437 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2438 ("%#x\n", pSel->Attr.u),
2439 false);
2440
2441 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2442 must equal SS.DPL for non-confroming segments.
2443 Note! This is also a hard requirement like above. */
2444 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2445 ? pSel->Attr.n.u2Dpl <= uStackDpl
2446 : pSel->Attr.n.u2Dpl == uStackDpl,
2447 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2448 false);
2449
2450 /*
2451 * The following two requirements are VT-x specific:
2452 * - G bit must be set if any high limit bits are set.
2453 * - G bit must be clear if any low limit bits are clear.
2454 */
2455 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2456 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2457 return true;
2458 return false;
2459}
2460
2461
2462/**
2463 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2464 * execution within VMX when unrestricted execution isn't
2465 * available.
2466 *
2467 * @returns true if selector is suitable for VMX, otherwise
2468 * false.
2469 * @param pSel Pointer to the selector to check
2470 * (DS/ES/FS/GS).
2471 */
2472static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2473{
2474 /*
2475 * Unusable segments are OK. These days they should be marked as such, as
2476 * but as an alternative we for old saved states and AMD<->VT-x migration
2477 * we also treat segments with all the attributes cleared as unusable.
2478 */
2479 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2480 return true;
2481
2482 /** @todo tighten these checks. Will require CPUM load adjusting. */
2483
2484 /* Segment must be accessed. */
2485 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2486 {
2487 /* Code segments must also be readable. */
2488 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2489 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2490 {
2491 /* The S bit must be set. */
2492 if (pSel->Attr.n.u1DescType)
2493 {
2494 /* Except for conforming segments, DPL >= RPL. */
2495 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2496 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2497 {
2498 /* Segment must be present. */
2499 if (pSel->Attr.n.u1Present)
2500 {
2501 /*
2502 * The following two requirements are VT-x specific:
2503 * - G bit must be set if any high limit bits are set.
2504 * - G bit must be clear if any low limit bits are clear.
2505 */
2506 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2507 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2508 return true;
2509 }
2510 }
2511 }
2512 }
2513 }
2514
2515 return false;
2516}
2517
2518
2519/**
2520 * Checks if the stack selector (SS) is suitable for execution
2521 * within VMX when unrestricted execution isn't available.
2522 *
2523 * @returns true if selector is suitable for VMX, otherwise
2524 * false.
2525 * @param pSel Pointer to the selector to check (SS).
2526 */
2527static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2528{
2529 /*
2530 * Unusable segments are OK. These days they should be marked as such, as
2531 * but as an alternative we for old saved states and AMD<->VT-x migration
2532 * we also treat segments with all the attributes cleared as unusable.
2533 */
2534 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2535 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2536 return true;
2537
2538 /*
2539 * Segment must be an accessed writable segment, it must be present.
2540 * Note! These are all standard requirements and if SS holds anything else
2541 * we've got buggy code somewhere!
2542 */
2543 AssertCompile(X86DESCATTR_TYPE == 0xf);
2544 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2545 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2546 ("%#x\n", pSel->Attr.u),
2547 false);
2548
2549 /* DPL must equal RPL.
2550 Note! This is also a hard requirement like above. */
2551 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2552 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2553 false);
2554
2555 /*
2556 * The following two requirements are VT-x specific:
2557 * - G bit must be set if any high limit bits are set.
2558 * - G bit must be clear if any low limit bits are clear.
2559 */
2560 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2561 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2562 return true;
2563 return false;
2564}
2565
2566
2567/**
2568 * Force execution of the current IO code in the recompiler.
2569 *
2570 * @returns VBox status code.
2571 * @param pVM The cross context VM structure.
2572 * @param pCtx Partial VM execution context.
2573 */
2574VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2575{
2576 PVMCPU pVCpu = VMMGetCpu(pVM);
2577
2578 Assert(HMIsEnabled(pVM));
2579 Log(("HMR3EmulateIoBlock\n"));
2580
2581 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2582 if (HMCanEmulateIoBlockEx(pCtx))
2583 {
2584 Log(("HMR3EmulateIoBlock -> enabled\n"));
2585 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2586 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2587 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2588 return VINF_EM_RESCHEDULE_REM;
2589 }
2590 return VINF_SUCCESS;
2591}
2592
2593
2594/**
2595 * Checks if we can currently use hardware accelerated raw mode.
2596 *
2597 * @returns true if we can currently use hardware acceleration, otherwise false.
2598 * @param pVM The cross context VM structure.
2599 * @param pCtx Partial VM execution context.
2600 */
2601VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2602{
2603 PVMCPU pVCpu = VMMGetCpu(pVM);
2604
2605 Assert(HMIsEnabled(pVM));
2606
2607 /* If we're still executing the IO code, then return false. */
2608 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2609 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2610 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2611 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2612 return false;
2613
2614 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2615
2616 /* AMD-V supports real & protected mode with or without paging. */
2617 if (pVM->hm.s.svm.fEnabled)
2618 {
2619 pVCpu->hm.s.fActive = true;
2620 return true;
2621 }
2622
2623 pVCpu->hm.s.fActive = false;
2624
2625 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2626 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2627 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2628
2629 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2630 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2631 {
2632 /*
2633 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2634 * guest execution feature is missing (VT-x only).
2635 */
2636 if (fSupportsRealMode)
2637 {
2638 if (CPUMIsGuestInRealModeEx(pCtx))
2639 {
2640 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2641 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2642 * If this is not true, we cannot execute real mode as V86 and have to fall
2643 * back to emulation.
2644 */
2645 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2646 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2647 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2648 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2649 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2650 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2651 {
2652 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2653 return false;
2654 }
2655 if ( (pCtx->cs.u32Limit != 0xffff)
2656 || (pCtx->ds.u32Limit != 0xffff)
2657 || (pCtx->es.u32Limit != 0xffff)
2658 || (pCtx->ss.u32Limit != 0xffff)
2659 || (pCtx->fs.u32Limit != 0xffff)
2660 || (pCtx->gs.u32Limit != 0xffff))
2661 {
2662 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2663 return false;
2664 }
2665 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2666 }
2667 else
2668 {
2669 /* Verify the requirements for executing code in protected
2670 mode. VT-x can't handle the CPU state right after a switch
2671 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2672 if (pVCpu->hm.s.vmx.fWasInRealMode)
2673 {
2674 /** @todo If guest is in V86 mode, these checks should be different! */
2675 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2676 {
2677 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2678 return false;
2679 }
2680 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2681 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2682 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2683 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2684 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2685 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2686 {
2687 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2688 return false;
2689 }
2690 }
2691 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2692 if (pCtx->gdtr.cbGdt)
2693 {
2694 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2695 {
2696 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2697 return false;
2698 }
2699 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2700 {
2701 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2702 return false;
2703 }
2704 }
2705 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2706 }
2707 }
2708 else
2709 {
2710 if ( !CPUMIsGuestInLongModeEx(pCtx)
2711 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2712 {
2713 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2714 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2715 return false;
2716
2717 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2718 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2719 return false;
2720
2721 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2722 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2723 * hidden registers (possible recompiler bug; see load_seg_vm) */
2724 if (pCtx->cs.Attr.n.u1Present == 0)
2725 return false;
2726 if (pCtx->ss.Attr.n.u1Present == 0)
2727 return false;
2728
2729 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2730 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2731 /** @todo This check is actually wrong, it doesn't take the direction of the
2732 * stack segment into account. But, it does the job for now. */
2733 if (pCtx->rsp >= pCtx->ss.u32Limit)
2734 return false;
2735 }
2736 }
2737 }
2738
2739 if (pVM->hm.s.vmx.fEnabled)
2740 {
2741 uint32_t mask;
2742
2743 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2744 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2745 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2746 mask &= ~X86_CR0_NE;
2747
2748 if (fSupportsRealMode)
2749 {
2750 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2751 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2752 }
2753 else
2754 {
2755 /* We support protected mode without paging using identity mapping. */
2756 mask &= ~X86_CR0_PG;
2757 }
2758 if ((pCtx->cr0 & mask) != mask)
2759 return false;
2760
2761 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2762 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2763 if ((pCtx->cr0 & mask) != 0)
2764 return false;
2765
2766 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2767 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2768 mask &= ~X86_CR4_VMXE;
2769 if ((pCtx->cr4 & mask) != mask)
2770 return false;
2771
2772 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2773 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2774 if ((pCtx->cr4 & mask) != 0)
2775 return false;
2776
2777 pVCpu->hm.s.fActive = true;
2778 return true;
2779 }
2780
2781 return false;
2782}
2783
2784
2785/**
2786 * Checks if we need to reschedule due to VMM device heap changes.
2787 *
2788 * @returns true if a reschedule is required, otherwise false.
2789 * @param pVM The cross context VM structure.
2790 * @param pCtx VM execution context.
2791 */
2792VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2793{
2794 /*
2795 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2796 * when the unrestricted guest execution feature is missing (VT-x only).
2797 */
2798 if ( pVM->hm.s.vmx.fEnabled
2799 && !pVM->hm.s.vmx.fUnrestrictedGuest
2800 && CPUMIsGuestInRealModeEx(pCtx)
2801 && !PDMVmmDevHeapIsEnabled(pVM))
2802 {
2803 return true;
2804 }
2805
2806 return false;
2807}
2808
2809
2810/**
2811 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2812 * event settings changes.
2813 *
2814 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2815 * function is just updating the VM globals.
2816 *
2817 * @param pVM The VM cross context VM structure.
2818 * @thread EMT(0)
2819 */
2820VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2821{
2822 /* Interrupts. */
2823 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2824 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2825
2826 /* CPU Exceptions. */
2827 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2828 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2829 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2830 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2831
2832 /* Common VM exits. */
2833 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2834 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2835 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2836 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2837
2838 /* Vendor specific VM exits. */
2839 if (HMR3IsVmxEnabled(pVM->pUVM))
2840 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2841 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2842 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2843 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2844 else
2845 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2846 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2847 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2848 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2849
2850 /* Done. */
2851 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2852}
2853
2854
2855/**
2856 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2857 *
2858 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2859 * per CPU settings.
2860 *
2861 * @param pVM The VM cross context VM structure.
2862 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2863 */
2864VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2865{
2866 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2867}
2868
2869
2870/**
2871 * Notification from EM about a rescheduling into hardware assisted execution
2872 * mode.
2873 *
2874 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2875 */
2876VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2877{
2878 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2879}
2880
2881
2882/**
2883 * Notification from EM about returning from instruction emulation (REM / EM).
2884 *
2885 * @param pVCpu The cross context virtual CPU structure.
2886 */
2887VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2888{
2889 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2890}
2891
2892
2893/**
2894 * Checks if we are currently using hardware acceleration.
2895 *
2896 * @returns true if hardware acceleration is being used, otherwise false.
2897 * @param pVCpu The cross context virtual CPU structure.
2898 */
2899VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2900{
2901 return pVCpu->hm.s.fActive;
2902}
2903
2904
2905/**
2906 * External interface for querying whether hardware acceleration is enabled.
2907 *
2908 * @returns true if VT-x or AMD-V is being used, otherwise false.
2909 * @param pUVM The user mode VM handle.
2910 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2911 */
2912VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2913{
2914 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2915 PVM pVM = pUVM->pVM;
2916 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2917 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2918}
2919
2920
2921/**
2922 * External interface for querying whether VT-x is being used.
2923 *
2924 * @returns true if VT-x is being used, otherwise false.
2925 * @param pUVM The user mode VM handle.
2926 * @sa HMR3IsSvmEnabled, HMIsEnabled
2927 */
2928VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2929{
2930 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2931 PVM pVM = pUVM->pVM;
2932 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2933 return pVM->hm.s.vmx.fEnabled
2934 && pVM->hm.s.vmx.fSupported
2935 && pVM->fHMEnabled;
2936}
2937
2938
2939/**
2940 * External interface for querying whether AMD-V is being used.
2941 *
2942 * @returns true if VT-x is being used, otherwise false.
2943 * @param pUVM The user mode VM handle.
2944 * @sa HMR3IsVmxEnabled, HMIsEnabled
2945 */
2946VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2947{
2948 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2949 PVM pVM = pUVM->pVM;
2950 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2951 return pVM->hm.s.svm.fEnabled
2952 && pVM->hm.s.svm.fSupported
2953 && pVM->fHMEnabled;
2954}
2955
2956
2957/**
2958 * Checks if we are currently using nested paging.
2959 *
2960 * @returns true if nested paging is being used, otherwise false.
2961 * @param pUVM The user mode VM handle.
2962 */
2963VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2964{
2965 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2966 PVM pVM = pUVM->pVM;
2967 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2968 return pVM->hm.s.fNestedPaging;
2969}
2970
2971
2972/**
2973 * Checks if virtualized APIC registers is enabled.
2974 *
2975 * When enabled this feature allows the hardware to access most of the
2976 * APIC registers in the virtual-APIC page without causing VM-exits. See
2977 * Intel spec. 29.1.1 "Virtualized APIC Registers".
2978 *
2979 * @returns true if virtualized APIC registers is enabled, otherwise
2980 * false.
2981 * @param pUVM The user mode VM handle.
2982 */
2983VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2984{
2985 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2986 PVM pVM = pUVM->pVM;
2987 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2988 return pVM->hm.s.fVirtApicRegs;
2989}
2990
2991
2992/**
2993 * Checks if APIC posted-interrupt processing is enabled.
2994 *
2995 * This returns whether we can deliver interrupts to the guest without
2996 * leaving guest-context by updating APIC state from host-context.
2997 *
2998 * @returns true if APIC posted-interrupt processing is enabled,
2999 * otherwise false.
3000 * @param pUVM The user mode VM handle.
3001 */
3002VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3003{
3004 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3005 PVM pVM = pUVM->pVM;
3006 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3007 return pVM->hm.s.fPostedIntrs;
3008}
3009
3010
3011/**
3012 * Checks if we are currently using VPID in VT-x mode.
3013 *
3014 * @returns true if VPID is being used, otherwise false.
3015 * @param pUVM The user mode VM handle.
3016 */
3017VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3018{
3019 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3020 PVM pVM = pUVM->pVM;
3021 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3022 return pVM->hm.s.vmx.fVpid;
3023}
3024
3025
3026/**
3027 * Checks if we are currently using VT-x unrestricted execution,
3028 * aka UX.
3029 *
3030 * @returns true if UX is being used, otherwise false.
3031 * @param pUVM The user mode VM handle.
3032 */
3033VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3034{
3035 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3036 PVM pVM = pUVM->pVM;
3037 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3038 return pVM->hm.s.vmx.fUnrestrictedGuest;
3039}
3040
3041
3042/**
3043 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3044 *
3045 * @returns true if an internal event is pending, otherwise false.
3046 * @param pVCpu The cross context virtual CPU structure.
3047 */
3048VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3049{
3050 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3051}
3052
3053
3054/**
3055 * Checks if the VMX-preemption timer is being used.
3056 *
3057 * @returns true if the VMX-preemption timer is being used, otherwise false.
3058 * @param pVM The cross context VM structure.
3059 */
3060VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3061{
3062 return HMIsEnabled(pVM)
3063 && pVM->hm.s.vmx.fEnabled
3064 && pVM->hm.s.vmx.fUsePreemptTimer;
3065}
3066
3067
3068/**
3069 * Restart an I/O instruction that was refused in ring-0
3070 *
3071 * @returns Strict VBox status code. Informational status codes other than the one documented
3072 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3073 * @retval VINF_SUCCESS Success.
3074 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3075 * status code must be passed on to EM.
3076 * @retval VERR_NOT_FOUND if no pending I/O instruction.
3077 *
3078 * @param pVM The cross context VM structure.
3079 * @param pVCpu The cross context virtual CPU structure.
3080 * @param pCtx Pointer to the guest CPU context.
3081 */
3082VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3083{
3084 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3085
3086 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3087
3088 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
3089 || enmType == HMPENDINGIO_INVALID)
3090 return VERR_NOT_FOUND;
3091
3092 VBOXSTRICTRC rcStrict;
3093 switch (enmType)
3094 {
3095 case HMPENDINGIO_PORT_READ:
3096 {
3097 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3098 uint32_t u32Val = 0;
3099
3100 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3101 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3102 if (IOM_SUCCESS(rcStrict))
3103 {
3104 /* Write back to the EAX register. */
3105 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3106 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3107 }
3108 break;
3109 }
3110
3111 case HMPENDINGIO_PORT_WRITE:
3112 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
3113 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
3114 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3115 if (IOM_SUCCESS(rcStrict))
3116 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3117 break;
3118
3119 default:
3120 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3121 }
3122
3123 if (IOM_SUCCESS(rcStrict))
3124 {
3125 /*
3126 * Check for I/O breakpoints.
3127 */
3128 uint32_t const uDr7 = pCtx->dr[7];
3129 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3130 && X86_DR7_ANY_RW_IO(uDr7)
3131 && (pCtx->cr4 & X86_CR4_DE))
3132 || DBGFBpIsHwIoArmed(pVM))
3133 {
3134 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3135 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3136 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3137 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3138 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3139 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
3140 rcStrict = rcStrict2;
3141 }
3142 }
3143 return rcStrict;
3144}
3145
3146
3147/**
3148 * Check fatal VT-x/AMD-V error and produce some meaningful
3149 * log release message.
3150 *
3151 * @param pVM The cross context VM structure.
3152 * @param iStatusCode VBox status code.
3153 */
3154VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3155{
3156 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3157 {
3158 PVMCPU pVCpu = &pVM->aCpus[i];
3159 switch (iStatusCode)
3160 {
3161 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3162 * might be getting inaccurate values for non-guru'ing EMTs. */
3163 case VERR_VMX_INVALID_VMCS_FIELD:
3164 break;
3165
3166 case VERR_VMX_INVALID_VMCS_PTR:
3167 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3168 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3169 pVCpu->hm.s.vmx.HCPhysVmcs));
3170 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3171 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3172 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3173 break;
3174
3175 case VERR_VMX_UNABLE_TO_START_VM:
3176 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3177 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3178 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3179
3180 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3181 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3182 {
3183 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3184 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3185 }
3186 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3187 {
3188 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3189 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3190 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3191 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3192 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3193 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3194 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3195 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3196 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3197 }
3198 /** @todo Log VM-entry event injection control fields
3199 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3200 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3201 break;
3202
3203 case VERR_VMX_INVALID_VMXON_PTR:
3204 break;
3205
3206 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3207 case VERR_VMX_INVALID_GUEST_STATE:
3208 case VERR_VMX_UNEXPECTED_EXIT:
3209 case VERR_SVM_UNKNOWN_EXIT:
3210 case VERR_SVM_UNEXPECTED_EXIT:
3211 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3212 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3213 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3214 {
3215 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
3216 LogRel(("HM: CPU[%u] idxExitHistoryFree %u\n", i, pVCpu->hm.s.idxExitHistoryFree));
3217 unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
3218 pVCpu->hm.s.idxExitHistoryFree - 1 :
3219 RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
3220 for (unsigned k = 0; k < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); k++)
3221 {
3222 LogRel(("HM: CPU[%u] auExitHistory[%2u] = %#x (%u) %s\n", i, k, pVCpu->hm.s.auExitHistory[k],
3223 pVCpu->hm.s.auExitHistory[k], idxLast == k ? "<-- Last" : ""));
3224 }
3225 break;
3226 }
3227 }
3228 }
3229
3230 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3231 {
3232 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3233 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3234 }
3235 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3236 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3237}
3238
3239
3240/**
3241 * Execute state save operation.
3242 *
3243 * @returns VBox status code.
3244 * @param pVM The cross context VM structure.
3245 * @param pSSM SSM operation handle.
3246 */
3247static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3248{
3249 int rc;
3250
3251 Log(("hmR3Save:\n"));
3252
3253 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3254 {
3255 /*
3256 * Save the basic bits - fortunately all the other things can be resynced on load.
3257 */
3258 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3259 AssertRCReturn(rc, rc);
3260 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3261 AssertRCReturn(rc, rc);
3262 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
3263 AssertRCReturn(rc, rc);
3264 /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
3265
3266 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3267 * perhaps not even that (the initial value of @c true is safe. */
3268 uint32_t u32Dummy = PGMMODE_REAL;
3269 rc = SSMR3PutU32(pSSM, u32Dummy);
3270 AssertRCReturn(rc, rc);
3271 rc = SSMR3PutU32(pSSM, u32Dummy);
3272 AssertRCReturn(rc, rc);
3273 rc = SSMR3PutU32(pSSM, u32Dummy);
3274 AssertRCReturn(rc, rc);
3275 }
3276
3277#ifdef VBOX_HM_WITH_GUEST_PATCHING
3278 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3279 AssertRCReturn(rc, rc);
3280 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3281 AssertRCReturn(rc, rc);
3282 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3283 AssertRCReturn(rc, rc);
3284
3285 /* Store all the guest patch records too. */
3286 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3287 AssertRCReturn(rc, rc);
3288
3289 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3290 {
3291 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3292
3293 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3294 AssertRCReturn(rc, rc);
3295
3296 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3297 AssertRCReturn(rc, rc);
3298
3299 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3300 AssertRCReturn(rc, rc);
3301
3302 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3303 AssertRCReturn(rc, rc);
3304
3305 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3306 AssertRCReturn(rc, rc);
3307
3308 AssertCompileSize(HMTPRINSTR, 4);
3309 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3310 AssertRCReturn(rc, rc);
3311
3312 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3313 AssertRCReturn(rc, rc);
3314
3315 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3316 AssertRCReturn(rc, rc);
3317
3318 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3319 AssertRCReturn(rc, rc);
3320
3321 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3322 AssertRCReturn(rc, rc);
3323 }
3324#endif
3325 return VINF_SUCCESS;
3326}
3327
3328
3329/**
3330 * Execute state load operation.
3331 *
3332 * @returns VBox status code.
3333 * @param pVM The cross context VM structure.
3334 * @param pSSM SSM operation handle.
3335 * @param uVersion Data layout version.
3336 * @param uPass The data pass.
3337 */
3338static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3339{
3340 int rc;
3341
3342 Log(("hmR3Load:\n"));
3343 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3344
3345 /*
3346 * Validate version.
3347 */
3348 if ( uVersion != HM_SAVED_STATE_VERSION
3349 && uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3350 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3351 {
3352 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3353 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3354 }
3355 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3356 {
3357 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3358 AssertRCReturn(rc, rc);
3359 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3360 AssertRCReturn(rc, rc);
3361 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3362 AssertRCReturn(rc, rc);
3363
3364 if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3365 {
3366 uint32_t val;
3367 /** @todo See note in hmR3Save(). */
3368 rc = SSMR3GetU32(pSSM, &val);
3369 AssertRCReturn(rc, rc);
3370 rc = SSMR3GetU32(pSSM, &val);
3371 AssertRCReturn(rc, rc);
3372 rc = SSMR3GetU32(pSSM, &val);
3373 AssertRCReturn(rc, rc);
3374 }
3375 }
3376#ifdef VBOX_HM_WITH_GUEST_PATCHING
3377 if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3378 {
3379 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3380 AssertRCReturn(rc, rc);
3381 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3382 AssertRCReturn(rc, rc);
3383 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3384 AssertRCReturn(rc, rc);
3385
3386 /* Fetch all TPR patch records. */
3387 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3388 AssertRCReturn(rc, rc);
3389
3390 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3391 {
3392 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3393
3394 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3395 AssertRCReturn(rc, rc);
3396
3397 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3398 AssertRCReturn(rc, rc);
3399
3400 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3401 AssertRCReturn(rc, rc);
3402
3403 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3404 AssertRCReturn(rc, rc);
3405
3406 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3407 AssertRCReturn(rc, rc);
3408
3409 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3410 AssertRCReturn(rc, rc);
3411
3412 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3413 pVM->hm.s.fTPRPatchingActive = true;
3414
3415 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3416
3417 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3418 AssertRCReturn(rc, rc);
3419
3420 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3421 AssertRCReturn(rc, rc);
3422
3423 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3424 AssertRCReturn(rc, rc);
3425
3426 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3427 AssertRCReturn(rc, rc);
3428
3429 Log(("hmR3Load: patch %d\n", i));
3430 Log(("Key = %x\n", pPatch->Core.Key));
3431 Log(("cbOp = %d\n", pPatch->cbOp));
3432 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3433 Log(("type = %d\n", pPatch->enmType));
3434 Log(("srcop = %d\n", pPatch->uSrcOperand));
3435 Log(("dstop = %d\n", pPatch->uDstOperand));
3436 Log(("cFaults = %d\n", pPatch->cFaults));
3437 Log(("target = %x\n", pPatch->pJumpTarget));
3438 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3439 AssertRC(rc);
3440 }
3441 }
3442#endif
3443
3444 return VINF_SUCCESS;
3445}
3446
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