VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 71522

Last change on this file since 71522 was 71415, checked in by vboxsync, 7 years ago

VMM/HM: Get rid of lazy FPU loading for AMD-V. Nested Hw.virt: Fix FPU related issues while executing nested-KVM DSL guests.
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File size: 168.8 KB
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1/* $Id: HM.cpp 71415 2018-03-21 09:29:22Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#include <VBox/vmm/cpum.h>
41#include <VBox/vmm/stam.h>
42#include <VBox/vmm/mm.h>
43#include <VBox/vmm/pdmapi.h>
44#include <VBox/vmm/pgm.h>
45#include <VBox/vmm/ssm.h>
46#include <VBox/vmm/trpm.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/iom.h>
49#include <VBox/vmm/iem.h>
50#include <VBox/vmm/patm.h>
51#include <VBox/vmm/csam.h>
52#include <VBox/vmm/selm.h>
53#include <VBox/vmm/nem.h>
54#ifdef VBOX_WITH_REM
55# include <VBox/vmm/rem.h>
56#endif
57#include <VBox/vmm/hm_vmx.h>
58#include <VBox/vmm/hm_svm.h>
59#include "HMInternal.h"
60#include <VBox/vmm/vm.h>
61#include <VBox/vmm/uvm.h>
62#include <VBox/err.h>
63#include <VBox/param.h>
64
65#include <iprt/assert.h>
66#include <VBox/log.h>
67#include <iprt/asm.h>
68#include <iprt/asm-amd64-x86.h>
69#include <iprt/env.h>
70#include <iprt/thread.h>
71
72
73/*********************************************************************************************************************************
74* Global Variables *
75*********************************************************************************************************************************/
76#define EXIT_REASON(def, val, str) #def " - " #val " - " str
77#define EXIT_REASON_NIL() NULL
78/** Exit reason descriptions for VT-x, used to describe statistics. */
79static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
80{
81 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
82 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
83 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
84 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
85 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
86 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
87 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
88 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
89 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
90 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
91 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
92 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
93 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
94 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
95 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
96 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
97 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
98 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
99 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
100 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
101 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
102 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
103 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
104 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
105 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
106 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
107 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
108 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
109 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
110 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
111 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
112 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
113 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
114 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
115 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
116 EXIT_REASON_NIL(),
117 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
118 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
119 EXIT_REASON_NIL(),
120 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
121 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
122 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
123 EXIT_REASON_NIL(),
124 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
125 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
126 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
127 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
128 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
129 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
130 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
131 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
132 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
133 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
134 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
135 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
136 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
137 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
138 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
139 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
140 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
141 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instrunction."),
142 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
143 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
144 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
145 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
146};
147/** Array index of the last valid VT-x exit reason. */
148#define MAX_EXITREASON_VTX 64
149
150/** A partial list of Exit reason descriptions for AMD-V, used to describe
151 * statistics.
152 *
153 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
154 * this array doesn't contain the entire set of exit reasons, we
155 * handle them via hmSvmGetSpecialExitReasonDesc(). */
156static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
157{
158 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
159 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
160 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
161 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
162 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
163 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
164 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
165 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
166 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
167 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
168 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
169 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
170 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
171 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
172 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
173 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
174 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
187 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
188 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
189 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
190 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
191 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
192 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
193 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
194 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
195 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
196 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
197 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
198 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
199 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
200 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
201 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
202 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
203 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
204 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
205 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
206 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
219 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
220 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
221 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
233 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
234 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
235 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
236 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
237 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
238 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
239 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
240 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
241 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
242 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
243 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
244 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
245 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
246 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
247 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
248 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
249 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
250 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
251 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
252 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
253 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
254 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
255 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
256 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
257 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
258 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
259 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
260 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR"),
261 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR"),
262 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
263 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
264 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
265 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
266 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
267 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
268 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
269 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
270 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
271 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
272 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
273 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
274 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
275 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
276 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
277 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
278 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
279 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
280 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
281 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT accessing protected port."),
282 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
283 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
284 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
285 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
286 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
287 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
288 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
289 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
290 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
291 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
292 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
293 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
294 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
295 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
296 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
297 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
298 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
299 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
300};
301/** Array index of the last valid AMD-V exit reason. */
302#define MAX_EXITREASON_AMDV 141
303
304/** Special exit reasons not covered in the array above. */
305#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
306#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
307#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
308
309/**
310 * Gets the SVM exit reason if it's one of the reasons not present in the @c
311 * g_apszAmdVExitReasons array.
312 *
313 * @returns The exit reason or NULL if unknown.
314 * @param uExit The exit.
315 */
316DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
317{
318 switch (uExit)
319 {
320 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
321 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
322 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
323 }
324 return EXIT_REASON_NIL();
325}
326#undef EXIT_REASON_NIL
327#undef EXIT_REASON
328
329/** @def HMVMX_REPORT_FEATURE
330 * Reports VT-x feature to the release log.
331 *
332 * @param allowed1 Mask of allowed feature bits.
333 * @param disallowed0 Mask of disallowed feature bits.
334 * @param strdesc The description string to report.
335 * @param featflag Mask of the feature to report.
336 */
337#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
338 do { \
339 if ((allowed1) & (featflag)) \
340 { \
341 if ((disallowed0) & (featflag)) \
342 LogRel(("HM: " strdesc " (must be set)\n")); \
343 else \
344 LogRel(("HM: " strdesc "\n")); \
345 } \
346 else \
347 LogRel(("HM: " strdesc " (must be cleared)\n")); \
348 } while (0)
349
350/** @def HMVMX_REPORT_ALLOWED_FEATURE
351 * Reports an allowed VT-x feature to the release log.
352 *
353 * @param allowed1 Mask of allowed feature bits.
354 * @param strdesc The description string to report.
355 * @param featflag Mask of the feature to report.
356 */
357#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
358 do { \
359 if ((allowed1) & (featflag)) \
360 LogRel(("HM: " strdesc "\n")); \
361 else \
362 LogRel(("HM: " strdesc " not supported\n")); \
363 } while (0)
364
365/** @def HMVMX_REPORT_MSR_CAPABILITY
366 * Reports MSR feature capability.
367 *
368 * @param msrcaps Mask of MSR feature bits.
369 * @param strdesc The description string to report.
370 * @param cap Mask of the feature to report.
371 */
372#define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
373 do { \
374 if ((msrcaps) & (cap)) \
375 LogRel(("HM: " strdesc "\n")); \
376 } while (0)
377
378
379/*********************************************************************************************************************************
380* Internal Functions *
381*********************************************************************************************************************************/
382static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
383static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
384static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
385static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
386static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
387static int hmR3InitCPU(PVM pVM);
388static int hmR3InitFinalizeR0(PVM pVM);
389static int hmR3InitFinalizeR0Intel(PVM pVM);
390static int hmR3InitFinalizeR0Amd(PVM pVM);
391static int hmR3TermCPU(PVM pVM);
392
393
394
395/**
396 * Initializes the HM.
397 *
398 * This is the very first component to really do init after CFGM so that we can
399 * establish the predominat execution engine for the VM prior to initializing
400 * other modules. It takes care of NEM initialization if needed (HM disabled or
401 * not available in HW).
402 *
403 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
404 * hypervisor API via NEM, and then back on raw-mode if that isn't available
405 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
406 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
407 * X, OS/2 and others).
408 *
409 * Note that a lot of the set up work is done in ring-0 and thus postponed till
410 * the ring-3 and ring-0 callback to HMR3InitCompleted.
411 *
412 * @returns VBox status code.
413 * @param pVM The cross context VM structure.
414 *
415 * @remarks Be careful with what we call here, since most of the VMM components
416 * are uninitialized.
417 */
418VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
419{
420 LogFlow(("HMR3Init\n"));
421
422 /*
423 * Assert alignment and sizes.
424 */
425 AssertCompileMemberAlignment(VM, hm.s, 32);
426 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
427
428 /*
429 * Register the saved state data unit.
430 */
431 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
432 NULL, NULL, NULL,
433 NULL, hmR3Save, NULL,
434 NULL, hmR3Load, NULL);
435 if (RT_FAILURE(rc))
436 return rc;
437
438 /*
439 * Register info handlers.
440 */
441 rc = DBGFR3InfoRegisterInternalEx(pVM, "exithistory", "Dumps the HM VM-exit history.", hmR3InfoExitHistory,
442 DBGFINFO_FLAGS_ALL_EMTS);
443 AssertRCReturn(rc, rc);
444
445 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
446 DBGFINFO_FLAGS_ALL_EMTS);
447 AssertRCReturn(rc, rc);
448
449 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
450 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
451 AssertRCReturn(rc, rc);
452
453 /*
454 * Read configuration.
455 */
456 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
457
458 /*
459 * Validate the HM settings.
460 */
461 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
462 "HMForced"
463 "|UseNEMInstead"
464 "|FallbackToNEM"
465 "|EnableNestedPaging"
466 "|EnableUX"
467 "|EnableLargePages"
468 "|EnableVPID"
469 "|IBPBOnVMExit"
470 "|IBPBOnVMEntry"
471 "|SpecCtrlByHost"
472 "|TPRPatchingEnabled"
473 "|64bitEnabled"
474 "|Exclusive"
475 "|MaxResumeLoops"
476 "|VmxPleGap"
477 "|VmxPleWindow"
478 "|UseVmxPreemptTimer"
479 "|SvmPauseFilter"
480 "|SvmPauseFilterThreshold"
481 "|SvmVirtVmsaveVmload"
482 "|SvmVGif",
483 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
484 if (RT_FAILURE(rc))
485 return rc;
486
487 /** @cfgm{/HM/HMForced, bool, false}
488 * Forces hardware virtualization, no falling back on raw-mode. HM must be
489 * enabled, i.e. /HMEnabled must be true. */
490 bool fHMForced;
491#ifdef VBOX_WITH_RAW_MODE
492 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
493 AssertRCReturn(rc, rc);
494 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
495 VERR_INVALID_PARAMETER);
496# if defined(RT_OS_DARWIN)
497 if (pVM->fHMEnabled)
498 fHMForced = true;
499# endif
500 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
501 VERR_INVALID_PARAMETER);
502 if (pVM->cCpus > 1)
503 fHMForced = true;
504#else /* !VBOX_WITH_RAW_MODE */
505 AssertRelease(pVM->fHMEnabled);
506 fHMForced = true;
507#endif /* !VBOX_WITH_RAW_MODE */
508
509 /** @cfgm{/HM/UseNEMInstead, bool, true}
510 * Don't use HM, use NEM instead. */
511 bool fUseNEMInstead = false;
512 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
513 AssertRCReturn(rc, rc);
514 if (fUseNEMInstead && pVM->fHMEnabled)
515 {
516 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
517 pVM->fHMEnabled = false;
518 }
519
520 /** @cfgm{/HM/FallbackToNEM, bool, true}
521 * Enables fallback on NEM. */
522 bool fFallbackToNEM = true;
523 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
524 AssertRCReturn(rc, rc);
525
526 /** @cfgm{/HM/EnableNestedPaging, bool, false}
527 * Enables nested paging (aka extended page tables). */
528 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
529 AssertRCReturn(rc, rc);
530
531 /** @cfgm{/HM/EnableUX, bool, true}
532 * Enables the VT-x unrestricted execution feature. */
533 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
534 AssertRCReturn(rc, rc);
535
536 /** @cfgm{/HM/EnableLargePages, bool, false}
537 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
538 * page table walking and maybe better TLB hit rate in some cases. */
539 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
540 AssertRCReturn(rc, rc);
541
542 /** @cfgm{/HM/EnableVPID, bool, false}
543 * Enables the VT-x VPID feature. */
544 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
545 AssertRCReturn(rc, rc);
546
547 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
548 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
549 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
550 AssertRCReturn(rc, rc);
551
552 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
553 * Enables AMD64 cpu features.
554 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
555 * already have the support. */
556#ifdef VBOX_ENABLE_64_BITS_GUESTS
557 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
558 AssertLogRelRCReturn(rc, rc);
559#else
560 pVM->hm.s.fAllow64BitGuests = false;
561#endif
562
563 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
564 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
565 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
566 * latest PAUSE instruction to be start of a new PAUSE loop.
567 */
568 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
569 AssertRCReturn(rc, rc);
570
571 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
572 * The pause-filter exiting window in TSC ticks. When the number of ticks
573 * between the current PAUSE instruction and first PAUSE of a loop exceeds
574 * VmxPleWindow, a VM-exit is triggered.
575 *
576 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
577 */
578 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
579 AssertRCReturn(rc, rc);
580
581 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
582 * A counter that is decrement each time a PAUSE instruction is executed by the
583 * guest. When the counter is 0, a \#VMEXIT is triggered.
584 */
585 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
586 AssertRCReturn(rc, rc);
587
588 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
589 * The pause filter threshold in ticks. When the elapsed time between two
590 * successive PAUSE instructions exceeds SvmPauseFilterThreshold, the PauseFilter
591 * count is reset to its initial value. However, if PAUSE is executed PauseFilter
592 * times within PauseFilterThreshold ticks, a VM-exit will be triggered.
593 *
594 * Setting both SvmPauseFilterCount and SvmPauseFilterCount to 0 disables
595 * pause-filter exiting.
596 */
597 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
598 AssertRCReturn(rc, rc);
599
600 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
601 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
602 * available. */
603 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
604 AssertRCReturn(rc, rc);
605
606 /** @cfgm{/HM/SvmVGif, bool, true}
607 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
608 * if it's available. */
609 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
610 AssertRCReturn(rc, rc);
611
612 /** @cfgm{/HM/Exclusive, bool}
613 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
614 * global init for each host CPU. If false, we do local init each time we wish
615 * to execute guest code.
616 *
617 * On Windows, default is false due to the higher risk of conflicts with other
618 * hypervisors.
619 *
620 * On Mac OS X, this setting is ignored since the code does not handle local
621 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
622 */
623#if defined(RT_OS_DARWIN)
624 pVM->hm.s.fGlobalInit = true;
625#else
626 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
627# if defined(RT_OS_WINDOWS)
628 false
629# else
630 true
631# endif
632 );
633 AssertLogRelRCReturn(rc, rc);
634#endif
635
636 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
637 * The number of times to resume guest execution before we forcibly return to
638 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
639 * determines the default value. */
640 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
641 AssertLogRelRCReturn(rc, rc);
642
643 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
644 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
645 * available. */
646 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
647 AssertLogRelRCReturn(rc, rc);
648
649 /** @cfgm{/HM/IBPBOnVMExit, bool}
650 * Costly paranoia setting. */
651 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
652 AssertLogRelRCReturn(rc, rc);
653
654 /** @cfgm{/HM/IBPBOnVMEntry, bool}
655 * Costly paranoia setting. */
656 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
657 AssertLogRelRCReturn(rc, rc);
658
659 /** @cfgm{/HM/SpecCtrlByHost, bool}
660 * Another expensive paranoia setting. */
661 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
662 AssertLogRelRCReturn(rc, rc);
663
664 /*
665 * Check if VT-x or AMD-v support according to the users wishes.
666 */
667 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
668 * VERR_SVM_IN_USE. */
669 if (pVM->fHMEnabled)
670 {
671 uint32_t fCaps;
672 rc = SUPR3QueryVTCaps(&fCaps);
673 if (RT_SUCCESS(rc))
674 {
675 if (fCaps & SUPVTCAPS_AMD_V)
676 {
677 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
678 pVM->hm.s.svm.fSupported = true;
679 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
680 }
681 else if (fCaps & SUPVTCAPS_VT_X)
682 {
683 const char *pszWhy;
684 rc = SUPR3QueryVTxSupported(&pszWhy);
685 if (RT_SUCCESS(rc))
686 {
687 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
688 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
689 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
690 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
691 pVM->hm.s.vmx.fSupported = true;
692 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
693 }
694 else
695 {
696 /*
697 * Before failing, try fallback to NEM if we're allowed to do that.
698 */
699 pVM->fHMEnabled = false;
700 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
701 if (fFallbackToNEM)
702 {
703 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
704 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
705
706 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
707 if ( RT_SUCCESS(rc2)
708 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
709 rc = VINF_SUCCESS;
710 }
711 if (RT_FAILURE(rc))
712 {
713 if (fHMForced)
714 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
715
716 /* Fall back to raw-mode. */
717 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
718 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
719 }
720 }
721 }
722 else
723 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
724 VERR_INTERNAL_ERROR_5);
725
726 /*
727 * Do we require a little bit or raw-mode for 64-bit guest execution?
728 */
729 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
730 && pVM->fHMEnabled
731 && pVM->hm.s.fAllow64BitGuests;
732
733 /*
734 * Disable nested paging and unrestricted guest execution now if they're
735 * configured so that CPUM can make decisions based on our configuration.
736 */
737 Assert(!pVM->hm.s.fNestedPaging);
738 if (pVM->hm.s.fAllowNestedPaging)
739 {
740 if (fCaps & SUPVTCAPS_NESTED_PAGING)
741 pVM->hm.s.fNestedPaging = true;
742 else
743 pVM->hm.s.fAllowNestedPaging = false;
744 }
745
746 if (fCaps & SUPVTCAPS_VT_X)
747 {
748 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
749 if (pVM->hm.s.vmx.fAllowUnrestricted)
750 {
751 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
752 && pVM->hm.s.fNestedPaging)
753 pVM->hm.s.vmx.fUnrestrictedGuest = true;
754 else
755 pVM->hm.s.vmx.fAllowUnrestricted = false;
756 }
757 }
758 }
759 else
760 {
761 const char *pszMsg;
762 switch (rc)
763 {
764 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
765 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
766 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
767 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
768 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
769 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
770 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
771 default:
772 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
773 }
774
775 /*
776 * Before failing, try fallback to NEM if we're allowed to do that.
777 */
778 pVM->fHMEnabled = false;
779 if (fFallbackToNEM)
780 {
781 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
782 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
783 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
784 if ( RT_SUCCESS(rc2)
785 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
786 rc = VINF_SUCCESS;
787 }
788 if (RT_FAILURE(rc))
789 {
790 if (fHMForced)
791 return VM_SET_ERROR(pVM, rc, pszMsg);
792
793 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
794 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
795 }
796 }
797 }
798 else
799 {
800 /*
801 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
802 */
803 if (!fUseNEMInstead)
804 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
805 else
806 {
807 rc = NEMR3Init(pVM, false /*fFallback*/, true);
808 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
809 if (RT_FAILURE(rc))
810 return rc;
811 }
812 }
813
814 return VINF_SUCCESS;
815}
816
817
818/**
819 * Initializes the per-VCPU HM.
820 *
821 * @returns VBox status code.
822 * @param pVM The cross context VM structure.
823 */
824static int hmR3InitCPU(PVM pVM)
825{
826 LogFlow(("HMR3InitCPU\n"));
827
828 if (!HMIsEnabled(pVM))
829 return VINF_SUCCESS;
830
831 for (VMCPUID i = 0; i < pVM->cCpus; i++)
832 {
833 PVMCPU pVCpu = &pVM->aCpus[i];
834 pVCpu->hm.s.fActive = false;
835 }
836
837#ifdef VBOX_WITH_STATISTICS
838 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
839 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
840 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
841 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
842 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
843#endif
844
845 /*
846 * Statistics.
847 */
848 for (VMCPUID i = 0; i < pVM->cCpus; i++)
849 {
850 PVMCPU pVCpu = &pVM->aCpus[i];
851 int rc;
852
853#ifdef VBOX_WITH_STATISTICS
854 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
855 "Profiling of RTMpPokeCpu",
856 "/PROF/CPU%d/HM/Poke", i);
857 AssertRC(rc);
858 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
859 "Profiling of poke wait",
860 "/PROF/CPU%d/HM/PokeWait", i);
861 AssertRC(rc);
862 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
863 "Profiling of poke wait when RTMpPokeCpu fails",
864 "/PROF/CPU%d/HM/PokeWaitFailed", i);
865 AssertRC(rc);
866 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
867 "Profiling of VMXR0RunGuestCode entry",
868 "/PROF/CPU%d/HM/StatEntry", i);
869 AssertRC(rc);
870 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
871 "Profiling of VMXR0RunGuestCode exit part 1",
872 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
873 AssertRC(rc);
874 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
875 "Profiling of VMXR0RunGuestCode exit part 2",
876 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
877 AssertRC(rc);
878
879 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
880 "I/O",
881 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
882 AssertRC(rc);
883 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
884 "MOV CRx",
885 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
886 AssertRC(rc);
887 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
888 "Exceptions, NMIs",
889 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
890 AssertRC(rc);
891
892 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
893 "Profiling of VMXR0LoadGuestState",
894 "/PROF/CPU%d/HM/StatLoadGuestState", i);
895 AssertRC(rc);
896 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
897 "Profiling of CPUMR0LoadGuestFPU",
898 "/PROF/CPU%d/HM/StatLoadGuestFpuState", i);
899 AssertRC(rc);
900 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
901 "Profiling of VMLAUNCH/VMRESUME.",
902 "/PROF/CPU%d/HM/InGC", i);
903 AssertRC(rc);
904
905# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
906 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
907 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
908 "/PROF/CPU%d/HM/Switcher3264", i);
909 AssertRC(rc);
910# endif
911
912# ifdef HM_PROFILE_EXIT_DISPATCH
913 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
914 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
915 "/PROF/CPU%d/HM/ExitDispatch", i);
916 AssertRC(rc);
917# endif
918
919#endif
920# define HM_REG_COUNTER(a, b, desc) \
921 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
922 AssertRC(rc);
923
924#ifdef VBOX_WITH_STATISTICS
925 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
926 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
927 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
928 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
929 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
930 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
931 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
932 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
933 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
934 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
935 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
936 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
937 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
938 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
939 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
940 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
941 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
942 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
943 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
944 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
945 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
946 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
947 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
948 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
949 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
950 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
951 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
952 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
953 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
954 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
955 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
956 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
957 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
958 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
959 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
960 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
961 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
962 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
963 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
964 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
965 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
966 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
967 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
968 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
969 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
970 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
971 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
972#endif
973 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
974#ifdef VBOX_WITH_STATISTICS
975 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
976 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
977 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
978 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
979 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
980
981 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
982 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
983 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
984 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
985 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
986 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
987 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
988 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
989 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
990#endif
991 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
992#ifdef VBOX_WITH_STATISTICS
993 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
994
995 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
996 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
997 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
998 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
999
1000 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
1001 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
1002 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
1003 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
1004 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
1005 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
1006 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
1007 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
1008 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
1009 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
1010 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
1011 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
1012 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
1013 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
1014
1015 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
1016 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
1017 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
1018
1019 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
1020 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
1021 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
1022
1023 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
1024 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
1025 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/GuestFpu", "VM-entry loading the guest-FPU state.");
1026
1027 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
1028 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
1029 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
1030 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
1031 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
1032 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
1033 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
1034 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
1035
1036#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1037 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
1038 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
1039#endif
1040
1041 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
1042 {
1043 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1044 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
1045 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
1046 AssertRC(rc);
1047 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1048 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
1049 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
1050 AssertRC(rc);
1051 }
1052
1053#undef HM_REG_COUNTER
1054
1055 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVTxExitReasons[0]
1056 : &g_apszAmdVExitReasons[0];
1057
1058 /*
1059 * Guest Exit reason stats.
1060 */
1061 pVCpu->hm.s.paStatExitReason = NULL;
1062 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
1063 (void **)&pVCpu->hm.s.paStatExitReason);
1064 AssertRCReturn(rc, rc);
1065 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1066 {
1067 if (papszDesc[j])
1068 {
1069 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1070 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
1071 AssertRCReturn(rc, rc);
1072 }
1073 }
1074 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1075 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
1076 AssertRCReturn(rc, rc);
1077 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
1078# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1079 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1080# else
1081 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
1082# endif
1083
1084#ifdef VBOX_WITH_NESTED_HWVIRT
1085 /*
1086 * Nested-guest Exit reason stats.
1087 */
1088 pVCpu->hm.s.paStatNestedExitReason = NULL;
1089 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
1090 (void **)&pVCpu->hm.s.paStatNestedExitReason);
1091 AssertRCReturn(rc, rc);
1092 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1093 {
1094 if (papszDesc[j])
1095 {
1096 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1097 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
1098 AssertRC(rc);
1099 }
1100 }
1101 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1102 STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
1103 AssertRCReturn(rc, rc);
1104 pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
1105# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1106 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1107# else
1108 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
1109# endif
1110#endif
1111
1112 /*
1113 * Injected events stats.
1114 */
1115 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
1116 AssertRCReturn(rc, rc);
1117 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1118# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1119 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1120# else
1121 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1122# endif
1123 for (unsigned j = 0; j < 255; j++)
1124 {
1125 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1126 "Injected event.",
1127 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1128 }
1129
1130#endif /* VBOX_WITH_STATISTICS */
1131 }
1132
1133#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1134 /*
1135 * Magic marker for searching in crash dumps.
1136 */
1137 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1138 {
1139 PVMCPU pVCpu = &pVM->aCpus[i];
1140
1141 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1142 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1143 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1144 }
1145#endif
1146
1147 return VINF_SUCCESS;
1148}
1149
1150
1151/**
1152 * Called when a init phase has completed.
1153 *
1154 * @returns VBox status code.
1155 * @param pVM The cross context VM structure.
1156 * @param enmWhat The phase that completed.
1157 */
1158VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1159{
1160 switch (enmWhat)
1161 {
1162 case VMINITCOMPLETED_RING3:
1163 return hmR3InitCPU(pVM);
1164 case VMINITCOMPLETED_RING0:
1165 return hmR3InitFinalizeR0(pVM);
1166 default:
1167 return VINF_SUCCESS;
1168 }
1169}
1170
1171
1172/**
1173 * Turns off normal raw mode features.
1174 *
1175 * @param pVM The cross context VM structure.
1176 */
1177static void hmR3DisableRawMode(PVM pVM)
1178{
1179 /* Reinit the paging mode to force the new shadow mode. */
1180 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1181 {
1182 PVMCPU pVCpu = &pVM->aCpus[i];
1183
1184 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1185 }
1186}
1187
1188
1189/**
1190 * Initialize VT-x or AMD-V.
1191 *
1192 * @returns VBox status code.
1193 * @param pVM The cross context VM structure.
1194 */
1195static int hmR3InitFinalizeR0(PVM pVM)
1196{
1197 int rc;
1198
1199 if (!HMIsEnabled(pVM))
1200 return VINF_SUCCESS;
1201
1202 /*
1203 * Hack to allow users to work around broken BIOSes that incorrectly set
1204 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1205 */
1206 if ( !pVM->hm.s.vmx.fSupported
1207 && !pVM->hm.s.svm.fSupported
1208 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
1209 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1210 {
1211 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1212 pVM->hm.s.svm.fSupported = true;
1213 pVM->hm.s.svm.fIgnoreInUseError = true;
1214 pVM->hm.s.lLastError = VINF_SUCCESS;
1215 }
1216
1217 /*
1218 * Report ring-0 init errors.
1219 */
1220 if ( !pVM->hm.s.vmx.fSupported
1221 && !pVM->hm.s.svm.fSupported)
1222 {
1223 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
1224 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1225 switch (pVM->hm.s.lLastError)
1226 {
1227 case VERR_VMX_IN_VMX_ROOT_MODE:
1228 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1229 case VERR_VMX_NO_VMX:
1230 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1231 case VERR_VMX_MSR_VMX_DISABLED:
1232 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1233 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1234 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1235 case VERR_VMX_MSR_LOCKING_FAILED:
1236 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1237 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1238 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1239 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1240 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1241
1242 case VERR_SVM_IN_USE:
1243 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1244 case VERR_SVM_NO_SVM:
1245 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1246 case VERR_SVM_DISABLED:
1247 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1248 }
1249 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
1250 }
1251
1252 /*
1253 * Enable VT-x or AMD-V on all host CPUs.
1254 */
1255 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1256 if (RT_FAILURE(rc))
1257 {
1258 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1259 HMR3CheckError(pVM, rc);
1260 return rc;
1261 }
1262
1263 /*
1264 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1265 * (Main should have taken care of this already)
1266 */
1267 if (!PDMHasIoApic(pVM))
1268 {
1269 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1270 pVM->hm.s.fTprPatchingAllowed = false;
1271 }
1272
1273 /*
1274 * Sync options.
1275 */
1276 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1277 * That will require a little bit of work, of course. */
1278 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1279 {
1280 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1281 PCPUMCTX pCpuCtx = CPUMQueryGuestCtxPtr(pVCpu);
1282 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1283 if (pVM->cpum.ro.HostFeatures.fIbpb)
1284 {
1285 if (pVM->hm.s.fIbpbOnVmExit)
1286 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1287 if (pVM->hm.s.fIbpbOnVmEntry)
1288 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1289 }
1290 if (iCpu == 0)
1291 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
1292 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
1293 }
1294
1295 /*
1296 * Do the vendor specific initialization
1297 *
1298 * Note! We disable release log buffering here since we're doing relatively
1299 * lot of logging and doesn't want to hit the disk with each LogRel
1300 * statement.
1301 */
1302 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1303 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1304 if (pVM->hm.s.vmx.fSupported)
1305 rc = hmR3InitFinalizeR0Intel(pVM);
1306 else
1307 rc = hmR3InitFinalizeR0Amd(pVM);
1308 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1309 RTLogRelSetBuffering(fOldBuffered);
1310 pVM->hm.s.fInitialized = true;
1311
1312 return rc;
1313}
1314
1315
1316/**
1317 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1318 */
1319static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1320{
1321 NOREF(pVM);
1322 NOREF(pvAllocation);
1323 NOREF(GCPhysAllocation);
1324}
1325
1326
1327/**
1328 * Finish VT-x initialization (after ring-0 init).
1329 *
1330 * @returns VBox status code.
1331 * @param pVM The cross context VM structure.
1332 */
1333static int hmR3InitFinalizeR0Intel(PVM pVM)
1334{
1335 int rc;
1336
1337 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1338 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1339
1340 uint64_t val;
1341 uint64_t zap;
1342
1343 LogRel(("HM: Using VT-x implementation 2.0\n"));
1344 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1345 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1346 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1347 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1348 if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1349 LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1350 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1351 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1352 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1353 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1354 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1355 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1356 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1357 LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1358 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1359
1360 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1361 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1362 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1363 HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1364 HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1365 HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1366 HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1367 HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1368
1369 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1370 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1371 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1372 HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1373 HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1374 HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1375 HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1376 HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1377 HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1378 HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1379 HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1380 HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1381 HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1382 HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1383 HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1384 HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1385 HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1386 HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1387 HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1388 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1389 HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1390 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1391 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1392 HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1393 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1394 {
1395 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1396 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1397 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1398 HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1399 HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1400 HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1401 HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1402 HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1403 HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1404 HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1405 HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1406 HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1407 HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1408 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1409 HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1410 HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1411 HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1412 HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1413 HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1414 HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1415 HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1416 HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1417 HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1418 HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1419 HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1420 }
1421
1422 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1423 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1424 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1425 HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1426 HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1427 HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1428 HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1429 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1430 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1431 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1432
1433 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1434 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1435 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1436 HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1437 HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1438 HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1439 HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1440 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1441 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1442 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1443 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1444 HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1445
1446 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1447 {
1448 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1449 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1450 HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1451 HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1452 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1453 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1454 HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1455 HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1456 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1457 HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1458 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1459 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1460 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1461 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1462 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1463 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1464 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1465 }
1466
1467 val = pVM->hm.s.vmx.Msrs.u64Misc;
1468 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1469 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1470 LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1471 else
1472 {
1473 LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1474 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1475 }
1476
1477 LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1478 LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1479 LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1480 LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1481 LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1482 LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1483 LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1484 LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1485
1486 /* Paranoia */
1487 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1488
1489 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1490 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1491 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1492 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1493
1494 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1495 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1496 LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1497
1498 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1499 if (val)
1500 {
1501 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
1502 HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1503 }
1504
1505 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1506
1507 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1508 {
1509 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1510 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1511 }
1512
1513 /*
1514 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1515 */
1516 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1517 || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1518 VERR_HM_IPE_1);
1519 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1520 || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1521 && pVM->hm.s.fNestedPaging),
1522 VERR_HM_IPE_1);
1523
1524 /*
1525 * Enable VPID if configured and supported.
1526 */
1527 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1528 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1529
1530#if 0
1531 /*
1532 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1533 */
1534 if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1535 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1536 pVM->hm.s.fVirtApicRegs = true;
1537
1538 /*
1539 * Enable posted-interrupt processing if supported.
1540 */
1541 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1542 * here. */
1543 if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1544 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1545 pVM->hm.s.fPostedIntrs = true;
1546#endif
1547
1548 /*
1549 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1550 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1551 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1552 */
1553 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1554 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1555 {
1556 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1557 LogRel(("HM: Disabled RDTSCP\n"));
1558 }
1559
1560 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1561 {
1562 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1563 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1564 if (RT_SUCCESS(rc))
1565 {
1566 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1567 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1568 esp. Figure 20-5.*/
1569 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1570 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1571
1572 /* Bit set to 0 means software interrupts are redirected to the
1573 8086 program interrupt handler rather than switching to
1574 protected-mode handler. */
1575 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1576
1577 /* Allow all port IO, so that port IO instructions do not cause
1578 exceptions and would instead cause a VM-exit (based on VT-x's
1579 IO bitmap which we currently configure to always cause an exit). */
1580 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1581 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1582
1583 /*
1584 * Construct a 1024 element page directory with 4 MB pages for
1585 * the identity mapped page table used in real and protected mode
1586 * without paging with EPT.
1587 */
1588 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1589 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1590 {
1591 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1592 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1593 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1594 | X86_PDE4M_G;
1595 }
1596
1597 /* We convert it here every time as PCI regions could be reconfigured. */
1598 if (PDMVmmDevHeapIsEnabled(pVM))
1599 {
1600 RTGCPHYS GCPhys;
1601 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1602 AssertRCReturn(rc, rc);
1603 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1604
1605 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1606 AssertRCReturn(rc, rc);
1607 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1608 }
1609 }
1610 else
1611 {
1612 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1613 pVM->hm.s.vmx.pRealModeTSS = NULL;
1614 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1615 return VMSetError(pVM, rc, RT_SRC_POS,
1616 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1617 }
1618 }
1619
1620 LogRel((pVM->hm.s.fAllow64BitGuests
1621 ? "HM: Guest support: 32-bit and 64-bit\n"
1622 : "HM: Guest support: 32-bit only\n"));
1623
1624 /*
1625 * Call ring-0 to set up the VM.
1626 */
1627 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1628 if (rc != VINF_SUCCESS)
1629 {
1630 AssertMsgFailed(("%Rrc\n", rc));
1631 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1632 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1633 {
1634 PVMCPU pVCpu = &pVM->aCpus[i];
1635 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1636 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1637 }
1638 HMR3CheckError(pVM, rc);
1639 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1640 }
1641
1642 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1643 LogRel(("HM: Enabled VMX\n"));
1644 pVM->hm.s.vmx.fEnabled = true;
1645
1646 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1647
1648 /*
1649 * Change the CPU features.
1650 */
1651 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1652 if (pVM->hm.s.fAllow64BitGuests)
1653 {
1654 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1655 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1656 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1657 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1658 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1659 }
1660 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1661 (we reuse the host EFER in the switcher). */
1662 /** @todo this needs to be fixed properly!! */
1663 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1664 {
1665 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1666 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1667 else
1668 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1669 }
1670
1671 /*
1672 * Log configuration details.
1673 */
1674 if (pVM->hm.s.fNestedPaging)
1675 {
1676 LogRel(("HM: Enabled nested paging\n"));
1677 if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1678 LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1679 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1680 LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1681 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1682 LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1683 else
1684 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1685
1686 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1687 LogRel(("HM: Enabled unrestricted guest execution\n"));
1688
1689#if HC_ARCH_BITS == 64
1690 if (pVM->hm.s.fLargePages)
1691 {
1692 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1693 PGMSetLargePageUsage(pVM, true);
1694 LogRel(("HM: Enabled large page support\n"));
1695 }
1696#endif
1697 }
1698 else
1699 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1700
1701 if (pVM->hm.s.fVirtApicRegs)
1702 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1703
1704 if (pVM->hm.s.fPostedIntrs)
1705 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1706
1707 if (pVM->hm.s.vmx.fVpid)
1708 {
1709 LogRel(("HM: Enabled VPID\n"));
1710 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1711 LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1712 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1713 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1714 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1715 LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1716 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1717 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1718 else
1719 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1720 }
1721 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1722 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1723
1724 if (pVM->hm.s.vmx.fUsePreemptTimer)
1725 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1726 else
1727 LogRel(("HM: Disabled VMX-preemption timer\n"));
1728
1729 return VINF_SUCCESS;
1730}
1731
1732
1733/**
1734 * Finish AMD-V initialization (after ring-0 init).
1735 *
1736 * @returns VBox status code.
1737 * @param pVM The cross context VM structure.
1738 */
1739static int hmR3InitFinalizeR0Amd(PVM pVM)
1740{
1741 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1742
1743 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1744
1745 uint32_t u32Family;
1746 uint32_t u32Model;
1747 uint32_t u32Stepping;
1748 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1749 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1750 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1751 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1752 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1753 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1754 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1755 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1756 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1757
1758 /*
1759 * Enumerate AMD-V features.
1760 */
1761 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1762 {
1763#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1764 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1765 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1766 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1767 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1768 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1769 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1770 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1771 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1772 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1773 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1774 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1775 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1776 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1777#undef HMSVM_REPORT_FEATURE
1778 };
1779
1780 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1781 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1782 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1783 {
1784 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1785 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1786 }
1787 if (fSvmFeatures)
1788 for (unsigned iBit = 0; iBit < 32; iBit++)
1789 if (RT_BIT_32(iBit) & fSvmFeatures)
1790 LogRel(("HM: Reserved bit %u\n", iBit));
1791
1792 /*
1793 * Nested paging is determined in HMR3Init, verify the sanity of that.
1794 */
1795 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1796 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1797 VERR_HM_IPE_1);
1798
1799#if 0
1800 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1801 * here. */
1802 if (RTR0IsPostIpiSupport())
1803 pVM->hm.s.fPostedIntrs = true;
1804#endif
1805
1806 /*
1807 * Call ring-0 to set up the VM.
1808 */
1809 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1810 if (rc != VINF_SUCCESS)
1811 {
1812 AssertMsgFailed(("%Rrc\n", rc));
1813 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1814 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1815 }
1816
1817 LogRel(("HM: Enabled SVM\n"));
1818 pVM->hm.s.svm.fEnabled = true;
1819
1820 if (pVM->hm.s.fNestedPaging)
1821 {
1822 LogRel(("HM: Enabled nested paging\n"));
1823
1824 /*
1825 * Enable large pages (2 MB) if applicable.
1826 */
1827#if HC_ARCH_BITS == 64
1828 if (pVM->hm.s.fLargePages)
1829 {
1830 PGMSetLargePageUsage(pVM, true);
1831 LogRel(("HM: Enabled large page support\n"));
1832 }
1833#endif
1834 }
1835
1836 if (pVM->hm.s.fVirtApicRegs)
1837 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1838
1839 if (pVM->hm.s.fPostedIntrs)
1840 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1841
1842 hmR3DisableRawMode(pVM);
1843
1844 /*
1845 * Change the CPU features.
1846 */
1847 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1848 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1849 if (pVM->hm.s.fAllow64BitGuests)
1850 {
1851 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1852 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1853 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1854 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1855 }
1856 /* Turn on NXE if PAE has been enabled. */
1857 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1858 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1859
1860 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1861
1862 LogRel((pVM->hm.s.fAllow64BitGuests
1863 ? "HM: Guest support: 32-bit and 64-bit\n"
1864 : "HM: Guest support: 32-bit only\n"));
1865
1866 return VINF_SUCCESS;
1867}
1868
1869
1870/**
1871 * Applies relocations to data and code managed by this
1872 * component. This function will be called at init and
1873 * whenever the VMM need to relocate it self inside the GC.
1874 *
1875 * @param pVM The cross context VM structure.
1876 */
1877VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1878{
1879 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1880
1881 /* Fetch the current paging mode during the relocate callback during state loading. */
1882 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1883 {
1884 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1885 {
1886 PVMCPU pVCpu = &pVM->aCpus[i];
1887 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1888 }
1889 }
1890#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1891 if (HMIsEnabled(pVM))
1892 {
1893 switch (PGMGetHostMode(pVM))
1894 {
1895 case PGMMODE_32_BIT:
1896 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1897 break;
1898
1899 case PGMMODE_PAE:
1900 case PGMMODE_PAE_NX:
1901 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1902 break;
1903
1904 default:
1905 AssertFailed();
1906 break;
1907 }
1908 }
1909#endif
1910 return;
1911}
1912
1913
1914/**
1915 * Notification callback which is called whenever there is a chance that a CR3
1916 * value might have changed.
1917 *
1918 * This is called by PGM.
1919 *
1920 * @param pVM The cross context VM structure.
1921 * @param pVCpu The cross context virtual CPU structure.
1922 * @param enmShadowMode New shadow paging mode.
1923 * @param enmGuestMode New guest paging mode.
1924 */
1925VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1926{
1927 RT_NOREF_PV(pVM);
1928
1929 /* Ignore page mode changes during state loading. */
1930 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1931 return;
1932
1933 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1934
1935 /*
1936 * If the guest left protected mode VMX execution, we'll have to be
1937 * extra careful if/when the guest switches back to protected mode.
1938 */
1939 if (enmGuestMode == PGMMODE_REAL)
1940 pVCpu->hm.s.vmx.fWasInRealMode = true;
1941
1942 Log4(("HMR3PagingModeChanged: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
1943 PGMGetModeName(enmShadowMode)));
1944}
1945
1946
1947/**
1948 * Terminates the HM.
1949 *
1950 * Termination means cleaning up and freeing all resources,
1951 * the VM itself is, at this point, powered off or suspended.
1952 *
1953 * @returns VBox status code.
1954 * @param pVM The cross context VM structure.
1955 */
1956VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1957{
1958 if (pVM->hm.s.vmx.pRealModeTSS)
1959 {
1960 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1961 pVM->hm.s.vmx.pRealModeTSS = 0;
1962 }
1963 hmR3TermCPU(pVM);
1964 return 0;
1965}
1966
1967
1968/**
1969 * Terminates the per-VCPU HM.
1970 *
1971 * @returns VBox status code.
1972 * @param pVM The cross context VM structure.
1973 */
1974static int hmR3TermCPU(PVM pVM)
1975{
1976 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1977 {
1978 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1979
1980#ifdef VBOX_WITH_STATISTICS
1981 if (pVCpu->hm.s.paStatExitReason)
1982 {
1983 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1984 pVCpu->hm.s.paStatExitReason = NULL;
1985 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1986 }
1987 if (pVCpu->hm.s.paStatInjectedIrqs)
1988 {
1989 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1990 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1991 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1992 }
1993#endif
1994
1995#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1996 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1997 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1998 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1999#endif
2000 }
2001 return 0;
2002}
2003
2004
2005/**
2006 * Resets a virtual CPU.
2007 *
2008 * Used by HMR3Reset and CPU hot plugging.
2009 *
2010 * @param pVCpu The cross context virtual CPU structure to reset.
2011 */
2012VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2013{
2014 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
2015 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2016 HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
2017
2018 pVCpu->hm.s.vmx.u32CR0Mask = 0;
2019 pVCpu->hm.s.vmx.u32CR4Mask = 0;
2020 pVCpu->hm.s.fActive = false;
2021 pVCpu->hm.s.Event.fPending = false;
2022 pVCpu->hm.s.vmx.fWasInRealMode = true;
2023 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
2024 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
2025
2026 /* Reset the contents of the read cache. */
2027 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
2028 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
2029 pCache->Read.aFieldVal[j] = 0;
2030
2031#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2032 /* Magic marker for searching in crash dumps. */
2033 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
2034 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2035#endif
2036}
2037
2038
2039/**
2040 * The VM is being reset.
2041 *
2042 * For the HM component this means that any GDT/LDT/TSS monitors
2043 * needs to be removed.
2044 *
2045 * @param pVM The cross context VM structure.
2046 */
2047VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2048{
2049 LogFlow(("HMR3Reset:\n"));
2050
2051 if (HMIsEnabled(pVM))
2052 hmR3DisableRawMode(pVM);
2053
2054 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2055 {
2056 PVMCPU pVCpu = &pVM->aCpus[i];
2057
2058 HMR3ResetCpu(pVCpu);
2059 }
2060
2061 /* Clear all patch information. */
2062 pVM->hm.s.pGuestPatchMem = 0;
2063 pVM->hm.s.pFreeGuestPatchMem = 0;
2064 pVM->hm.s.cbGuestPatchMem = 0;
2065 pVM->hm.s.cPatches = 0;
2066 pVM->hm.s.PatchTree = 0;
2067 pVM->hm.s.fTPRPatchingActive = false;
2068 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2069}
2070
2071
2072/**
2073 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2074 *
2075 * @returns VBox strict status code.
2076 * @param pVM The cross context VM structure.
2077 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2078 * @param pvUser Unused.
2079 */
2080static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2081{
2082 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2083
2084 /* Only execute the handler on the VCPU the original patch request was issued. */
2085 if (pVCpu->idCpu != idCpu)
2086 return VINF_SUCCESS;
2087
2088 Log(("hmR3RemovePatches\n"));
2089 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2090 {
2091 uint8_t abInstr[15];
2092 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2093 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2094 int rc;
2095
2096#ifdef LOG_ENABLED
2097 char szOutput[256];
2098
2099 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2100 szOutput, sizeof(szOutput), NULL);
2101 if (RT_SUCCESS(rc))
2102 Log(("Patched instr: %s\n", szOutput));
2103#endif
2104
2105 /* Check if the instruction is still the same. */
2106 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2107 if (rc != VINF_SUCCESS)
2108 {
2109 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2110 continue; /* swapped out or otherwise removed; skip it. */
2111 }
2112
2113 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2114 {
2115 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2116 continue; /* skip it. */
2117 }
2118
2119 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2120 AssertRC(rc);
2121
2122#ifdef LOG_ENABLED
2123 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2124 szOutput, sizeof(szOutput), NULL);
2125 if (RT_SUCCESS(rc))
2126 Log(("Original instr: %s\n", szOutput));
2127#endif
2128 }
2129 pVM->hm.s.cPatches = 0;
2130 pVM->hm.s.PatchTree = 0;
2131 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2132 pVM->hm.s.fTPRPatchingActive = false;
2133 return VINF_SUCCESS;
2134}
2135
2136
2137/**
2138 * Worker for enabling patching in a VT-x/AMD-V guest.
2139 *
2140 * @returns VBox status code.
2141 * @param pVM The cross context VM structure.
2142 * @param idCpu VCPU to execute hmR3RemovePatches on.
2143 * @param pPatchMem Patch memory range.
2144 * @param cbPatchMem Size of the memory range.
2145 */
2146static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2147{
2148 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2149 AssertRC(rc);
2150
2151 pVM->hm.s.pGuestPatchMem = pPatchMem;
2152 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2153 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2154 return VINF_SUCCESS;
2155}
2156
2157
2158/**
2159 * Enable patching in a VT-x/AMD-V guest
2160 *
2161 * @returns VBox status code.
2162 * @param pVM The cross context VM structure.
2163 * @param pPatchMem Patch memory range.
2164 * @param cbPatchMem Size of the memory range.
2165 */
2166VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2167{
2168 VM_ASSERT_EMT(pVM);
2169 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2170 if (pVM->cCpus > 1)
2171 {
2172 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2173 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2174 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2175 AssertRC(rc);
2176 return rc;
2177 }
2178 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2179}
2180
2181
2182/**
2183 * Disable patching in a VT-x/AMD-V guest.
2184 *
2185 * @returns VBox status code.
2186 * @param pVM The cross context VM structure.
2187 * @param pPatchMem Patch memory range.
2188 * @param cbPatchMem Size of the memory range.
2189 */
2190VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2191{
2192 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2193 RT_NOREF2(pPatchMem, cbPatchMem);
2194
2195 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2196 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2197
2198 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2199 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2200 (void *)(uintptr_t)VMMGetCpuId(pVM));
2201 AssertRC(rc);
2202
2203 pVM->hm.s.pGuestPatchMem = 0;
2204 pVM->hm.s.pFreeGuestPatchMem = 0;
2205 pVM->hm.s.cbGuestPatchMem = 0;
2206 pVM->hm.s.fTPRPatchingActive = false;
2207 return VINF_SUCCESS;
2208}
2209
2210
2211/**
2212 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2213 *
2214 * @returns VBox strict status code.
2215 * @param pVM The cross context VM structure.
2216 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2217 * @param pvUser User specified CPU context.
2218 *
2219 */
2220static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2221{
2222 /*
2223 * Only execute the handler on the VCPU the original patch request was
2224 * issued. (The other CPU(s) might not yet have switched to protected
2225 * mode, nor have the correct memory context.)
2226 */
2227 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2228 if (pVCpu->idCpu != idCpu)
2229 return VINF_SUCCESS;
2230
2231 /*
2232 * We're racing other VCPUs here, so don't try patch the instruction twice
2233 * and make sure there is still room for our patch record.
2234 */
2235 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2236 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2237 if (pPatch)
2238 {
2239 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2240 return VINF_SUCCESS;
2241 }
2242 uint32_t const idx = pVM->hm.s.cPatches;
2243 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2244 {
2245 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2246 return VINF_SUCCESS;
2247 }
2248 pPatch = &pVM->hm.s.aPatches[idx];
2249
2250 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2251
2252 /*
2253 * Disassembler the instruction and get cracking.
2254 */
2255 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2256 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2257 uint32_t cbOp;
2258 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2259 AssertRC(rc);
2260 if ( rc == VINF_SUCCESS
2261 && pDis->pCurInstr->uOpcode == OP_MOV
2262 && cbOp >= 3)
2263 {
2264 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2265
2266 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2267 AssertRC(rc);
2268
2269 pPatch->cbOp = cbOp;
2270
2271 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2272 {
2273 /* write. */
2274 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2275 {
2276 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2277 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2278 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2279 }
2280 else
2281 {
2282 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2283 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2284 pPatch->uSrcOperand = pDis->Param2.uValue;
2285 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2286 }
2287 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2288 AssertRC(rc);
2289
2290 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2291 pPatch->cbNewOp = sizeof(s_abVMMCall);
2292 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2293 }
2294 else
2295 {
2296 /*
2297 * TPR Read.
2298 *
2299 * Found:
2300 * mov eax, dword [fffe0080] (5 bytes)
2301 * Check if next instruction is:
2302 * shr eax, 4
2303 */
2304 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2305
2306 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2307 uint8_t const cbOpMmio = cbOp;
2308 uint64_t const uSavedRip = pCtx->rip;
2309
2310 pCtx->rip += cbOp;
2311 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2312 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2313 pCtx->rip = uSavedRip;
2314
2315 if ( rc == VINF_SUCCESS
2316 && pDis->pCurInstr->uOpcode == OP_SHR
2317 && pDis->Param1.fUse == DISUSE_REG_GEN32
2318 && pDis->Param1.Base.idxGenReg == idxMmioReg
2319 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2320 && pDis->Param2.uValue == 4
2321 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2322 {
2323 uint8_t abInstr[15];
2324
2325 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2326 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2327 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2328 AssertRC(rc);
2329
2330 pPatch->cbOp = cbOpMmio + cbOp;
2331
2332 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2333 abInstr[0] = 0xF0;
2334 abInstr[1] = 0x0F;
2335 abInstr[2] = 0x20;
2336 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2337 for (unsigned i = 4; i < pPatch->cbOp; i++)
2338 abInstr[i] = 0x90; /* nop */
2339
2340 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2341 AssertRC(rc);
2342
2343 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2344 pPatch->cbNewOp = pPatch->cbOp;
2345 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2346
2347 Log(("Acceptable read/shr candidate!\n"));
2348 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2349 }
2350 else
2351 {
2352 pPatch->enmType = HMTPRINSTR_READ;
2353 pPatch->uDstOperand = idxMmioReg;
2354
2355 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2356 AssertRC(rc);
2357
2358 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2359 pPatch->cbNewOp = sizeof(s_abVMMCall);
2360 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2361 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2362 }
2363 }
2364
2365 pPatch->Core.Key = pCtx->eip;
2366 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2367 AssertRC(rc);
2368
2369 pVM->hm.s.cPatches++;
2370 return VINF_SUCCESS;
2371 }
2372
2373 /*
2374 * Save invalid patch, so we will not try again.
2375 */
2376 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2377 pPatch->Core.Key = pCtx->eip;
2378 pPatch->enmType = HMTPRINSTR_INVALID;
2379 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2380 AssertRC(rc);
2381 pVM->hm.s.cPatches++;
2382 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2383 return VINF_SUCCESS;
2384}
2385
2386
2387/**
2388 * Callback to patch a TPR instruction (jump to generated code).
2389 *
2390 * @returns VBox strict status code.
2391 * @param pVM The cross context VM structure.
2392 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2393 * @param pvUser User specified CPU context.
2394 *
2395 */
2396static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2397{
2398 /*
2399 * Only execute the handler on the VCPU the original patch request was
2400 * issued. (The other CPU(s) might not yet have switched to protected
2401 * mode, nor have the correct memory context.)
2402 */
2403 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2404 if (pVCpu->idCpu != idCpu)
2405 return VINF_SUCCESS;
2406
2407 /*
2408 * We're racing other VCPUs here, so don't try patch the instruction twice
2409 * and make sure there is still room for our patch record.
2410 */
2411 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2412 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2413 if (pPatch)
2414 {
2415 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2416 return VINF_SUCCESS;
2417 }
2418 uint32_t const idx = pVM->hm.s.cPatches;
2419 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2420 {
2421 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2422 return VINF_SUCCESS;
2423 }
2424 pPatch = &pVM->hm.s.aPatches[idx];
2425
2426 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2427 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2428
2429 /*
2430 * Disassemble the instruction and get cracking.
2431 */
2432 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2433 uint32_t cbOp;
2434 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2435 AssertRC(rc);
2436 if ( rc == VINF_SUCCESS
2437 && pDis->pCurInstr->uOpcode == OP_MOV
2438 && cbOp >= 5)
2439 {
2440 uint8_t aPatch[64];
2441 uint32_t off = 0;
2442
2443 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2444 AssertRC(rc);
2445
2446 pPatch->cbOp = cbOp;
2447 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2448
2449 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2450 {
2451 /*
2452 * TPR write:
2453 *
2454 * push ECX [51]
2455 * push EDX [52]
2456 * push EAX [50]
2457 * xor EDX,EDX [31 D2]
2458 * mov EAX,EAX [89 C0]
2459 * or
2460 * mov EAX,0000000CCh [B8 CC 00 00 00]
2461 * mov ECX,0C0000082h [B9 82 00 00 C0]
2462 * wrmsr [0F 30]
2463 * pop EAX [58]
2464 * pop EDX [5A]
2465 * pop ECX [59]
2466 * jmp return_address [E9 return_address]
2467 *
2468 */
2469 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2470
2471 aPatch[off++] = 0x51; /* push ecx */
2472 aPatch[off++] = 0x52; /* push edx */
2473 if (!fUsesEax)
2474 aPatch[off++] = 0x50; /* push eax */
2475 aPatch[off++] = 0x31; /* xor edx, edx */
2476 aPatch[off++] = 0xD2;
2477 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2478 {
2479 if (!fUsesEax)
2480 {
2481 aPatch[off++] = 0x89; /* mov eax, src_reg */
2482 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2483 }
2484 }
2485 else
2486 {
2487 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2488 aPatch[off++] = 0xB8; /* mov eax, immediate */
2489 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2490 off += sizeof(uint32_t);
2491 }
2492 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2493 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2494 off += sizeof(uint32_t);
2495
2496 aPatch[off++] = 0x0F; /* wrmsr */
2497 aPatch[off++] = 0x30;
2498 if (!fUsesEax)
2499 aPatch[off++] = 0x58; /* pop eax */
2500 aPatch[off++] = 0x5A; /* pop edx */
2501 aPatch[off++] = 0x59; /* pop ecx */
2502 }
2503 else
2504 {
2505 /*
2506 * TPR read:
2507 *
2508 * push ECX [51]
2509 * push EDX [52]
2510 * push EAX [50]
2511 * mov ECX,0C0000082h [B9 82 00 00 C0]
2512 * rdmsr [0F 32]
2513 * mov EAX,EAX [89 C0]
2514 * pop EAX [58]
2515 * pop EDX [5A]
2516 * pop ECX [59]
2517 * jmp return_address [E9 return_address]
2518 *
2519 */
2520 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2521
2522 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2523 aPatch[off++] = 0x51; /* push ecx */
2524 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2525 aPatch[off++] = 0x52; /* push edx */
2526 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2527 aPatch[off++] = 0x50; /* push eax */
2528
2529 aPatch[off++] = 0x31; /* xor edx, edx */
2530 aPatch[off++] = 0xD2;
2531
2532 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2533 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2534 off += sizeof(uint32_t);
2535
2536 aPatch[off++] = 0x0F; /* rdmsr */
2537 aPatch[off++] = 0x32;
2538
2539 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2540 {
2541 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2542 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2543 }
2544
2545 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2546 aPatch[off++] = 0x58; /* pop eax */
2547 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2548 aPatch[off++] = 0x5A; /* pop edx */
2549 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2550 aPatch[off++] = 0x59; /* pop ecx */
2551 }
2552 aPatch[off++] = 0xE9; /* jmp return_address */
2553 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2554 off += sizeof(RTRCUINTPTR);
2555
2556 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2557 {
2558 /* Write new code to the patch buffer. */
2559 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2560 AssertRC(rc);
2561
2562#ifdef LOG_ENABLED
2563 uint32_t cbCurInstr;
2564 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2565 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2566 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2567 {
2568 char szOutput[256];
2569 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2570 szOutput, sizeof(szOutput), &cbCurInstr);
2571 if (RT_SUCCESS(rc))
2572 Log(("Patch instr %s\n", szOutput));
2573 else
2574 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2575 }
2576#endif
2577
2578 pPatch->aNewOpcode[0] = 0xE9;
2579 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2580
2581 /* Overwrite the TPR instruction with a jump. */
2582 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2583 AssertRC(rc);
2584
2585 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2586
2587 pVM->hm.s.pFreeGuestPatchMem += off;
2588 pPatch->cbNewOp = 5;
2589
2590 pPatch->Core.Key = pCtx->eip;
2591 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2592 AssertRC(rc);
2593
2594 pVM->hm.s.cPatches++;
2595 pVM->hm.s.fTPRPatchingActive = true;
2596 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2597 return VINF_SUCCESS;
2598 }
2599
2600 Log(("Ran out of space in our patch buffer!\n"));
2601 }
2602 else
2603 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2604
2605
2606 /*
2607 * Save invalid patch, so we will not try again.
2608 */
2609 pPatch = &pVM->hm.s.aPatches[idx];
2610 pPatch->Core.Key = pCtx->eip;
2611 pPatch->enmType = HMTPRINSTR_INVALID;
2612 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2613 AssertRC(rc);
2614 pVM->hm.s.cPatches++;
2615 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2616 return VINF_SUCCESS;
2617}
2618
2619
2620/**
2621 * Attempt to patch TPR mmio instructions.
2622 *
2623 * @returns VBox status code.
2624 * @param pVM The cross context VM structure.
2625 * @param pVCpu The cross context virtual CPU structure.
2626 * @param pCtx Pointer to the guest CPU context.
2627 */
2628VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2629{
2630 NOREF(pCtx);
2631 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2632 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2633 (void *)(uintptr_t)pVCpu->idCpu);
2634 AssertRC(rc);
2635 return rc;
2636}
2637
2638
2639/**
2640 * Checks if a code selector (CS) is suitable for execution
2641 * within VMX when unrestricted execution isn't available.
2642 *
2643 * @returns true if selector is suitable for VMX, otherwise
2644 * false.
2645 * @param pSel Pointer to the selector to check (CS).
2646 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2647 */
2648static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2649{
2650 /*
2651 * Segment must be an accessed code segment, it must be present and it must
2652 * be usable.
2653 * Note! These are all standard requirements and if CS holds anything else
2654 * we've got buggy code somewhere!
2655 */
2656 AssertCompile(X86DESCATTR_TYPE == 0xf);
2657 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2658 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2659 ("%#x\n", pSel->Attr.u),
2660 false);
2661
2662 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2663 must equal SS.DPL for non-confroming segments.
2664 Note! This is also a hard requirement like above. */
2665 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2666 ? pSel->Attr.n.u2Dpl <= uStackDpl
2667 : pSel->Attr.n.u2Dpl == uStackDpl,
2668 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2669 false);
2670
2671 /*
2672 * The following two requirements are VT-x specific:
2673 * - G bit must be set if any high limit bits are set.
2674 * - G bit must be clear if any low limit bits are clear.
2675 */
2676 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2677 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2678 return true;
2679 return false;
2680}
2681
2682
2683/**
2684 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2685 * execution within VMX when unrestricted execution isn't
2686 * available.
2687 *
2688 * @returns true if selector is suitable for VMX, otherwise
2689 * false.
2690 * @param pSel Pointer to the selector to check
2691 * (DS/ES/FS/GS).
2692 */
2693static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2694{
2695 /*
2696 * Unusable segments are OK. These days they should be marked as such, as
2697 * but as an alternative we for old saved states and AMD<->VT-x migration
2698 * we also treat segments with all the attributes cleared as unusable.
2699 */
2700 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2701 return true;
2702
2703 /** @todo tighten these checks. Will require CPUM load adjusting. */
2704
2705 /* Segment must be accessed. */
2706 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2707 {
2708 /* Code segments must also be readable. */
2709 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2710 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2711 {
2712 /* The S bit must be set. */
2713 if (pSel->Attr.n.u1DescType)
2714 {
2715 /* Except for conforming segments, DPL >= RPL. */
2716 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2717 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2718 {
2719 /* Segment must be present. */
2720 if (pSel->Attr.n.u1Present)
2721 {
2722 /*
2723 * The following two requirements are VT-x specific:
2724 * - G bit must be set if any high limit bits are set.
2725 * - G bit must be clear if any low limit bits are clear.
2726 */
2727 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2728 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2729 return true;
2730 }
2731 }
2732 }
2733 }
2734 }
2735
2736 return false;
2737}
2738
2739
2740/**
2741 * Checks if the stack selector (SS) is suitable for execution
2742 * within VMX when unrestricted execution isn't available.
2743 *
2744 * @returns true if selector is suitable for VMX, otherwise
2745 * false.
2746 * @param pSel Pointer to the selector to check (SS).
2747 */
2748static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2749{
2750 /*
2751 * Unusable segments are OK. These days they should be marked as such, as
2752 * but as an alternative we for old saved states and AMD<->VT-x migration
2753 * we also treat segments with all the attributes cleared as unusable.
2754 */
2755 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2756 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2757 return true;
2758
2759 /*
2760 * Segment must be an accessed writable segment, it must be present.
2761 * Note! These are all standard requirements and if SS holds anything else
2762 * we've got buggy code somewhere!
2763 */
2764 AssertCompile(X86DESCATTR_TYPE == 0xf);
2765 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2766 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2767 ("%#x\n", pSel->Attr.u),
2768 false);
2769
2770 /* DPL must equal RPL.
2771 Note! This is also a hard requirement like above. */
2772 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2773 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2774 false);
2775
2776 /*
2777 * The following two requirements are VT-x specific:
2778 * - G bit must be set if any high limit bits are set.
2779 * - G bit must be clear if any low limit bits are clear.
2780 */
2781 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2782 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2783 return true;
2784 return false;
2785}
2786
2787
2788/**
2789 * Force execution of the current IO code in the recompiler.
2790 *
2791 * @returns VBox status code.
2792 * @param pVM The cross context VM structure.
2793 * @param pCtx Partial VM execution context.
2794 */
2795VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2796{
2797 PVMCPU pVCpu = VMMGetCpu(pVM);
2798
2799 Assert(HMIsEnabled(pVM));
2800 Log(("HMR3EmulateIoBlock\n"));
2801
2802 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2803 if (HMCanEmulateIoBlockEx(pCtx))
2804 {
2805 Log(("HMR3EmulateIoBlock -> enabled\n"));
2806 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2807 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2808 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2809 return VINF_EM_RESCHEDULE_REM;
2810 }
2811 return VINF_SUCCESS;
2812}
2813
2814
2815/**
2816 * Checks if we can currently use hardware accelerated raw mode.
2817 *
2818 * @returns true if we can currently use hardware acceleration, otherwise false.
2819 * @param pVM The cross context VM structure.
2820 * @param pCtx Partial VM execution context.
2821 */
2822VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2823{
2824 PVMCPU pVCpu = VMMGetCpu(pVM);
2825
2826 Assert(HMIsEnabled(pVM));
2827
2828#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
2829 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
2830 {
2831 Log(("HMR3CanExecuteGuest: In nested-guest mode - returning false"));
2832 return false;
2833 }
2834#endif
2835
2836 /* If we're still executing the IO code, then return false. */
2837 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2838 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2839 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2840 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2841 return false;
2842
2843 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2844
2845 /* AMD-V supports real & protected mode with or without paging. */
2846 if (pVM->hm.s.svm.fEnabled)
2847 {
2848 pVCpu->hm.s.fActive = true;
2849 return true;
2850 }
2851
2852 pVCpu->hm.s.fActive = false;
2853
2854 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2855 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2856 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2857
2858 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2859 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2860 {
2861 /*
2862 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2863 * guest execution feature is missing (VT-x only).
2864 */
2865 if (fSupportsRealMode)
2866 {
2867 if (CPUMIsGuestInRealModeEx(pCtx))
2868 {
2869 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2870 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2871 * If this is not true, we cannot execute real mode as V86 and have to fall
2872 * back to emulation.
2873 */
2874 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2875 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2876 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2877 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2878 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2879 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2880 {
2881 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2882 return false;
2883 }
2884 if ( (pCtx->cs.u32Limit != 0xffff)
2885 || (pCtx->ds.u32Limit != 0xffff)
2886 || (pCtx->es.u32Limit != 0xffff)
2887 || (pCtx->ss.u32Limit != 0xffff)
2888 || (pCtx->fs.u32Limit != 0xffff)
2889 || (pCtx->gs.u32Limit != 0xffff))
2890 {
2891 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2892 return false;
2893 }
2894 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2895 }
2896 else
2897 {
2898 /* Verify the requirements for executing code in protected
2899 mode. VT-x can't handle the CPU state right after a switch
2900 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2901 if (pVCpu->hm.s.vmx.fWasInRealMode)
2902 {
2903 /** @todo If guest is in V86 mode, these checks should be different! */
2904 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2905 {
2906 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2907 return false;
2908 }
2909 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2910 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2911 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2912 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2913 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2914 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2915 {
2916 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2917 return false;
2918 }
2919 }
2920 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2921 if (pCtx->gdtr.cbGdt)
2922 {
2923 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2924 {
2925 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2926 return false;
2927 }
2928 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2929 {
2930 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2931 return false;
2932 }
2933 }
2934 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2935 }
2936 }
2937 else
2938 {
2939 if ( !CPUMIsGuestInLongModeEx(pCtx)
2940 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2941 {
2942 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2943 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2944 return false;
2945
2946 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2947 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2948 return false;
2949
2950 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2951 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2952 * hidden registers (possible recompiler bug; see load_seg_vm) */
2953 if (pCtx->cs.Attr.n.u1Present == 0)
2954 return false;
2955 if (pCtx->ss.Attr.n.u1Present == 0)
2956 return false;
2957
2958 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2959 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2960 /** @todo This check is actually wrong, it doesn't take the direction of the
2961 * stack segment into account. But, it does the job for now. */
2962 if (pCtx->rsp >= pCtx->ss.u32Limit)
2963 return false;
2964 }
2965 }
2966 }
2967
2968 if (pVM->hm.s.vmx.fEnabled)
2969 {
2970 uint32_t mask;
2971
2972 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2973 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2974 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2975 mask &= ~X86_CR0_NE;
2976
2977 if (fSupportsRealMode)
2978 {
2979 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2980 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2981 }
2982 else
2983 {
2984 /* We support protected mode without paging using identity mapping. */
2985 mask &= ~X86_CR0_PG;
2986 }
2987 if ((pCtx->cr0 & mask) != mask)
2988 return false;
2989
2990 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2991 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2992 if ((pCtx->cr0 & mask) != 0)
2993 return false;
2994
2995 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2996 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2997 mask &= ~X86_CR4_VMXE;
2998 if ((pCtx->cr4 & mask) != mask)
2999 return false;
3000
3001 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
3002 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
3003 if ((pCtx->cr4 & mask) != 0)
3004 return false;
3005
3006 pVCpu->hm.s.fActive = true;
3007 return true;
3008 }
3009
3010 return false;
3011}
3012
3013
3014/**
3015 * Checks if we need to reschedule due to VMM device heap changes.
3016 *
3017 * @returns true if a reschedule is required, otherwise false.
3018 * @param pVM The cross context VM structure.
3019 * @param pCtx VM execution context.
3020 */
3021VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
3022{
3023 /*
3024 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
3025 * when the unrestricted guest execution feature is missing (VT-x only).
3026 */
3027 if ( pVM->hm.s.vmx.fEnabled
3028 && !pVM->hm.s.vmx.fUnrestrictedGuest
3029 && CPUMIsGuestInRealModeEx(pCtx)
3030 && !PDMVmmDevHeapIsEnabled(pVM))
3031 {
3032 return true;
3033 }
3034
3035 return false;
3036}
3037
3038
3039/**
3040 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
3041 * event settings changes.
3042 *
3043 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
3044 * function is just updating the VM globals.
3045 *
3046 * @param pVM The VM cross context VM structure.
3047 * @thread EMT(0)
3048 */
3049VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
3050{
3051 /* Interrupts. */
3052 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
3053 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
3054
3055 /* CPU Exceptions. */
3056 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
3057 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
3058 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3059 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3060
3061 /* Common VM exits. */
3062 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
3063 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
3064 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3065 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3066
3067 /* Vendor specific VM exits. */
3068 if (HMR3IsVmxEnabled(pVM->pUVM))
3069 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
3070 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
3071 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3072 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3073 else
3074 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
3075 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
3076 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3077 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3078
3079 /* Done. */
3080 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
3081}
3082
3083
3084/**
3085 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
3086 *
3087 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
3088 * per CPU settings.
3089 *
3090 * @param pVM The VM cross context VM structure.
3091 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3092 */
3093VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
3094{
3095 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
3096}
3097
3098
3099/**
3100 * Notification from EM about a rescheduling into hardware assisted execution
3101 * mode.
3102 *
3103 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3104 */
3105VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
3106{
3107 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3108}
3109
3110
3111/**
3112 * Notification from EM about returning from instruction emulation (REM / EM).
3113 *
3114 * @param pVCpu The cross context virtual CPU structure.
3115 */
3116VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
3117{
3118 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3119}
3120
3121
3122/**
3123 * Checks if we are currently using hardware acceleration.
3124 *
3125 * @returns true if hardware acceleration is being used, otherwise false.
3126 * @param pVCpu The cross context virtual CPU structure.
3127 */
3128VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
3129{
3130 return pVCpu->hm.s.fActive;
3131}
3132
3133
3134/**
3135 * External interface for querying whether hardware acceleration is enabled.
3136 *
3137 * @returns true if VT-x or AMD-V is being used, otherwise false.
3138 * @param pUVM The user mode VM handle.
3139 * @sa HMIsEnabled, HMIsEnabledNotMacro.
3140 */
3141VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
3142{
3143 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3144 PVM pVM = pUVM->pVM;
3145 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3146 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
3147}
3148
3149
3150/**
3151 * External interface for querying whether VT-x is being used.
3152 *
3153 * @returns true if VT-x is being used, otherwise false.
3154 * @param pUVM The user mode VM handle.
3155 * @sa HMR3IsSvmEnabled, HMIsEnabled
3156 */
3157VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
3158{
3159 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3160 PVM pVM = pUVM->pVM;
3161 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3162 return pVM->hm.s.vmx.fEnabled
3163 && pVM->hm.s.vmx.fSupported
3164 && pVM->fHMEnabled;
3165}
3166
3167
3168/**
3169 * External interface for querying whether AMD-V is being used.
3170 *
3171 * @returns true if VT-x is being used, otherwise false.
3172 * @param pUVM The user mode VM handle.
3173 * @sa HMR3IsVmxEnabled, HMIsEnabled
3174 */
3175VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3176{
3177 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3178 PVM pVM = pUVM->pVM;
3179 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3180 return pVM->hm.s.svm.fEnabled
3181 && pVM->hm.s.svm.fSupported
3182 && pVM->fHMEnabled;
3183}
3184
3185
3186/**
3187 * Checks if we are currently using nested paging.
3188 *
3189 * @returns true if nested paging is being used, otherwise false.
3190 * @param pUVM The user mode VM handle.
3191 */
3192VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3193{
3194 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3195 PVM pVM = pUVM->pVM;
3196 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3197 return pVM->hm.s.fNestedPaging;
3198}
3199
3200
3201/**
3202 * Checks if virtualized APIC registers is enabled.
3203 *
3204 * When enabled this feature allows the hardware to access most of the
3205 * APIC registers in the virtual-APIC page without causing VM-exits. See
3206 * Intel spec. 29.1.1 "Virtualized APIC Registers".
3207 *
3208 * @returns true if virtualized APIC registers is enabled, otherwise
3209 * false.
3210 * @param pUVM The user mode VM handle.
3211 */
3212VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3213{
3214 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3215 PVM pVM = pUVM->pVM;
3216 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3217 return pVM->hm.s.fVirtApicRegs;
3218}
3219
3220
3221/**
3222 * Checks if APIC posted-interrupt processing is enabled.
3223 *
3224 * This returns whether we can deliver interrupts to the guest without
3225 * leaving guest-context by updating APIC state from host-context.
3226 *
3227 * @returns true if APIC posted-interrupt processing is enabled,
3228 * otherwise false.
3229 * @param pUVM The user mode VM handle.
3230 */
3231VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3232{
3233 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3234 PVM pVM = pUVM->pVM;
3235 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3236 return pVM->hm.s.fPostedIntrs;
3237}
3238
3239
3240/**
3241 * Checks if we are currently using VPID in VT-x mode.
3242 *
3243 * @returns true if VPID is being used, otherwise false.
3244 * @param pUVM The user mode VM handle.
3245 */
3246VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3247{
3248 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3249 PVM pVM = pUVM->pVM;
3250 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3251 return pVM->hm.s.vmx.fVpid;
3252}
3253
3254
3255/**
3256 * Checks if we are currently using VT-x unrestricted execution,
3257 * aka UX.
3258 *
3259 * @returns true if UX is being used, otherwise false.
3260 * @param pUVM The user mode VM handle.
3261 */
3262VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3263{
3264 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3265 PVM pVM = pUVM->pVM;
3266 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3267 return pVM->hm.s.vmx.fUnrestrictedGuest;
3268}
3269
3270
3271/**
3272 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3273 *
3274 * @returns true if an internal event is pending, otherwise false.
3275 * @param pVCpu The cross context virtual CPU structure.
3276 */
3277VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3278{
3279 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3280}
3281
3282
3283/**
3284 * Checks if the VMX-preemption timer is being used.
3285 *
3286 * @returns true if the VMX-preemption timer is being used, otherwise false.
3287 * @param pVM The cross context VM structure.
3288 */
3289VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3290{
3291 return HMIsEnabled(pVM)
3292 && pVM->hm.s.vmx.fEnabled
3293 && pVM->hm.s.vmx.fUsePreemptTimer;
3294}
3295
3296
3297/**
3298 * Restart an I/O instruction that was refused in ring-0
3299 *
3300 * @returns Strict VBox status code. Informational status codes other than the one documented
3301 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3302 * @retval VINF_SUCCESS Success.
3303 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3304 * status code must be passed on to EM.
3305 * @retval VERR_NOT_FOUND if no pending I/O instruction.
3306 *
3307 * @param pVM The cross context VM structure.
3308 * @param pVCpu The cross context virtual CPU structure.
3309 * @param pCtx Pointer to the guest CPU context.
3310 */
3311VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3312{
3313 /*
3314 * Check if we've got relevant data pending.
3315 */
3316 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3317 if (enmType == HMPENDINGIO_INVALID)
3318 return VERR_NOT_FOUND;
3319 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3320 if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
3321 return VERR_NOT_FOUND;
3322
3323 /*
3324 * Execute pending I/O.
3325 */
3326 VBOXSTRICTRC rcStrict;
3327 switch (enmType)
3328 {
3329 case HMPENDINGIO_PORT_READ:
3330 {
3331 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3332 uint32_t u32Val = 0;
3333
3334 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3335 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3336 if (IOM_SUCCESS(rcStrict))
3337 {
3338 /* Write back to the EAX register. */
3339 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3340 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3341 }
3342 break;
3343 }
3344
3345 default:
3346 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3347 }
3348
3349 if (IOM_SUCCESS(rcStrict))
3350 {
3351 /*
3352 * Check for I/O breakpoints.
3353 */
3354 uint32_t const uDr7 = pCtx->dr[7];
3355 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3356 && X86_DR7_ANY_RW_IO(uDr7)
3357 && (pCtx->cr4 & X86_CR4_DE))
3358 || DBGFBpIsHwIoArmed(pVM))
3359 {
3360 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3361 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3362 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3363 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3364 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3365 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
3366 rcStrict = rcStrict2;
3367 }
3368 }
3369 return rcStrict;
3370}
3371
3372
3373/**
3374 * Check fatal VT-x/AMD-V error and produce some meaningful
3375 * log release message.
3376 *
3377 * @param pVM The cross context VM structure.
3378 * @param iStatusCode VBox status code.
3379 */
3380VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3381{
3382 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3383 {
3384 PVMCPU pVCpu = &pVM->aCpus[i];
3385 switch (iStatusCode)
3386 {
3387 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3388 * might be getting inaccurate values for non-guru'ing EMTs. */
3389 case VERR_VMX_INVALID_VMCS_FIELD:
3390 break;
3391
3392 case VERR_VMX_INVALID_VMCS_PTR:
3393 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3394 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3395 pVCpu->hm.s.vmx.HCPhysVmcs));
3396 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3397 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3398 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3399 break;
3400
3401 case VERR_VMX_UNABLE_TO_START_VM:
3402 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3403 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3404 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3405
3406 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3407 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3408 {
3409 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3410 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3411 }
3412 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3413 {
3414 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3415 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3416 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3417 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3418 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3419 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3420 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3421 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3422 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3423 }
3424 /** @todo Log VM-entry event injection control fields
3425 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3426 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3427 break;
3428
3429 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3430 case VERR_VMX_INVALID_VMXON_PTR:
3431 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3432 case VERR_VMX_INVALID_GUEST_STATE:
3433 case VERR_VMX_UNEXPECTED_EXIT:
3434 case VERR_SVM_UNKNOWN_EXIT:
3435 case VERR_SVM_UNEXPECTED_EXIT:
3436 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3437 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3438 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3439 break;
3440 }
3441 }
3442
3443 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3444 {
3445 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3446 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3447 }
3448 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3449 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3450}
3451
3452
3453/**
3454 * Execute state save operation.
3455 *
3456 * @returns VBox status code.
3457 * @param pVM The cross context VM structure.
3458 * @param pSSM SSM operation handle.
3459 */
3460static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3461{
3462 int rc;
3463
3464 Log(("hmR3Save:\n"));
3465
3466 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3467 {
3468 /*
3469 * Save the basic bits - fortunately all the other things can be resynced on load.
3470 */
3471 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3472 AssertRCReturn(rc, rc);
3473 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3474 AssertRCReturn(rc, rc);
3475 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
3476 AssertRCReturn(rc, rc);
3477 /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
3478
3479 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3480 * perhaps not even that (the initial value of @c true is safe. */
3481 uint32_t u32Dummy = PGMMODE_REAL;
3482 rc = SSMR3PutU32(pSSM, u32Dummy);
3483 AssertRCReturn(rc, rc);
3484 rc = SSMR3PutU32(pSSM, u32Dummy);
3485 AssertRCReturn(rc, rc);
3486 rc = SSMR3PutU32(pSSM, u32Dummy);
3487 AssertRCReturn(rc, rc);
3488 }
3489
3490#ifdef VBOX_HM_WITH_GUEST_PATCHING
3491 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3492 AssertRCReturn(rc, rc);
3493 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3494 AssertRCReturn(rc, rc);
3495 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3496 AssertRCReturn(rc, rc);
3497
3498 /* Store all the guest patch records too. */
3499 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3500 AssertRCReturn(rc, rc);
3501
3502 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3503 {
3504 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3505
3506 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3507 AssertRCReturn(rc, rc);
3508
3509 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3510 AssertRCReturn(rc, rc);
3511
3512 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3513 AssertRCReturn(rc, rc);
3514
3515 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3516 AssertRCReturn(rc, rc);
3517
3518 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3519 AssertRCReturn(rc, rc);
3520
3521 AssertCompileSize(HMTPRINSTR, 4);
3522 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3523 AssertRCReturn(rc, rc);
3524
3525 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3526 AssertRCReturn(rc, rc);
3527
3528 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3529 AssertRCReturn(rc, rc);
3530
3531 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3532 AssertRCReturn(rc, rc);
3533
3534 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3535 AssertRCReturn(rc, rc);
3536 }
3537#endif
3538 return VINF_SUCCESS;
3539}
3540
3541
3542/**
3543 * Execute state load operation.
3544 *
3545 * @returns VBox status code.
3546 * @param pVM The cross context VM structure.
3547 * @param pSSM SSM operation handle.
3548 * @param uVersion Data layout version.
3549 * @param uPass The data pass.
3550 */
3551static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3552{
3553 int rc;
3554
3555 Log(("hmR3Load:\n"));
3556 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3557
3558 /*
3559 * Validate version.
3560 */
3561 if ( uVersion != HM_SAVED_STATE_VERSION
3562 && uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3563 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3564 {
3565 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3566 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3567 }
3568 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3569 {
3570 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3571 AssertRCReturn(rc, rc);
3572 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3573 AssertRCReturn(rc, rc);
3574 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3575 AssertRCReturn(rc, rc);
3576
3577 if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3578 {
3579 uint32_t val;
3580 /** @todo See note in hmR3Save(). */
3581 rc = SSMR3GetU32(pSSM, &val);
3582 AssertRCReturn(rc, rc);
3583 rc = SSMR3GetU32(pSSM, &val);
3584 AssertRCReturn(rc, rc);
3585 rc = SSMR3GetU32(pSSM, &val);
3586 AssertRCReturn(rc, rc);
3587 }
3588 }
3589#ifdef VBOX_HM_WITH_GUEST_PATCHING
3590 if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3591 {
3592 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3593 AssertRCReturn(rc, rc);
3594 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3595 AssertRCReturn(rc, rc);
3596 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3597 AssertRCReturn(rc, rc);
3598
3599 /* Fetch all TPR patch records. */
3600 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3601 AssertRCReturn(rc, rc);
3602
3603 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3604 {
3605 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3606
3607 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3608 AssertRCReturn(rc, rc);
3609
3610 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3611 AssertRCReturn(rc, rc);
3612
3613 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3614 AssertRCReturn(rc, rc);
3615
3616 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3617 AssertRCReturn(rc, rc);
3618
3619 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3620 AssertRCReturn(rc, rc);
3621
3622 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3623 AssertRCReturn(rc, rc);
3624
3625 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3626 pVM->hm.s.fTPRPatchingActive = true;
3627
3628 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3629
3630 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3631 AssertRCReturn(rc, rc);
3632
3633 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3634 AssertRCReturn(rc, rc);
3635
3636 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3637 AssertRCReturn(rc, rc);
3638
3639 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3640 AssertRCReturn(rc, rc);
3641
3642 Log(("hmR3Load: patch %d\n", i));
3643 Log(("Key = %x\n", pPatch->Core.Key));
3644 Log(("cbOp = %d\n", pPatch->cbOp));
3645 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3646 Log(("type = %d\n", pPatch->enmType));
3647 Log(("srcop = %d\n", pPatch->uSrcOperand));
3648 Log(("dstop = %d\n", pPatch->uDstOperand));
3649 Log(("cFaults = %d\n", pPatch->cFaults));
3650 Log(("target = %x\n", pPatch->pJumpTarget));
3651 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3652 AssertRC(rc);
3653 }
3654 }
3655#endif
3656
3657 return VINF_SUCCESS;
3658}
3659
3660
3661/**
3662 * Displays the guest VM-exit history.
3663 *
3664 * @param pVM The cross context VM structure.
3665 * @param pHlp The info helper functions.
3666 * @param pszArgs Arguments, ignored.
3667 */
3668static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3669{
3670 NOREF(pszArgs);
3671 PVMCPU pVCpu = VMMGetCpu(pVM);
3672 if (!pVCpu)
3673 pVCpu = &pVM->aCpus[0];
3674
3675 if (HMIsEnabled(pVM))
3676 {
3677 bool const fIsVtx = pVM->hm.s.vmx.fSupported;
3678 const char * const *papszDesc;
3679 unsigned cMaxExitDesc;
3680 if (fIsVtx)
3681 {
3682 cMaxExitDesc = MAX_EXITREASON_VTX;
3683 papszDesc = &g_apszVTxExitReasons[0];
3684 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x VM-exit history:\n", pVCpu->idCpu);
3685 }
3686 else
3687 {
3688 cMaxExitDesc = MAX_EXITREASON_AMDV;
3689 papszDesc = &g_apszAmdVExitReasons[0];
3690 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V #VMEXIT history:\n", pVCpu->idCpu);
3691 }
3692
3693 pHlp->pfnPrintf(pHlp, " idxExitHistoryFree = %u\n", pVCpu->hm.s.idxExitHistoryFree);
3694 unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
3695 pVCpu->hm.s.idxExitHistoryFree - 1 :
3696 RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
3697 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); i++)
3698 {
3699 uint16_t const uExit = pVCpu->hm.s.auExitHistory[i];
3700 const char *pszExit = NULL;
3701 if (uExit <= cMaxExitDesc)
3702 pszExit = papszDesc[uExit];
3703 else if (!fIsVtx)
3704 pszExit = hmSvmGetSpecialExitReasonDesc(uExit);
3705 else
3706 pszExit = NULL;
3707
3708 pHlp->pfnPrintf(pHlp, " auExitHistory[%2u] = 0x%04x %s %s\n", i, uExit, pszExit,
3709 idxLast == i ? "<-- Latest exit" : "");
3710 }
3711 pHlp->pfnPrintf(pHlp, "HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3712 }
3713 else
3714 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3715}
3716
3717
3718/**
3719 * Displays the HM pending event.
3720 *
3721 * @param pVM The cross context VM structure.
3722 * @param pHlp The info helper functions.
3723 * @param pszArgs Arguments, ignored.
3724 */
3725static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3726{
3727 NOREF(pszArgs);
3728 PVMCPU pVCpu = VMMGetCpu(pVM);
3729 if (!pVCpu)
3730 pVCpu = &pVM->aCpus[0];
3731
3732 if (HMIsEnabled(pVM))
3733 {
3734 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3735 if (pVCpu->hm.s.Event.fPending)
3736 {
3737 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3738 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3739 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3740 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3741 }
3742 }
3743 else
3744 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3745}
3746
3747
3748/**
3749 * Displays the SVM nested-guest VMCB cache.
3750 *
3751 * @param pVM The cross context VM structure.
3752 * @param pHlp The info helper functions.
3753 * @param pszArgs Arguments, ignored.
3754 */
3755static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3756{
3757 NOREF(pszArgs);
3758 PVMCPU pVCpu = VMMGetCpu(pVM);
3759 if (!pVCpu)
3760 pVCpu = &pVM->aCpus[0];
3761
3762 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3763 if ( fSvmEnabled
3764 && pVM->cpum.ro.GuestFeatures.fSvm)
3765 {
3766 PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
3767 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3768 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3769 pHlp->pfnPrintf(pHlp, " fHMCachedVmcb = %#RTbool\n", pCtx->hwvirt.svm.fHMCachedVmcb);
3770 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3771 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3772 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3773 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3774 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3775 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3776 pHlp->pfnPrintf(pHlp, " u64IOPMPhysAddr = %#RX64\n", pVmcbNstGstCache->u64IOPMPhysAddr);
3777 pHlp->pfnPrintf(pHlp, " u64MSRPMPhysAddr = %#RX64\n", pVmcbNstGstCache->u64MSRPMPhysAddr);
3778 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3779 pHlp->pfnPrintf(pHlp, " u32VmcbCleanBits = %#RX32\n", pVmcbNstGstCache->u32VmcbCleanBits);
3780 pHlp->pfnPrintf(pHlp, " TLBCtrl = %#RX64\n", pVmcbNstGstCache->TLBCtrl);
3781 pHlp->pfnPrintf(pHlp, " u32ASID = %#RX64\n", pVmcbNstGstCache->TLBCtrl.n.u32ASID);
3782 pHlp->pfnPrintf(pHlp, " u8TLBFlush = %#RX64\n", pVmcbNstGstCache->TLBCtrl.n.u8TLBFlush);
3783 pHlp->pfnPrintf(pHlp, " u1NestedPaging = %RTbool\n", pVmcbNstGstCache->u1NestedPaging);
3784 pHlp->pfnPrintf(pHlp, " u1LbrVirt = %RTbool\n", pVmcbNstGstCache->u1LbrVirt);
3785 pHlp->pfnPrintf(pHlp, " u64CR0 = %#RX64\n", pVmcbNstGstCache->u64CR0);
3786 pHlp->pfnPrintf(pHlp, " u64CR3 = %#RX64\n", pVmcbNstGstCache->u64CR3);
3787 pHlp->pfnPrintf(pHlp, " u64CR4 = %#RX64\n", pVmcbNstGstCache->u64CR4);
3788 pHlp->pfnPrintf(pHlp, " u64EFER = %#RX64\n", pVmcbNstGstCache->u64EFER);
3789 pHlp->pfnPrintf(pHlp, " u64DBGCTL = %#RX64\n", pVmcbNstGstCache->u64DBGCTL);
3790 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3791 }
3792 else
3793 {
3794 if (!fSvmEnabled)
3795 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3796 else
3797 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3798 }
3799}
3800
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