VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 76267

Last change on this file since 76267 was 76198, checked in by vboxsync, 6 years ago

VMM: Nested VMX: bugref:9180 Use Intel terminology of 'allowed-0' and 'allowed-1'.
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  • Property svn:keywords set to Id Revision
File size: 160.4 KB
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1/* $Id: HM.cpp 76198 2018-12-13 07:17:44Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#define VMCPU_INCL_CPUM_GST_CTX
41#include <VBox/vmm/cpum.h>
42#include <VBox/vmm/stam.h>
43#include <VBox/vmm/mm.h>
44#include <VBox/vmm/em.h>
45#include <VBox/vmm/pdmapi.h>
46#include <VBox/vmm/pgm.h>
47#include <VBox/vmm/ssm.h>
48#include <VBox/vmm/trpm.h>
49#include <VBox/vmm/dbgf.h>
50#include <VBox/vmm/iom.h>
51#include <VBox/vmm/iem.h>
52#include <VBox/vmm/patm.h>
53#include <VBox/vmm/csam.h>
54#include <VBox/vmm/selm.h>
55#include <VBox/vmm/nem.h>
56#ifdef VBOX_WITH_REM
57# include <VBox/vmm/rem.h>
58#endif
59#include <VBox/vmm/hm_vmx.h>
60#include <VBox/vmm/hm_svm.h>
61#include "HMInternal.h"
62#include <VBox/vmm/vm.h>
63#include <VBox/vmm/uvm.h>
64#include <VBox/err.h>
65#include <VBox/param.h>
66
67#include <iprt/assert.h>
68#include <VBox/log.h>
69#include <iprt/asm.h>
70#include <iprt/asm-amd64-x86.h>
71#include <iprt/env.h>
72#include <iprt/thread.h>
73
74
75/*********************************************************************************************************************************
76* Global Variables *
77*********************************************************************************************************************************/
78#define EXIT_REASON(def, val, str) #def " - " #val " - " str
79#define EXIT_REASON_NIL() NULL
80/** Exit reason descriptions for VT-x, used to describe statistics and exit
81 * history. */
82static const char * const g_apszVmxExitReasons[MAX_EXITREASON_STAT] =
83{
84 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
85 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
86 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
87 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
88 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
89 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
90 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
91 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
92 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
93 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
94 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
95 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
96 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
97 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
98 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
99 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
100 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
101 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
102 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
103 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
104 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
105 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
106 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
107 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
108 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
109 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
110 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
111 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
112 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
113 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
114 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
115 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
116 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
117 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
118 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
119 EXIT_REASON_NIL(),
120 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
121 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
122 EXIT_REASON_NIL(),
123 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
124 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
125 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
126 EXIT_REASON_NIL(),
127 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
128 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
129 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
130 EXIT_REASON(VMX_EXIT_GDTR_IDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
131 EXIT_REASON(VMX_EXIT_LDTR_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
132 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
133 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
134 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
135 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
136 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
137 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
138 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
139 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
140 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
141 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
142 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
143 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
144 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instruction."),
145 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
146 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
147 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
148 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
149};
150/** Array index of the last valid VT-x exit reason. */
151#define MAX_EXITREASON_VTX 64
152
153/** A partial list of \#EXIT reason descriptions for AMD-V, used to describe
154 * statistics and exit history.
155 *
156 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
157 * this array doesn't contain the entire set of exit reasons, we
158 * handle them via hmSvmGetSpecialExitReasonDesc(). */
159static const char * const g_apszSvmExitReasons[MAX_EXITREASON_STAT] =
160{
161 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
162 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
163 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
164 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
165 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
166 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
167 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
168 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
169 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
170 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
171 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
172 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
173 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
174 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
175 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
176 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
187 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
188 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
189 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
190 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
191 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
192 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
193 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
194 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
195 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
196 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
197 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
198 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
199 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
200 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
201 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
202 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
203 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
204 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
205 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
206 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
207 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
208 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
219 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
220 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
221 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
222 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
223 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
224 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
225 EXIT_REASON(SVM_EXIT_XCPT_0 , 64, "Exception 0 (#DE)."),
226 EXIT_REASON(SVM_EXIT_XCPT_1 , 65, "Exception 1 (#DB)."),
227 EXIT_REASON(SVM_EXIT_XCPT_2 , 66, "Exception 2 (#NMI)."),
228 EXIT_REASON(SVM_EXIT_XCPT_3 , 67, "Exception 3 (#BP)."),
229 EXIT_REASON(SVM_EXIT_XCPT_4 , 68, "Exception 4 (#OF)."),
230 EXIT_REASON(SVM_EXIT_XCPT_5 , 69, "Exception 5 (#BR)."),
231 EXIT_REASON(SVM_EXIT_XCPT_6 , 70, "Exception 6 (#UD)."),
232 EXIT_REASON(SVM_EXIT_XCPT_7 , 71, "Exception 7 (#NM)."),
233 EXIT_REASON(SVM_EXIT_XCPT_8 , 72, "Exception 8 (#DF)."),
234 EXIT_REASON(SVM_EXIT_XCPT_9 , 73, "Exception 9 (#CO_SEG_OVERRUN)."),
235 EXIT_REASON(SVM_EXIT_XCPT_10 , 74, "Exception 10 (#TS)."),
236 EXIT_REASON(SVM_EXIT_XCPT_11 , 75, "Exception 11 (#NP)."),
237 EXIT_REASON(SVM_EXIT_XCPT_12 , 76, "Exception 12 (#SS)."),
238 EXIT_REASON(SVM_EXIT_XCPT_13 , 77, "Exception 13 (#GP)."),
239 EXIT_REASON(SVM_EXIT_XCPT_14 , 78, "Exception 14 (#PF)."),
240 EXIT_REASON(SVM_EXIT_XCPT_15 , 79, "Exception 15 (0x0f)."),
241 EXIT_REASON(SVM_EXIT_XCPT_16 , 80, "Exception 16 (#MF)."),
242 EXIT_REASON(SVM_EXIT_XCPT_17 , 81, "Exception 17 (#AC)."),
243 EXIT_REASON(SVM_EXIT_XCPT_18 , 82, "Exception 18 (#MC)."),
244 EXIT_REASON(SVM_EXIT_XCPT_19 , 83, "Exception 19 (#XF)."),
245 EXIT_REASON(SVM_EXIT_XCPT_20 , 84, "Exception 20 (#VE)."),
246 EXIT_REASON(SVM_EXIT_XCPT_21 , 85, "Exception 22 (0x15)."),
247 EXIT_REASON(SVM_EXIT_XCPT_22 , 86, "Exception 22 (0x16)."),
248 EXIT_REASON(SVM_EXIT_XCPT_23 , 87, "Exception 23 (0x17)."),
249 EXIT_REASON(SVM_EXIT_XCPT_24 , 88, "Exception 24 (0x18)."),
250 EXIT_REASON(SVM_EXIT_XCPT_25 , 89, "Exception 25 (0x19)."),
251 EXIT_REASON(SVM_EXIT_XCPT_26 , 90, "Exception 26 (0x1a)."),
252 EXIT_REASON(SVM_EXIT_XCPT_27 , 91, "Exception 27 (0x1b)."),
253 EXIT_REASON(SVM_EXIT_XCPT_28 , 92, "Exception 28 (0x1c)."),
254 EXIT_REASON(SVM_EXIT_XCPT_29 , 93, "Exception 29 (0x1d)."),
255 EXIT_REASON(SVM_EXIT_XCPT_30 , 94, "Exception 30 (#SX)."),
256 EXIT_REASON(SVM_EXIT_XCPT_31 , 95, "Exception 31 (0x1F)."),
257 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
258 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
259 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
260 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
261 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
262 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Selective CR0 Write (to bits other than CR0.TS and CR0.MP)."),
263 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR."),
264 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR."),
265 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
266 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
267 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
268 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
269 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
270 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
271 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
272 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
273 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
274 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
275 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
276 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
277 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
278 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
279 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
280 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
281 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
282 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
283 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
284 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT/INS/OUTS instruction."),
285 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
286 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
287 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "FERR Freeze; CPU frozen in an x87/mmx instruction waiting for interrupt."),
288 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
289 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
290 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
291 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
292 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
293 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
294 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
295 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
296 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
297 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
298 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
299 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
300 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
301 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
302 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
303};
304/** Array index of the last valid AMD-V exit reason. */
305#define MAX_EXITREASON_AMDV 141
306
307/** Special exit reasons not covered in the array above. */
308#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
309#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
310#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
311
312/**
313 * Gets the SVM exit reason if it's one of the reasons not present in the @c
314 * g_apszSvmExitReasons array.
315 *
316 * @returns The exit reason or NULL if unknown.
317 * @param uExit The exit.
318 */
319DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
320{
321 switch (uExit)
322 {
323 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
324 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
325 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
326 }
327 return EXIT_REASON_NIL();
328}
329#undef EXIT_REASON_NIL
330#undef EXIT_REASON
331
332/** @def HMVMX_REPORT_FEAT
333 * Reports VT-x feature to the release log.
334 *
335 * @param a_uAllowed1 Mask of allowed-1 feature bits.
336 * @param a_uAllowed0 Mask of allowed-0 feature bits.
337 * @param a_StrDesc The description string to report.
338 * @param a_Featflag Mask of the feature to report.
339 */
340#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
341 do { \
342 if ((a_uAllowed1) & (a_Featflag)) \
343 { \
344 if ((a_uAllowed0) & (a_Featflag)) \
345 LogRel(("HM: " a_StrDesc " (must be set)\n")); \
346 else \
347 LogRel(("HM: " a_StrDesc "\n")); \
348 } \
349 else \
350 LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
351 } while (0)
352
353/** @def HMVMX_REPORT_ALLOWED_FEAT
354 * Reports an allowed VT-x feature to the release log.
355 *
356 * @param a_uAllowed1 Mask of allowed-1 feature bits.
357 * @param a_StrDesc The description string to report.
358 * @param a_FeatFlag Mask of the feature to report.
359 */
360#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
361 do { \
362 if ((a_uAllowed1) & (a_FeatFlag)) \
363 LogRel(("HM: " a_StrDesc "\n")); \
364 else \
365 LogRel(("HM: " a_StrDesc " not supported\n")); \
366 } while (0)
367
368/** @def HMVMX_REPORT_MSR_CAP
369 * Reports MSR feature capability.
370 *
371 * @param a_MsrCaps Mask of MSR feature bits.
372 * @param a_StrDesc The description string to report.
373 * @param a_fCap Mask of the feature to report.
374 */
375#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
376 do { \
377 if ((a_MsrCaps) & (a_fCap)) \
378 LogRel(("HM: " a_StrDesc "\n")); \
379 } while (0)
380
381/** @def HMVMX_LOGREL_FEAT
382 * Dumps a feature flag from a bitmap of features to the release log.
383 *
384 * @param a_fVal The value of all the features.
385 * @param a_fMask The specific bitmask of the feature.
386 */
387#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
388 do { \
389 if ((a_fVal) & (a_fMask)) \
390 LogRel(("HM: %s\n", #a_fMask)); \
391 } while (0)
392
393
394/*********************************************************************************************************************************
395* Internal Functions *
396*********************************************************************************************************************************/
397static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
398static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
399static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
400static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
401static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
402static int hmR3InitCPU(PVM pVM);
403static int hmR3InitFinalizeR0(PVM pVM);
404static int hmR3InitFinalizeR0Intel(PVM pVM);
405static int hmR3InitFinalizeR0Amd(PVM pVM);
406static int hmR3TermCPU(PVM pVM);
407
408
409
410/**
411 * Initializes the HM.
412 *
413 * This is the very first component to really do init after CFGM so that we can
414 * establish the predominant execution engine for the VM prior to initializing
415 * other modules. It takes care of NEM initialization if needed (HM disabled or
416 * not available in HW).
417 *
418 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
419 * hypervisor API via NEM, and then back on raw-mode if that isn't available
420 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
421 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
422 * X, OS/2 and others).
423 *
424 * Note that a lot of the set up work is done in ring-0 and thus postponed till
425 * the ring-3 and ring-0 callback to HMR3InitCompleted.
426 *
427 * @returns VBox status code.
428 * @param pVM The cross context VM structure.
429 *
430 * @remarks Be careful with what we call here, since most of the VMM components
431 * are uninitialized.
432 */
433VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
434{
435 LogFlow(("HMR3Init\n"));
436
437 /*
438 * Assert alignment and sizes.
439 */
440 AssertCompileMemberAlignment(VM, hm.s, 32);
441 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
442
443 /*
444 * Register the saved state data unit.
445 */
446 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
447 NULL, NULL, NULL,
448 NULL, hmR3Save, NULL,
449 NULL, hmR3Load, NULL);
450 if (RT_FAILURE(rc))
451 return rc;
452
453 /*
454 * Register info handlers.
455 */
456 rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
457 AssertRCReturn(rc, rc);
458
459 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
460 DBGFINFO_FLAGS_ALL_EMTS);
461 AssertRCReturn(rc, rc);
462
463 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
464 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
465 AssertRCReturn(rc, rc);
466
467 /*
468 * Read configuration.
469 */
470 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
471
472 /*
473 * Validate the HM settings.
474 */
475 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
476 "HMForced"
477 "|UseNEMInstead"
478 "|FallbackToNEM"
479 "|EnableNestedPaging"
480 "|EnableUX"
481 "|EnableLargePages"
482 "|EnableVPID"
483 "|IBPBOnVMExit"
484 "|IBPBOnVMEntry"
485 "|SpecCtrlByHost"
486 "|TPRPatchingEnabled"
487 "|64bitEnabled"
488 "|Exclusive"
489 "|MaxResumeLoops"
490 "|VmxPleGap"
491 "|VmxPleWindow"
492 "|UseVmxPreemptTimer"
493 "|SvmPauseFilter"
494 "|SvmPauseFilterThreshold"
495 "|SvmVirtVmsaveVmload"
496 "|SvmVGif"
497 "|LovelyMesaDrvWorkaround",
498 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
499 if (RT_FAILURE(rc))
500 return rc;
501
502 /** @cfgm{/HM/HMForced, bool, false}
503 * Forces hardware virtualization, no falling back on raw-mode. HM must be
504 * enabled, i.e. /HMEnabled must be true. */
505 bool fHMForced;
506#ifdef VBOX_WITH_RAW_MODE
507 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
508 AssertRCReturn(rc, rc);
509 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
510 VERR_INVALID_PARAMETER);
511# if defined(RT_OS_DARWIN)
512 if (pVM->fHMEnabled)
513 fHMForced = true;
514# endif
515 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
516 VERR_INVALID_PARAMETER);
517 if (pVM->cCpus > 1)
518 fHMForced = true;
519#else /* !VBOX_WITH_RAW_MODE */
520 AssertRelease(pVM->fHMEnabled);
521 fHMForced = true;
522#endif /* !VBOX_WITH_RAW_MODE */
523
524 /** @cfgm{/HM/UseNEMInstead, bool, true}
525 * Don't use HM, use NEM instead. */
526 bool fUseNEMInstead = false;
527 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
528 AssertRCReturn(rc, rc);
529 if (fUseNEMInstead && pVM->fHMEnabled)
530 {
531 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
532 pVM->fHMEnabled = false;
533 }
534
535 /** @cfgm{/HM/FallbackToNEM, bool, true}
536 * Enables fallback on NEM. */
537 bool fFallbackToNEM = true;
538 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
539 AssertRCReturn(rc, rc);
540
541 /** @cfgm{/HM/EnableNestedPaging, bool, false}
542 * Enables nested paging (aka extended page tables). */
543 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
544 AssertRCReturn(rc, rc);
545
546 /** @cfgm{/HM/EnableUX, bool, true}
547 * Enables the VT-x unrestricted execution feature. */
548 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
549 AssertRCReturn(rc, rc);
550
551 /** @cfgm{/HM/EnableLargePages, bool, false}
552 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
553 * page table walking and maybe better TLB hit rate in some cases. */
554 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
555 AssertRCReturn(rc, rc);
556
557 /** @cfgm{/HM/EnableVPID, bool, false}
558 * Enables the VT-x VPID feature. */
559 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
560 AssertRCReturn(rc, rc);
561
562 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
563 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
564 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
565 AssertRCReturn(rc, rc);
566
567 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
568 * Enables AMD64 cpu features.
569 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
570 * already have the support. */
571#ifdef VBOX_ENABLE_64_BITS_GUESTS
572 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
573 AssertLogRelRCReturn(rc, rc);
574#else
575 pVM->hm.s.fAllow64BitGuests = false;
576#endif
577
578 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
579 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
580 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
581 * latest PAUSE instruction to be start of a new PAUSE loop.
582 */
583 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
584 AssertRCReturn(rc, rc);
585
586 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
587 * The pause-filter exiting window in TSC ticks. When the number of ticks
588 * between the current PAUSE instruction and first PAUSE of a loop exceeds
589 * VmxPleWindow, a VM-exit is triggered.
590 *
591 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
592 */
593 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
594 AssertRCReturn(rc, rc);
595
596 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
597 * A counter that is decrement each time a PAUSE instruction is executed by the
598 * guest. When the counter is 0, a \#VMEXIT is triggered.
599 *
600 * Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
601 */
602 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
603 AssertRCReturn(rc, rc);
604
605 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
606 * The pause filter threshold in ticks. When the elapsed time (in ticks) between
607 * two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
608 * PauseFilter count is reset to its initial value. However, if PAUSE is
609 * executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
610 * be triggered.
611 *
612 * Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
613 * activated.
614 */
615 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
616 AssertRCReturn(rc, rc);
617
618 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
619 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
620 * available. */
621 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
622 AssertRCReturn(rc, rc);
623
624 /** @cfgm{/HM/SvmVGif, bool, true}
625 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
626 * if it's available. */
627 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
628 AssertRCReturn(rc, rc);
629
630 /** @cfgm{/HM/Exclusive, bool}
631 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
632 * global init for each host CPU. If false, we do local init each time we wish
633 * to execute guest code.
634 *
635 * On Windows, default is false due to the higher risk of conflicts with other
636 * hypervisors.
637 *
638 * On Mac OS X, this setting is ignored since the code does not handle local
639 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
640 */
641#if defined(RT_OS_DARWIN)
642 pVM->hm.s.fGlobalInit = true;
643#else
644 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
645# if defined(RT_OS_WINDOWS)
646 false
647# else
648 true
649# endif
650 );
651 AssertLogRelRCReturn(rc, rc);
652#endif
653
654 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
655 * The number of times to resume guest execution before we forcibly return to
656 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
657 * determines the default value. */
658 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
659 AssertLogRelRCReturn(rc, rc);
660
661 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
662 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
663 * available. */
664 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
665 AssertLogRelRCReturn(rc, rc);
666
667 /** @cfgm{/HM/IBPBOnVMExit, bool}
668 * Costly paranoia setting. */
669 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
670 AssertLogRelRCReturn(rc, rc);
671
672 /** @cfgm{/HM/IBPBOnVMEntry, bool}
673 * Costly paranoia setting. */
674 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
675 AssertLogRelRCReturn(rc, rc);
676
677 /** @cfgm{/HM/SpecCtrlByHost, bool}
678 * Another expensive paranoia setting. */
679 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
680 AssertLogRelRCReturn(rc, rc);
681
682 /** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
683 * Workaround for mesa vmsvga 3d driver making incorrect assumptions about
684 * the hypervisor it is running under. */
685 bool f;
686 rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &f, false);
687 AssertLogRelRCReturn(rc, rc);
688 for (VMCPUID i = 0; i < pVM->cCpus; i++)
689 pVM->aCpus[i].hm.s.fTrapXcptGpForLovelyMesaDrv = f;
690
691 /*
692 * Check if VT-x or AMD-v support according to the users wishes.
693 */
694 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
695 * VERR_SVM_IN_USE. */
696 if (pVM->fHMEnabled)
697 {
698 uint32_t fCaps;
699 rc = SUPR3QueryVTCaps(&fCaps);
700 if (RT_SUCCESS(rc))
701 {
702 if (fCaps & SUPVTCAPS_AMD_V)
703 {
704 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
705 pVM->hm.s.svm.fSupported = true;
706 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
707 }
708 else if (fCaps & SUPVTCAPS_VT_X)
709 {
710 const char *pszWhy;
711 rc = SUPR3QueryVTxSupported(&pszWhy);
712 if (RT_SUCCESS(rc))
713 {
714 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
715 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
716 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
717 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
718 pVM->hm.s.vmx.fSupported = true;
719 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
720 }
721 else
722 {
723 /*
724 * Before failing, try fallback to NEM if we're allowed to do that.
725 */
726 pVM->fHMEnabled = false;
727 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
728 if (fFallbackToNEM)
729 {
730 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
731 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
732
733 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
734 if ( RT_SUCCESS(rc2)
735 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
736 rc = VINF_SUCCESS;
737 }
738 if (RT_FAILURE(rc))
739 {
740 if (fHMForced)
741 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
742
743 /* Fall back to raw-mode. */
744 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
745 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
746 }
747 }
748 }
749 else
750 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
751 VERR_INTERNAL_ERROR_5);
752
753 /*
754 * Do we require a little bit or raw-mode for 64-bit guest execution?
755 */
756 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
757 && pVM->fHMEnabled
758 && pVM->hm.s.fAllow64BitGuests;
759
760 /*
761 * Disable nested paging and unrestricted guest execution now if they're
762 * configured so that CPUM can make decisions based on our configuration.
763 */
764 Assert(!pVM->hm.s.fNestedPaging);
765 if (pVM->hm.s.fAllowNestedPaging)
766 {
767 if (fCaps & SUPVTCAPS_NESTED_PAGING)
768 pVM->hm.s.fNestedPaging = true;
769 else
770 pVM->hm.s.fAllowNestedPaging = false;
771 }
772
773 if (fCaps & SUPVTCAPS_VT_X)
774 {
775 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
776 if (pVM->hm.s.vmx.fAllowUnrestricted)
777 {
778 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
779 && pVM->hm.s.fNestedPaging)
780 pVM->hm.s.vmx.fUnrestrictedGuest = true;
781 else
782 pVM->hm.s.vmx.fAllowUnrestricted = false;
783 }
784 }
785 }
786 else
787 {
788 const char *pszMsg;
789 switch (rc)
790 {
791 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
792 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
793 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
794 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
795 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
796 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
797 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
798 default:
799 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
800 }
801
802 /*
803 * Before failing, try fallback to NEM if we're allowed to do that.
804 */
805 pVM->fHMEnabled = false;
806 if (fFallbackToNEM)
807 {
808 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
809 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
810 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
811 if ( RT_SUCCESS(rc2)
812 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
813 rc = VINF_SUCCESS;
814 }
815 if (RT_FAILURE(rc))
816 {
817 if (fHMForced)
818 return VM_SET_ERROR(pVM, rc, pszMsg);
819
820 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
821 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
822 }
823 }
824 }
825 else
826 {
827 /*
828 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
829 */
830 if (!fUseNEMInstead)
831 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
832 else
833 {
834 rc = NEMR3Init(pVM, false /*fFallback*/, true);
835 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
836 if (RT_FAILURE(rc))
837 return rc;
838 }
839 }
840
841 return VINF_SUCCESS;
842}
843
844
845/**
846 * Initializes the per-VCPU HM.
847 *
848 * @returns VBox status code.
849 * @param pVM The cross context VM structure.
850 */
851static int hmR3InitCPU(PVM pVM)
852{
853 LogFlow(("HMR3InitCPU\n"));
854
855 if (!HMIsEnabled(pVM))
856 return VINF_SUCCESS;
857
858 for (VMCPUID i = 0; i < pVM->cCpus; i++)
859 {
860 PVMCPU pVCpu = &pVM->aCpus[i];
861 pVCpu->hm.s.fActive = false;
862 }
863
864#ifdef VBOX_WITH_STATISTICS
865 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
866 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
867 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
868 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
869 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
870#endif
871
872 /*
873 * Statistics.
874 */
875 for (VMCPUID i = 0; i < pVM->cCpus; i++)
876 {
877 PVMCPU pVCpu = &pVM->aCpus[i];
878 int rc;
879
880#ifdef VBOX_WITH_STATISTICS
881 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
882 "Profiling of RTMpPokeCpu.",
883 "/PROF/CPU%d/HM/Poke", i);
884 AssertRC(rc);
885 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
886 "Profiling of poke wait.",
887 "/PROF/CPU%d/HM/PokeWait", i);
888 AssertRC(rc);
889 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
890 "Profiling of poke wait when RTMpPokeCpu fails.",
891 "/PROF/CPU%d/HM/PokeWaitFailed", i);
892 AssertRC(rc);
893 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
894 "Profiling of entry until entering GC.",
895 "/PROF/CPU%d/HM/Entry", i);
896 AssertRC(rc);
897 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPreExit, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
898 "Profiling of pre-exit processing after returning from GC.",
899 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
900 AssertRC(rc);
901 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitHandling, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
902 "Profiling of exit handling (longjmps not included!)",
903 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
904 AssertRC(rc);
905
906 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
907 "I/O.",
908 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
909 AssertRC(rc);
910 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
911 "MOV CRx.",
912 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
913 AssertRC(rc);
914 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
915 "Exceptions, NMIs.",
916 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
917 AssertRC(rc);
918
919 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatImportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
920 "Profiling of importing guest state from hardware after VM-exit.",
921 "/PROF/CPU%d/HM/ImportGuestState", i);
922 AssertRC(rc);
923 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExportGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
924 "Profiling of exporting guest state to hardware before VM-entry.",
925 "/PROF/CPU%d/HM/ExportGuestState", i);
926 AssertRC(rc);
927 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestFpuState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
928 "Profiling of CPUMR0LoadGuestFPU.",
929 "/PROF/CPU%d/HM/LoadGuestFpuState", i);
930 AssertRC(rc);
931 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
932 "Profiling of execution of guest-code in hardware.",
933 "/PROF/CPU%d/HM/InGC", i);
934 AssertRC(rc);
935
936# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
937 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
938 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
939 "/PROF/CPU%d/HM/Switcher3264", i);
940 AssertRC(rc);
941# endif
942
943# ifdef HM_PROFILE_EXIT_DISPATCH
944 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
945 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
946 "/PROF/CPU%d/HM/ExitDispatch", i);
947 AssertRC(rc);
948# endif
949
950#endif
951# define HM_REG_COUNTER(a, b, desc) \
952 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
953 AssertRC(rc);
954
955#ifdef VBOX_WITH_STATISTICS
956 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
957 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
958 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
959 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
960 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
961 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
962 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
963 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
964 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
965 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
966 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
967 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
968 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
969 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
970 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
971 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
972 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "HLT instruction.");
973 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "RDMSR instruction.");
974 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "WRMSR instruction.");
975 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "MWAIT instruction.");
976 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "MONITOR instruction.");
977 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR-Write", "Debug register write.");
978 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR-Read", "Debug register read.");
979 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR0", "CR0 read.");
980 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR2", "CR2 read.");
981 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR3", "CR3 read.");
982 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR4", "CR4 read.");
983 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Read, "/HM/CPU%d/Exit/Instr/CR-Read/CR8", "CR8 read.");
984 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR0Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR0", "CR0 write.");
985 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR2Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR2", "CR2 write.");
986 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR3Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR3", "CR3 write.");
987 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR4Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR4", "CR4 write.");
988 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCR8Write, "/HM/CPU%d/Exit/Instr/CR-Write/CR8", "CR8 write.");
989 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "CLTS instruction.");
990 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "LMSW instruction.");
991 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "CLI instruction.");
992 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "STI instruction.");
993 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "PUSHF instruction.");
994 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "POPF instruction.");
995 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "IRET instruction.");
996 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "INT instruction.");
997 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
998 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
999 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
1000 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
1001 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
1002 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
1003 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Physical maskable interrupt (host).");
1004#endif
1005 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
1006#ifdef VBOX_WITH_STATISTICS
1007 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
1008 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
1009 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Task switch.");
1010 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
1011 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
1012
1013 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
1014 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
1015 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
1016 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
1017 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
1018 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
1019 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
1020 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
1021 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
1022#endif
1023 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
1024#ifdef VBOX_WITH_STATISTICS
1025 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptExportHostState, "/HM/CPU%d/Switch/ExportHostState", "Preemption caused us to re-export the host state.");
1026
1027 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
1028 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
1029 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
1030 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
1031
1032 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
1033 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
1034 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
1035 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
1036 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
1037 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
1038 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
1039 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
1040 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
1041 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
1042 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
1043 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
1044 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
1045 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
1046
1047 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
1048 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
1049 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
1050
1051 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
1052 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
1053 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
1054
1055 HM_REG_COUNTER(&pVCpu->hm.s.StatExportMinimal, "/HM/CPU%d/Export/Minimal", "VM-entry exporting minimal guest-state.");
1056 HM_REG_COUNTER(&pVCpu->hm.s.StatExportFull, "/HM/CPU%d/Export/Full", "VM-entry exporting the full guest-state.");
1057 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadGuestFpu, "/HM/CPU%d/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
1058
1059 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
1060 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
1061 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelAttr, "/HM/CPU%d/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector limit.");
1062 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
1063 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
1064 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
1065 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
1066
1067#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1068 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
1069 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
1070#endif
1071
1072#undef HM_REG_COUNTER
1073
1074 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVmxExitReasons[0]
1075 : &g_apszSvmExitReasons[0];
1076
1077 /*
1078 * Guest Exit reason stats.
1079 */
1080 pVCpu->hm.s.paStatExitReason = NULL;
1081 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
1082 (void **)&pVCpu->hm.s.paStatExitReason);
1083 AssertRCReturn(rc, rc);
1084 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1085 {
1086 if (papszDesc[j])
1087 {
1088 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1089 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
1090 AssertRCReturn(rc, rc);
1091 }
1092 }
1093 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1094 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
1095 AssertRCReturn(rc, rc);
1096 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
1097# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1098 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1099# else
1100 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
1101# endif
1102
1103#ifdef VBOX_WITH_NESTED_HWVIRT_SVM
1104 /*
1105 * Nested-guest Exit reason stats.
1106 */
1107 pVCpu->hm.s.paStatNestedExitReason = NULL;
1108 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
1109 (void **)&pVCpu->hm.s.paStatNestedExitReason);
1110 AssertRCReturn(rc, rc);
1111 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1112 {
1113 if (papszDesc[j])
1114 {
1115 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1116 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
1117 AssertRC(rc);
1118 }
1119 }
1120 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1121 STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
1122 AssertRCReturn(rc, rc);
1123 pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
1124# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1125 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1126# else
1127 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
1128# endif
1129#endif
1130
1131 /*
1132 * Injected events stats.
1133 */
1134 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
1135 AssertRCReturn(rc, rc);
1136 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1137# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1138 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1139# else
1140 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1141# endif
1142 for (unsigned j = 0; j < 255; j++)
1143 {
1144 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1145 "Injected event.",
1146 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1147 }
1148
1149#endif /* VBOX_WITH_STATISTICS */
1150 }
1151
1152#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1153 /*
1154 * Magic marker for searching in crash dumps.
1155 */
1156 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1157 {
1158 PVMCPU pVCpu = &pVM->aCpus[i];
1159
1160 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1161 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1162 pCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
1163 }
1164#endif
1165
1166 return VINF_SUCCESS;
1167}
1168
1169
1170/**
1171 * Called when a init phase has completed.
1172 *
1173 * @returns VBox status code.
1174 * @param pVM The cross context VM structure.
1175 * @param enmWhat The phase that completed.
1176 */
1177VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1178{
1179 switch (enmWhat)
1180 {
1181 case VMINITCOMPLETED_RING3:
1182 return hmR3InitCPU(pVM);
1183 case VMINITCOMPLETED_RING0:
1184 return hmR3InitFinalizeR0(pVM);
1185 default:
1186 return VINF_SUCCESS;
1187 }
1188}
1189
1190
1191/**
1192 * Turns off normal raw mode features.
1193 *
1194 * @param pVM The cross context VM structure.
1195 */
1196static void hmR3DisableRawMode(PVM pVM)
1197{
1198/** @todo r=bird: HM shouldn't be doing this crap. */
1199 /* Reinit the paging mode to force the new shadow mode. */
1200 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1201 {
1202 PVMCPU pVCpu = &pVM->aCpus[i];
1203 PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1204 }
1205}
1206
1207
1208/**
1209 * Initialize VT-x or AMD-V.
1210 *
1211 * @returns VBox status code.
1212 * @param pVM The cross context VM structure.
1213 */
1214static int hmR3InitFinalizeR0(PVM pVM)
1215{
1216 int rc;
1217
1218 if (!HMIsEnabled(pVM))
1219 return VINF_SUCCESS;
1220
1221 /*
1222 * Hack to allow users to work around broken BIOSes that incorrectly set
1223 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1224 */
1225 if ( !pVM->hm.s.vmx.fSupported
1226 && !pVM->hm.s.svm.fSupported
1227 && pVM->hm.s.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1228 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1229 {
1230 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1231 pVM->hm.s.svm.fSupported = true;
1232 pVM->hm.s.svm.fIgnoreInUseError = true;
1233 pVM->hm.s.rcInit = VINF_SUCCESS;
1234 }
1235
1236 /*
1237 * Report ring-0 init errors.
1238 */
1239 if ( !pVM->hm.s.vmx.fSupported
1240 && !pVM->hm.s.svm.fSupported)
1241 {
1242 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.rcInit));
1243 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatCtrl));
1244 switch (pVM->hm.s.rcInit)
1245 {
1246 case VERR_VMX_IN_VMX_ROOT_MODE:
1247 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1248 case VERR_VMX_NO_VMX:
1249 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1250 case VERR_VMX_MSR_VMX_DISABLED:
1251 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1252 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1253 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1254 case VERR_VMX_MSR_LOCKING_FAILED:
1255 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1256 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1257 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1258 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1259 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1260
1261 case VERR_SVM_IN_USE:
1262 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1263 case VERR_SVM_NO_SVM:
1264 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1265 case VERR_SVM_DISABLED:
1266 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1267 }
1268 return VMSetError(pVM, pVM->hm.s.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.rcInit);
1269 }
1270
1271 /*
1272 * Enable VT-x or AMD-V on all host CPUs.
1273 */
1274 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1275 if (RT_FAILURE(rc))
1276 {
1277 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1278 HMR3CheckError(pVM, rc);
1279 return rc;
1280 }
1281
1282 /*
1283 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1284 * (Main should have taken care of this already)
1285 */
1286 if (!PDMHasIoApic(pVM))
1287 {
1288 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1289 pVM->hm.s.fTprPatchingAllowed = false;
1290 }
1291
1292 /*
1293 * Sync options.
1294 */
1295 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1296 * That will require a little bit of work, of course. */
1297 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1298 {
1299 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1300 PCPUMCTX pCpuCtx = &pVCpu->cpum.GstCtx;
1301 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1302 if (pVM->cpum.ro.HostFeatures.fIbpb)
1303 {
1304 if (pVM->hm.s.fIbpbOnVmExit)
1305 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1306 if (pVM->hm.s.fIbpbOnVmEntry)
1307 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1308 }
1309 if (iCpu == 0)
1310 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
1311 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
1312 }
1313
1314 /*
1315 * Do the vendor specific initialization
1316 *
1317 * Note! We disable release log buffering here since we're doing relatively
1318 * lot of logging and doesn't want to hit the disk with each LogRel
1319 * statement.
1320 */
1321 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1322 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1323 if (pVM->hm.s.vmx.fSupported)
1324 rc = hmR3InitFinalizeR0Intel(pVM);
1325 else
1326 rc = hmR3InitFinalizeR0Amd(pVM);
1327 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1328 RTLogRelSetBuffering(fOldBuffered);
1329 pVM->hm.s.fInitialized = true;
1330
1331 return rc;
1332}
1333
1334
1335/**
1336 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1337 */
1338static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1339{
1340 NOREF(pVM);
1341 NOREF(pvAllocation);
1342 NOREF(GCPhysAllocation);
1343}
1344
1345
1346/**
1347 * Returns a description of the VMCS (and associated regions') memory type given the
1348 * IA32_VMX_BASIC MSR.
1349 *
1350 * @returns The descriptive memory type.
1351 * @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1352 */
1353static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1354{
1355 uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1356 switch (uMemType)
1357 {
1358 case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1359 case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1360 }
1361 return "Unknown";
1362}
1363
1364
1365/**
1366 * Returns a single-line description of all the activity-states supported by the CPU
1367 * given the IA32_VMX_MISC MSR.
1368 *
1369 * @returns All supported activity states.
1370 * @param uMsrMisc IA32_VMX_MISC MSR value.
1371 */
1372static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1373{
1374 static const char * const s_apszActStates[] =
1375 {
1376 "",
1377 " ( HLT )",
1378 " ( SHUTDOWN )",
1379 " ( HLT SHUTDOWN )",
1380 " ( SIPI_WAIT )",
1381 " ( HLT SIPI_WAIT )",
1382 " ( SHUTDOWN SIPI_WAIT )",
1383 " ( HLT SHUTDOWN SIPI_WAIT )"
1384 };
1385 uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1386 Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1387 return s_apszActStates[idxActStates];
1388}
1389
1390
1391/**
1392 * Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1393 *
1394 * @param fFeatMsr The feature control MSR value.
1395 */
1396static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1397{
1398 uint64_t const val = fFeatMsr;
1399 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1400 HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1401 HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1402 HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1403 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1404 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1405 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1406 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1407 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1408 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1409 HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1410 HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1411 HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1412 HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1413 HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1414 if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1415 LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1416}
1417
1418
1419/**
1420 * Reports MSR_IA32_VMX_BASIC MSR to the log.
1421 *
1422 * @param uBasicMsr The VMX basic MSR value.
1423 */
1424static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1425{
1426 LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1427 LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1428 LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1429 LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1430 "< 4 GB" : "None"));
1431 LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1432 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1433 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1434 LogRel(("HM: Supports true capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1435}
1436
1437
1438/**
1439 * Reports MSR_IA32_PINBASED_CTLS to the log.
1440 *
1441 * @param pVmxMsr Pointer to the VMX MSR.
1442 */
1443static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1444{
1445 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1446 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1447 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1448 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1449 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1450 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1451 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1452 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1453}
1454
1455
1456/**
1457 * Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1458 *
1459 * @param pVmxMsr Pointer to the VMX MSR.
1460 */
1461static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1462{
1463 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1464 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1465 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1466 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1467 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1468 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1469 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1470 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1471 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1472 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1473 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1474 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1475 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1476 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1477 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1478 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1479 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1480 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1481 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1482 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1483 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1484 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1485 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1486 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1487}
1488
1489
1490/**
1491 * Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1492 *
1493 * @param pVmxMsr Pointer to the VMX MSR.
1494 */
1495static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1496{
1497 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1498 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1499 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1500 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1501 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1502 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1503 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1504 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1505 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1506 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1507 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1508 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1509 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1510 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1511 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1512 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1513 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1514 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1515 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1516 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1517 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1518 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_VE", VMX_PROC_CTLS2_EPT_VE);
1519 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_FROM_PT", VMX_PROC_CTLS2_CONCEAL_FROM_PT);
1520 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1521 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1522}
1523
1524
1525/**
1526 * Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1527 *
1528 * @param pVmxMsr Pointer to the VMX MSR.
1529 */
1530static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1531{
1532 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1533 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1534 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1535 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1536 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1537 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1538 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1539 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1540 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1541 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1542}
1543
1544
1545/**
1546 * Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1547 *
1548 * @param pVmxMsr Pointer to the VMX MSR.
1549 */
1550static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1551{
1552 uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1553 uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1554 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1555 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1556 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1557 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1558 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1559 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1560 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1561 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1562 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1563 HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1564}
1565
1566
1567/**
1568 * Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1569 *
1570 * @param fCaps The VMX EPT/VPID capability MSR value.
1571 */
1572static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1573{
1574 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1575 HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1576 HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1577 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1578 HMVMX_REPORT_MSR_CAP(fCaps, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1579 HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1580 HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1581 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1582 HMVMX_REPORT_MSR_CAP(fCaps, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1583 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1584 HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1585 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1586 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1587 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1588 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1589 HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1590}
1591
1592
1593/**
1594 * Reports MSR_IA32_VMX_MISC MSR to the log.
1595 *
1596 * @param pVM Pointer to the VM.
1597 * @param fMisc The VMX misc. MSR value.
1598 */
1599static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1600{
1601 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1602 uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1603 if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1604 LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1605 else
1606 {
1607 LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1608 pVM->hm.s.vmx.cPreemptTimerShift));
1609 }
1610 LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1611 LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1612 hmR3VmxGetActivityStateAllDesc(fMisc)));
1613 LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1614 LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1615 LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1616 LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1617 VMX_MISC_MAX_MSRS(fMisc)));
1618 LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1619 LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1620 LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1621 LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1622}
1623
1624
1625/**
1626 * Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1627 *
1628 * @param uVmcsEnum The VMX VMCS enum MSR value.
1629 */
1630static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1631{
1632 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1633 LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1634}
1635
1636
1637/**
1638 * Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1639 *
1640 * @param uVmFunc The VMX VMFUNC MSR value.
1641 */
1642static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1643{
1644 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1645 HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1646}
1647
1648
1649/**
1650 * Reports VMX CR0, CR4 fixed MSRs.
1651 *
1652 * @param pMsrs Pointer to the VMX MSRs.
1653 */
1654static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1655{
1656 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1657 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1658 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1659 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1660}
1661
1662
1663/**
1664 * Finish VT-x initialization (after ring-0 init).
1665 *
1666 * @returns VBox status code.
1667 * @param pVM The cross context VM structure.
1668 */
1669static int hmR3InitFinalizeR0Intel(PVM pVM)
1670{
1671 int rc;
1672
1673 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1674 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatCtrl != 0, VERR_HM_IPE_4);
1675
1676 LogRel(("HM: Using VT-x implementation 2.0\n"));
1677 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1678 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1679 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1680 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1681
1682 hmR3VmxReportFeatCtlMsr(pVM->hm.s.vmx.Msrs.u64FeatCtrl);
1683 hmR3VmxReportBasicMsr(pVM->hm.s.vmx.Msrs.u64Basic);
1684
1685 hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.PinCtls);
1686 hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.vmx.Msrs.ProcCtls);
1687 if (pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1688 hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.vmx.Msrs.ProcCtls2);
1689
1690 hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.vmx.Msrs.EntryCtls);
1691 hmR3VmxReportExitCtlsMsr(&pVM->hm.s.vmx.Msrs.ExitCtls);
1692
1693 if (RT_BF_GET(pVM->hm.s.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1694 {
1695 /* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1696 LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TruePinCtls));
1697 LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueProcCtls));
1698 LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueEntryCtls));
1699 LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.TrueExitCtls));
1700 }
1701
1702 hmR3VmxReportMiscMsr(pVM, pVM->hm.s.vmx.Msrs.u64Misc);
1703 hmR3VmxReportVmcsEnumMsr(pVM->hm.s.vmx.Msrs.u64VmcsEnum);
1704 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1705 hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.vmx.Msrs.u64EptVpidCaps);
1706 if (pVM->hm.s.vmx.Msrs.u64VmFunc)
1707 hmR3VmxReportVmFuncMsr(pVM->hm.s.vmx.Msrs.u64VmFunc);
1708 hmR3VmxReportCrFixedMsrs(&pVM->hm.s.vmx.Msrs);
1709
1710 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1711 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1712 {
1713 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1714 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1715 }
1716
1717 /*
1718 * EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1719 */
1720 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1721 || (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1722 VERR_HM_IPE_1);
1723 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1724 || ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1725 && pVM->hm.s.fNestedPaging),
1726 VERR_HM_IPE_1);
1727
1728 /*
1729 * Enable VPID if configured and supported.
1730 */
1731 if (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VPID)
1732 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1733
1734#if 0
1735 /*
1736 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1737 */
1738 if ( (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_APIC_REG_VIRT)
1739 && (pVM->hm.s.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_VIRT_INTR_DELIVERY))
1740 pVM->hm.s.fVirtApicRegs = true;
1741
1742 /*
1743 * Enable posted-interrupt processing if supported.
1744 */
1745 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1746 * here. */
1747 if ( (pVM->hm.s.vmx.Msrs.PinCtls.n.allowed1 & VMX_PIN_CTLS_POSTED_INT)
1748 && (pVM->hm.s.vmx.Msrs.ExitCtls.n.allowed1 & VMX_EXIT_CTLS_ACK_EXT_INT))
1749 pVM->hm.s.fPostedIntrs = true;
1750#endif
1751
1752 /*
1753 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1754 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1755 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1756 */
1757 if ( !(pVM->hm.s.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1758 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1759 {
1760 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1761 LogRel(("HM: Disabled RDTSCP\n"));
1762 }
1763
1764 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1765 {
1766 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1767 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1768 if (RT_SUCCESS(rc))
1769 {
1770 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1771 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1772 esp. Figure 20-5.*/
1773 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1774 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1775
1776 /* Bit set to 0 means software interrupts are redirected to the
1777 8086 program interrupt handler rather than switching to
1778 protected-mode handler. */
1779 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1780
1781 /* Allow all port IO, so that port IO instructions do not cause
1782 exceptions and would instead cause a VM-exit (based on VT-x's
1783 IO bitmap which we currently configure to always cause an exit). */
1784 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1785 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1786
1787 /*
1788 * Construct a 1024 element page directory with 4 MB pages for the identity mapped
1789 * page table used in real and protected mode without paging with EPT.
1790 */
1791 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1792 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1793 {
1794 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1795 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1796 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1797 | X86_PDE4M_G;
1798 }
1799
1800 /* We convert it here every time as PCI regions could be reconfigured. */
1801 if (PDMVmmDevHeapIsEnabled(pVM))
1802 {
1803 RTGCPHYS GCPhys;
1804 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1805 AssertRCReturn(rc, rc);
1806 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1807
1808 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1809 AssertRCReturn(rc, rc);
1810 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1811 }
1812 }
1813 else
1814 {
1815 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1816 pVM->hm.s.vmx.pRealModeTSS = NULL;
1817 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1818 return VMSetError(pVM, rc, RT_SRC_POS,
1819 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1820 }
1821 }
1822
1823 LogRel((pVM->hm.s.fAllow64BitGuests
1824 ? "HM: Guest support: 32-bit and 64-bit\n"
1825 : "HM: Guest support: 32-bit only\n"));
1826
1827 /*
1828 * Call ring-0 to set up the VM.
1829 */
1830 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1831 if (rc != VINF_SUCCESS)
1832 {
1833 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1834 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1835 {
1836 PVMCPU pVCpu = &pVM->aCpus[i];
1837 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1838 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1839 }
1840 HMR3CheckError(pVM, rc);
1841 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1842 }
1843
1844 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1845 LogRel(("HM: Enabled VMX\n"));
1846 pVM->hm.s.vmx.fEnabled = true;
1847
1848 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1849
1850 /*
1851 * Change the CPU features.
1852 */
1853 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1854 if (pVM->hm.s.fAllow64BitGuests)
1855 {
1856 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1857 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1858 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1859 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1860 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1861 }
1862 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1863 (we reuse the host EFER in the switcher). */
1864 /** @todo this needs to be fixed properly!! */
1865 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1866 {
1867 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1868 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1869 else
1870 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1871 }
1872
1873 /*
1874 * Log configuration details.
1875 */
1876 if (pVM->hm.s.fNestedPaging)
1877 {
1878 LogRel(("HM: Enabled nested paging\n"));
1879 if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1880 LogRel(("HM: EPT flush type = Single context\n"));
1881 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1882 LogRel(("HM: EPT flush type = All contexts\n"));
1883 else if (pVM->hm.s.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1884 LogRel(("HM: EPT flush type = Not supported\n"));
1885 else
1886 LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushEpt));
1887
1888 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1889 LogRel(("HM: Enabled unrestricted guest execution\n"));
1890
1891#if HC_ARCH_BITS == 64
1892 if (pVM->hm.s.fLargePages)
1893 {
1894 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1895 PGMSetLargePageUsage(pVM, true);
1896 LogRel(("HM: Enabled large page support\n"));
1897 }
1898#endif
1899 }
1900 else
1901 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1902
1903 if (pVM->hm.s.fVirtApicRegs)
1904 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1905
1906 if (pVM->hm.s.fPostedIntrs)
1907 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1908
1909 if (pVM->hm.s.vmx.fVpid)
1910 {
1911 LogRel(("HM: Enabled VPID\n"));
1912 if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1913 LogRel(("HM: VPID flush type = Individual addresses\n"));
1914 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1915 LogRel(("HM: VPID flush type = Single context\n"));
1916 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1917 LogRel(("HM: VPID flush type = All contexts\n"));
1918 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1919 LogRel(("HM: VPID flush type = Single context retain globals\n"));
1920 else
1921 LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.vmx.enmTlbFlushVpid));
1922 }
1923 else if (pVM->hm.s.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1924 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1925
1926 if (pVM->hm.s.vmx.fUsePreemptTimer)
1927 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1928 else
1929 LogRel(("HM: Disabled VMX-preemption timer\n"));
1930
1931 return VINF_SUCCESS;
1932}
1933
1934
1935/**
1936 * Finish AMD-V initialization (after ring-0 init).
1937 *
1938 * @returns VBox status code.
1939 * @param pVM The cross context VM structure.
1940 */
1941static int hmR3InitFinalizeR0Amd(PVM pVM)
1942{
1943 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1944
1945 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1946
1947 uint32_t u32Family;
1948 uint32_t u32Model;
1949 uint32_t u32Stepping;
1950 if (HMSvmIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1951 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1952 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1953 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1954 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1955 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1956 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1957
1958 /*
1959 * Enumerate AMD-V features.
1960 */
1961 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1962 {
1963#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1964 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1965 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1966 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1967 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1968 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1969 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1970 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1971 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1972 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1973 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1974 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1975 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1976 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1977#undef HMSVM_REPORT_FEATURE
1978 };
1979
1980 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1981 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1982 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1983 {
1984 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1985 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1986 }
1987 if (fSvmFeatures)
1988 for (unsigned iBit = 0; iBit < 32; iBit++)
1989 if (RT_BIT_32(iBit) & fSvmFeatures)
1990 LogRel(("HM: Reserved bit %u\n", iBit));
1991
1992 /*
1993 * Nested paging is determined in HMR3Init, verify the sanity of that.
1994 */
1995 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1996 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1997 VERR_HM_IPE_1);
1998
1999#if 0
2000 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
2001 * here. */
2002 if (RTR0IsPostIpiSupport())
2003 pVM->hm.s.fPostedIntrs = true;
2004#endif
2005
2006 /*
2007 * Call ring-0 to set up the VM.
2008 */
2009 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
2010 if (rc != VINF_SUCCESS)
2011 {
2012 AssertMsgFailed(("%Rrc\n", rc));
2013 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
2014 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
2015 }
2016
2017 LogRel(("HM: Enabled SVM\n"));
2018 pVM->hm.s.svm.fEnabled = true;
2019
2020 if (pVM->hm.s.fNestedPaging)
2021 {
2022 LogRel(("HM: Enabled nested paging\n"));
2023
2024 /*
2025 * Enable large pages (2 MB) if applicable.
2026 */
2027#if HC_ARCH_BITS == 64
2028 if (pVM->hm.s.fLargePages)
2029 {
2030 PGMSetLargePageUsage(pVM, true);
2031 LogRel(("HM: Enabled large page support\n"));
2032 }
2033#endif
2034 }
2035
2036 if (pVM->hm.s.fVirtApicRegs)
2037 LogRel(("HM: Enabled APIC-register virtualization support\n"));
2038
2039 if (pVM->hm.s.fPostedIntrs)
2040 LogRel(("HM: Enabled posted-interrupt processing support\n"));
2041
2042 hmR3DisableRawMode(pVM);
2043
2044 /*
2045 * Change the CPU features.
2046 */
2047 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
2048 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
2049 if (pVM->hm.s.fAllow64BitGuests)
2050 {
2051 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
2052 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
2053 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
2054 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
2055 }
2056 /* Turn on NXE if PAE has been enabled. */
2057 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
2058 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
2059
2060 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
2061
2062 LogRel((pVM->hm.s.fAllow64BitGuests
2063 ? "HM: Guest support: 32-bit and 64-bit\n"
2064 : "HM: Guest support: 32-bit only\n"));
2065
2066 return VINF_SUCCESS;
2067}
2068
2069
2070/**
2071 * Applies relocations to data and code managed by this
2072 * component. This function will be called at init and
2073 * whenever the VMM need to relocate it self inside the GC.
2074 *
2075 * @param pVM The cross context VM structure.
2076 */
2077VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
2078{
2079 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
2080
2081 /* Fetch the current paging mode during the relocate callback during state loading. */
2082 if (VMR3GetState(pVM) == VMSTATE_LOADING)
2083 {
2084 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2085 {
2086 PVMCPU pVCpu = &pVM->aCpus[i];
2087 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
2088 }
2089 }
2090#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
2091 if (HMIsEnabled(pVM))
2092 {
2093 switch (PGMGetHostMode(pVM))
2094 {
2095 case PGMMODE_32_BIT:
2096 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
2097 break;
2098
2099 case PGMMODE_PAE:
2100 case PGMMODE_PAE_NX:
2101 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
2102 break;
2103
2104 default:
2105 AssertFailed();
2106 break;
2107 }
2108 }
2109#endif
2110 return;
2111}
2112
2113
2114/**
2115 * Terminates the HM.
2116 *
2117 * Termination means cleaning up and freeing all resources,
2118 * the VM itself is, at this point, powered off or suspended.
2119 *
2120 * @returns VBox status code.
2121 * @param pVM The cross context VM structure.
2122 */
2123VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
2124{
2125 if (pVM->hm.s.vmx.pRealModeTSS)
2126 {
2127 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
2128 pVM->hm.s.vmx.pRealModeTSS = 0;
2129 }
2130 hmR3TermCPU(pVM);
2131 return 0;
2132}
2133
2134
2135/**
2136 * Terminates the per-VCPU HM.
2137 *
2138 * @returns VBox status code.
2139 * @param pVM The cross context VM structure.
2140 */
2141static int hmR3TermCPU(PVM pVM)
2142{
2143 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2144 {
2145 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
2146
2147#ifdef VBOX_WITH_STATISTICS
2148 if (pVCpu->hm.s.paStatExitReason)
2149 {
2150 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
2151 pVCpu->hm.s.paStatExitReason = NULL;
2152 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
2153 }
2154 if (pVCpu->hm.s.paStatInjectedIrqs)
2155 {
2156 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
2157 pVCpu->hm.s.paStatInjectedIrqs = NULL;
2158 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
2159 }
2160#endif
2161
2162#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2163 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
2164 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
2165 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
2166#endif
2167 }
2168 return 0;
2169}
2170
2171
2172/**
2173 * Resets a virtual CPU.
2174 *
2175 * Used by HMR3Reset and CPU hot plugging.
2176 *
2177 * @param pVCpu The cross context virtual CPU structure to reset.
2178 */
2179VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2180{
2181 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
2182 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2183 pVCpu->hm.s.fCtxChanged |= HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST;
2184
2185 pVCpu->hm.s.fActive = false;
2186 pVCpu->hm.s.Event.fPending = false;
2187 pVCpu->hm.s.vmx.fWasInRealMode = true;
2188 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
2189 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
2190
2191 /* Reset the contents of the read cache. */
2192 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
2193 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
2194 pCache->Read.aFieldVal[j] = 0;
2195
2196#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2197 /* Magic marker for searching in crash dumps. */
2198 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
2199 pCache->uMagic = UINT64_C(0xdeadbeefdeadbeef);
2200#endif
2201}
2202
2203
2204/**
2205 * The VM is being reset.
2206 *
2207 * For the HM component this means that any GDT/LDT/TSS monitors
2208 * needs to be removed.
2209 *
2210 * @param pVM The cross context VM structure.
2211 */
2212VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2213{
2214 LogFlow(("HMR3Reset:\n"));
2215
2216 if (HMIsEnabled(pVM))
2217 hmR3DisableRawMode(pVM);
2218
2219 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2220 {
2221 PVMCPU pVCpu = &pVM->aCpus[i];
2222
2223 HMR3ResetCpu(pVCpu);
2224 }
2225
2226 /* Clear all patch information. */
2227 pVM->hm.s.pGuestPatchMem = 0;
2228 pVM->hm.s.pFreeGuestPatchMem = 0;
2229 pVM->hm.s.cbGuestPatchMem = 0;
2230 pVM->hm.s.cPatches = 0;
2231 pVM->hm.s.PatchTree = 0;
2232 pVM->hm.s.fTPRPatchingActive = false;
2233 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2234}
2235
2236
2237/**
2238 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2239 *
2240 * @returns VBox strict status code.
2241 * @param pVM The cross context VM structure.
2242 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2243 * @param pvUser Unused.
2244 */
2245static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2246{
2247 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2248
2249 /* Only execute the handler on the VCPU the original patch request was issued. */
2250 if (pVCpu->idCpu != idCpu)
2251 return VINF_SUCCESS;
2252
2253 Log(("hmR3RemovePatches\n"));
2254 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2255 {
2256 uint8_t abInstr[15];
2257 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2258 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2259 int rc;
2260
2261#ifdef LOG_ENABLED
2262 char szOutput[256];
2263 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2264 szOutput, sizeof(szOutput), NULL);
2265 if (RT_SUCCESS(rc))
2266 Log(("Patched instr: %s\n", szOutput));
2267#endif
2268
2269 /* Check if the instruction is still the same. */
2270 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2271 if (rc != VINF_SUCCESS)
2272 {
2273 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2274 continue; /* swapped out or otherwise removed; skip it. */
2275 }
2276
2277 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2278 {
2279 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2280 continue; /* skip it. */
2281 }
2282
2283 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2284 AssertRC(rc);
2285
2286#ifdef LOG_ENABLED
2287 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2288 szOutput, sizeof(szOutput), NULL);
2289 if (RT_SUCCESS(rc))
2290 Log(("Original instr: %s\n", szOutput));
2291#endif
2292 }
2293 pVM->hm.s.cPatches = 0;
2294 pVM->hm.s.PatchTree = 0;
2295 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2296 pVM->hm.s.fTPRPatchingActive = false;
2297 return VINF_SUCCESS;
2298}
2299
2300
2301/**
2302 * Worker for enabling patching in a VT-x/AMD-V guest.
2303 *
2304 * @returns VBox status code.
2305 * @param pVM The cross context VM structure.
2306 * @param idCpu VCPU to execute hmR3RemovePatches on.
2307 * @param pPatchMem Patch memory range.
2308 * @param cbPatchMem Size of the memory range.
2309 */
2310static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2311{
2312 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2313 AssertRC(rc);
2314
2315 pVM->hm.s.pGuestPatchMem = pPatchMem;
2316 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2317 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2318 return VINF_SUCCESS;
2319}
2320
2321
2322/**
2323 * Enable patching in a VT-x/AMD-V guest
2324 *
2325 * @returns VBox status code.
2326 * @param pVM The cross context VM structure.
2327 * @param pPatchMem Patch memory range.
2328 * @param cbPatchMem Size of the memory range.
2329 */
2330VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2331{
2332 VM_ASSERT_EMT(pVM);
2333 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2334 if (pVM->cCpus > 1)
2335 {
2336 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2337 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2338 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2339 AssertRC(rc);
2340 return rc;
2341 }
2342 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2343}
2344
2345
2346/**
2347 * Disable patching in a VT-x/AMD-V guest.
2348 *
2349 * @returns VBox status code.
2350 * @param pVM The cross context VM structure.
2351 * @param pPatchMem Patch memory range.
2352 * @param cbPatchMem Size of the memory range.
2353 */
2354VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2355{
2356 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2357 RT_NOREF2(pPatchMem, cbPatchMem);
2358
2359 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2360 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2361
2362 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2363 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2364 (void *)(uintptr_t)VMMGetCpuId(pVM));
2365 AssertRC(rc);
2366
2367 pVM->hm.s.pGuestPatchMem = 0;
2368 pVM->hm.s.pFreeGuestPatchMem = 0;
2369 pVM->hm.s.cbGuestPatchMem = 0;
2370 pVM->hm.s.fTPRPatchingActive = false;
2371 return VINF_SUCCESS;
2372}
2373
2374
2375/**
2376 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2377 *
2378 * @returns VBox strict status code.
2379 * @param pVM The cross context VM structure.
2380 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2381 * @param pvUser User specified CPU context.
2382 *
2383 */
2384static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2385{
2386 /*
2387 * Only execute the handler on the VCPU the original patch request was
2388 * issued. (The other CPU(s) might not yet have switched to protected
2389 * mode, nor have the correct memory context.)
2390 */
2391 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2392 if (pVCpu->idCpu != idCpu)
2393 return VINF_SUCCESS;
2394
2395 /*
2396 * We're racing other VCPUs here, so don't try patch the instruction twice
2397 * and make sure there is still room for our patch record.
2398 */
2399 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2400 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2401 if (pPatch)
2402 {
2403 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2404 return VINF_SUCCESS;
2405 }
2406 uint32_t const idx = pVM->hm.s.cPatches;
2407 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2408 {
2409 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2410 return VINF_SUCCESS;
2411 }
2412 pPatch = &pVM->hm.s.aPatches[idx];
2413
2414 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2415
2416 /*
2417 * Disassembler the instruction and get cracking.
2418 */
2419 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2420 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2421 uint32_t cbOp;
2422 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2423 AssertRC(rc);
2424 if ( rc == VINF_SUCCESS
2425 && pDis->pCurInstr->uOpcode == OP_MOV
2426 && cbOp >= 3)
2427 {
2428 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2429
2430 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2431 AssertRC(rc);
2432
2433 pPatch->cbOp = cbOp;
2434
2435 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2436 {
2437 /* write. */
2438 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2439 {
2440 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2441 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2442 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2443 }
2444 else
2445 {
2446 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2447 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2448 pPatch->uSrcOperand = pDis->Param2.uValue;
2449 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2450 }
2451 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2452 AssertRC(rc);
2453
2454 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2455 pPatch->cbNewOp = sizeof(s_abVMMCall);
2456 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2457 }
2458 else
2459 {
2460 /*
2461 * TPR Read.
2462 *
2463 * Found:
2464 * mov eax, dword [fffe0080] (5 bytes)
2465 * Check if next instruction is:
2466 * shr eax, 4
2467 */
2468 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2469
2470 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2471 uint8_t const cbOpMmio = cbOp;
2472 uint64_t const uSavedRip = pCtx->rip;
2473
2474 pCtx->rip += cbOp;
2475 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2476 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2477 pCtx->rip = uSavedRip;
2478
2479 if ( rc == VINF_SUCCESS
2480 && pDis->pCurInstr->uOpcode == OP_SHR
2481 && pDis->Param1.fUse == DISUSE_REG_GEN32
2482 && pDis->Param1.Base.idxGenReg == idxMmioReg
2483 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2484 && pDis->Param2.uValue == 4
2485 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2486 {
2487 uint8_t abInstr[15];
2488
2489 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2490 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2491 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2492 AssertRC(rc);
2493
2494 pPatch->cbOp = cbOpMmio + cbOp;
2495
2496 /* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2497 abInstr[0] = 0xf0;
2498 abInstr[1] = 0x0f;
2499 abInstr[2] = 0x20;
2500 abInstr[3] = 0xc0 | pDis->Param1.Base.idxGenReg;
2501 for (unsigned i = 4; i < pPatch->cbOp; i++)
2502 abInstr[i] = 0x90; /* nop */
2503
2504 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2505 AssertRC(rc);
2506
2507 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2508 pPatch->cbNewOp = pPatch->cbOp;
2509 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2510
2511 Log(("Acceptable read/shr candidate!\n"));
2512 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2513 }
2514 else
2515 {
2516 pPatch->enmType = HMTPRINSTR_READ;
2517 pPatch->uDstOperand = idxMmioReg;
2518
2519 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2520 AssertRC(rc);
2521
2522 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2523 pPatch->cbNewOp = sizeof(s_abVMMCall);
2524 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2525 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2526 }
2527 }
2528
2529 pPatch->Core.Key = pCtx->eip;
2530 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2531 AssertRC(rc);
2532
2533 pVM->hm.s.cPatches++;
2534 return VINF_SUCCESS;
2535 }
2536
2537 /*
2538 * Save invalid patch, so we will not try again.
2539 */
2540 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2541 pPatch->Core.Key = pCtx->eip;
2542 pPatch->enmType = HMTPRINSTR_INVALID;
2543 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2544 AssertRC(rc);
2545 pVM->hm.s.cPatches++;
2546 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2547 return VINF_SUCCESS;
2548}
2549
2550
2551/**
2552 * Callback to patch a TPR instruction (jump to generated code).
2553 *
2554 * @returns VBox strict status code.
2555 * @param pVM The cross context VM structure.
2556 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2557 * @param pvUser User specified CPU context.
2558 *
2559 */
2560static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2561{
2562 /*
2563 * Only execute the handler on the VCPU the original patch request was
2564 * issued. (The other CPU(s) might not yet have switched to protected
2565 * mode, nor have the correct memory context.)
2566 */
2567 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2568 if (pVCpu->idCpu != idCpu)
2569 return VINF_SUCCESS;
2570
2571 /*
2572 * We're racing other VCPUs here, so don't try patch the instruction twice
2573 * and make sure there is still room for our patch record.
2574 */
2575 PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2576 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2577 if (pPatch)
2578 {
2579 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2580 return VINF_SUCCESS;
2581 }
2582 uint32_t const idx = pVM->hm.s.cPatches;
2583 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2584 {
2585 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2586 return VINF_SUCCESS;
2587 }
2588 pPatch = &pVM->hm.s.aPatches[idx];
2589
2590 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2591 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2592
2593 /*
2594 * Disassemble the instruction and get cracking.
2595 */
2596 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2597 uint32_t cbOp;
2598 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2599 AssertRC(rc);
2600 if ( rc == VINF_SUCCESS
2601 && pDis->pCurInstr->uOpcode == OP_MOV
2602 && cbOp >= 5)
2603 {
2604 uint8_t aPatch[64];
2605 uint32_t off = 0;
2606
2607 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2608 AssertRC(rc);
2609
2610 pPatch->cbOp = cbOp;
2611 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2612
2613 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2614 {
2615 /*
2616 * TPR write:
2617 *
2618 * push ECX [51]
2619 * push EDX [52]
2620 * push EAX [50]
2621 * xor EDX,EDX [31 D2]
2622 * mov EAX,EAX [89 C0]
2623 * or
2624 * mov EAX,0000000CCh [B8 CC 00 00 00]
2625 * mov ECX,0C0000082h [B9 82 00 00 C0]
2626 * wrmsr [0F 30]
2627 * pop EAX [58]
2628 * pop EDX [5A]
2629 * pop ECX [59]
2630 * jmp return_address [E9 return_address]
2631 */
2632 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2633
2634 aPatch[off++] = 0x51; /* push ecx */
2635 aPatch[off++] = 0x52; /* push edx */
2636 if (!fUsesEax)
2637 aPatch[off++] = 0x50; /* push eax */
2638 aPatch[off++] = 0x31; /* xor edx, edx */
2639 aPatch[off++] = 0xd2;
2640 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2641 {
2642 if (!fUsesEax)
2643 {
2644 aPatch[off++] = 0x89; /* mov eax, src_reg */
2645 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2646 }
2647 }
2648 else
2649 {
2650 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2651 aPatch[off++] = 0xb8; /* mov eax, immediate */
2652 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2653 off += sizeof(uint32_t);
2654 }
2655 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2656 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2657 off += sizeof(uint32_t);
2658
2659 aPatch[off++] = 0x0f; /* wrmsr */
2660 aPatch[off++] = 0x30;
2661 if (!fUsesEax)
2662 aPatch[off++] = 0x58; /* pop eax */
2663 aPatch[off++] = 0x5a; /* pop edx */
2664 aPatch[off++] = 0x59; /* pop ecx */
2665 }
2666 else
2667 {
2668 /*
2669 * TPR read:
2670 *
2671 * push ECX [51]
2672 * push EDX [52]
2673 * push EAX [50]
2674 * mov ECX,0C0000082h [B9 82 00 00 C0]
2675 * rdmsr [0F 32]
2676 * mov EAX,EAX [89 C0]
2677 * pop EAX [58]
2678 * pop EDX [5A]
2679 * pop ECX [59]
2680 * jmp return_address [E9 return_address]
2681 */
2682 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2683
2684 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2685 aPatch[off++] = 0x51; /* push ecx */
2686 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2687 aPatch[off++] = 0x52; /* push edx */
2688 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2689 aPatch[off++] = 0x50; /* push eax */
2690
2691 aPatch[off++] = 0x31; /* xor edx, edx */
2692 aPatch[off++] = 0xd2;
2693
2694 aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2695 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2696 off += sizeof(uint32_t);
2697
2698 aPatch[off++] = 0x0f; /* rdmsr */
2699 aPatch[off++] = 0x32;
2700
2701 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2702 {
2703 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2704 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2705 }
2706
2707 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2708 aPatch[off++] = 0x58; /* pop eax */
2709 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2710 aPatch[off++] = 0x5a; /* pop edx */
2711 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2712 aPatch[off++] = 0x59; /* pop ecx */
2713 }
2714 aPatch[off++] = 0xe9; /* jmp return_address */
2715 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2716 off += sizeof(RTRCUINTPTR);
2717
2718 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2719 {
2720 /* Write new code to the patch buffer. */
2721 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2722 AssertRC(rc);
2723
2724#ifdef LOG_ENABLED
2725 uint32_t cbCurInstr;
2726 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2727 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2728 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2729 {
2730 char szOutput[256];
2731 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2732 szOutput, sizeof(szOutput), &cbCurInstr);
2733 if (RT_SUCCESS(rc))
2734 Log(("Patch instr %s\n", szOutput));
2735 else
2736 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2737 }
2738#endif
2739
2740 pPatch->aNewOpcode[0] = 0xE9;
2741 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2742
2743 /* Overwrite the TPR instruction with a jump. */
2744 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2745 AssertRC(rc);
2746
2747 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2748
2749 pVM->hm.s.pFreeGuestPatchMem += off;
2750 pPatch->cbNewOp = 5;
2751
2752 pPatch->Core.Key = pCtx->eip;
2753 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2754 AssertRC(rc);
2755
2756 pVM->hm.s.cPatches++;
2757 pVM->hm.s.fTPRPatchingActive = true;
2758 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2759 return VINF_SUCCESS;
2760 }
2761
2762 Log(("Ran out of space in our patch buffer!\n"));
2763 }
2764 else
2765 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2766
2767
2768 /*
2769 * Save invalid patch, so we will not try again.
2770 */
2771 pPatch = &pVM->hm.s.aPatches[idx];
2772 pPatch->Core.Key = pCtx->eip;
2773 pPatch->enmType = HMTPRINSTR_INVALID;
2774 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2775 AssertRC(rc);
2776 pVM->hm.s.cPatches++;
2777 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2778 return VINF_SUCCESS;
2779}
2780
2781
2782/**
2783 * Attempt to patch TPR mmio instructions.
2784 *
2785 * @returns VBox status code.
2786 * @param pVM The cross context VM structure.
2787 * @param pVCpu The cross context virtual CPU structure.
2788 */
2789VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2790{
2791 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2792 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2793 (void *)(uintptr_t)pVCpu->idCpu);
2794 AssertRC(rc);
2795 return rc;
2796}
2797
2798
2799/**
2800 * Checks if we need to reschedule due to VMM device heap changes.
2801 *
2802 * @returns true if a reschedule is required, otherwise false.
2803 * @param pVM The cross context VM structure.
2804 * @param pCtx VM execution context.
2805 */
2806VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2807{
2808 /*
2809 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2810 * when the unrestricted guest execution feature is missing (VT-x only).
2811 */
2812 if ( pVM->hm.s.vmx.fEnabled
2813 && !pVM->hm.s.vmx.fUnrestrictedGuest
2814 && CPUMIsGuestInRealModeEx(pCtx)
2815 && !PDMVmmDevHeapIsEnabled(pVM))
2816 return true;
2817
2818 return false;
2819}
2820
2821
2822/**
2823 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2824 * event settings changes.
2825 *
2826 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2827 * function is just updating the VM globals.
2828 *
2829 * @param pVM The VM cross context VM structure.
2830 * @thread EMT(0)
2831 */
2832VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2833{
2834 /* Interrupts. */
2835 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2836 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2837
2838 /* CPU Exceptions. */
2839 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2840 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2841 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2842 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2843
2844 /* Common VM exits. */
2845 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2846 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2847 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2848 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2849
2850 /* Vendor specific VM exits. */
2851 if (HMR3IsVmxEnabled(pVM->pUVM))
2852 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2853 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2854 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2855 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2856 else
2857 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2858 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2859 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2860 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2861
2862 /* Done. */
2863 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2864}
2865
2866
2867/**
2868 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2869 *
2870 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2871 * per CPU settings.
2872 *
2873 * @param pVM The VM cross context VM structure.
2874 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2875 */
2876VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2877{
2878 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2879}
2880
2881
2882/**
2883 * Checks if we are currently using hardware acceleration.
2884 *
2885 * @returns true if hardware acceleration is being used, otherwise false.
2886 * @param pVCpu The cross context virtual CPU structure.
2887 */
2888VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2889{
2890 return pVCpu->hm.s.fActive;
2891}
2892
2893
2894/**
2895 * External interface for querying whether hardware acceleration is enabled.
2896 *
2897 * @returns true if VT-x or AMD-V is being used, otherwise false.
2898 * @param pUVM The user mode VM handle.
2899 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2900 */
2901VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2902{
2903 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2904 PVM pVM = pUVM->pVM;
2905 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2906 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2907}
2908
2909
2910/**
2911 * External interface for querying whether VT-x is being used.
2912 *
2913 * @returns true if VT-x is being used, otherwise false.
2914 * @param pUVM The user mode VM handle.
2915 * @sa HMR3IsSvmEnabled, HMIsEnabled
2916 */
2917VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2918{
2919 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2920 PVM pVM = pUVM->pVM;
2921 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2922 return pVM->hm.s.vmx.fEnabled
2923 && pVM->hm.s.vmx.fSupported
2924 && pVM->fHMEnabled;
2925}
2926
2927
2928/**
2929 * External interface for querying whether AMD-V is being used.
2930 *
2931 * @returns true if VT-x is being used, otherwise false.
2932 * @param pUVM The user mode VM handle.
2933 * @sa HMR3IsVmxEnabled, HMIsEnabled
2934 */
2935VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2936{
2937 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2938 PVM pVM = pUVM->pVM;
2939 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2940 return pVM->hm.s.svm.fEnabled
2941 && pVM->hm.s.svm.fSupported
2942 && pVM->fHMEnabled;
2943}
2944
2945
2946/**
2947 * Checks if we are currently using nested paging.
2948 *
2949 * @returns true if nested paging is being used, otherwise false.
2950 * @param pUVM The user mode VM handle.
2951 */
2952VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2953{
2954 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2955 PVM pVM = pUVM->pVM;
2956 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2957 return pVM->hm.s.fNestedPaging;
2958}
2959
2960
2961/**
2962 * Checks if virtualized APIC registers is enabled.
2963 *
2964 * When enabled this feature allows the hardware to access most of the
2965 * APIC registers in the virtual-APIC page without causing VM-exits. See
2966 * Intel spec. 29.1.1 "Virtualized APIC Registers".
2967 *
2968 * @returns true if virtualized APIC registers is enabled, otherwise
2969 * false.
2970 * @param pUVM The user mode VM handle.
2971 */
2972VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
2973{
2974 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2975 PVM pVM = pUVM->pVM;
2976 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2977 return pVM->hm.s.fVirtApicRegs;
2978}
2979
2980
2981/**
2982 * Checks if APIC posted-interrupt processing is enabled.
2983 *
2984 * This returns whether we can deliver interrupts to the guest without
2985 * leaving guest-context by updating APIC state from host-context.
2986 *
2987 * @returns true if APIC posted-interrupt processing is enabled,
2988 * otherwise false.
2989 * @param pUVM The user mode VM handle.
2990 */
2991VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2992{
2993 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2994 PVM pVM = pUVM->pVM;
2995 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2996 return pVM->hm.s.fPostedIntrs;
2997}
2998
2999
3000/**
3001 * Checks if we are currently using VPID in VT-x mode.
3002 *
3003 * @returns true if VPID is being used, otherwise false.
3004 * @param pUVM The user mode VM handle.
3005 */
3006VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3007{
3008 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3009 PVM pVM = pUVM->pVM;
3010 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3011 return pVM->hm.s.vmx.fVpid;
3012}
3013
3014
3015/**
3016 * Checks if we are currently using VT-x unrestricted execution,
3017 * aka UX.
3018 *
3019 * @returns true if UX is being used, otherwise false.
3020 * @param pUVM The user mode VM handle.
3021 */
3022VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3023{
3024 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3025 PVM pVM = pUVM->pVM;
3026 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3027 return pVM->hm.s.vmx.fUnrestrictedGuest
3028 || pVM->hm.s.svm.fSupported;
3029}
3030
3031
3032/**
3033 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3034 *
3035 * @returns true if an internal event is pending, otherwise false.
3036 * @param pVCpu The cross context virtual CPU structure.
3037 */
3038VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3039{
3040 return HMIsEnabled(pVCpu->pVMR3)
3041 && pVCpu->hm.s.Event.fPending;
3042}
3043
3044
3045/**
3046 * Checks if the VMX-preemption timer is being used.
3047 *
3048 * @returns true if the VMX-preemption timer is being used, otherwise false.
3049 * @param pVM The cross context VM structure.
3050 */
3051VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3052{
3053 return HMIsEnabled(pVM)
3054 && pVM->hm.s.vmx.fEnabled
3055 && pVM->hm.s.vmx.fUsePreemptTimer;
3056}
3057
3058
3059/**
3060 * Check fatal VT-x/AMD-V error and produce some meaningful
3061 * log release message.
3062 *
3063 * @param pVM The cross context VM structure.
3064 * @param iStatusCode VBox status code.
3065 */
3066VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3067{
3068 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3069 {
3070 PVMCPU pVCpu = &pVM->aCpus[i];
3071 switch (iStatusCode)
3072 {
3073 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3074 * might be getting inaccurate values for non-guru'ing EMTs. */
3075 case VERR_VMX_INVALID_VMCS_FIELD:
3076 break;
3077
3078 case VERR_VMX_INVALID_VMCS_PTR:
3079 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3080 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3081 pVCpu->hm.s.vmx.HCPhysVmcs));
3082 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3083 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3084 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3085 break;
3086
3087 case VERR_VMX_UNABLE_TO_START_VM:
3088 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3089 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3090 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3091
3092 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3093 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3094 {
3095 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3096 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3097 }
3098 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3099 {
3100 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3101 {
3102 uint32_t const u32Val = pVCpu->hm.s.vmx.u32PinCtls;
3103 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
3104 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
3105 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
3106 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
3107 HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
3108 }
3109 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3110 {
3111 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls;
3112 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
3113 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
3114 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
3115 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
3116 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
3117 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
3118 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
3119 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
3120 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
3121 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
3122 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
3123 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
3124 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
3125 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
3126 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
3127 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
3128 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
3129 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
3130 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
3131 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
3132 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
3133 }
3134 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3135 {
3136 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ProcCtls2;
3137 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
3138 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
3139 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
3140 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
3141 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
3142 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
3143 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
3144 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
3145 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
3146 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
3147 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
3148 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
3149 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
3150 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
3151 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
3152 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
3153 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
3154 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
3155 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_VE );
3156 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_FROM_PT );
3157 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
3158 HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
3159 }
3160 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3161 {
3162 uint32_t const u32Val = pVCpu->hm.s.vmx.u32EntryCtls;
3163 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
3164 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
3165 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
3166 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
3167 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
3168 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
3169 HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
3170 }
3171 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3172 {
3173 uint32_t const u32Val = pVCpu->hm.s.vmx.u32ExitCtls;
3174 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
3175 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
3176 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
3177 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
3178 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
3179 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
3180 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
3181 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
3182 HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
3183 }
3184 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3185 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3186 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3187 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3188 }
3189 /** @todo Log VM-entry event injection control fields
3190 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3191 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3192 break;
3193
3194 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3195 case VERR_VMX_INVALID_VMXON_PTR:
3196 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3197 case VERR_VMX_INVALID_GUEST_STATE:
3198 case VERR_VMX_UNEXPECTED_EXIT:
3199 case VERR_SVM_UNKNOWN_EXIT:
3200 case VERR_SVM_UNEXPECTED_EXIT:
3201 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3202 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3203 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3204 break;
3205 }
3206 }
3207
3208 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3209 {
3210 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed1));
3211 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.vmx.Msrs.EntryCtls.n.allowed0));
3212 }
3213 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3214 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3215}
3216
3217
3218/**
3219 * Execute state save operation.
3220 *
3221 * Save only data that cannot be re-loaded while entering HM ring-0 code. This
3222 * is because we always save the VM state from ring-3 and thus most HM state
3223 * will be re-synced dynamically at runtime and don't need to be part of the VM
3224 * saved state.
3225 *
3226 * @returns VBox status code.
3227 * @param pVM The cross context VM structure.
3228 * @param pSSM SSM operation handle.
3229 */
3230static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3231{
3232 int rc;
3233
3234 Log(("hmR3Save:\n"));
3235
3236 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3237 {
3238 Assert(!pVM->aCpus[i].hm.s.Event.fPending);
3239 if (pVM->cpum.ro.GuestFeatures.fSvm)
3240 {
3241 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3242 rc = SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3243 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3244 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3245 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3246 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3247 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3248 rc |= SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3249 rc |= SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3250 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3251 rc |= SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3252 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3253 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3254 rc |= SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3255 AssertRCReturn(rc, rc);
3256 }
3257 }
3258
3259 /* Save the guest patch data. */
3260 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3261 rc |= SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3262 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3263
3264 /* Store all the guest patch records too. */
3265 rc |= SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3266 AssertRCReturn(rc, rc);
3267
3268 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3269 {
3270 AssertCompileSize(HMTPRINSTR, 4);
3271 PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3272 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3273 rc |= SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3274 rc |= SSMR3PutU32(pSSM, pPatch->cbOp);
3275 rc |= SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3276 rc |= SSMR3PutU32(pSSM, pPatch->cbNewOp);
3277 rc |= SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3278 rc |= SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3279 rc |= SSMR3PutU32(pSSM, pPatch->uDstOperand);
3280 rc |= SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3281 rc |= SSMR3PutU32(pSSM, pPatch->cFaults);
3282 AssertRCReturn(rc, rc);
3283 }
3284
3285 return VINF_SUCCESS;
3286}
3287
3288
3289/**
3290 * Execute state load operation.
3291 *
3292 * @returns VBox status code.
3293 * @param pVM The cross context VM structure.
3294 * @param pSSM SSM operation handle.
3295 * @param uVersion Data layout version.
3296 * @param uPass The data pass.
3297 */
3298static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3299{
3300 int rc;
3301
3302 LogFlowFunc(("uVersion=%u\n", uVersion));
3303 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3304
3305 /*
3306 * Validate version.
3307 */
3308 if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3309 && uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3310 && uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3311 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3312 {
3313 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3314 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3315 }
3316
3317 /*
3318 * Load per-VCPU state.
3319 */
3320 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3321 {
3322 if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3323 {
3324 /* Load the SVM nested hw.virt state if the VM is configured for it. */
3325 if (pVM->cpum.ro.GuestFeatures.fSvm)
3326 {
3327 PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVM->aCpus[i].hm.s.svm.NstGstVmcbCache;
3328 rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3329 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3330 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3331 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3332 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3333 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3334 rc |= SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3335 rc |= SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3336 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3337 rc |= SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3338 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3339 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3340 rc |= SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3341 AssertRCReturn(rc, rc);
3342 }
3343 }
3344 else
3345 {
3346 /* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3347 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3348 rc |= SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3349 rc |= SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3350
3351 /* VMX fWasInRealMode related data. */
3352 uint32_t uDummy;
3353 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3354 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3355 rc |= SSMR3GetU32(pSSM, &uDummy); AssertRCReturn(rc, rc);
3356 AssertRCReturn(rc, rc);
3357 }
3358 }
3359
3360 /*
3361 * Load TPR patching data.
3362 */
3363 if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3364 {
3365 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3366 rc |= SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3367 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3368
3369 /* Fetch all TPR patch records. */
3370 rc |= SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3371 AssertRCReturn(rc, rc);
3372 for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3373 {
3374 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3375 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3376 rc |= SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3377 rc |= SSMR3GetU32(pSSM, &pPatch->cbOp);
3378 rc |= SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3379 rc |= SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3380 rc |= SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3381
3382 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3383 pVM->hm.s.fTPRPatchingActive = true;
3384 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3385
3386 rc |= SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3387 rc |= SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3388 rc |= SSMR3GetU32(pSSM, &pPatch->cFaults);
3389 rc |= SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3390 AssertRCReturn(rc, rc);
3391
3392 LogFlow(("hmR3Load: patch %d\n", i));
3393 LogFlow(("Key = %x\n", pPatch->Core.Key));
3394 LogFlow(("cbOp = %d\n", pPatch->cbOp));
3395 LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3396 LogFlow(("type = %d\n", pPatch->enmType));
3397 LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3398 LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3399 LogFlow(("cFaults = %d\n", pPatch->cFaults));
3400 LogFlow(("target = %x\n", pPatch->pJumpTarget));
3401
3402 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3403 AssertRCReturn(rc, rc);
3404 }
3405 }
3406
3407 return VINF_SUCCESS;
3408}
3409
3410
3411/**
3412 * Gets the name of a VT-x exit code.
3413 *
3414 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3415 * @param uExit The VT-x exit to name.
3416 */
3417VMMR3DECL(const char *) HMR3GetVmxExitName(uint32_t uExit)
3418{
3419 if (uExit < RT_ELEMENTS(g_apszVmxExitReasons))
3420 return g_apszVmxExitReasons[uExit];
3421 return NULL;
3422}
3423
3424
3425/**
3426 * Gets the name of an AMD-V exit code.
3427 *
3428 * @returns Pointer to read only string if @a uExit is known, otherwise NULL.
3429 * @param uExit The AMD-V exit to name.
3430 */
3431VMMR3DECL(const char *) HMR3GetSvmExitName(uint32_t uExit)
3432{
3433 if (uExit < RT_ELEMENTS(g_apszSvmExitReasons))
3434 return g_apszSvmExitReasons[uExit];
3435 return hmSvmGetSpecialExitReasonDesc(uExit);
3436}
3437
3438
3439/**
3440 * Displays HM info.
3441 *
3442 * @param pVM The cross context VM structure.
3443 * @param pHlp The info helper functions.
3444 * @param pszArgs Arguments, ignored.
3445 */
3446static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3447{
3448 NOREF(pszArgs);
3449 PVMCPU pVCpu = VMMGetCpu(pVM);
3450 if (!pVCpu)
3451 pVCpu = &pVM->aCpus[0];
3452
3453 if (HMIsEnabled(pVM))
3454 {
3455 if (pVM->hm.s.vmx.fSupported)
3456 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3457 else
3458 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3459 pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3460 pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3461 }
3462 else
3463 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3464}
3465
3466
3467/**
3468 * Displays the HM pending event.
3469 *
3470 * @param pVM The cross context VM structure.
3471 * @param pHlp The info helper functions.
3472 * @param pszArgs Arguments, ignored.
3473 */
3474static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3475{
3476 NOREF(pszArgs);
3477 PVMCPU pVCpu = VMMGetCpu(pVM);
3478 if (!pVCpu)
3479 pVCpu = &pVM->aCpus[0];
3480
3481 if (HMIsEnabled(pVM))
3482 {
3483 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3484 if (pVCpu->hm.s.Event.fPending)
3485 {
3486 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3487 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3488 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3489 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3490 }
3491 }
3492 else
3493 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3494}
3495
3496
3497/**
3498 * Displays the SVM nested-guest VMCB cache.
3499 *
3500 * @param pVM The cross context VM structure.
3501 * @param pHlp The info helper functions.
3502 * @param pszArgs Arguments, ignored.
3503 */
3504static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3505{
3506 NOREF(pszArgs);
3507 PVMCPU pVCpu = VMMGetCpu(pVM);
3508 if (!pVCpu)
3509 pVCpu = &pVM->aCpus[0];
3510
3511 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3512 if ( fSvmEnabled
3513 && pVM->cpum.ro.GuestFeatures.fSvm)
3514 {
3515 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3516 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3517 pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3518 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3519 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3520 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3521 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3522 pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3523 pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3524 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3525 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3526 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3527 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3528 pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3529 pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3530 }
3531 else
3532 {
3533 if (!fSvmEnabled)
3534 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3535 else
3536 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3537 }
3538}
3539
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