HM.cpp@ 93725

Last change on this file since 93725 was 93725, checked in by vboxsync, 3 years ago
VMM: More arm64 adjustments. bugref:9898
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1	/* $Id: HM.cpp 93725 2022-02-14 13:46:16Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2022 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#define VMCPU_INCL_CPUM_GST_CTX
41	#include <VBox/vmm/cpum.h>
42	#include <VBox/vmm/stam.h>
43	#include <VBox/vmm/em.h>
44	#include <VBox/vmm/pdmapi.h>
45	#include <VBox/vmm/pgm.h>
46	#include <VBox/vmm/ssm.h>
47	#include <VBox/vmm/gim.h>
48	#include <VBox/vmm/trpm.h>
49	#include <VBox/vmm/dbgf.h>
50	#include <VBox/vmm/iom.h>
51	#include <VBox/vmm/iem.h>
52	#include <VBox/vmm/selm.h>
53	#include <VBox/vmm/nem.h>
54	#include <VBox/vmm/hm_vmx.h>
55	#include <VBox/vmm/hm_svm.h>
56	#include "HMInternal.h"
57	#include <VBox/vmm/vmcc.h>
58	#include <VBox/err.h>
59	#include <VBox/param.h>
60
61	#include <iprt/assert.h>
62	#include <VBox/log.h>
63	#include <iprt/asm.h>
64	#if defined(RT_ARCH_AMD64) \|\| defined(RT_ARCH_X86)
65	# include <iprt/asm-amd64-x86.h>
66	#endif
67	#include <iprt/env.h>
68	#include <iprt/thread.h>
69
70
71	/*********************************************************************************************************************************
72	* Defined Constants And Macros *
73	*********************************************************************************************************************************/
74	/** @def HMVMX_REPORT_FEAT
75	* Reports VT-x feature to the release log.
76	*
77	* @param a_uAllowed1 Mask of allowed-1 feature bits.
78	* @param a_uAllowed0 Mask of allowed-0 feature bits.
79	* @param a_StrDesc The description string to report.
80	* @param a_Featflag Mask of the feature to report.
81	*/
82	#define HMVMX_REPORT_FEAT(a_uAllowed1, a_uAllowed0, a_StrDesc, a_Featflag) \
83	do { \
84	if ((a_uAllowed1) & (a_Featflag)) \
85	{ \
86	if ((a_uAllowed0) & (a_Featflag)) \
87	LogRel(("HM: " a_StrDesc " (must be set)\n")); \
88	else \
89	LogRel(("HM: " a_StrDesc "\n")); \
90	} \
91	else \
92	LogRel(("HM: " a_StrDesc " (must be cleared)\n")); \
93	} while (0)
94
95	/** @def HMVMX_REPORT_ALLOWED_FEAT
96	* Reports an allowed VT-x feature to the release log.
97	*
98	* @param a_uAllowed1 Mask of allowed-1 feature bits.
99	* @param a_StrDesc The description string to report.
100	* @param a_FeatFlag Mask of the feature to report.
101	*/
102	#define HMVMX_REPORT_ALLOWED_FEAT(a_uAllowed1, a_StrDesc, a_FeatFlag) \
103	do { \
104	if ((a_uAllowed1) & (a_FeatFlag)) \
105	LogRel(("HM: " a_StrDesc "\n")); \
106	else \
107	LogRel(("HM: " a_StrDesc " not supported\n")); \
108	} while (0)
109
110	/** @def HMVMX_REPORT_MSR_CAP
111	* Reports MSR feature capability.
112	*
113	* @param a_MsrCaps Mask of MSR feature bits.
114	* @param a_StrDesc The description string to report.
115	* @param a_fCap Mask of the feature to report.
116	*/
117	#define HMVMX_REPORT_MSR_CAP(a_MsrCaps, a_StrDesc, a_fCap) \
118	do { \
119	if ((a_MsrCaps) & (a_fCap)) \
120	LogRel(("HM: " a_StrDesc "\n")); \
121	} while (0)
122
123	/** @def HMVMX_LOGREL_FEAT
124	* Dumps a feature flag from a bitmap of features to the release log.
125	*
126	* @param a_fVal The value of all the features.
127	* @param a_fMask The specific bitmask of the feature.
128	*/
129	#define HMVMX_LOGREL_FEAT(a_fVal, a_fMask) \
130	do { \
131	if ((a_fVal) & (a_fMask)) \
132	LogRel(("HM: %s\n", #a_fMask)); \
133	} while (0)
134
135
136	/*********************************************************************************************************************************
137	* Internal Functions *
138	*********************************************************************************************************************************/
139	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
140	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
141	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
142	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
143	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
144	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
145	static int hmR3InitFinalizeR3(PVM pVM);
146	static int hmR3InitFinalizeR0(PVM pVM);
147	static int hmR3InitFinalizeR0Intel(PVM pVM);
148	static int hmR3InitFinalizeR0Amd(PVM pVM);
149	static int hmR3TermCPU(PVM pVM);
150
151
152	#ifdef VBOX_WITH_STATISTICS
153	/**
154	* Returns the name of the hardware exception.
155	*
156	* @returns The name of the hardware exception.
157	* @param uVector The exception vector.
158	*/
159	static const char *hmR3GetXcptName(uint8_t uVector)
160	{
161	switch (uVector)
162	{
163	case X86_XCPT_DE: return "#DE";
164	case X86_XCPT_DB: return "#DB";
165	case X86_XCPT_NMI: return "#NMI";
166	case X86_XCPT_BP: return "#BP";
167	case X86_XCPT_OF: return "#OF";
168	case X86_XCPT_BR: return "#BR";
169	case X86_XCPT_UD: return "#UD";
170	case X86_XCPT_NM: return "#NM";
171	case X86_XCPT_DF: return "#DF";
172	case X86_XCPT_CO_SEG_OVERRUN: return "#CO_SEG_OVERRUN";
173	case X86_XCPT_TS: return "#TS";
174	case X86_XCPT_NP: return "#NP";
175	case X86_XCPT_SS: return "#SS";
176	case X86_XCPT_GP: return "#GP";
177	case X86_XCPT_PF: return "#PF";
178	case X86_XCPT_MF: return "#MF";
179	case X86_XCPT_AC: return "#AC";
180	case X86_XCPT_MC: return "#MC";
181	case X86_XCPT_XF: return "#XF";
182	case X86_XCPT_VE: return "#VE";
183	case X86_XCPT_CP: return "#CP";
184	case X86_XCPT_VC: return "#VC";
185	case X86_XCPT_SX: return "#SX";
186	}
187	return "Reserved";
188	}
189	#endif /* VBOX_WITH_STATISTICS */
190
191
192	/**
193	* Initializes the HM.
194	*
195	* This is the very first component to really do init after CFGM so that we can
196	* establish the predominant execution engine for the VM prior to initializing
197	* other modules. It takes care of NEM initialization if needed (HM disabled or
198	* not available in HW).
199	*
200	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
201	* hypervisor API via NEM, and then back on raw-mode if that isn't available
202	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
203	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
204	* X, OS/2 and others).
205	*
206	* Note that a lot of the set up work is done in ring-0 and thus postponed till
207	* the ring-3 and ring-0 callback to HMR3InitCompleted.
208	*
209	* @returns VBox status code.
210	* @param pVM The cross context VM structure.
211	*
212	* @remarks Be careful with what we call here, since most of the VMM components
213	* are uninitialized.
214	*/
215	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
216	{
217	LogFlowFunc(("\n"));
218
219	/*
220	* Assert alignment and sizes.
221	*/
222	AssertCompileMemberAlignment(VM, hm.s, 32);
223	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
224
225	/*
226	* Register the saved state data unit.
227	*/
228	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
229	NULL, NULL, NULL,
230	NULL, hmR3Save, NULL,
231	NULL, hmR3Load, NULL);
232	if (RT_FAILURE(rc))
233	return rc;
234
235	/*
236	* Read configuration.
237	*/
238	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
239
240	/*
241	* Validate the HM settings.
242	*/
243	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
244	"HMForced" /* implied 'true' these days */
245	"\|UseNEMInstead"
246	"\|FallbackToNEM"
247	"\|EnableNestedPaging"
248	"\|EnableUX"
249	"\|EnableLargePages"
250	"\|EnableVPID"
251	"\|IBPBOnVMExit"
252	"\|IBPBOnVMEntry"
253	"\|SpecCtrlByHost"
254	"\|L1DFlushOnSched"
255	"\|L1DFlushOnVMEntry"
256	"\|MDSClearOnSched"
257	"\|MDSClearOnVMEntry"
258	"\|TPRPatchingEnabled"
259	"\|64bitEnabled"
260	"\|Exclusive"
261	"\|MaxResumeLoops"
262	"\|VmxPleGap"
263	"\|VmxPleWindow"
264	"\|VmxLbr"
265	"\|UseVmxPreemptTimer"
266	"\|SvmPauseFilter"
267	"\|SvmPauseFilterThreshold"
268	"\|SvmVirtVmsaveVmload"
269	"\|SvmVGif"
270	"\|LovelyMesaDrvWorkaround"
271	"\|MissingOS2TlbFlushWorkaround",
272	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
273	if (RT_FAILURE(rc))
274	return rc;
275
276	/** @cfgm{/HM/HMForced, bool, false}
277	* Forces hardware virtualization, no falling back on raw-mode. HM must be
278	* enabled, i.e. /HMEnabled must be true. */
279	bool fHMForced;
280	AssertRelease(pVM->fHMEnabled);
281	fHMForced = true;
282
283	/** @cfgm{/HM/UseNEMInstead, bool, true}
284	* Don't use HM, use NEM instead. */
285	bool fUseNEMInstead = false;
286	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
287	AssertRCReturn(rc, rc);
288	if (fUseNEMInstead && pVM->fHMEnabled)
289	{
290	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
291	pVM->fHMEnabled = false;
292	}
293
294	/** @cfgm{/HM/FallbackToNEM, bool, true}
295	* Enables fallback on NEM. */
296	bool fFallbackToNEM = true;
297	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
298	AssertRCReturn(rc, rc);
299
300	/** @cfgm{/HM/EnableNestedPaging, bool, false}
301	* Enables nested paging (aka extended page tables). */
302	bool fAllowNestedPaging = false;
303	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &fAllowNestedPaging, false);
304	AssertRCReturn(rc, rc);
305
306	/** @cfgm{/HM/EnableUX, bool, true}
307	* Enables the VT-x unrestricted execution feature. */
308	bool fAllowUnrestricted = true;
309	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &fAllowUnrestricted, true);
310	AssertRCReturn(rc, rc);
311
312	/** @cfgm{/HM/EnableLargePages, bool, false}
313	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
314	* page table walking and maybe better TLB hit rate in some cases. */
315	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
316	AssertRCReturn(rc, rc);
317
318	/** @cfgm{/HM/EnableVPID, bool, false}
319	* Enables the VT-x VPID feature. */
320	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
321	AssertRCReturn(rc, rc);
322
323	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
324	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
325	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
326	AssertRCReturn(rc, rc);
327
328	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
329	* Enables AMD64 cpu features.
330	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
331	* already have the support. */
332	#ifdef VBOX_WITH_64_BITS_GUESTS
333	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuestsCfg, HC_ARCH_BITS == 64);
334	AssertLogRelRCReturn(rc, rc);
335	#else
336	pVM->hm.s.fAllow64BitGuestsCfg = false;
337	#endif
338
339	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
340	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
341	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
342	* latest PAUSE instruction to be start of a new PAUSE loop.
343	*/
344	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
345	AssertRCReturn(rc, rc);
346
347	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
348	* The pause-filter exiting window in TSC ticks. When the number of ticks
349	* between the current PAUSE instruction and first PAUSE of a loop exceeds
350	* VmxPleWindow, a VM-exit is triggered.
351	*
352	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
353	*/
354	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
355	AssertRCReturn(rc, rc);
356
357	/** @cfgm{/HM/VmxLbr, bool, false}
358	* Whether to enable LBR for the guest. This is disabled by default as it's only
359	* useful while debugging and enabling it causes a noticeable performance hit. */
360	rc = CFGMR3QueryBoolDef(pCfgHm, "VmxLbr", &pVM->hm.s.vmx.fLbrCfg, false);
361	AssertRCReturn(rc, rc);
362
363	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
364	* A counter that is decrement each time a PAUSE instruction is executed by the
365	* guest. When the counter is 0, a \#VMEXIT is triggered.
366	*
367	* Setting SvmPauseFilterCount to 0 disables pause-filter exiting.
368	*/
369	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
370	AssertRCReturn(rc, rc);
371
372	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
373	* The pause filter threshold in ticks. When the elapsed time (in ticks) between
374	* two successive PAUSE instructions exceeds SvmPauseFilterThreshold, the
375	* PauseFilter count is reset to its initial value. However, if PAUSE is
376	* executed PauseFilter times within PauseFilterThreshold ticks, a VM-exit will
377	* be triggered.
378	*
379	* Requires SvmPauseFilterCount to be non-zero for pause-filter threshold to be
380	* activated.
381	*/
382	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
383	AssertRCReturn(rc, rc);
384
385	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
386	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
387	* available. */
388	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
389	AssertRCReturn(rc, rc);
390
391	/** @cfgm{/HM/SvmVGif, bool, true}
392	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
393	* if it's available. */
394	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
395	AssertRCReturn(rc, rc);
396
397	/** @cfgm{/HM/SvmLbrVirt, bool, false}
398	* Whether to make use of the LBR virtualization feature of the CPU if it's
399	* available. This is disabled by default as it's only useful while debugging
400	* and enabling it causes a small hit to performance. */
401	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmLbrVirt", &pVM->hm.s.svm.fLbrVirt, false);
402	AssertRCReturn(rc, rc);
403
404	/** @cfgm{/HM/Exclusive, bool}
405	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
406	* global init for each host CPU. If false, we do local init each time we wish
407	* to execute guest code.
408	*
409	* On Windows, default is false due to the higher risk of conflicts with other
410	* hypervisors.
411	*
412	* On Mac OS X, this setting is ignored since the code does not handle local
413	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
414	*/
415	#if defined(RT_OS_DARWIN)
416	pVM->hm.s.fGlobalInit = true;
417	#else
418	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
419	# if defined(RT_OS_WINDOWS)
420	false
421	# else
422	true
423	# endif
424	);
425	AssertLogRelRCReturn(rc, rc);
426	#endif
427
428	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
429	* The number of times to resume guest execution before we forcibly return to
430	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
431	* determines the default value. */
432	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoopsCfg, 0 /* set by R0 later */);
433	AssertLogRelRCReturn(rc, rc);
434
435	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
436	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
437	* available. */
438	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimerCfg, true);
439	AssertLogRelRCReturn(rc, rc);
440
441	/** @cfgm{/HM/IBPBOnVMExit, bool}
442	* Costly paranoia setting. */
443	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
444	AssertLogRelRCReturn(rc, rc);
445
446	/** @cfgm{/HM/IBPBOnVMEntry, bool}
447	* Costly paranoia setting. */
448	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
449	AssertLogRelRCReturn(rc, rc);
450
451	/** @cfgm{/HM/L1DFlushOnSched, bool, true}
452	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
453	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnSched", &pVM->hm.s.fL1dFlushOnSched, true);
454	AssertLogRelRCReturn(rc, rc);
455
456	/** @cfgm{/HM/L1DFlushOnVMEntry, bool}
457	* CVE-2018-3646 workaround, ignored on CPUs that aren't affected. */
458	rc = CFGMR3QueryBoolDef(pCfgHm, "L1DFlushOnVMEntry", &pVM->hm.s.fL1dFlushOnVmEntry, false);
459	AssertLogRelRCReturn(rc, rc);
460
461	/* Disable L1DFlushOnSched if L1DFlushOnVMEntry is enabled. */
462	if (pVM->hm.s.fL1dFlushOnVmEntry)
463	pVM->hm.s.fL1dFlushOnSched = false;
464
465	/** @cfgm{/HM/SpecCtrlByHost, bool}
466	* Another expensive paranoia setting. */
467	rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
468	AssertLogRelRCReturn(rc, rc);
469
470	/** @cfgm{/HM/MDSClearOnSched, bool, true}
471	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
472	* ignored on CPUs that aren't affected. */
473	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnSched", &pVM->hm.s.fMdsClearOnSched, true);
474	AssertLogRelRCReturn(rc, rc);
475
476	/** @cfgm{/HM/MDSClearOnVmEntry, bool, false}
477	* CVE-2018-12126, CVE-2018-12130, CVE-2018-12127, CVE-2019-11091 workaround,
478	* ignored on CPUs that aren't affected. */
479	rc = CFGMR3QueryBoolDef(pCfgHm, "MDSClearOnVmEntry", &pVM->hm.s.fMdsClearOnVmEntry, false);
480	AssertLogRelRCReturn(rc, rc);
481
482	/* Disable MDSClearOnSched if MDSClearOnVmEntry is enabled. */
483	if (pVM->hm.s.fMdsClearOnVmEntry)
484	pVM->hm.s.fMdsClearOnSched = false;
485
486	/** @cfgm{/HM/LovelyMesaDrvWorkaround,bool}
487	* Workaround for mesa vmsvga 3d driver making incorrect assumptions about
488	* the hypervisor it is running under. */
489	bool fMesaWorkaround;
490	rc = CFGMR3QueryBoolDef(pCfgHm, "LovelyMesaDrvWorkaround", &fMesaWorkaround, false);
491	AssertLogRelRCReturn(rc, rc);
492	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
493	{
494	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
495	pVCpu->hm.s.fTrapXcptGpForLovelyMesaDrv = fMesaWorkaround;
496	}
497
498	/** @cfgm{/HM/MissingOS2TlbFlushWorkaround,bool}
499	* Workaround OS/2 not flushing the TLB after page directory and page table
500	* modifications when returning to protected mode from a real mode call
501	* (TESTCFG.SYS typically crashes). See ticketref:20625 for details. */
502	rc = CFGMR3QueryBoolDef(pCfgHm, "MissingOS2TlbFlushWorkaround", &pVM->hm.s.fMissingOS2TlbFlushWorkaround, false);
503	AssertLogRelRCReturn(rc, rc);
504
505	/*
506	* Check if VT-x or AMD-v support according to the users wishes.
507	*/
508	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
509	* VERR_SVM_IN_USE. */
510	if (pVM->fHMEnabled)
511	{
512	/*
513	* Register info handlers.
514	*/
515	rc = DBGFR3InfoRegisterInternalEx(pVM, "hm", "Dumps HM info.", hmR3Info, DBGFINFO_FLAGS_ALL_EMTS);
516	AssertRCReturn(rc, rc);
517
518	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
519	DBGFINFO_FLAGS_ALL_EMTS);
520	AssertRCReturn(rc, rc);
521
522	rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
523	hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
524	AssertRCReturn(rc, rc);
525
526	rc = DBGFR3InfoRegisterInternalEx(pVM, "lbr", "Dumps the HM LBR info.", hmR3InfoLbr, DBGFINFO_FLAGS_ALL_EMTS);
527	AssertRCReturn(rc, rc);
528
529
530	uint32_t fCaps;
531	rc = SUPR3QueryVTCaps(&fCaps);
532	if (RT_SUCCESS(rc))
533	{
534	if (fCaps & SUPVTCAPS_AMD_V)
535	{
536	pVM->hm.s.svm.fSupported = true;
537	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
538	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
539	}
540	else if (fCaps & SUPVTCAPS_VT_X)
541	{
542	const char *pszWhy;
543	rc = SUPR3QueryVTxSupported(&pszWhy);
544	if (RT_SUCCESS(rc))
545	{
546	pVM->hm.s.vmx.fSupported = true;
547	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
548	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
549	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
550	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
551	VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
552	}
553	else
554	{
555	/*
556	* Before failing, try fallback to NEM if we're allowed to do that.
557	*/
558	pVM->fHMEnabled = false;
559	Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
560	if (fFallbackToNEM)
561	{
562	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
563	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
564
565	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
566	if ( RT_SUCCESS(rc2)
567	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
568	rc = VINF_SUCCESS;
569	}
570	if (RT_FAILURE(rc))
571	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
572	}
573	}
574	else
575	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
576	VERR_INTERNAL_ERROR_5);
577
578	/*
579	* Disable nested paging and unrestricted guest execution now if they're
580	* configured so that CPUM can make decisions based on our configuration.
581	*/
582	if ( fAllowNestedPaging
583	&& (fCaps & SUPVTCAPS_NESTED_PAGING))
584	{
585	pVM->hm.s.fNestedPagingCfg = true;
586	if (fCaps & SUPVTCAPS_VT_X)
587	{
588	if ( fAllowUnrestricted
589	&& (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST))
590	pVM->hm.s.vmx.fUnrestrictedGuestCfg = true;
591	else
592	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
593	}
594	}
595	else
596	Assert(!pVM->hm.s.fNestedPagingCfg);
597	}
598	else
599	{
600	const char *pszMsg;
601	switch (rc)
602	{
603	case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
604	case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
605	case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
606	case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
607	case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
608	case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
609	case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
610	case VERR_SUP_DRIVERLESS: pszMsg = "Driverless mode"; break;
611	default:
612	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
613	}
614
615	/*
616	* Before failing, try fallback to NEM if we're allowed to do that.
617	*/
618	pVM->fHMEnabled = false;
619	if (fFallbackToNEM)
620	{
621	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
622	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
623	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
624	if ( RT_SUCCESS(rc2)
625	&& pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
626	{
627	rc = VINF_SUCCESS;
628
629	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
630	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
631	}
632	}
633	if (RT_FAILURE(rc))
634	return VM_SET_ERROR(pVM, rc, pszMsg);
635	}
636	}
637	else
638	{
639	/*
640	* Disabled HM mean raw-mode, unless NEM is supposed to be used.
641	*/
642	if (fUseNEMInstead)
643	{
644	rc = NEMR3Init(pVM, false /fFallback/, true);
645	ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
646	if (RT_FAILURE(rc))
647	return rc;
648
649	/* For some reason, HM is in charge or large pages. Make sure to enable them: */
650	PGMSetLargePageUsage(pVM, pVM->hm.s.fLargePages);
651	}
652	if ( pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET
653	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_RAW_MODE
654	\|\| pVM->bMainExecutionEngine == VM_EXEC_ENGINE_HW_VIRT /* paranoia */)
655	return VM_SET_ERROR(pVM, rc, "Misconfigured VM: No guest execution engine available!");
656	}
657
658	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET);
659	Assert(pVM->bMainExecutionEngine != VM_EXEC_ENGINE_RAW_MODE);
660	return VINF_SUCCESS;
661	}
662
663
664	/**
665	* Initializes HM components after ring-3 phase has been fully initialized.
666	*
667	* @returns VBox status code.
668	* @param pVM The cross context VM structure.
669	*/
670	static int hmR3InitFinalizeR3(PVM pVM)
671	{
672	LogFlowFunc(("\n"));
673
674	if (!HMIsEnabled(pVM))
675	return VINF_SUCCESS;
676
677	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
678	{
679	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
680	pVCpu->hm.s.fActive = false;
681	pVCpu->hm.s.fGIMTrapXcptUD = GIMShouldTrapXcptUD(pVCpu); /* Is safe to call now since GIMR3Init() has completed. */
682	}
683
684	/*
685	* Check if L1D flush is needed/possible.
686	*/
687	if ( !pVM->cpum.ro.HostFeatures.fFlushCmd
688	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
689	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End
690	\|\| pVM->cpum.ro.HostFeatures.fArchVmmNeedNotFlushL1d
691	\|\| pVM->cpum.ro.HostFeatures.fArchRdclNo)
692	pVM->hm.s.fL1dFlushOnSched = pVM->hm.s.fL1dFlushOnVmEntry = false;
693
694	/*
695	* Check if MDS flush is needed/possible.
696	* On atoms and knight family CPUs, we will only allow clearing on scheduling.
697	*/
698	if ( !pVM->cpum.ro.HostFeatures.fMdsClear
699	\|\| pVM->cpum.ro.HostFeatures.fArchMdsNo)
700	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
701	else if ( ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Atom_Airmount
702	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Atom_End)
703	\|\| ( pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Phi_KnightsLanding
704	&& pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Phi_End))
705	{
706	if (!pVM->hm.s.fMdsClearOnSched)
707	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry;
708	pVM->hm.s.fMdsClearOnVmEntry = false;
709	}
710	else if ( pVM->cpum.ro.HostFeatures.enmMicroarch < kCpumMicroarch_Intel_Core7_Nehalem
711	\|\| pVM->cpum.ro.HostFeatures.enmMicroarch >= kCpumMicroarch_Intel_Core7_End)
712	pVM->hm.s.fMdsClearOnSched = pVM->hm.s.fMdsClearOnVmEntry = false;
713
714	/*
715	* Statistics.
716	*/
717	#ifdef VBOX_WITH_STATISTICS
718	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
719	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
720	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8", STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
721	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC", STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
722	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
723	#endif
724
725	bool const fCpuSupportsVmx = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() \|\| ASMIsShanghaiCpu();
726	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
727	{
728	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
729	PHMCPU pHmCpu = &pVCpu->hm.s;
730	int rc;
731
732	# define HM_REG_STAT(a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szNmFmt, a_szDesc) do { \
733	rc = STAMR3RegisterF(pVM, a_pVar, a_enmType, s_enmVisibility, a_enmUnit, a_szDesc, a_szNmFmt, idCpu); \
734	AssertRC(rc); \
735	} while (0)
736	# define HM_REG_PROFILE(a_pVar, a_szNmFmt, a_szDesc) \
737	HM_REG_STAT(a_pVar, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, a_szNmFmt, a_szDesc)
738
739	#ifdef VBOX_WITH_STATISTICS
740
741	HM_REG_PROFILE(&pHmCpu->StatPoke, "/PROF/CPU%u/HM/Poke", "Profiling of RTMpPokeCpu.");
742	HM_REG_PROFILE(&pHmCpu->StatSpinPoke, "/PROF/CPU%u/HM/PokeWait", "Profiling of poke wait.");
743	HM_REG_PROFILE(&pHmCpu->StatSpinPokeFailed, "/PROF/CPU%u/HM/PokeWaitFailed", "Profiling of poke wait when RTMpPokeCpu fails.");
744	HM_REG_PROFILE(&pHmCpu->StatEntry, "/PROF/CPU%u/HM/Entry", "Profiling of entry until entering GC.");
745	HM_REG_PROFILE(&pHmCpu->StatPreExit, "/PROF/CPU%u/HM/SwitchFromGC_1", "Profiling of pre-exit processing after returning from GC.");
746	HM_REG_PROFILE(&pHmCpu->StatExitHandling, "/PROF/CPU%u/HM/SwitchFromGC_2", "Profiling of exit handling (longjmps not included!)");
747	HM_REG_PROFILE(&pHmCpu->StatExitIO, "/PROF/CPU%u/HM/SwitchFromGC_2/IO", "I/O.");
748	HM_REG_PROFILE(&pHmCpu->StatExitMovCRx, "/PROF/CPU%u/HM/SwitchFromGC_2/MovCRx", "MOV CRx.");
749	HM_REG_PROFILE(&pHmCpu->StatExitXcptNmi, "/PROF/CPU%u/HM/SwitchFromGC_2/XcptNmi", "Exceptions, NMIs.");
750	HM_REG_PROFILE(&pHmCpu->StatExitVmentry, "/PROF/CPU%u/HM/SwitchFromGC_2/Vmentry", "VMLAUNCH/VMRESUME on Intel or VMRUN on AMD.");
751	HM_REG_PROFILE(&pHmCpu->StatImportGuestState, "/PROF/CPU%u/HM/ImportGuestState", "Profiling of importing guest state from hardware after VM-exit.");
752	HM_REG_PROFILE(&pHmCpu->StatExportGuestState, "/PROF/CPU%u/HM/ExportGuestState", "Profiling of exporting guest state to hardware before VM-entry.");
753	HM_REG_PROFILE(&pHmCpu->StatLoadGuestFpuState, "/PROF/CPU%u/HM/LoadGuestFpuState", "Profiling of CPUMR0LoadGuestFPU.");
754	HM_REG_PROFILE(&pHmCpu->StatInGC, "/PROF/CPU%u/HM/InGC", "Profiling of execution of guest-code in hardware.");
755	# ifdef HM_PROFILE_EXIT_DISPATCH
756	HM_REG_STAT(&pHmCpu->StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
757	"/PROF/CPU%u/HM/ExitDispatch", "Profiling the dispatching of exit handlers.");
758	# endif
759	#endif
760	# define HM_REG_COUNTER(a, b, desc) HM_REG_STAT(a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, b, desc)
761
762	#ifdef VBOX_WITH_STATISTICS
763	HM_REG_COUNTER(&pHmCpu->StatExitAll, "/HM/CPU%u/Exit/All", "Total exits (excludes nested-guest and debug loops exits).");
764	HM_REG_COUNTER(&pHmCpu->StatDebugExitAll, "/HM/CPU%u/Exit/DebugAll", "Total debug-loop exits.");
765	HM_REG_COUNTER(&pHmCpu->StatNestedExitAll, "/HM/CPU%u/Exit/NestedGuest/All", "Total nested-guest exits.");
766	HM_REG_COUNTER(&pHmCpu->StatExitShadowNM, "/HM/CPU%u/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
767	HM_REG_COUNTER(&pHmCpu->StatExitGuestNM, "/HM/CPU%u/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
768	HM_REG_COUNTER(&pHmCpu->StatExitShadowPF, "/HM/CPU%u/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
769	HM_REG_COUNTER(&pHmCpu->StatExitShadowPFEM, "/HM/CPU%u/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
770	HM_REG_COUNTER(&pHmCpu->StatExitGuestPF, "/HM/CPU%u/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
771	HM_REG_COUNTER(&pHmCpu->StatExitGuestUD, "/HM/CPU%u/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
772	HM_REG_COUNTER(&pHmCpu->StatExitGuestSS, "/HM/CPU%u/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
773	HM_REG_COUNTER(&pHmCpu->StatExitGuestNP, "/HM/CPU%u/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
774	HM_REG_COUNTER(&pHmCpu->StatExitGuestTS, "/HM/CPU%u/Exit/Trap/Gst/#TS", "Guest #TS (task switch) exception.");
775	HM_REG_COUNTER(&pHmCpu->StatExitGuestOF, "/HM/CPU%u/Exit/Trap/Gst/#OF", "Guest #OF (overflow) exception.");
776	HM_REG_COUNTER(&pHmCpu->StatExitGuestGP, "/HM/CPU%u/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
777	HM_REG_COUNTER(&pHmCpu->StatExitGuestDE, "/HM/CPU%u/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
778	HM_REG_COUNTER(&pHmCpu->StatExitGuestDF, "/HM/CPU%u/Exit/Trap/Gst/#DF", "Guest #DF (double fault) exception.");
779	HM_REG_COUNTER(&pHmCpu->StatExitGuestBR, "/HM/CPU%u/Exit/Trap/Gst/#BR", "Guest #BR (boundary range exceeded) exception.");
780	#endif
781	HM_REG_COUNTER(&pHmCpu->StatExitGuestAC, "/HM/CPU%u/Exit/Trap/Gst/#AC", "Guest #AC (alignment check) exception.");
782	if (fCpuSupportsVmx)
783	HM_REG_COUNTER(&pHmCpu->StatExitGuestACSplitLock, "/HM/CPU%u/Exit/Trap/Gst/#AC-split-lock", "Guest triggered #AC due to split-lock being enabled on the host (interpreted).");
784	#ifdef VBOX_WITH_STATISTICS
785	HM_REG_COUNTER(&pHmCpu->StatExitGuestDB, "/HM/CPU%u/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
786	HM_REG_COUNTER(&pHmCpu->StatExitGuestMF, "/HM/CPU%u/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
787	HM_REG_COUNTER(&pHmCpu->StatExitGuestBP, "/HM/CPU%u/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
788	HM_REG_COUNTER(&pHmCpu->StatExitGuestXF, "/HM/CPU%u/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
789	HM_REG_COUNTER(&pHmCpu->StatExitGuestXcpUnk, "/HM/CPU%u/Exit/Trap/Gst/Other", "Other guest exceptions.");
790	HM_REG_COUNTER(&pHmCpu->StatExitRdmsr, "/HM/CPU%u/Exit/Instr/Rdmsr", "MSR read.");
791	HM_REG_COUNTER(&pHmCpu->StatExitWrmsr, "/HM/CPU%u/Exit/Instr/Wrmsr", "MSR write.");
792	HM_REG_COUNTER(&pHmCpu->StatExitDRxWrite, "/HM/CPU%u/Exit/Instr/DR-Write", "Debug register write.");
793	HM_REG_COUNTER(&pHmCpu->StatExitDRxRead, "/HM/CPU%u/Exit/Instr/DR-Read", "Debug register read.");
794	HM_REG_COUNTER(&pHmCpu->StatExitCR0Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR0", "CR0 read.");
795	HM_REG_COUNTER(&pHmCpu->StatExitCR2Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR2", "CR2 read.");
796	HM_REG_COUNTER(&pHmCpu->StatExitCR3Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR3", "CR3 read.");
797	HM_REG_COUNTER(&pHmCpu->StatExitCR4Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR4", "CR4 read.");
798	HM_REG_COUNTER(&pHmCpu->StatExitCR8Read, "/HM/CPU%u/Exit/Instr/CR-Read/CR8", "CR8 read.");
799	HM_REG_COUNTER(&pHmCpu->StatExitCR0Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR0", "CR0 write.");
800	HM_REG_COUNTER(&pHmCpu->StatExitCR2Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR2", "CR2 write.");
801	HM_REG_COUNTER(&pHmCpu->StatExitCR3Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR3", "CR3 write.");
802	HM_REG_COUNTER(&pHmCpu->StatExitCR4Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR4", "CR4 write.");
803	HM_REG_COUNTER(&pHmCpu->StatExitCR8Write, "/HM/CPU%u/Exit/Instr/CR-Write/CR8", "CR8 write.");
804	HM_REG_COUNTER(&pHmCpu->StatExitClts, "/HM/CPU%u/Exit/Instr/CLTS", "CLTS instruction.");
805	HM_REG_COUNTER(&pHmCpu->StatExitLmsw, "/HM/CPU%u/Exit/Instr/LMSW", "LMSW instruction.");
806	HM_REG_COUNTER(&pHmCpu->StatExitXdtrAccess, "/HM/CPU%u/Exit/Instr/XdtrAccess", "GDTR, IDTR, LDTR access.");
807	HM_REG_COUNTER(&pHmCpu->StatExitIOWrite, "/HM/CPU%u/Exit/Instr/IO/Write", "I/O write.");
808	HM_REG_COUNTER(&pHmCpu->StatExitIORead, "/HM/CPU%u/Exit/Instr/IO/Read", "I/O read.");
809	HM_REG_COUNTER(&pHmCpu->StatExitIOStringWrite, "/HM/CPU%u/Exit/Instr/IO/WriteString", "String I/O write.");
810	HM_REG_COUNTER(&pHmCpu->StatExitIOStringRead, "/HM/CPU%u/Exit/Instr/IO/ReadString", "String I/O read.");
811	HM_REG_COUNTER(&pHmCpu->StatExitIntWindow, "/HM/CPU%u/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts.");
812	HM_REG_COUNTER(&pHmCpu->StatExitExtInt, "/HM/CPU%u/Exit/ExtInt", "Physical maskable interrupt (host).");
813	#endif
814	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGC, "/HM/CPU%u/Exit/HostNmiInGC", "Host NMI received while in guest context.");
815	HM_REG_COUNTER(&pHmCpu->StatExitHostNmiInGCIpi, "/HM/CPU%u/Exit/HostNmiInGCIpi", "Host NMI received while in guest context dispatched using IPIs.");
816	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/Exit/PreemptTimer", "VMX-preemption timer expired.");
817	#ifdef VBOX_WITH_STATISTICS
818	HM_REG_COUNTER(&pHmCpu->StatExitTprBelowThreshold, "/HM/CPU%u/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
819	HM_REG_COUNTER(&pHmCpu->StatExitTaskSwitch, "/HM/CPU%u/Exit/TaskSwitch", "Task switch caused through task gate in IDT.");
820	HM_REG_COUNTER(&pHmCpu->StatExitApicAccess, "/HM/CPU%u/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
821
822	HM_REG_COUNTER(&pHmCpu->StatSwitchTprMaskedIrq, "/HM/CPU%u/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
823	HM_REG_COUNTER(&pHmCpu->StatSwitchGuestIrq, "/HM/CPU%u/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
824	HM_REG_COUNTER(&pHmCpu->StatSwitchPendingHostIrq, "/HM/CPU%u/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
825	HM_REG_COUNTER(&pHmCpu->StatSwitchHmToR3FF, "/HM/CPU%u/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
826	HM_REG_COUNTER(&pHmCpu->StatSwitchVmReq, "/HM/CPU%u/Switch/VmReq", "Exit to ring-3 due to pending VM requests.");
827	HM_REG_COUNTER(&pHmCpu->StatSwitchPgmPoolFlush, "/HM/CPU%u/Switch/PgmPoolFlush", "Exit to ring-3 due to pending PGM pool flush.");
828	HM_REG_COUNTER(&pHmCpu->StatSwitchDma, "/HM/CPU%u/Switch/PendingDma", "Exit to ring-3 due to pending DMA requests.");
829	HM_REG_COUNTER(&pHmCpu->StatSwitchExitToR3, "/HM/CPU%u/Switch/ExitToR3", "Exit to ring-3 (total).");
830	HM_REG_COUNTER(&pHmCpu->StatSwitchLongJmpToR3, "/HM/CPU%u/Switch/LongJmpToR3", "Longjump to ring-3.");
831	HM_REG_COUNTER(&pHmCpu->StatSwitchMaxResumeLoops, "/HM/CPU%u/Switch/MaxResumeLoops", "Maximum VMRESUME inner-loop counter reached.");
832	HM_REG_COUNTER(&pHmCpu->StatSwitchHltToR3, "/HM/CPU%u/Switch/HltToR3", "HLT causing us to go to ring-3.");
833	HM_REG_COUNTER(&pHmCpu->StatSwitchApicAccessToR3, "/HM/CPU%u/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
834	#endif
835	HM_REG_COUNTER(&pHmCpu->StatSwitchPreempt, "/HM/CPU%u/Switch/Preempting", "EMT has been preempted while in HM context.");
836	#ifdef VBOX_WITH_STATISTICS
837	HM_REG_COUNTER(&pHmCpu->StatSwitchNstGstVmexit, "/HM/CPU%u/Switch/NstGstVmexit", "Nested-guest VM-exit occurred.");
838
839	HM_REG_COUNTER(&pHmCpu->StatInjectInterrupt, "/HM/CPU%u/EventInject/Interrupt", "Injected an external interrupt into the guest.");
840	HM_REG_COUNTER(&pHmCpu->StatInjectXcpt, "/HM/CPU%u/EventInject/Trap", "Injected an exception into the guest.");
841	HM_REG_COUNTER(&pHmCpu->StatInjectReflect, "/HM/CPU%u/EventInject/Reflect", "Reflecting an exception caused due to event injection.");
842	HM_REG_COUNTER(&pHmCpu->StatInjectConvertDF, "/HM/CPU%u/EventInject/ReflectDF", "Injected a converted #DF caused due to event injection.");
843	HM_REG_COUNTER(&pHmCpu->StatInjectInterpret, "/HM/CPU%u/EventInject/Interpret", "Falling back to interpreter for handling exception caused due to event injection.");
844	HM_REG_COUNTER(&pHmCpu->StatInjectReflectNPF, "/HM/CPU%u/EventInject/ReflectNPF", "Reflecting event that caused an EPT violation / nested #PF.");
845
846	HM_REG_COUNTER(&pHmCpu->StatFlushPage, "/HM/CPU%u/Flush/Page", "Invalidating a guest page on all guest CPUs.");
847	HM_REG_COUNTER(&pHmCpu->StatFlushPageManual, "/HM/CPU%u/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
848	HM_REG_COUNTER(&pHmCpu->StatFlushPhysPageManual, "/HM/CPU%u/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
849	HM_REG_COUNTER(&pHmCpu->StatFlushTlb, "/HM/CPU%u/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
850	HM_REG_COUNTER(&pHmCpu->StatFlushTlbManual, "/HM/CPU%u/Flush/TLB/Manual", "Request a full guest-TLB flush.");
851	HM_REG_COUNTER(&pHmCpu->StatFlushTlbNstGst, "/HM/CPU%u/Flush/TLB/NestedGuest", "Request a nested-guest-TLB flush.");
852	HM_REG_COUNTER(&pHmCpu->StatFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
853	HM_REG_COUNTER(&pHmCpu->StatNoFlushTlbWorldSwitch, "/HM/CPU%u/Flush/TLB/Skipped", "No TLB flushing required.");
854	HM_REG_COUNTER(&pHmCpu->StatFlushEntire, "/HM/CPU%u/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
855	HM_REG_COUNTER(&pHmCpu->StatFlushAsid, "/HM/CPU%u/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
856	HM_REG_COUNTER(&pHmCpu->StatFlushNestedPaging, "/HM/CPU%u/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
857	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgVirt, "/HM/CPU%u/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
858	HM_REG_COUNTER(&pHmCpu->StatFlushTlbInvlpgPhys, "/HM/CPU%u/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
859	HM_REG_COUNTER(&pHmCpu->StatTlbShootdown, "/HM/CPU%u/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
860	HM_REG_COUNTER(&pHmCpu->StatTlbShootdownFlush, "/HM/CPU%u/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
861
862	HM_REG_COUNTER(&pHmCpu->StatTscParavirt, "/HM/CPU%u/TSC/Paravirt", "Paravirtualized TSC in effect.");
863	HM_REG_COUNTER(&pHmCpu->StatTscOffset, "/HM/CPU%u/TSC/Offset", "TSC offsetting is in effect.");
864	HM_REG_COUNTER(&pHmCpu->StatTscIntercept, "/HM/CPU%u/TSC/Intercept", "Intercept TSC accesses.");
865
866	HM_REG_COUNTER(&pHmCpu->StatDRxArmed, "/HM/CPU%u/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
867	HM_REG_COUNTER(&pHmCpu->StatDRxContextSwitch, "/HM/CPU%u/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
868	HM_REG_COUNTER(&pHmCpu->StatDRxIoCheck, "/HM/CPU%u/Debug/IOCheck", "Checking for I/O breakpoint.");
869
870	HM_REG_COUNTER(&pHmCpu->StatExportMinimal, "/HM/CPU%u/Export/Minimal", "VM-entry exporting minimal guest-state.");
871	HM_REG_COUNTER(&pHmCpu->StatExportFull, "/HM/CPU%u/Export/Full", "VM-entry exporting the full guest-state.");
872	HM_REG_COUNTER(&pHmCpu->StatLoadGuestFpu, "/HM/CPU%u/Export/GuestFpu", "VM-entry loading the guest-FPU state.");
873	HM_REG_COUNTER(&pHmCpu->StatExportHostState, "/HM/CPU%u/Export/HostState", "VM-entry exporting host-state.");
874
875	if (fCpuSupportsVmx)
876	{
877	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRip, "/HM/CPU%u/WriteHostRIP", "Number of VMX_VMCS_HOST_RIP instructions.");
878	HM_REG_COUNTER(&pHmCpu->StatVmxWriteHostRsp, "/HM/CPU%u/WriteHostRSP", "Number of VMX_VMCS_HOST_RSP instructions.");
879	HM_REG_COUNTER(&pHmCpu->StatVmxVmLaunch, "/HM/CPU%u/VMLaunch", "Number of VM-entries using VMLAUNCH.");
880	HM_REG_COUNTER(&pHmCpu->StatVmxVmResume, "/HM/CPU%u/VMResume", "Number of VM-entries using VMRESUME.");
881	}
882
883	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelBase, "/HM/CPU%u/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
884	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelLimit, "/HM/CPU%u/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
885	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRmSelAttr, "/HM/CPU%u/VMXCheck/RMSelAttrs", "Could not use VMX due to unsuitable real-mode selector attributes.");
886
887	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelBase, "/HM/CPU%u/VMXCheck/V86SelBase", "Could not use VMX due to unsuitable v8086-mode selector base.");
888	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelLimit, "/HM/CPU%u/VMXCheck/V86SelLimit", "Could not use VMX due to unsuitable v8086-mode selector limit.");
889	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadV86SelAttr, "/HM/CPU%u/VMXCheck/V86SelAttrs", "Could not use VMX due to unsuitable v8086-mode selector attributes.");
890
891	HM_REG_COUNTER(&pHmCpu->StatVmxCheckRmOk, "/HM/CPU%u/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
892	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadSel, "/HM/CPU%u/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
893	HM_REG_COUNTER(&pHmCpu->StatVmxCheckBadRpl, "/HM/CPU%u/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
894	HM_REG_COUNTER(&pHmCpu->StatVmxCheckPmOk, "/HM/CPU%u/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
895	#endif
896	if (fCpuSupportsVmx)
897	{
898	HM_REG_COUNTER(&pHmCpu->StatExitPreemptTimer, "/HM/CPU%u/PreemptTimer", "VMX-preemption timer fired.");
899	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadline, "/HM/CPU%u/PreemptTimer/ReusingDeadline", "VMX-preemption timer arming logic using previously calculated deadline");
900	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionReusingDeadlineExpired, "/HM/CPU%u/PreemptTimer/ReusingDeadlineExpired", "VMX-preemption timer arming logic found previous deadline already expired (ignored)");
901	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadline, "/HM/CPU%u/PreemptTimer/RecalcingDeadline", "VMX-preemption timer arming logic recalculating the deadline (slightly expensive)");
902	HM_REG_COUNTER(&pHmCpu->StatVmxPreemptionRecalcingDeadlineExpired, "/HM/CPU%u/PreemptTimer/RecalcingDeadlineExpired", "VMX-preemption timer arming logic found recalculated deadline expired (ignored)");
903	}
904	#ifdef VBOX_WITH_STATISTICS
905	/*
906	* Guest Exit reason stats.
907	*/
908	if (fCpuSupportsVmx)
909	{
910	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
911	{
912	const char *pszExitName = HMGetVmxExitName(j);
913	if (pszExitName)
914	{
915	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
916	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
917	AssertRCReturn(rc, rc);
918	}
919	}
920	}
921	else
922	{
923	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
924	{
925	const char *pszExitName = HMGetSvmExitName(j);
926	if (pszExitName)
927	{
928	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
929	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/Reason/%02x", idCpu, j);
930	AssertRC(rc);
931	}
932	}
933	}
934	HM_REG_COUNTER(&pHmCpu->StatExitReasonNpf, "/HM/CPU%u/Exit/Reason/#NPF", "Nested page faults");
935
936	#if defined(VBOX_WITH_NESTED_HWVIRT_SVM) \|\| defined(VBOX_WITH_NESTED_HWVIRT_VMX)
937	/*
938	* Nested-guest VM-exit reason stats.
939	*/
940	if (fCpuSupportsVmx)
941	{
942	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
943	{
944	const char *pszExitName = HMGetVmxExitName(j);
945	if (pszExitName)
946	{
947	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
948	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
949	AssertRC(rc);
950	}
951	}
952	}
953	else
954	{
955	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
956	{
957	const char *pszExitName = HMGetSvmExitName(j);
958	if (pszExitName)
959	{
960	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
961	STAMUNIT_OCCURENCES, pszExitName, "/HM/CPU%u/Exit/NestedGuest/Reason/%02x", idCpu, j);
962	AssertRC(rc);
963	}
964	}
965	}
966	HM_REG_COUNTER(&pHmCpu->StatNestedExitReasonNpf, "/HM/CPU%u/Exit/NestedGuest/Reason/#NPF", "Nested page faults");
967	#endif
968
969	/*
970	* Injected interrupts stats.
971	*/
972	char szDesc[64];
973	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedIrqs); j++)
974	{
975	RTStrPrintf(&szDesc[0], sizeof(szDesc), "Interrupt %u", j);
976	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
977	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectIntr/%02X", idCpu, j);
978	AssertRC(rc);
979	}
980
981	/*
982	* Injected exception stats.
983	*/
984	for (unsigned j = 0; j < RT_ELEMENTS(pHmCpu->aStatInjectedXcpts); j++)
985	{
986	RTStrPrintf(&szDesc[0], sizeof(szDesc), "%s exception", hmR3GetXcptName(j));
987	rc = STAMR3RegisterF(pVM, &pHmCpu->aStatInjectedXcpts[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
988	STAMUNIT_OCCURENCES, szDesc, "/HM/CPU%u/EventInject/InjectXcpt/%02X", idCpu, j);
989	AssertRC(rc);
990	}
991
992	#endif /* VBOX_WITH_STATISTICS */
993	#undef HM_REG_COUNTER
994	#undef HM_REG_PROFILE
995	#undef HM_REG_STAT
996	}
997
998	return VINF_SUCCESS;
999	}
1000
1001
1002	/**
1003	* Called when a init phase has completed.
1004	*
1005	* @returns VBox status code.
1006	* @param pVM The cross context VM structure.
1007	* @param enmWhat The phase that completed.
1008	*/
1009	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1010	{
1011	switch (enmWhat)
1012	{
1013	case VMINITCOMPLETED_RING3:
1014	return hmR3InitFinalizeR3(pVM);
1015	case VMINITCOMPLETED_RING0:
1016	return hmR3InitFinalizeR0(pVM);
1017	default:
1018	return VINF_SUCCESS;
1019	}
1020	}
1021
1022
1023	/**
1024	* Turns off normal raw mode features.
1025	*
1026	* @param pVM The cross context VM structure.
1027	*/
1028	static void hmR3DisableRawMode(PVM pVM)
1029	{
1030	/** @todo r=bird: HM shouldn't be doing this crap. */
1031	/* Reinit the paging mode to force the new shadow mode. */
1032	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1033	{
1034	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1035	PGMHCChangeMode(pVM, pVCpu, PGMMODE_REAL);
1036	}
1037	}
1038
1039
1040	/**
1041	* Initialize VT-x or AMD-V.
1042	*
1043	* @returns VBox status code.
1044	* @param pVM The cross context VM structure.
1045	*/
1046	static int hmR3InitFinalizeR0(PVM pVM)
1047	{
1048	int rc;
1049
1050	if (!HMIsEnabled(pVM))
1051	return VINF_SUCCESS;
1052
1053	/*
1054	* Hack to allow users to work around broken BIOSes that incorrectly set
1055	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1056	*/
1057	if ( !pVM->hm.s.vmx.fSupported
1058	&& !pVM->hm.s.svm.fSupported
1059	&& pVM->hm.s.ForR3.rcInit == VERR_SVM_IN_USE /* implies functional AMD-V */
1060	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1061	{
1062	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1063	pVM->hm.s.svm.fSupported = true;
1064	pVM->hm.s.svm.fIgnoreInUseError = true;
1065	pVM->hm.s.ForR3.rcInit = VINF_SUCCESS;
1066	}
1067
1068	/*
1069	* Report ring-0 init errors.
1070	*/
1071	if ( !pVM->hm.s.vmx.fSupported
1072	&& !pVM->hm.s.svm.fSupported)
1073	{
1074	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.ForR3.rcInit));
1075	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.ForR3.vmx.u64HostFeatCtrl));
1076	switch (pVM->hm.s.ForR3.rcInit)
1077	{
1078	case VERR_VMX_IN_VMX_ROOT_MODE:
1079	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1080	case VERR_VMX_NO_VMX:
1081	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1082	case VERR_VMX_MSR_VMX_DISABLED:
1083	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1084	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1085	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1086	case VERR_VMX_MSR_LOCKING_FAILED:
1087	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1088	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1089	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1090	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1091	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1092
1093	case VERR_SVM_IN_USE:
1094	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1095	case VERR_SVM_NO_SVM:
1096	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1097	case VERR_SVM_DISABLED:
1098	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1099	}
1100	return VMSetError(pVM, pVM->hm.s.ForR3.rcInit, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.ForR3.rcInit);
1101	}
1102
1103	/*
1104	* Enable VT-x or AMD-V on all host CPUs.
1105	*/
1106	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1107	if (RT_FAILURE(rc))
1108	{
1109	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1110	HMR3CheckError(pVM, rc);
1111	return rc;
1112	}
1113
1114	/*
1115	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1116	* (Main should have taken care of this already)
1117	*/
1118	if (!PDMHasIoApic(pVM))
1119	{
1120	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1121	pVM->hm.s.fTprPatchingAllowed = false;
1122	}
1123
1124	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool fL1dFlushOnVmEntry=%RTbool); fL1dFlushOnSched=%RTbool fMdsClearOnVmEntry=%RTbool\n",
1125	pVM->hm.s.ForR3.fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry, pVM->hm.s.fL1dFlushOnVmEntry,
1126	pVM->hm.s.fL1dFlushOnSched, pVM->hm.s.fMdsClearOnVmEntry));
1127
1128	/*
1129	* Do the vendor specific initialization
1130	*
1131	* Note! We disable release log buffering here since we're doing relatively
1132	* lot of logging and doesn't want to hit the disk with each LogRel
1133	* statement.
1134	*/
1135	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1136	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1137	if (pVM->hm.s.vmx.fSupported)
1138	rc = hmR3InitFinalizeR0Intel(pVM);
1139	else
1140	rc = hmR3InitFinalizeR0Amd(pVM);
1141	LogRel((pVM->hm.s.fGlobalInit ? "HM: VT-x/AMD-V init method: Global\n"
1142	: "HM: VT-x/AMD-V init method: Local\n"));
1143	RTLogRelSetBuffering(fOldBuffered);
1144	pVM->hm.s.fInitialized = true;
1145
1146	return rc;
1147	}
1148
1149
1150	/**
1151	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1152	*/
1153	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1154	{
1155	NOREF(pVM);
1156	NOREF(pvAllocation);
1157	NOREF(GCPhysAllocation);
1158	}
1159
1160
1161	/**
1162	* Returns a description of the VMCS (and associated regions') memory type given the
1163	* IA32_VMX_BASIC MSR.
1164	*
1165	* @returns The descriptive memory type.
1166	* @param uMsrVmxBasic IA32_VMX_BASIC MSR value.
1167	*/
1168	static const char *hmR3VmxGetMemTypeDesc(uint64_t uMsrVmxBasic)
1169	{
1170	uint8_t const uMemType = RT_BF_GET(uMsrVmxBasic, VMX_BF_BASIC_VMCS_MEM_TYPE);
1171	switch (uMemType)
1172	{
1173	case VMX_BASIC_MEM_TYPE_WB: return "Write Back (WB)";
1174	case VMX_BASIC_MEM_TYPE_UC: return "Uncacheable (UC)";
1175	}
1176	return "Unknown";
1177	}
1178
1179
1180	/**
1181	* Returns a single-line description of all the activity-states supported by the CPU
1182	* given the IA32_VMX_MISC MSR.
1183	*
1184	* @returns All supported activity states.
1185	* @param uMsrMisc IA32_VMX_MISC MSR value.
1186	*/
1187	static const char *hmR3VmxGetActivityStateAllDesc(uint64_t uMsrMisc)
1188	{
1189	static const char * const s_apszActStates[] =
1190	{
1191	"",
1192	" ( HLT )",
1193	" ( SHUTDOWN )",
1194	" ( HLT SHUTDOWN )",
1195	" ( SIPI_WAIT )",
1196	" ( HLT SIPI_WAIT )",
1197	" ( SHUTDOWN SIPI_WAIT )",
1198	" ( HLT SHUTDOWN SIPI_WAIT )"
1199	};
1200	uint8_t const idxActStates = RT_BF_GET(uMsrMisc, VMX_BF_MISC_ACTIVITY_STATES);
1201	Assert(idxActStates < RT_ELEMENTS(s_apszActStates));
1202	return s_apszActStates[idxActStates];
1203	}
1204
1205
1206	/**
1207	* Reports MSR_IA32_FEATURE_CONTROL MSR to the log.
1208	*
1209	* @param fFeatMsr The feature control MSR value.
1210	*/
1211	static void hmR3VmxReportFeatCtlMsr(uint64_t fFeatMsr)
1212	{
1213	uint64_t const val = fFeatMsr;
1214	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", val));
1215	HMVMX_REPORT_MSR_CAP(val, "LOCK", MSR_IA32_FEATURE_CONTROL_LOCK);
1216	HMVMX_REPORT_MSR_CAP(val, "SMX_VMXON", MSR_IA32_FEATURE_CONTROL_SMX_VMXON);
1217	HMVMX_REPORT_MSR_CAP(val, "VMXON", MSR_IA32_FEATURE_CONTROL_VMXON);
1218	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN0", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_0);
1219	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN1", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_1);
1220	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN2", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_2);
1221	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN3", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_3);
1222	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN4", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_4);
1223	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN5", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_5);
1224	HMVMX_REPORT_MSR_CAP(val, "SENTER_LOCAL_FN6", MSR_IA32_FEATURE_CONTROL_SENTER_LOCAL_FN_6);
1225	HMVMX_REPORT_MSR_CAP(val, "SENTER_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SENTER_GLOBAL_EN);
1226	HMVMX_REPORT_MSR_CAP(val, "SGX_LAUNCH_EN", MSR_IA32_FEATURE_CONTROL_SGX_LAUNCH_EN);
1227	HMVMX_REPORT_MSR_CAP(val, "SGX_GLOBAL_EN", MSR_IA32_FEATURE_CONTROL_SGX_GLOBAL_EN);
1228	HMVMX_REPORT_MSR_CAP(val, "LMCE", MSR_IA32_FEATURE_CONTROL_LMCE);
1229	if (!(val & MSR_IA32_FEATURE_CONTROL_LOCK))
1230	LogRel(("HM: MSR_IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1231	}
1232
1233
1234	/**
1235	* Reports MSR_IA32_VMX_BASIC MSR to the log.
1236	*
1237	* @param uBasicMsr The VMX basic MSR value.
1238	*/
1239	static void hmR3VmxReportBasicMsr(uint64_t uBasicMsr)
1240	{
1241	LogRel(("HM: MSR_IA32_VMX_BASIC = %#RX64\n", uBasicMsr));
1242	LogRel(("HM: VMCS id = %#x\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_ID)));
1243	LogRel(("HM: VMCS size = %u bytes\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_SIZE)));
1244	LogRel(("HM: VMCS physical address limit = %s\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_PHYSADDR_WIDTH) ?
1245	"< 4 GB" : "None"));
1246	LogRel(("HM: VMCS memory type = %s\n", hmR3VmxGetMemTypeDesc(uBasicMsr)));
1247	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_DUAL_MON)));
1248	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_VMCS_INS_OUTS)));
1249	LogRel(("HM: Supports true-capability MSRs = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_TRUE_CTLS)));
1250	LogRel(("HM: VM-entry Xcpt error-code optional = %RTbool\n", RT_BF_GET(uBasicMsr, VMX_BF_BASIC_XCPT_ERRCODE)));
1251	}
1252
1253
1254	/**
1255	* Reports MSR_IA32_PINBASED_CTLS to the log.
1256	*
1257	* @param pVmxMsr Pointer to the VMX MSR.
1258	*/
1259	static void hmR3VmxReportPinBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1260	{
1261	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1262	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1263	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVmxMsr->u));
1264	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EXT_INT_EXIT", VMX_PIN_CTLS_EXT_INT_EXIT);
1265	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_EXIT", VMX_PIN_CTLS_NMI_EXIT);
1266	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRTUAL_NMI", VMX_PIN_CTLS_VIRT_NMI);
1267	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PREEMPT_TIMER", VMX_PIN_CTLS_PREEMPT_TIMER);
1268	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "POSTED_INT", VMX_PIN_CTLS_POSTED_INT);
1269	}
1270
1271
1272	/**
1273	* Reports MSR_IA32_VMX_PROCBASED_CTLS MSR to the log.
1274	*
1275	* @param pVmxMsr Pointer to the VMX MSR.
1276	*/
1277	static void hmR3VmxReportProcBasedCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1278	{
1279	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1280	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1281	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVmxMsr->u));
1282	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INT_WINDOW_EXIT", VMX_PROC_CTLS_INT_WINDOW_EXIT);
1283	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TSC_OFFSETTING", VMX_PROC_CTLS_USE_TSC_OFFSETTING);
1284	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HLT_EXIT", VMX_PROC_CTLS_HLT_EXIT);
1285	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVLPG_EXIT", VMX_PROC_CTLS_INVLPG_EXIT);
1286	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MWAIT_EXIT", VMX_PROC_CTLS_MWAIT_EXIT);
1287	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDPMC_EXIT", VMX_PROC_CTLS_RDPMC_EXIT);
1288	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSC_EXIT", VMX_PROC_CTLS_RDTSC_EXIT);
1289	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_LOAD_EXIT", VMX_PROC_CTLS_CR3_LOAD_EXIT);
1290	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR3_STORE_EXIT", VMX_PROC_CTLS_CR3_STORE_EXIT);
1291	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TERTIARY_CTLS", VMX_PROC_CTLS_USE_TERTIARY_CTLS);
1292	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_LOAD_EXIT", VMX_PROC_CTLS_CR8_LOAD_EXIT);
1293	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CR8_STORE_EXIT", VMX_PROC_CTLS_CR8_STORE_EXIT);
1294	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_TPR_SHADOW", VMX_PROC_CTLS_USE_TPR_SHADOW);
1295	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "NMI_WINDOW_EXIT", VMX_PROC_CTLS_NMI_WINDOW_EXIT);
1296	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MOV_DR_EXIT", VMX_PROC_CTLS_MOV_DR_EXIT);
1297	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNCOND_IO_EXIT", VMX_PROC_CTLS_UNCOND_IO_EXIT);
1298	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_IO_BITMAPS", VMX_PROC_CTLS_USE_IO_BITMAPS);
1299	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_TRAP_FLAG", VMX_PROC_CTLS_MONITOR_TRAP_FLAG);
1300	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_MSR_BITMAPS", VMX_PROC_CTLS_USE_MSR_BITMAPS);
1301	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MONITOR_EXIT", VMX_PROC_CTLS_MONITOR_EXIT);
1302	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_EXIT", VMX_PROC_CTLS_PAUSE_EXIT);
1303	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USE_SECONDARY_CTLS", VMX_PROC_CTLS_USE_SECONDARY_CTLS);
1304	}
1305
1306
1307	/**
1308	* Reports MSR_IA32_VMX_PROCBASED_CTLS2 MSR to the log.
1309	*
1310	* @param pVmxMsr Pointer to the VMX MSR.
1311	*/
1312	static void hmR3VmxReportProcBasedCtls2Msr(PCVMXCTLSMSR pVmxMsr)
1313	{
1314	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1315	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1316	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVmxMsr->u));
1317	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_APIC_ACCESS", VMX_PROC_CTLS2_VIRT_APIC_ACCESS);
1318	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT", VMX_PROC_CTLS2_EPT);
1319	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DESC_TABLE_EXIT", VMX_PROC_CTLS2_DESC_TABLE_EXIT);
1320	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDTSCP", VMX_PROC_CTLS2_RDTSCP);
1321	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_X2APIC_MODE", VMX_PROC_CTLS2_VIRT_X2APIC_MODE);
1322	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VPID", VMX_PROC_CTLS2_VPID);
1323	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "WBINVD_EXIT", VMX_PROC_CTLS2_WBINVD_EXIT);
1324	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "UNRESTRICTED_GUEST", VMX_PROC_CTLS2_UNRESTRICTED_GUEST);
1325	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "APIC_REG_VIRT", VMX_PROC_CTLS2_APIC_REG_VIRT);
1326	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VIRT_INT_DELIVERY", VMX_PROC_CTLS2_VIRT_INT_DELIVERY);
1327	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PAUSE_LOOP_EXIT", VMX_PROC_CTLS2_PAUSE_LOOP_EXIT);
1328	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDRAND_EXIT", VMX_PROC_CTLS2_RDRAND_EXIT);
1329	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "INVPCID", VMX_PROC_CTLS2_INVPCID);
1330	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMFUNC", VMX_PROC_CTLS2_VMFUNC);
1331	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "VMCS_SHADOWING", VMX_PROC_CTLS2_VMCS_SHADOWING);
1332	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLS_EXIT", VMX_PROC_CTLS2_ENCLS_EXIT);
1333	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "RDSEED_EXIT", VMX_PROC_CTLS2_RDSEED_EXIT);
1334	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PML", VMX_PROC_CTLS2_PML);
1335	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "EPT_XCPT_VE", VMX_PROC_CTLS2_EPT_XCPT_VE);
1336	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
1337	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "XSAVES_XRSTORS", VMX_PROC_CTLS2_XSAVES_XRSTORS);
1338	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "MODE_BASED_EPT_PERM", VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
1339	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SPP_EPT", VMX_PROC_CTLS2_SPP_EPT);
1340	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "PT_EPT", VMX_PROC_CTLS2_PT_EPT);
1341	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "TSC_SCALING", VMX_PROC_CTLS2_TSC_SCALING);
1342	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "USER_WAIT_PAUSE", VMX_PROC_CTLS2_USER_WAIT_PAUSE);
1343	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENCLV_EXIT", VMX_PROC_CTLS2_ENCLV_EXIT);
1344	}
1345
1346
1347	/**
1348	* Reports MSR_IA32_VMX_PROCBASED_CTLS3 MSR to the log.
1349	*
1350	* @param uProcCtls3 The tertiary processor-based VM-execution control MSR.
1351	*/
1352	static void hmR3VmxReportProcBasedCtls3Msr(uint64_t uProcCtls3)
1353	{
1354	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS3 = %#RX64\n", uProcCtls3));
1355	LogRel(("HM: LOADIWKEY_EXIT = %RTbool\n", RT_BOOL(uProcCtls3 & VMX_PROC_CTLS3_LOADIWKEY_EXIT)));
1356	}
1357
1358
1359	/**
1360	* Reports MSR_IA32_VMX_ENTRY_CTLS to the log.
1361	*
1362	* @param pVmxMsr Pointer to the VMX MSR.
1363	*/
1364	static void hmR3VmxReportEntryCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1365	{
1366	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1367	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1368	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVmxMsr->u));
1369	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_DEBUG", VMX_ENTRY_CTLS_LOAD_DEBUG);
1370	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "IA32E_MODE_GUEST", VMX_ENTRY_CTLS_IA32E_MODE_GUEST);
1371	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ENTRY_TO_SMM", VMX_ENTRY_CTLS_ENTRY_TO_SMM);
1372	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "DEACTIVATE_DUAL_MON", VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
1373	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_ENTRY_CTLS_LOAD_PERF_MSR);
1374	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_ENTRY_CTLS_LOAD_PAT_MSR);
1375	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_ENTRY_CTLS_LOAD_EFER_MSR);
1376	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_BNDCFGS_MSR", VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR);
1377	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
1378	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_RTIT_CTL_MSR", VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR);
1379	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_ENTRY_CTLS_LOAD_CET_STATE);
1380	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_ENTRY_CTLS_LOAD_PKRS_MSR);
1381	}
1382
1383
1384	/**
1385	* Reports MSR_IA32_VMX_EXIT_CTLS to the log.
1386	*
1387	* @param pVmxMsr Pointer to the VMX MSR.
1388	*/
1389	static void hmR3VmxReportExitCtlsMsr(PCVMXCTLSMSR pVmxMsr)
1390	{
1391	uint64_t const fAllowed1 = pVmxMsr->n.allowed1;
1392	uint64_t const fAllowed0 = pVmxMsr->n.allowed0;
1393	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVmxMsr->u));
1394	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_DEBUG", VMX_EXIT_CTLS_SAVE_DEBUG);
1395	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "HOST_ADDR_SPACE_SIZE", VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE);
1396	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PERF_MSR", VMX_EXIT_CTLS_LOAD_PERF_MSR);
1397	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "ACK_EXT_INT", VMX_EXIT_CTLS_ACK_EXT_INT);
1398	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PAT_MSR", VMX_EXIT_CTLS_SAVE_PAT_MSR);
1399	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PAT_MSR", VMX_EXIT_CTLS_LOAD_PAT_MSR);
1400	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_EFER_MSR", VMX_EXIT_CTLS_SAVE_EFER_MSR);
1401	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_EFER_MSR", VMX_EXIT_CTLS_LOAD_EFER_MSR);
1402	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "SAVE_PREEMPT_TIMER", VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER);
1403	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_BNDCFGS_MSR", VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR);
1404	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CONCEAL_VMX_FROM_PT", VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT);
1405	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "CLEAR_RTIT_CTL_MSR", VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR);
1406	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_CET_STATE", VMX_EXIT_CTLS_LOAD_CET_STATE);
1407	HMVMX_REPORT_FEAT(fAllowed1, fAllowed0, "LOAD_PKRS_MSR", VMX_EXIT_CTLS_LOAD_PKRS_MSR);
1408	}
1409
1410
1411	/**
1412	* Reports MSR_IA32_VMX_EPT_VPID_CAP MSR to the log.
1413	*
1414	* @param fCaps The VMX EPT/VPID capability MSR value.
1415	*/
1416	static void hmR3VmxReportEptVpidCapsMsr(uint64_t fCaps)
1417	{
1418	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", fCaps));
1419	HMVMX_REPORT_MSR_CAP(fCaps, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1420	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1421	HMVMX_REPORT_MSR_CAP(fCaps, "PAGE_WALK_LENGTH_5", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_5);
1422	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_UC", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_UC);
1423	HMVMX_REPORT_MSR_CAP(fCaps, "MEMTYPE_WB", MSR_IA32_VMX_EPT_VPID_CAP_MEMTYPE_WB);
1424	HMVMX_REPORT_MSR_CAP(fCaps, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1425	HMVMX_REPORT_MSR_CAP(fCaps, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1426	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1427	HMVMX_REPORT_MSR_CAP(fCaps, "ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_ACCESS_DIRTY);
1428	HMVMX_REPORT_MSR_CAP(fCaps, "ADVEXITINFO_EPT_VIOLATION", MSR_IA32_VMX_EPT_VPID_CAP_ADVEXITINFO_EPT_VIOLATION);
1429	HMVMX_REPORT_MSR_CAP(fCaps, "SUPER_SHW_STACK", MSR_IA32_VMX_EPT_VPID_CAP_SUPER_SHW_STACK);
1430	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1431	HMVMX_REPORT_MSR_CAP(fCaps, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1432	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1433	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1434	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1435	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1436	HMVMX_REPORT_MSR_CAP(fCaps, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1437	}
1438
1439
1440	/**
1441	* Reports MSR_IA32_VMX_MISC MSR to the log.
1442	*
1443	* @param pVM Pointer to the VM.
1444	* @param fMisc The VMX misc. MSR value.
1445	*/
1446	static void hmR3VmxReportMiscMsr(PVM pVM, uint64_t fMisc)
1447	{
1448	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", fMisc));
1449	uint8_t const cPreemptTimerShift = RT_BF_GET(fMisc, VMX_BF_MISC_PREEMPT_TIMER_TSC);
1450	if (cPreemptTimerShift == pVM->hm.s.vmx.cPreemptTimerShift)
1451	LogRel(("HM: PREEMPT_TIMER_TSC = %#x\n", cPreemptTimerShift));
1452	else
1453	{
1454	LogRel(("HM: PREEMPT_TIMER_TSC = %#x - erratum detected, using %#x instead\n", cPreemptTimerShift,
1455	pVM->hm.s.vmx.cPreemptTimerShift));
1456	}
1457	LogRel(("HM: EXIT_SAVE_EFER_LMA = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_EXIT_SAVE_EFER_LMA)));
1458	LogRel(("HM: ACTIVITY_STATES = %#x%s\n", RT_BF_GET(fMisc, VMX_BF_MISC_ACTIVITY_STATES),
1459	hmR3VmxGetActivityStateAllDesc(fMisc)));
1460	LogRel(("HM: INTEL_PT = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_INTEL_PT)));
1461	LogRel(("HM: SMM_READ_SMBASE_MSR = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_SMM_READ_SMBASE_MSR)));
1462	LogRel(("HM: CR3_TARGET = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_CR3_TARGET)));
1463	LogRel(("HM: MAX_MSR = %#x ( %u )\n", RT_BF_GET(fMisc, VMX_BF_MISC_MAX_MSRS),
1464	VMX_MISC_MAX_MSRS(fMisc)));
1465	LogRel(("HM: VMXOFF_BLOCK_SMI = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMXOFF_BLOCK_SMI)));
1466	LogRel(("HM: VMWRITE_ALL = %RTbool\n", RT_BF_GET(fMisc, VMX_BF_MISC_VMWRITE_ALL)));
1467	LogRel(("HM: ENTRY_INJECT_SOFT_INT = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_ENTRY_INJECT_SOFT_INT)));
1468	LogRel(("HM: MSEG_ID = %#x\n", RT_BF_GET(fMisc, VMX_BF_MISC_MSEG_ID)));
1469	}
1470
1471
1472	/**
1473	* Reports MSR_IA32_VMX_VMCS_ENUM MSR to the log.
1474	*
1475	* @param uVmcsEnum The VMX VMCS enum MSR value.
1476	*/
1477	static void hmR3VmxReportVmcsEnumMsr(uint64_t uVmcsEnum)
1478	{
1479	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", uVmcsEnum));
1480	LogRel(("HM: HIGHEST_IDX = %#x\n", RT_BF_GET(uVmcsEnum, VMX_BF_VMCS_ENUM_HIGHEST_IDX)));
1481	}
1482
1483
1484	/**
1485	* Reports MSR_IA32_VMX_VMFUNC MSR to the log.
1486	*
1487	* @param uVmFunc The VMX VMFUNC MSR value.
1488	*/
1489	static void hmR3VmxReportVmFuncMsr(uint64_t uVmFunc)
1490	{
1491	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", uVmFunc));
1492	HMVMX_REPORT_ALLOWED_FEAT(uVmFunc, "EPTP_SWITCHING", RT_BF_GET(uVmFunc, VMX_BF_VMFUNC_EPTP_SWITCHING));
1493	}
1494
1495
1496	/**
1497	* Reports VMX CR0, CR4 fixed MSRs.
1498	*
1499	* @param pMsrs Pointer to the VMX MSRs.
1500	*/
1501	static void hmR3VmxReportCrFixedMsrs(PVMXMSRS pMsrs)
1502	{
1503	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pMsrs->u64Cr0Fixed0));
1504	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pMsrs->u64Cr0Fixed1));
1505	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pMsrs->u64Cr4Fixed0));
1506	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pMsrs->u64Cr4Fixed1));
1507	}
1508
1509
1510	/**
1511	* Finish VT-x initialization (after ring-0 init).
1512	*
1513	* @returns VBox status code.
1514	* @param pVM The cross context VM structure.
1515	*/
1516	static int hmR3InitFinalizeR0Intel(PVM pVM)
1517	{
1518	int rc;
1519
1520	LogFunc(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1521	AssertLogRelReturn(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl != 0, VERR_HM_IPE_4);
1522
1523	LogRel(("HM: Using VT-x implementation 3.0\n"));
1524	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1525	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostCr4));
1526	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostMsrEfer));
1527	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.ForR3.vmx.u64HostSmmMonitorCtl));
1528
1529	hmR3VmxReportFeatCtlMsr(pVM->hm.s.ForR3.vmx.u64HostFeatCtrl);
1530	hmR3VmxReportBasicMsr(pVM->hm.s.ForR3.vmx.Msrs.u64Basic);
1531
1532	hmR3VmxReportPinBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.PinCtls);
1533	hmR3VmxReportProcBasedCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls);
1534	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1535	hmR3VmxReportProcBasedCtls2Msr(&pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2);
1536	if (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_TERTIARY_CTLS)
1537	hmR3VmxReportProcBasedCtls3Msr(pVM->hm.s.ForR3.vmx.Msrs.u64ProcCtls3);
1538
1539	hmR3VmxReportEntryCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.EntryCtls);
1540	hmR3VmxReportExitCtlsMsr(&pVM->hm.s.ForR3.vmx.Msrs.ExitCtls);
1541
1542	if (RT_BF_GET(pVM->hm.s.ForR3.vmx.Msrs.u64Basic, VMX_BF_BASIC_TRUE_CTLS))
1543	{
1544	/* We don't extensively dump the true capability MSRs as we don't use them, see @bugref{9180#c5}. */
1545	LogRel(("HM: MSR_IA32_VMX_TRUE_PINBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TruePinCtls));
1546	LogRel(("HM: MSR_IA32_VMX_TRUE_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueProcCtls));
1547	LogRel(("HM: MSR_IA32_VMX_TRUE_ENTRY_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueEntryCtls));
1548	LogRel(("HM: MSR_IA32_VMX_TRUE_EXIT_CTLS = %#RX64\n", pVM->hm.s.ForR3.vmx.Msrs.TrueExitCtls));
1549	}
1550
1551	hmR3VmxReportMiscMsr(pVM, pVM->hm.s.ForR3.vmx.Msrs.u64Misc);
1552	hmR3VmxReportVmcsEnumMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmcsEnum);
1553	if (pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps)
1554	hmR3VmxReportEptVpidCapsMsr(pVM->hm.s.ForR3.vmx.Msrs.u64EptVpidCaps);
1555	if (pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc)
1556	hmR3VmxReportVmFuncMsr(pVM->hm.s.ForR3.vmx.Msrs.u64VmFunc);
1557	hmR3VmxReportCrFixedMsrs(&pVM->hm.s.ForR3.vmx.Msrs);
1558
1559	#ifdef TODO_9217_VMCSINFO
1560	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1561	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1562	{
1563	PCVMXVMCSINFOSHARED pVmcsInfo = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfo;
1564	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
1565	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfo->HCPhysVmcs));
1566	}
1567	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
1568	if (pVM->cpum.ro.GuestFeatures.fVmx)
1569	{
1570	LogRel(("HM: Nested-guest:\n"));
1571	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1572	{
1573	PCVMXVMCSINFOSHARED pVmcsInfoNstGst = &pVM->apCpusR3[idCpu]->hm.s.vmx.VmcsInfoNstGst;
1574	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysMsrBitmap));
1575	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", idCpu, pVmcsInfoNstGst->HCPhysVmcs));
1576	}
1577	}
1578	#endif
1579	#endif /* TODO_9217_VMCSINFO */
1580
1581	/*
1582	* EPT and unrestricted guest execution are determined in HMR3Init, verify the sanity of that.
1583	*/
1584	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1585	\|\| (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_EPT),
1586	VERR_HM_IPE_1);
1587	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuestCfg
1588	\|\| ( (pVM->hm.s.ForR3.vmx.Msrs.ProcCtls2.n.allowed1 & VMX_PROC_CTLS2_UNRESTRICTED_GUEST)
1589	&& pVM->hm.s.fNestedPagingCfg),
1590	VERR_HM_IPE_1);
1591
1592	/*
1593	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1594	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1595	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1596	*/
1597	if ( !(pVM->hm.s.ForR3.vmx.Msrs.ProcCtls.n.allowed1 & VMX_PROC_CTLS_USE_SECONDARY_CTLS)
1598	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1599	{
1600	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1601	LogRel(("HM: Disabled RDTSCP\n"));
1602	}
1603
1604	if (!pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1605	{
1606	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1607	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1608	if (RT_SUCCESS(rc))
1609	{
1610	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1611	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1612	esp. Figure 20-5.*/
1613	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1614	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1615
1616	/* Bit set to 0 means software interrupts are redirected to the
1617	8086 program interrupt handler rather than switching to
1618	protected-mode handler. */
1619	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1620
1621	/* Allow all port IO, so that port IO instructions do not cause
1622	exceptions and would instead cause a VM-exit (based on VT-x's
1623	IO bitmap which we currently configure to always cause an exit). */
1624	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, X86_PAGE_SIZE * 2);
1625	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1626
1627	/*
1628	* Construct a 1024 element page directory with 4 MB pages for the identity mapped
1629	* page table used in real and protected mode without paging with EPT.
1630	*/
1631	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + X86_PAGE_SIZE 3);
1632	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1633	{
1634	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1635	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1636	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1637	\| X86_PDE4M_G;
1638	}
1639
1640	/* We convert it here every time as PCI regions could be reconfigured. */
1641	if (PDMVmmDevHeapIsEnabled(pVM))
1642	{
1643	RTGCPHYS GCPhys;
1644	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1645	AssertRCReturn(rc, rc);
1646	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1647
1648	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1649	AssertRCReturn(rc, rc);
1650	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1651	}
1652	}
1653	else
1654	{
1655	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1656	pVM->hm.s.vmx.pRealModeTSS = NULL;
1657	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1658	return VMSetError(pVM, rc, RT_SRC_POS,
1659	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1660	}
1661	}
1662
1663	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1664	: "HM: Guest support: 32-bit only\n"));
1665
1666	/*
1667	* Call ring-0 to set up the VM.
1668	*/
1669	rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1670	if (rc != VINF_SUCCESS)
1671	{
1672	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1673	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1674	{
1675	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1676	LogRel(("HM: CPU[%u] Last instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
1677	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", idCpu, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1678	}
1679	HMR3CheckError(pVM, rc);
1680	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1681	}
1682
1683	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.ForR3.vmx.fSupportsVmcsEfer));
1684	LogRel(("HM: Enabled VMX\n"));
1685	pVM->hm.s.vmx.fEnabled = true;
1686
1687	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1688
1689	/*
1690	* Change the CPU features.
1691	*/
1692	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1693	if (pVM->hm.s.fAllow64BitGuestsCfg)
1694	{
1695	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1696	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1697	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* (Long mode only on Intel CPUs.) */
1698	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1699	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1700	}
1701	/* Given that we're on a long mode host, we can simply enable NX for PAE capable guests. */
1702	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1703	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1704
1705	/*
1706	* Log configuration details.
1707	*/
1708	if (pVM->hm.s.fNestedPagingCfg)
1709	{
1710	LogRel(("HM: Enabled nested paging\n"));
1711	if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_SINGLE_CONTEXT)
1712	LogRel(("HM: EPT flush type = Single context\n"));
1713	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_ALL_CONTEXTS)
1714	LogRel(("HM: EPT flush type = All contexts\n"));
1715	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushEpt == VMXTLBFLUSHEPT_NOT_SUPPORTED)
1716	LogRel(("HM: EPT flush type = Not supported\n"));
1717	else
1718	LogRel(("HM: EPT flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushEpt));
1719
1720	if (pVM->hm.s.vmx.fUnrestrictedGuestCfg)
1721	LogRel(("HM: Enabled unrestricted guest execution\n"));
1722
1723	if (pVM->hm.s.fLargePages)
1724	{
1725	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1726	PGMSetLargePageUsage(pVM, true);
1727	LogRel(("HM: Enabled large page support\n"));
1728	}
1729	}
1730	else
1731	Assert(!pVM->hm.s.vmx.fUnrestrictedGuestCfg);
1732
1733	if (pVM->hm.s.ForR3.vmx.fVpid)
1734	{
1735	LogRel(("HM: Enabled VPID\n"));
1736	if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_INDIV_ADDR)
1737	LogRel(("HM: VPID flush type = Individual addresses\n"));
1738	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT)
1739	LogRel(("HM: VPID flush type = Single context\n"));
1740	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_ALL_CONTEXTS)
1741	LogRel(("HM: VPID flush type = All contexts\n"));
1742	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1743	LogRel(("HM: VPID flush type = Single context retain globals\n"));
1744	else
1745	LogRel(("HM: VPID flush type = %#x\n", pVM->hm.s.ForR3.vmx.enmTlbFlushVpid));
1746	}
1747	else if (pVM->hm.s.ForR3.vmx.enmTlbFlushVpid == VMXTLBFLUSHVPID_NOT_SUPPORTED)
1748	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1749
1750	if (pVM->hm.s.vmx.fUsePreemptTimerCfg)
1751	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1752	else
1753	LogRel(("HM: Disabled VMX-preemption timer\n"));
1754
1755	if (pVM->hm.s.fVirtApicRegs)
1756	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1757
1758	if (pVM->hm.s.fPostedIntrs)
1759	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1760
1761	if (pVM->hm.s.ForR3.vmx.fUseVmcsShadowing)
1762	{
1763	bool const fFullVmcsShadow = RT_BOOL(pVM->hm.s.ForR3.vmx.Msrs.u64Misc & VMX_MISC_VMWRITE_ALL);
1764	LogRel(("HM: Enabled %s VMCS shadowing\n", fFullVmcsShadow ? "full" : "partial"));
1765	}
1766
1767	return VINF_SUCCESS;
1768	}
1769
1770
1771	/**
1772	* Finish AMD-V initialization (after ring-0 init).
1773	*
1774	* @returns VBox status code.
1775	* @param pVM The cross context VM structure.
1776	*/
1777	static int hmR3InitFinalizeR0Amd(PVM pVM)
1778	{
1779	LogFunc(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1780
1781	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1782
1783	uint32_t u32Family;
1784	uint32_t u32Model;
1785	uint32_t u32Stepping;
1786	if (HMIsSubjectToSvmErratum170(&u32Family, &u32Model, &u32Stepping))
1787	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1788	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoopsCfg));
1789	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.ForR3.svm.u64MsrHwcr));
1790	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.ForR3.svm.u32Rev));
1791	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.ForR3.uMaxAsid));
1792	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.ForR3.svm.fFeatures));
1793
1794	/*
1795	* Enumerate AMD-V features.
1796	*/
1797	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1798	{
1799	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1800	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1801	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1802	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1803	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1804	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1805	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1806	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1807	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1808	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1809	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1810	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1811	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1812	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1813	HMSVM_REPORT_FEATURE("GMET", X86_CPUID_SVM_FEATURE_EDX_GMET),
1814	#undef HMSVM_REPORT_FEATURE
1815	};
1816
1817	uint32_t fSvmFeatures = pVM->hm.s.ForR3.svm.fFeatures;
1818	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1819	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1820	{
1821	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1822	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1823	}
1824	if (fSvmFeatures)
1825	for (unsigned iBit = 0; iBit < 32; iBit++)
1826	if (RT_BIT_32(iBit) & fSvmFeatures)
1827	LogRel(("HM: Reserved bit %u\n", iBit));
1828
1829	/*
1830	* Nested paging is determined in HMR3Init, verify the sanity of that.
1831	*/
1832	AssertLogRelReturn( !pVM->hm.s.fNestedPagingCfg
1833	\|\| (pVM->hm.s.ForR3.svm.fFeatures & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1834	VERR_HM_IPE_1);
1835
1836	#if 0
1837	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1838	* here. */
1839	if (RTR0IsPostIpiSupport())
1840	pVM->hm.s.fPostedIntrs = true;
1841	#endif
1842
1843	/*
1844	* Determine whether we need to intercept #UD in SVM mode for emulating
1845	* intel SYSENTER/SYSEXIT on AMD64, as these instructions results in #UD
1846	* when executed in long-mode. This is only really applicable when
1847	* non-default CPU profiles are in effect, i.e. guest vendor differs
1848	* from the host one.
1849	*/
1850	if (CPUMGetGuestCpuVendor(pVM) != CPUMGetHostCpuVendor(pVM))
1851	switch (CPUMGetGuestCpuVendor(pVM))
1852	{
1853	case CPUMCPUVENDOR_INTEL:
1854	case CPUMCPUVENDOR_VIA: /?/
1855	case CPUMCPUVENDOR_SHANGHAI: /?/
1856	switch (CPUMGetHostCpuVendor(pVM))
1857	{
1858	case CPUMCPUVENDOR_AMD:
1859	case CPUMCPUVENDOR_HYGON:
1860	if (pVM->hm.s.fAllow64BitGuestsCfg)
1861	{
1862	LogRel(("HM: Intercepting #UD for emulating SYSENTER/SYSEXIT in long mode.\n"));
1863	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1864	pVM->apCpusR3[idCpu]->hm.s.svm.fEmulateLongModeSysEnterExit = true;
1865	}
1866	break;
1867	default: break;
1868	}
1869	default: break;
1870	}
1871
1872	/*
1873	* Call ring-0 to set up the VM.
1874	*/
1875	int rc = SUPR3CallVMMR0Ex(VMCC_GET_VMR0_FOR_CALL(pVM), 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1876	if (rc != VINF_SUCCESS)
1877	{
1878	AssertMsgFailed(("%Rrc\n", rc));
1879	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1880	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1881	}
1882
1883	LogRel(("HM: Enabled SVM\n"));
1884	pVM->hm.s.svm.fEnabled = true;
1885
1886	if (pVM->hm.s.fNestedPagingCfg)
1887	{
1888	LogRel(("HM: Enabled nested paging\n"));
1889
1890	/*
1891	* Enable large pages (2 MB) if applicable.
1892	*/
1893	if (pVM->hm.s.fLargePages)
1894	{
1895	PGMSetLargePageUsage(pVM, true);
1896	LogRel(("HM: Enabled large page support\n"));
1897	}
1898	}
1899
1900	if (pVM->hm.s.fVirtApicRegs)
1901	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1902
1903	if (pVM->hm.s.fPostedIntrs)
1904	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1905
1906	hmR3DisableRawMode(pVM);
1907
1908	/*
1909	* Change the CPU features.
1910	*/
1911	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1912	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1913	if (pVM->hm.s.fAllow64BitGuestsCfg)
1914	{
1915	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1916	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1917	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1918	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1919	}
1920	/* Turn on NXE if PAE has been enabled. */
1921	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1922	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1923
1924	LogRel((pVM->hm.s.fTprPatchingAllowed ? "HM: Enabled TPR patching\n"
1925	: "HM: Disabled TPR patching\n"));
1926
1927	LogRel((pVM->hm.s.fAllow64BitGuestsCfg ? "HM: Guest support: 32-bit and 64-bit\n"
1928	: "HM: Guest support: 32-bit only\n"));
1929	return VINF_SUCCESS;
1930	}
1931
1932
1933	/**
1934	* Applies relocations to data and code managed by this
1935	* component. This function will be called at init and
1936	* whenever the VMM need to relocate it self inside the GC.
1937	*
1938	* @param pVM The cross context VM structure.
1939	*/
1940	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1941	{
1942	/* Fetch the current paging mode during the relocate callback during state loading. */
1943	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1944	{
1945	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
1946	{
1947	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
1948	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1949	}
1950	}
1951	}
1952
1953
1954	/**
1955	* Terminates the HM.
1956	*
1957	* Termination means cleaning up and freeing all resources,
1958	* the VM itself is, at this point, powered off or suspended.
1959	*
1960	* @returns VBox status code.
1961	* @param pVM The cross context VM structure.
1962	*/
1963	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1964	{
1965	if (pVM->hm.s.vmx.pRealModeTSS)
1966	{
1967	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1968	pVM->hm.s.vmx.pRealModeTSS = 0;
1969	}
1970	hmR3TermCPU(pVM);
1971	return 0;
1972	}
1973
1974
1975	/**
1976	* Terminates the per-VCPU HM.
1977	*
1978	* @returns VBox status code.
1979	* @param pVM The cross context VM structure.
1980	*/
1981	static int hmR3TermCPU(PVM pVM)
1982	{
1983	RT_NOREF(pVM);
1984	return VINF_SUCCESS;
1985	}
1986
1987
1988	/**
1989	* Resets a virtual CPU.
1990	*
1991	* Used by HMR3Reset and CPU hot plugging.
1992	*
1993	* @param pVCpu The cross context virtual CPU structure to reset.
1994	*/
1995	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1996	{
1997	/* Sync. entire state on VM reset ring-0 re-entry. It's safe to reset
1998	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1999	pVCpu->hm.s.fCtxChanged \|= HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST;
2000
2001	pVCpu->hm.s.fActive = false;
2002	pVCpu->hm.s.Event.fPending = false;
2003	pVCpu->hm.s.vmx.u64GstMsrApicBase = 0;
2004	pVCpu->hm.s.vmx.VmcsInfo.fWasInRealMode = true;
2005	#ifdef VBOX_WITH_NESTED_HWVIRT_VMX
2006	if (pVCpu->CTX_SUFF(pVM)->cpum.ro.GuestFeatures.fVmx)
2007	pVCpu->hm.s.vmx.VmcsInfoNstGst.fWasInRealMode = true;
2008	#endif
2009	}
2010
2011
2012	/**
2013	* The VM is being reset.
2014	*
2015	* For the HM component this means that any GDT/LDT/TSS monitors
2016	* needs to be removed.
2017	*
2018	* @param pVM The cross context VM structure.
2019	*/
2020	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2021	{
2022	LogFlow(("HMR3Reset:\n"));
2023
2024	if (HMIsEnabled(pVM))
2025	hmR3DisableRawMode(pVM);
2026
2027	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2028	HMR3ResetCpu(pVM->apCpusR3[idCpu]);
2029
2030	/* Clear all patch information. */
2031	pVM->hm.s.pGuestPatchMem = 0;
2032	pVM->hm.s.pFreeGuestPatchMem = 0;
2033	pVM->hm.s.cbGuestPatchMem = 0;
2034	pVM->hm.s.cPatches = 0;
2035	pVM->hm.s.PatchTree = 0;
2036	pVM->hm.s.fTprPatchingActive = false;
2037	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2038	}
2039
2040
2041	/**
2042	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2043	*
2044	* @returns VBox strict status code.
2045	* @param pVM The cross context VM structure.
2046	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2047	* @param pvUser Unused.
2048	*/
2049	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2050	{
2051	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2052
2053	/* Only execute the handler on the VCPU the original patch request was issued. */
2054	if (pVCpu->idCpu != idCpu)
2055	return VINF_SUCCESS;
2056
2057	Log(("hmR3RemovePatches\n"));
2058	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2059	{
2060	uint8_t abInstr[15];
2061	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2062	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2063	int rc;
2064
2065	#ifdef LOG_ENABLED
2066	char szOutput[256];
2067	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2068	szOutput, sizeof(szOutput), NULL);
2069	if (RT_SUCCESS(rc))
2070	Log(("Patched instr: %s\n", szOutput));
2071	#endif
2072
2073	/* Check if the instruction is still the same. */
2074	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2075	if (rc != VINF_SUCCESS)
2076	{
2077	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2078	continue; /* swapped out or otherwise removed; skip it. */
2079	}
2080
2081	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2082	{
2083	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2084	continue; /* skip it. */
2085	}
2086
2087	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2088	AssertRC(rc);
2089
2090	#ifdef LOG_ENABLED
2091	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2092	szOutput, sizeof(szOutput), NULL);
2093	if (RT_SUCCESS(rc))
2094	Log(("Original instr: %s\n", szOutput));
2095	#endif
2096	}
2097	pVM->hm.s.cPatches = 0;
2098	pVM->hm.s.PatchTree = 0;
2099	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2100	pVM->hm.s.fTprPatchingActive = false;
2101	return VINF_SUCCESS;
2102	}
2103
2104
2105	/**
2106	* Worker for enabling patching in a VT-x/AMD-V guest.
2107	*
2108	* @returns VBox status code.
2109	* @param pVM The cross context VM structure.
2110	* @param idCpu VCPU to execute hmR3RemovePatches on.
2111	* @param pPatchMem Patch memory range.
2112	* @param cbPatchMem Size of the memory range.
2113	*/
2114	static DECLCALLBACK(int) hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2115	{
2116	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2117	AssertRC(rc);
2118
2119	pVM->hm.s.pGuestPatchMem = pPatchMem;
2120	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2121	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2122	return VINF_SUCCESS;
2123	}
2124
2125
2126	/**
2127	* Enable patching in a VT-x/AMD-V guest
2128	*
2129	* @returns VBox status code.
2130	* @param pVM The cross context VM structure.
2131	* @param pPatchMem Patch memory range.
2132	* @param cbPatchMem Size of the memory range.
2133	*/
2134	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2135	{
2136	VM_ASSERT_EMT(pVM);
2137	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2138	if (pVM->cCpus > 1)
2139	{
2140	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2141	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2142	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2143	AssertRC(rc);
2144	return rc;
2145	}
2146	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2147	}
2148
2149
2150	/**
2151	* Disable patching in a VT-x/AMD-V guest.
2152	*
2153	* @returns VBox status code.
2154	* @param pVM The cross context VM structure.
2155	* @param pPatchMem Patch memory range.
2156	* @param cbPatchMem Size of the memory range.
2157	*/
2158	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2159	{
2160	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2161	RT_NOREF2(pPatchMem, cbPatchMem);
2162
2163	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2164	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2165
2166	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2167	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2168	(void *)(uintptr_t)VMMGetCpuId(pVM));
2169	AssertRC(rc);
2170
2171	pVM->hm.s.pGuestPatchMem = 0;
2172	pVM->hm.s.pFreeGuestPatchMem = 0;
2173	pVM->hm.s.cbGuestPatchMem = 0;
2174	pVM->hm.s.fTprPatchingActive = false;
2175	return VINF_SUCCESS;
2176	}
2177
2178
2179	/**
2180	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2181	*
2182	* @returns VBox strict status code.
2183	* @param pVM The cross context VM structure.
2184	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2185	* @param pvUser User specified CPU context.
2186	*
2187	*/
2188	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2189	{
2190	/*
2191	* Only execute the handler on the VCPU the original patch request was
2192	* issued. (The other CPU(s) might not yet have switched to protected
2193	* mode, nor have the correct memory context.)
2194	*/
2195	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2196	if (pVCpu->idCpu != idCpu)
2197	return VINF_SUCCESS;
2198
2199	/*
2200	* We're racing other VCPUs here, so don't try patch the instruction twice
2201	* and make sure there is still room for our patch record.
2202	*/
2203	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2204	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2205	if (pPatch)
2206	{
2207	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2208	return VINF_SUCCESS;
2209	}
2210	uint32_t const idx = pVM->hm.s.cPatches;
2211	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2212	{
2213	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2214	return VINF_SUCCESS;
2215	}
2216	pPatch = &pVM->hm.s.aPatches[idx];
2217
2218	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2219
2220	/*
2221	* Disassembler the instruction and get cracking.
2222	*/
2223	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2224	DISCPUSTATE Dis;
2225	uint32_t cbOp;
2226	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2227	AssertRC(rc);
2228	if ( rc == VINF_SUCCESS
2229	&& Dis.pCurInstr->uOpcode == OP_MOV
2230	&& cbOp >= 3)
2231	{
2232	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2233
2234	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2235	AssertRC(rc);
2236
2237	pPatch->cbOp = cbOp;
2238
2239	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2240	{
2241	/* write. */
2242	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2243	{
2244	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2245	pPatch->uSrcOperand = Dis.Param2.Base.idxGenReg;
2246	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", Dis.Param2.Base.idxGenReg));
2247	}
2248	else
2249	{
2250	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2251	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2252	pPatch->uSrcOperand = Dis.Param2.uValue;
2253	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", Dis.Param2.uValue));
2254	}
2255	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2256	AssertRC(rc);
2257
2258	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2259	pPatch->cbNewOp = sizeof(s_abVMMCall);
2260	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2261	}
2262	else
2263	{
2264	/*
2265	* TPR Read.
2266	*
2267	* Found:
2268	* mov eax, dword [fffe0080] (5 bytes)
2269	* Check if next instruction is:
2270	* shr eax, 4
2271	*/
2272	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2273
2274	uint8_t const idxMmioReg = Dis.Param1.Base.idxGenReg;
2275	uint8_t const cbOpMmio = cbOp;
2276	uint64_t const uSavedRip = pCtx->rip;
2277
2278	pCtx->rip += cbOp;
2279	rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2280	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2281	pCtx->rip = uSavedRip;
2282
2283	if ( rc == VINF_SUCCESS
2284	&& Dis.pCurInstr->uOpcode == OP_SHR
2285	&& Dis.Param1.fUse == DISUSE_REG_GEN32
2286	&& Dis.Param1.Base.idxGenReg == idxMmioReg
2287	&& Dis.Param2.fUse == DISUSE_IMMEDIATE8
2288	&& Dis.Param2.uValue == 4
2289	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2290	{
2291	uint8_t abInstr[15];
2292
2293	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2294	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2295	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2296	AssertRC(rc);
2297
2298	pPatch->cbOp = cbOpMmio + cbOp;
2299
2300	/* 0xf0, 0x0f, 0x20, 0xc0 = mov eax, cr8 */
2301	abInstr[0] = 0xf0;
2302	abInstr[1] = 0x0f;
2303	abInstr[2] = 0x20;
2304	abInstr[3] = 0xc0 \| Dis.Param1.Base.idxGenReg;
2305	for (unsigned i = 4; i < pPatch->cbOp; i++)
2306	abInstr[i] = 0x90; /* nop */
2307
2308	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2309	AssertRC(rc);
2310
2311	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2312	pPatch->cbNewOp = pPatch->cbOp;
2313	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2314
2315	Log(("Acceptable read/shr candidate!\n"));
2316	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2317	}
2318	else
2319	{
2320	pPatch->enmType = HMTPRINSTR_READ;
2321	pPatch->uDstOperand = idxMmioReg;
2322
2323	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2324	AssertRC(rc);
2325
2326	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2327	pPatch->cbNewOp = sizeof(s_abVMMCall);
2328	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2329	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2330	}
2331	}
2332
2333	pPatch->Core.Key = pCtx->eip;
2334	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2335	AssertRC(rc);
2336
2337	pVM->hm.s.cPatches++;
2338	return VINF_SUCCESS;
2339	}
2340
2341	/*
2342	* Save invalid patch, so we will not try again.
2343	*/
2344	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2345	pPatch->Core.Key = pCtx->eip;
2346	pPatch->enmType = HMTPRINSTR_INVALID;
2347	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2348	AssertRC(rc);
2349	pVM->hm.s.cPatches++;
2350	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2351	return VINF_SUCCESS;
2352	}
2353
2354
2355	/**
2356	* Callback to patch a TPR instruction (jump to generated code).
2357	*
2358	* @returns VBox strict status code.
2359	* @param pVM The cross context VM structure.
2360	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2361	* @param pvUser User specified CPU context.
2362	*
2363	*/
2364	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2365	{
2366	/*
2367	* Only execute the handler on the VCPU the original patch request was
2368	* issued. (The other CPU(s) might not yet have switched to protected
2369	* mode, nor have the correct memory context.)
2370	*/
2371	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2372	if (pVCpu->idCpu != idCpu)
2373	return VINF_SUCCESS;
2374
2375	/*
2376	* We're racing other VCPUs here, so don't try patch the instruction twice
2377	* and make sure there is still room for our patch record.
2378	*/
2379	PCPUMCTX pCtx = &pVCpu->cpum.GstCtx;
2380	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2381	if (pPatch)
2382	{
2383	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2384	return VINF_SUCCESS;
2385	}
2386	uint32_t const idx = pVM->hm.s.cPatches;
2387	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2388	{
2389	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2390	return VINF_SUCCESS;
2391	}
2392	pPatch = &pVM->hm.s.aPatches[idx];
2393
2394	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2395	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2396
2397	/*
2398	* Disassemble the instruction and get cracking.
2399	*/
2400	DISCPUSTATE Dis;
2401	uint32_t cbOp;
2402	int rc = EMInterpretDisasCurrent(pVM, pVCpu, &Dis, &cbOp);
2403	AssertRC(rc);
2404	if ( rc == VINF_SUCCESS
2405	&& Dis.pCurInstr->uOpcode == OP_MOV
2406	&& cbOp >= 5)
2407	{
2408	uint8_t aPatch[64];
2409	uint32_t off = 0;
2410
2411	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2412	AssertRC(rc);
2413
2414	pPatch->cbOp = cbOp;
2415	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2416
2417	if (Dis.Param1.fUse == DISUSE_DISPLACEMENT32)
2418	{
2419	/*
2420	* TPR write:
2421	*
2422	* push ECX [51]
2423	* push EDX [52]
2424	* push EAX [50]
2425	* xor EDX,EDX [31 D2]
2426	* mov EAX,EAX [89 C0]
2427	* or
2428	* mov EAX,0000000CCh [B8 CC 00 00 00]
2429	* mov ECX,0C0000082h [B9 82 00 00 C0]
2430	* wrmsr [0F 30]
2431	* pop EAX [58]
2432	* pop EDX [5A]
2433	* pop ECX [59]
2434	* jmp return_address [E9 return_address]
2435	*/
2436	bool fUsesEax = (Dis.Param2.fUse == DISUSE_REG_GEN32 && Dis.Param2.Base.idxGenReg == DISGREG_EAX);
2437
2438	aPatch[off++] = 0x51; /* push ecx */
2439	aPatch[off++] = 0x52; /* push edx */
2440	if (!fUsesEax)
2441	aPatch[off++] = 0x50; /* push eax */
2442	aPatch[off++] = 0x31; /* xor edx, edx */
2443	aPatch[off++] = 0xd2;
2444	if (Dis.Param2.fUse == DISUSE_REG_GEN32)
2445	{
2446	if (!fUsesEax)
2447	{
2448	aPatch[off++] = 0x89; /* mov eax, src_reg */
2449	aPatch[off++] = MAKE_MODRM(3, Dis.Param2.Base.idxGenReg, DISGREG_EAX);
2450	}
2451	}
2452	else
2453	{
2454	Assert(Dis.Param2.fUse == DISUSE_IMMEDIATE32);
2455	aPatch[off++] = 0xb8; /* mov eax, immediate */
2456	(uint32_t )&aPatch[off] = Dis.Param2.uValue;
2457	off += sizeof(uint32_t);
2458	}
2459	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2460	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2461	off += sizeof(uint32_t);
2462
2463	aPatch[off++] = 0x0f; /* wrmsr */
2464	aPatch[off++] = 0x30;
2465	if (!fUsesEax)
2466	aPatch[off++] = 0x58; /* pop eax */
2467	aPatch[off++] = 0x5a; /* pop edx */
2468	aPatch[off++] = 0x59; /* pop ecx */
2469	}
2470	else
2471	{
2472	/*
2473	* TPR read:
2474	*
2475	* push ECX [51]
2476	* push EDX [52]
2477	* push EAX [50]
2478	* mov ECX,0C0000082h [B9 82 00 00 C0]
2479	* rdmsr [0F 32]
2480	* mov EAX,EAX [89 C0]
2481	* pop EAX [58]
2482	* pop EDX [5A]
2483	* pop ECX [59]
2484	* jmp return_address [E9 return_address]
2485	*/
2486	Assert(Dis.Param1.fUse == DISUSE_REG_GEN32);
2487
2488	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2489	aPatch[off++] = 0x51; /* push ecx */
2490	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2491	aPatch[off++] = 0x52; /* push edx */
2492	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2493	aPatch[off++] = 0x50; /* push eax */
2494
2495	aPatch[off++] = 0x31; /* xor edx, edx */
2496	aPatch[off++] = 0xd2;
2497
2498	aPatch[off++] = 0xb9; /* mov ecx, 0xc0000082 */
2499	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2500	off += sizeof(uint32_t);
2501
2502	aPatch[off++] = 0x0f; /* rdmsr */
2503	aPatch[off++] = 0x32;
2504
2505	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2506	{
2507	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2508	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, Dis.Param1.Base.idxGenReg);
2509	}
2510
2511	if (Dis.Param1.Base.idxGenReg != DISGREG_EAX)
2512	aPatch[off++] = 0x58; /* pop eax */
2513	if (Dis.Param1.Base.idxGenReg != DISGREG_EDX )
2514	aPatch[off++] = 0x5a; /* pop edx */
2515	if (Dis.Param1.Base.idxGenReg != DISGREG_ECX)
2516	aPatch[off++] = 0x59; /* pop ecx */
2517	}
2518	aPatch[off++] = 0xe9; /* jmp return_address */
2519	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2520	off += sizeof(RTRCUINTPTR);
2521
2522	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2523	{
2524	/* Write new code to the patch buffer. */
2525	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2526	AssertRC(rc);
2527
2528	#ifdef LOG_ENABLED
2529	uint32_t cbCurInstr;
2530	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2531	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2532	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2533	{
2534	char szOutput[256];
2535	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2536	szOutput, sizeof(szOutput), &cbCurInstr);
2537	if (RT_SUCCESS(rc))
2538	Log(("Patch instr %s\n", szOutput));
2539	else
2540	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2541	}
2542	#endif
2543
2544	pPatch->aNewOpcode[0] = 0xE9;
2545	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2546
2547	/* Overwrite the TPR instruction with a jump. */
2548	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2549	AssertRC(rc);
2550
2551	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2552
2553	pVM->hm.s.pFreeGuestPatchMem += off;
2554	pPatch->cbNewOp = 5;
2555
2556	pPatch->Core.Key = pCtx->eip;
2557	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2558	AssertRC(rc);
2559
2560	pVM->hm.s.cPatches++;
2561	pVM->hm.s.fTprPatchingActive = true;
2562	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2563	return VINF_SUCCESS;
2564	}
2565
2566	Log(("Ran out of space in our patch buffer!\n"));
2567	}
2568	else
2569	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2570
2571
2572	/*
2573	* Save invalid patch, so we will not try again.
2574	*/
2575	pPatch = &pVM->hm.s.aPatches[idx];
2576	pPatch->Core.Key = pCtx->eip;
2577	pPatch->enmType = HMTPRINSTR_INVALID;
2578	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2579	AssertRC(rc);
2580	pVM->hm.s.cPatches++;
2581	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2582	return VINF_SUCCESS;
2583	}
2584
2585
2586	/**
2587	* Attempt to patch TPR mmio instructions.
2588	*
2589	* @returns VBox status code.
2590	* @param pVM The cross context VM structure.
2591	* @param pVCpu The cross context virtual CPU structure.
2592	*/
2593	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu)
2594	{
2595	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2596	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2597	(void *)(uintptr_t)pVCpu->idCpu);
2598	AssertRC(rc);
2599	return rc;
2600	}
2601
2602
2603	/**
2604	* Checks if we need to reschedule due to VMM device heap changes.
2605	*
2606	* @returns true if a reschedule is required, otherwise false.
2607	* @param pVM The cross context VM structure.
2608	* @param pCtx VM execution context.
2609	*/
2610	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCCPUMCTX pCtx)
2611	{
2612	/*
2613	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2614	* when the unrestricted guest execution feature is missing (VT-x only).
2615	*/
2616	if ( pVM->hm.s.vmx.fEnabled
2617	&& !pVM->hm.s.vmx.fUnrestrictedGuestCfg
2618	&& CPUMIsGuestInRealModeEx(pCtx)
2619	&& !PDMVmmDevHeapIsEnabled(pVM))
2620	return true;
2621
2622	return false;
2623	}
2624
2625
2626	/**
2627	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
2628	* event settings changes.
2629	*
2630	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2631	* function is just updating the VM globals.
2632	*
2633	* @param pVM The VM cross context VM structure.
2634	* @thread EMT(0)
2635	*/
2636	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2637	{
2638	/* Interrupts. */
2639	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2640	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
2641
2642	/* CPU Exceptions. */
2643	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2644	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2645	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2646	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2647
2648	/* Common VM exits. */
2649	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2650	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2651	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2652	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2653
2654	/* Vendor specific VM exits. */
2655	if (HMR3IsVmxEnabled(pVM->pUVM))
2656	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2657	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2658	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2659	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2660	else
2661	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2662	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2663	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2664	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2665
2666	/* Done. */
2667	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2668	}
2669
2670
2671	/**
2672	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2673	*
2674	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2675	* per CPU settings.
2676	*
2677	* @param pVM The VM cross context VM structure.
2678	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2679	*/
2680	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2681	{
2682	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
2683	}
2684
2685
2686	/**
2687	* Checks if we are currently using hardware acceleration.
2688	*
2689	* @returns true if hardware acceleration is being used, otherwise false.
2690	* @param pVCpu The cross context virtual CPU structure.
2691	*/
2692	VMMR3_INT_DECL(bool) HMR3IsActive(PCVMCPU pVCpu)
2693	{
2694	return pVCpu->hm.s.fActive;
2695	}
2696
2697
2698	/**
2699	* External interface for querying whether hardware acceleration is enabled.
2700	*
2701	* @returns true if VT-x or AMD-V is being used, otherwise false.
2702	* @param pUVM The user mode VM handle.
2703	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2704	*/
2705	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2706	{
2707	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2708	PVM pVM = pUVM->pVM;
2709	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2710	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2711	}
2712
2713
2714	/**
2715	* External interface for querying whether VT-x is being used.
2716	*
2717	* @returns true if VT-x is being used, otherwise false.
2718	* @param pUVM The user mode VM handle.
2719	* @sa HMR3IsSvmEnabled, HMIsEnabled
2720	*/
2721	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2722	{
2723	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2724	PVM pVM = pUVM->pVM;
2725	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2726	return pVM->hm.s.vmx.fEnabled
2727	&& pVM->hm.s.vmx.fSupported
2728	&& pVM->fHMEnabled;
2729	}
2730
2731
2732	/**
2733	* External interface for querying whether AMD-V is being used.
2734	*
2735	* @returns true if VT-x is being used, otherwise false.
2736	* @param pUVM The user mode VM handle.
2737	* @sa HMR3IsVmxEnabled, HMIsEnabled
2738	*/
2739	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2740	{
2741	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2742	PVM pVM = pUVM->pVM;
2743	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2744	return pVM->hm.s.svm.fEnabled
2745	&& pVM->hm.s.svm.fSupported
2746	&& pVM->fHMEnabled;
2747	}
2748
2749
2750	/**
2751	* Checks if we are currently using nested paging.
2752	*
2753	* @returns true if nested paging is being used, otherwise false.
2754	* @param pUVM The user mode VM handle.
2755	*/
2756	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2757	{
2758	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2759	PVM pVM = pUVM->pVM;
2760	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2761	return pVM->hm.s.fNestedPagingCfg;
2762	}
2763
2764
2765	/**
2766	* Checks if virtualized APIC registers are enabled.
2767	*
2768	* When enabled this feature allows the hardware to access most of the
2769	* APIC registers in the virtual-APIC page without causing VM-exits. See
2770	* Intel spec. 29.1.1 "Virtualized APIC Registers".
2771	*
2772	* @returns true if virtualized APIC registers is enabled, otherwise
2773	* false.
2774	* @param pUVM The user mode VM handle.
2775	*/
2776	VMMR3DECL(bool) HMR3AreVirtApicRegsEnabled(PUVM pUVM)
2777	{
2778	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2779	PVM pVM = pUVM->pVM;
2780	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2781	return pVM->hm.s.fVirtApicRegs;
2782	}
2783
2784
2785	/**
2786	* Checks if APIC posted-interrupt processing is enabled.
2787	*
2788	* This returns whether we can deliver interrupts to the guest without
2789	* leaving guest-context by updating APIC state from host-context.
2790	*
2791	* @returns true if APIC posted-interrupt processing is enabled,
2792	* otherwise false.
2793	* @param pUVM The user mode VM handle.
2794	*/
2795	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
2796	{
2797	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2798	PVM pVM = pUVM->pVM;
2799	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2800	return pVM->hm.s.fPostedIntrs;
2801	}
2802
2803
2804	/**
2805	* Checks if we are currently using VPID in VT-x mode.
2806	*
2807	* @returns true if VPID is being used, otherwise false.
2808	* @param pUVM The user mode VM handle.
2809	*/
2810	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2811	{
2812	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2813	PVM pVM = pUVM->pVM;
2814	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2815	return pVM->hm.s.ForR3.vmx.fVpid;
2816	}
2817
2818
2819	/**
2820	* Checks if we are currently using VT-x unrestricted execution,
2821	* aka UX.
2822	*
2823	* @returns true if UX is being used, otherwise false.
2824	* @param pUVM The user mode VM handle.
2825	*/
2826	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2827	{
2828	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2829	PVM pVM = pUVM->pVM;
2830	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2831	return pVM->hm.s.vmx.fUnrestrictedGuestCfg
2832	\|\| pVM->hm.s.svm.fSupported;
2833	}
2834
2835
2836	/**
2837	* Checks if the VMX-preemption timer is being used.
2838	*
2839	* @returns true if the VMX-preemption timer is being used, otherwise false.
2840	* @param pVM The cross context VM structure.
2841	*/
2842	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2843	{
2844	return HMIsEnabled(pVM)
2845	&& pVM->hm.s.vmx.fEnabled
2846	&& pVM->hm.s.vmx.fUsePreemptTimerCfg;
2847	}
2848
2849
2850	#ifdef TODO_9217_VMCSINFO
2851	/**
2852	* Helper for HMR3CheckError to log VMCS controls to the release log.
2853	*
2854	* @param idCpu The Virtual CPU ID.
2855	* @param pVmcsInfo The VMCS info. object.
2856	*/
2857	static void hmR3CheckErrorLogVmcsCtls(VMCPUID idCpu, PCVMXVMCSINFO pVmcsInfo)
2858	{
2859	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", idCpu, pVmcsInfo->u32PinCtls));
2860	{
2861	uint32_t const u32Val = pVmcsInfo->u32PinCtls;
2862	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_EXT_INT_EXIT );
2863	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_NMI_EXIT );
2864	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_VIRT_NMI );
2865	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_PREEMPT_TIMER);
2866	HMVMX_LOGREL_FEAT(u32Val, VMX_PIN_CTLS_POSTED_INT );
2867	}
2868	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls));
2869	{
2870	uint32_t const u32Val = pVmcsInfo->u32ProcCtls;
2871	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INT_WINDOW_EXIT );
2872	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TSC_OFFSETTING);
2873	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_HLT_EXIT );
2874	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_INVLPG_EXIT );
2875	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MWAIT_EXIT );
2876	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDPMC_EXIT );
2877	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_RDTSC_EXIT );
2878	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_LOAD_EXIT );
2879	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR3_STORE_EXIT );
2880	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TERTIARY_CTLS );
2881	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_LOAD_EXIT );
2882	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_CR8_STORE_EXIT );
2883	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_TPR_SHADOW );
2884	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_NMI_WINDOW_EXIT );
2885	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MOV_DR_EXIT );
2886	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_UNCOND_IO_EXIT );
2887	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_IO_BITMAPS );
2888	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_TRAP_FLAG );
2889	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_MSR_BITMAPS );
2890	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_MONITOR_EXIT );
2891	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_PAUSE_EXIT );
2892	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS_USE_SECONDARY_CTLS);
2893	}
2894	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", idCpu, pVmcsInfo->u32ProcCtls2));
2895	{
2896	uint32_t const u32Val = pVmcsInfo->u32ProcCtls2;
2897	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_APIC_ACCESS );
2898	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT );
2899	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_DESC_TABLE_EXIT );
2900	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDTSCP );
2901	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_X2APIC_MODE );
2902	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VPID );
2903	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_WBINVD_EXIT );
2904	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_UNRESTRICTED_GUEST );
2905	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_APIC_REG_VIRT );
2906	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VIRT_INT_DELIVERY );
2907	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PAUSE_LOOP_EXIT );
2908	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDRAND_EXIT );
2909	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_INVPCID );
2910	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMFUNC );
2911	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_VMCS_SHADOWING );
2912	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLS_EXIT );
2913	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_RDSEED_EXIT );
2914	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PML );
2915	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_EPT_XCPT_VE );
2916	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_CONCEAL_VMX_FROM_PT);
2917	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_XSAVES_XRSTORS );
2918	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_MODE_BASED_EPT_PERM);
2919	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_SPP_EPT );
2920	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_PT_EPT );
2921	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_TSC_SCALING );
2922	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_USER_WAIT_PAUSE );
2923	HMVMX_LOGREL_FEAT(u32Val, VMX_PROC_CTLS2_ENCLV_EXIT );
2924	}
2925	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", idCpu, pVmcsInfo->u32EntryCtls));
2926	{
2927	uint32_t const u32Val = pVmcsInfo->u32EntryCtls;
2928	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_DEBUG );
2929	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_IA32E_MODE_GUEST );
2930	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_ENTRY_TO_SMM );
2931	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_DEACTIVATE_DUAL_MON);
2932	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PERF_MSR );
2933	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PAT_MSR );
2934	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_EFER_MSR );
2935	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_BNDCFGS_MSR );
2936	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_CONCEAL_VMX_FROM_PT);
2937	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_RTIT_CTL_MSR );
2938	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_CET_STATE );
2939	HMVMX_LOGREL_FEAT(u32Val, VMX_ENTRY_CTLS_LOAD_PKRS_MSR );
2940	}
2941	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", idCpu, pVmcsInfo->u32ExitCtls));
2942	{
2943	uint32_t const u32Val = pVmcsInfo->u32ExitCtls;
2944	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_DEBUG );
2945	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_HOST_ADDR_SPACE_SIZE );
2946	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PERF_MSR );
2947	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_ACK_EXT_INT );
2948	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PAT_MSR );
2949	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PAT_MSR );
2950	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_EFER_MSR );
2951	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_EFER_MSR );
2952	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_SAVE_PREEMPT_TIMER );
2953	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_BNDCFGS_MSR );
2954	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CONCEAL_VMX_FROM_PT );
2955	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_CLEAR_RTIT_CTL_MSR );
2956	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_CET_STATE );
2957	HMVMX_LOGREL_FEAT(u32Val, VMX_EXIT_CTLS_LOAD_PKRS_MSR );
2958	}
2959	}
2960	#endif
2961
2962
2963	/**
2964	* Check fatal VT-x/AMD-V error and produce some meaningful
2965	* log release message.
2966	*
2967	* @param pVM The cross context VM structure.
2968	* @param iStatusCode VBox status code.
2969	*/
2970	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2971	{
2972	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
2973	{
2974	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2975	* might be getting inaccurate values for non-guru'ing EMTs. */
2976	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
2977	#ifdef TODO_9217_VMCSINFO
2978	PCVMXVMCSINFOSHARED pVmcsInfo = hmGetVmxActiveVmcsInfoShared(pVCpu);
2979	#endif
2980	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
2981	switch (iStatusCode)
2982	{
2983	case VERR_VMX_INVALID_VMCS_PTR:
2984	{
2985	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2986	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
2987	#ifdef TODO_9217_VMCSINFO
2988	LogRel(("HM: CPU[%u] Current pointer %#RHp vs %#RHp\n", idCpu, pVCpu->hm.s.vmx.LastError.HCPhysCurrentVmcs,
2989	pVmcsInfo->HCPhysVmcs));
2990	#endif
2991	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32VmcsRev));
2992	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2993	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2994	break;
2995	}
2996
2997	case VERR_VMX_UNABLE_TO_START_VM:
2998	{
2999	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3000	LogRel(("HM: CPU[%u] %s VMCS active\n", idCpu, fNstGstVmcsActive ? "Nested-guest" : "Guest"));
3001	LogRel(("HM: CPU[%u] Instruction error %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32InstrError));
3002	LogRel(("HM: CPU[%u] Exit reason %#x\n", idCpu, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3003
3004	if ( pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMLAUNCH_NON_CLEAR_VMCS
3005	\|\| pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMRESUME_NON_LAUNCHED_VMCS)
3006	{
3007	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3008	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", idCpu, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3009	}
3010	else if (pVCpu->hm.s.vmx.LastError.u32InstrError == VMXINSTRERR_VMENTRY_INVALID_CTLS)
3011	{
3012	#ifdef TODO_9217_VMCSINFO
3013	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3014	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", idCpu, pVmcsInfo->HCPhysMsrBitmap));
3015	LogRel(("HM: CPU[%u] HCPhysGuestMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrLoad));
3016	LogRel(("HM: CPU[%u] HCPhysGuestMsrStore %#RHp\n", idCpu, pVmcsInfo->HCPhysGuestMsrStore));
3017	LogRel(("HM: CPU[%u] HCPhysHostMsrLoad %#RHp\n", idCpu, pVmcsInfo->HCPhysHostMsrLoad));
3018	LogRel(("HM: CPU[%u] cEntryMsrLoad %u\n", idCpu, pVmcsInfo->cEntryMsrLoad));
3019	LogRel(("HM: CPU[%u] cExitMsrStore %u\n", idCpu, pVmcsInfo->cExitMsrStore));
3020	LogRel(("HM: CPU[%u] cExitMsrLoad %u\n", idCpu, pVmcsInfo->cExitMsrLoad));
3021	#endif
3022	}
3023	/** @todo Log VM-entry event injection control fields
3024	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3025	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3026	break;
3027	}
3028
3029	case VERR_VMX_INVALID_GUEST_STATE:
3030	{
3031	LogRel(("HM: VERR_VMX_INVALID_GUEST_STATE:\n"));
3032	LogRel(("HM: CPU[%u] HM error = %#RX32\n", idCpu, pVCpu->hm.s.u32HMError));
3033	LogRel(("HM: CPU[%u] Guest-intr. state = %#RX32\n", idCpu, pVCpu->hm.s.vmx.LastError.u32GuestIntrState));
3034	#ifdef TODO_9217_VMCSINFO
3035	hmR3CheckErrorLogVmcsCtls(idCpu, pVmcsInfo);
3036	#endif
3037	break;
3038	}
3039
3040	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3041	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3042	case VERR_VMX_INVALID_VMXON_PTR:
3043	case VERR_VMX_UNEXPECTED_EXIT:
3044	case VERR_VMX_INVALID_VMCS_FIELD:
3045	case VERR_SVM_UNKNOWN_EXIT:
3046	case VERR_SVM_UNEXPECTED_EXIT:
3047	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3048	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3049	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3050	break;
3051	}
3052	}
3053
3054	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3055	{
3056	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-1 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed1));
3057	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed-0 %#RX32\n", pVM->hm.s.ForR3.vmx.Msrs.EntryCtls.n.allowed0));
3058	}
3059	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3060	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.ForR3.vmx.HCPhysVmxEnableError));
3061	}
3062
3063
3064	/**
3065	* Execute state save operation.
3066	*
3067	* Save only data that cannot be re-loaded while entering HM ring-0 code. This
3068	* is because we always save the VM state from ring-3 and thus most HM state
3069	* will be re-synced dynamically at runtime and don't need to be part of the VM
3070	* saved state.
3071	*
3072	* @returns VBox status code.
3073	* @param pVM The cross context VM structure.
3074	* @param pSSM SSM operation handle.
3075	*/
3076	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3077	{
3078	Log(("hmR3Save:\n"));
3079
3080	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3081	{
3082	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3083	Assert(!pVCpu->hm.s.Event.fPending);
3084	if (pVM->cpum.ro.GuestFeatures.fSvm)
3085	{
3086	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3087	SSMR3PutBool(pSSM, pVmcbNstGstCache->fCacheValid);
3088	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdCRx);
3089	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrCRx);
3090	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptRdDRx);
3091	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16InterceptWrDRx);
3092	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterThreshold);
3093	SSMR3PutU16(pSSM, pVmcbNstGstCache->u16PauseFilterCount);
3094	SSMR3PutU32(pSSM, pVmcbNstGstCache->u32InterceptXcpt);
3095	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64InterceptCtrl);
3096	SSMR3PutU64(pSSM, pVmcbNstGstCache->u64TSCOffset);
3097	SSMR3PutBool(pSSM, pVmcbNstGstCache->fVIntrMasking);
3098	SSMR3PutBool(pSSM, pVmcbNstGstCache->fNestedPaging);
3099	SSMR3PutBool(pSSM, pVmcbNstGstCache->fLbrVirt);
3100	}
3101	}
3102
3103	/* Save the guest patch data. */
3104	SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3105	SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3106	SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3107
3108	/* Store all the guest patch records too. */
3109	int rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3110	if (RT_FAILURE(rc))
3111	return rc;
3112
3113	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3114	{
3115	AssertCompileSize(HMTPRINSTR, 4);
3116	PCHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3117	SSMR3PutU32(pSSM, pPatch->Core.Key);
3118	SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3119	SSMR3PutU32(pSSM, pPatch->cbOp);
3120	SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3121	SSMR3PutU32(pSSM, pPatch->cbNewOp);
3122	SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3123	SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3124	SSMR3PutU32(pSSM, pPatch->uDstOperand);
3125	SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3126	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3127	if (RT_FAILURE(rc))
3128	return rc;
3129	}
3130
3131	return VINF_SUCCESS;
3132	}
3133
3134
3135	/**
3136	* Execute state load operation.
3137	*
3138	* @returns VBox status code.
3139	* @param pVM The cross context VM structure.
3140	* @param pSSM SSM operation handle.
3141	* @param uVersion Data layout version.
3142	* @param uPass The data pass.
3143	*/
3144	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3145	{
3146	int rc;
3147
3148	LogFlowFunc(("uVersion=%u\n", uVersion));
3149	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3150
3151	/*
3152	* Validate version.
3153	*/
3154	if ( uVersion != HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT
3155	&& uVersion != HM_SAVED_STATE_VERSION_TPR_PATCHING
3156	&& uVersion != HM_SAVED_STATE_VERSION_NO_TPR_PATCHING
3157	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3158	{
3159	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3160	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3161	}
3162
3163	/*
3164	* Load per-VCPU state.
3165	*/
3166	for (VMCPUID idCpu = 0; idCpu < pVM->cCpus; idCpu++)
3167	{
3168	PVMCPU pVCpu = pVM->apCpusR3[idCpu];
3169	if (uVersion >= HM_SAVED_STATE_VERSION_SVM_NESTED_HWVIRT)
3170	{
3171	/* Load the SVM nested hw.virt state if the VM is configured for it. */
3172	if (pVM->cpum.ro.GuestFeatures.fSvm)
3173	{
3174	PSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3175	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fCacheValid);
3176	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdCRx);
3177	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrCRx);
3178	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptRdDRx);
3179	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16InterceptWrDRx);
3180	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterThreshold);
3181	SSMR3GetU16(pSSM, &pVmcbNstGstCache->u16PauseFilterCount);
3182	SSMR3GetU32(pSSM, &pVmcbNstGstCache->u32InterceptXcpt);
3183	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64InterceptCtrl);
3184	SSMR3GetU64(pSSM, &pVmcbNstGstCache->u64TSCOffset);
3185	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fVIntrMasking);
3186	SSMR3GetBool(pSSM, &pVmcbNstGstCache->fNestedPaging);
3187	rc = SSMR3GetBool(pSSM, &pVmcbNstGstCache->fLbrVirt);
3188	AssertRCReturn(rc, rc);
3189	}
3190	}
3191	else
3192	{
3193	/* Pending HM event (obsolete for a long time since TPRM holds the info.) */
3194	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.fPending);
3195	SSMR3GetU32(pSSM, &pVCpu->hm.s.Event.u32ErrCode);
3196	SSMR3GetU64(pSSM, &pVCpu->hm.s.Event.u64IntInfo);
3197
3198	/* VMX fWasInRealMode related data. */
3199	uint32_t uDummy;
3200	SSMR3GetU32(pSSM, &uDummy);
3201	SSMR3GetU32(pSSM, &uDummy);
3202	rc = SSMR3GetU32(pSSM, &uDummy);
3203	AssertRCReturn(rc, rc);
3204	}
3205	}
3206
3207	/*
3208	* Load TPR patching data.
3209	*/
3210	if (uVersion >= HM_SAVED_STATE_VERSION_TPR_PATCHING)
3211	{
3212	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3213	SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3214	SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3215
3216	/* Fetch all TPR patch records. */
3217	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3218	AssertRCReturn(rc, rc);
3219	for (uint32_t i = 0; i < pVM->hm.s.cPatches; i++)
3220	{
3221	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3222	SSMR3GetU32(pSSM, &pPatch->Core.Key);
3223	SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3224	SSMR3GetU32(pSSM, &pPatch->cbOp);
3225	SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3226	SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3227	SSM_GET_ENUM32_RET(pSSM, pPatch->enmType, HMTPRINSTR);
3228
3229	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3230	pVM->hm.s.fTprPatchingActive = true;
3231	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTprPatchingActive == false);
3232
3233	SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3234	SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3235	SSMR3GetU32(pSSM, &pPatch->cFaults);
3236	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3237	AssertRCReturn(rc, rc);
3238
3239	LogFlow(("hmR3Load: patch %d\n", i));
3240	LogFlow(("Key = %x\n", pPatch->Core.Key));
3241	LogFlow(("cbOp = %d\n", pPatch->cbOp));
3242	LogFlow(("cbNewOp = %d\n", pPatch->cbNewOp));
3243	LogFlow(("type = %d\n", pPatch->enmType));
3244	LogFlow(("srcop = %d\n", pPatch->uSrcOperand));
3245	LogFlow(("dstop = %d\n", pPatch->uDstOperand));
3246	LogFlow(("cFaults = %d\n", pPatch->cFaults));
3247	LogFlow(("target = %x\n", pPatch->pJumpTarget));
3248
3249	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3250	AssertRCReturn(rc, rc);
3251	}
3252	}
3253
3254	return VINF_SUCCESS;
3255	}
3256
3257
3258	/**
3259	* Displays HM info.
3260	*
3261	* @param pVM The cross context VM structure.
3262	* @param pHlp The info helper functions.
3263	* @param pszArgs Arguments, ignored.
3264	*/
3265	static DECLCALLBACK(void) hmR3Info(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3266	{
3267	NOREF(pszArgs);
3268	PVMCPU pVCpu = VMMGetCpu(pVM);
3269	if (!pVCpu)
3270	pVCpu = pVM->apCpusR3[0];
3271
3272	if (HMIsEnabled(pVM))
3273	{
3274	if (pVM->hm.s.vmx.fSupported)
3275	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x info:\n", pVCpu->idCpu);
3276	else
3277	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V info:\n", pVCpu->idCpu);
3278	pHlp->pfnPrintf(pHlp, " HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3279	pHlp->pfnPrintf(pHlp, " rcLastExitToR3 = %Rrc\n", pVCpu->hm.s.rcLastExitToR3);
3280	if (pVM->hm.s.vmx.fSupported)
3281	{
3282	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3283	bool const fRealOnV86Active = pVmcsInfoShared->RealMode.fRealOnV86Active;
3284	bool const fNstGstVmcsActive = pVCpu->hm.s.vmx.fSwitchedToNstGstVmcsCopyForRing3;
3285
3286	pHlp->pfnPrintf(pHlp, " %s VMCS active\n", fNstGstVmcsActive ? "Nested-guest" : "Guest");
3287	pHlp->pfnPrintf(pHlp, " Real-on-v86 active = %RTbool\n", fRealOnV86Active);
3288	if (fRealOnV86Active)
3289	{
3290	pHlp->pfnPrintf(pHlp, " EFlags = %#x\n", pVmcsInfoShared->RealMode.Eflags.u32);
3291	pHlp->pfnPrintf(pHlp, " Attr CS = %#x\n", pVmcsInfoShared->RealMode.AttrCS.u);
3292	pHlp->pfnPrintf(pHlp, " Attr SS = %#x\n", pVmcsInfoShared->RealMode.AttrSS.u);
3293	pHlp->pfnPrintf(pHlp, " Attr DS = %#x\n", pVmcsInfoShared->RealMode.AttrDS.u);
3294	pHlp->pfnPrintf(pHlp, " Attr ES = %#x\n", pVmcsInfoShared->RealMode.AttrES.u);
3295	pHlp->pfnPrintf(pHlp, " Attr FS = %#x\n", pVmcsInfoShared->RealMode.AttrFS.u);
3296	pHlp->pfnPrintf(pHlp, " Attr GS = %#x\n", pVmcsInfoShared->RealMode.AttrGS.u);
3297	}
3298	}
3299	}
3300	else
3301	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3302	}
3303
3304
3305	/**
3306	* Displays the HM Last-Branch-Record info. for the guest.
3307	*
3308	* @param pVM The cross context VM structure.
3309	* @param pHlp The info helper functions.
3310	* @param pszArgs Arguments, ignored.
3311	*/
3312	static DECLCALLBACK(void) hmR3InfoLbr(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3313	{
3314	NOREF(pszArgs);
3315	PVMCPU pVCpu = VMMGetCpu(pVM);
3316	if (!pVCpu)
3317	pVCpu = pVM->apCpusR3[0];
3318
3319	if (!HMIsEnabled(pVM))
3320	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3321	else if (HMIsVmxActive(pVM))
3322	{
3323	if (pVM->hm.s.vmx.fLbrCfg)
3324	{
3325	PCVMXVMCSINFOSHARED pVmcsInfoShared = hmGetVmxActiveVmcsInfoShared(pVCpu);
3326	uint32_t const cLbrStack = pVM->hm.s.ForR3.vmx.idLbrFromIpMsrLast - pVM->hm.s.ForR3.vmx.idLbrFromIpMsrFirst + 1;
3327
3328	/** @todo r=ramshankar: The index technically varies depending on the CPU, but
3329	* 0xf should cover everything we support thus far. Fix if necessary
3330	* later. */
3331	uint32_t const idxTopOfStack = pVmcsInfoShared->u64LbrTosMsr & 0xf;
3332	if (idxTopOfStack > cLbrStack)
3333	{
3334	pHlp->pfnPrintf(pHlp, "Top-of-stack LBR MSR seems corrupt (index=%u, msr=%#RX64) expected index < %u\n",
3335	idxTopOfStack, pVmcsInfoShared->u64LbrTosMsr, cLbrStack);
3336	return;
3337	}
3338
3339	/*
3340	* Dump the circular buffer of LBR records starting from the most recent record (contained in idxTopOfStack).
3341	*/
3342	pHlp->pfnPrintf(pHlp, "CPU[%u]: LBRs (most-recent first)\n", pVCpu->idCpu);
3343	uint32_t idxCurrent = idxTopOfStack;
3344	Assert(idxTopOfStack < cLbrStack);
3345	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrFromIpMsr) <= cLbrStack);
3346	Assert(RT_ELEMENTS(pVmcsInfoShared->au64LbrToIpMsr) <= cLbrStack);
3347	for (;;)
3348	{
3349	if (pVM->hm.s.ForR3.vmx.idLbrToIpMsrFirst)
3350	pHlp->pfnPrintf(pHlp, " Branch (%2u): From IP=%#016RX64 - To IP=%#016RX64\n", idxCurrent,
3351	pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent], pVmcsInfoShared->au64LbrToIpMsr[idxCurrent]);
3352	else
3353	pHlp->pfnPrintf(pHlp, " Branch (%2u): LBR=%#RX64\n", idxCurrent, pVmcsInfoShared->au64LbrFromIpMsr[idxCurrent]);
3354
3355	idxCurrent = (idxCurrent - 1) % cLbrStack;
3356	if (idxCurrent == idxTopOfStack)
3357	break;
3358	}
3359	}
3360	else
3361	pHlp->pfnPrintf(pHlp, "VM not configured to record LBRs for the guest\n");
3362	}
3363	else
3364	{
3365	Assert(HMIsSvmActive(pVM));
3366	/** @todo SVM: LBRs (get them from VMCB if possible). */
3367	pHlp->pfnPrintf(pHlp, "SVM LBR not implemented.\n");
3368	}
3369	}
3370
3371
3372	/**
3373	* Displays the HM pending event.
3374	*
3375	* @param pVM The cross context VM structure.
3376	* @param pHlp The info helper functions.
3377	* @param pszArgs Arguments, ignored.
3378	*/
3379	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3380	{
3381	NOREF(pszArgs);
3382	PVMCPU pVCpu = VMMGetCpu(pVM);
3383	if (!pVCpu)
3384	pVCpu = pVM->apCpusR3[0];
3385
3386	if (HMIsEnabled(pVM))
3387	{
3388	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3389	if (pVCpu->hm.s.Event.fPending)
3390	{
3391	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3392	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3393	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3394	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3395	}
3396	}
3397	else
3398	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3399	}
3400
3401
3402	/**
3403	* Displays the SVM nested-guest VMCB cache.
3404	*
3405	* @param pVM The cross context VM structure.
3406	* @param pHlp The info helper functions.
3407	* @param pszArgs Arguments, ignored.
3408	*/
3409	static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3410	{
3411	NOREF(pszArgs);
3412	PVMCPU pVCpu = VMMGetCpu(pVM);
3413	if (!pVCpu)
3414	pVCpu = pVM->apCpusR3[0];
3415
3416	bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3417	if ( fSvmEnabled
3418	&& pVM->cpum.ro.GuestFeatures.fSvm)
3419	{
3420	PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3421	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3422	pHlp->pfnPrintf(pHlp, " fCacheValid = %#RTbool\n", pVmcbNstGstCache->fCacheValid);
3423	pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3424	pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3425	pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3426	pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3427	pHlp->pfnPrintf(pHlp, " u16PauseFilterThreshold = %#RX16\n", pVmcbNstGstCache->u16PauseFilterThreshold);
3428	pHlp->pfnPrintf(pHlp, " u16PauseFilterCount = %#RX16\n", pVmcbNstGstCache->u16PauseFilterCount);
3429	pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3430	pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3431	pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3432	pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3433	pHlp->pfnPrintf(pHlp, " fNestedPaging = %RTbool\n", pVmcbNstGstCache->fNestedPaging);
3434	pHlp->pfnPrintf(pHlp, " fLbrVirt = %RTbool\n", pVmcbNstGstCache->fLbrVirt);
3435	}
3436	else
3437	{
3438	if (!fSvmEnabled)
3439	pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3440	else
3441	pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3442	}
3443	}
3444

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 93725

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