VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 43469

Last change on this file since 43469 was 43469, checked in by vboxsync, 12 years ago

VMM: HM bits.
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File size: 135.7 KB
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1/* $Id: HM.cpp 43469 2012-09-28 15:40:14Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2012 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/err.h>
42#include <VBox/param.h>
43
44#include <iprt/assert.h>
45#include <VBox/log.h>
46#include <iprt/asm.h>
47#include <iprt/asm-amd64-x86.h>
48#include <iprt/string.h>
49#include <iprt/env.h>
50#include <iprt/thread.h>
51
52/*******************************************************************************
53* Global Variables *
54*******************************************************************************/
55#ifdef VBOX_WITH_STATISTICS
56# define EXIT_REASON(def, val, str) #def " - " #val " - " str
57# define EXIT_REASON_NIL() NULL
58/** Exit reason descriptions for VT-x, used to describe statistics. */
59static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
60{
61 EXIT_REASON(VMX_EXIT_EXCEPTION , 0, "Exception or non-maskable interrupt (NMI)."),
62 EXIT_REASON(VMX_EXIT_EXTERNAL_IRQ , 1, "External interrupt."),
63 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
64 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
65 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
66 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
67 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
68 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
69 EXIT_REASON_NIL(),
70 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
71 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
74 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
75 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
76 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
77 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
78 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
79 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
80 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
81 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
82 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
83 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
84 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
85 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
86 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
87 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
88 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
89 EXIT_REASON(VMX_EXIT_CRX_MOVE , 28, "Control-register accesses."),
90 EXIT_REASON(VMX_EXIT_DRX_MOVE , 29, "Debug-register accesses."),
91 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
92 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
93 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
94 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
95 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
96 EXIT_REASON_NIL(),
97 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
98 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
101 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
102 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
103 EXIT_REASON_NIL(),
104 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
105 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
108 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
109 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
110 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
111 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
112 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
113 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
114 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
115 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
116 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
117 EXIT_REASON_NIL()
118};
119/** Exit reason descriptions for AMD-V, used to describe statistics. */
120static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
121{
122 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
123 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
124 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
125 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
126 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
127 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
128 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
129 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
130 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
131 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
132 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
133 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
134 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
135 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
136 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
137 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
138 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
154 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
155 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
156 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
157 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
158 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
159 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
160 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
161 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
162 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
163 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
164 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
165 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
166 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
167 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
168 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
169 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
170 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
186 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
218 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
219 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
221 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
222 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
223 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
224 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
225 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
226 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
227 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
230 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
232 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
233 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
234 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
235 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
236 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
237 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
238 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
239 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
240 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
241 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
242 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
243 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
245 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
246 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
247 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
248 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
249 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
250 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
251 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
252 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
253 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
254 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
255 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
256 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
257 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
258 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
259 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
260 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
261 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
262 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
263 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
264 EXIT_REASON_NIL()
265};
266# undef EXIT_REASON
267# undef EXIT_REASON_NIL
268#endif /* VBOX_WITH_STATISTICS */
269
270/*******************************************************************************
271* Internal Functions *
272*******************************************************************************/
273static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
274static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
275static int hmR3InitCPU(PVM pVM);
276static int hmR3InitFinalizeR0(PVM pVM);
277static int hmR3TermCPU(PVM pVM);
278
279
280/**
281 * Initializes the HM.
282 *
283 * @returns VBox status code.
284 * @param pVM Pointer to the VM.
285 */
286VMMR3DECL(int) HMR3Init(PVM pVM)
287{
288 LogFlow(("HMR3Init\n"));
289
290 /*
291 * Assert alignment and sizes.
292 */
293 AssertCompileMemberAlignment(VM, hm.s, 32);
294 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
295
296 /* Some structure checks. */
297 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
298 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
299 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
300
301 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
302 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
303 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
304 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
305 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
306 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
307 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
308 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
309 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
310 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
311 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
312
313
314 /*
315 * Register the saved state data unit.
316 */
317 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
318 NULL, NULL, NULL,
319 NULL, hmR3Save, NULL,
320 NULL, hmR3Load, NULL);
321 if (RT_FAILURE(rc))
322 return rc;
323
324 /* Misc initialisation. */
325 pVM->hm.s.vmx.fSupported = false;
326 pVM->hm.s.svm.fSupported = false;
327 pVM->hm.s.vmx.fEnabled = false;
328 pVM->hm.s.svm.fEnabled = false;
329
330 pVM->hm.s.fNestedPaging = false;
331 pVM->hm.s.fLargePages = false;
332
333 /* Disabled by default. */
334 pVM->fHMEnabled = false;
335
336 /*
337 * Check CFGM options.
338 */
339 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
340 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
341 /* Nested paging: disabled by default. */
342 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
343 AssertRC(rc);
344
345 /* Large pages: disabled by default. */
346 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
347 AssertRC(rc);
348
349 /* VT-x VPID: disabled by default. */
350 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVPID, false);
351 AssertRC(rc);
352
353 /* HM support must be explicitely enabled in the configuration file. */
354 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
355 AssertRC(rc);
356
357 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
358 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
359 AssertRC(rc);
360
361#ifdef RT_OS_DARWIN
362 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
363#else
364 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
365#endif
366 {
367 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
368 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
369 return VERR_HM_CONFIG_MISMATCH;
370 }
371
372 if (VMMIsHwVirtExtForced(pVM))
373 pVM->fHMEnabled = true;
374
375#if HC_ARCH_BITS == 32
376 /*
377 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
378 * (To use the default, don't set 64bitEnabled in CFGM.)
379 */
380 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
381 AssertLogRelRCReturn(rc, rc);
382 if (pVM->hm.s.fAllow64BitGuests)
383 {
384# ifdef RT_OS_DARWIN
385 if (!VMMIsHwVirtExtForced(pVM))
386# else
387 if (!pVM->hm.s.fAllowed)
388# endif
389 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
390 }
391#else
392 /*
393 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
394 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
395 */
396 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
397 AssertLogRelRCReturn(rc, rc);
398#endif
399
400
401 /*
402 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
403 * or local init each time we wish to execute guest code.
404 *
405 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
406 */
407 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
408#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
409 false
410#else
411 true
412#endif
413 );
414
415 /* Max number of resume loops. */
416 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
417 AssertRC(rc);
418
419 return rc;
420}
421
422
423/**
424 * Initializes the per-VCPU HM.
425 *
426 * @returns VBox status code.
427 * @param pVM Pointer to the VM.
428 */
429static int hmR3InitCPU(PVM pVM)
430{
431 LogFlow(("HMR3InitCPU\n"));
432
433 for (VMCPUID i = 0; i < pVM->cCpus; i++)
434 {
435 PVMCPU pVCpu = &pVM->aCpus[i];
436
437 pVCpu->hm.s.fActive = false;
438 }
439
440#ifdef VBOX_WITH_STATISTICS
441 STAM_REG(pVM, &pVM->hm.s.StatTPRPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
442 STAM_REG(pVM, &pVM->hm.s.StatTPRPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
443 STAM_REG(pVM, &pVM->hm.s.StatTPRReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
444 STAM_REG(pVM, &pVM->hm.s.StatTPRReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
445
446 /*
447 * Statistics.
448 */
449 for (VMCPUID i = 0; i < pVM->cCpus; i++)
450 {
451 PVMCPU pVCpu = &pVM->aCpus[i];
452 int rc;
453
454 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of RTMpPokeCpu",
455 "/PROF/HM/CPU%d/Poke", i);
456 AssertRC(rc);
457 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait",
458 "/PROF/HM/CPU%d/PokeWait", i);
459 AssertRC(rc);
460 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of poke wait when RTMpPokeCpu fails",
461 "/PROF/HM/CPU%d/PokeWaitFailed", i);
462 AssertRC(rc);
463 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode entry",
464 "/PROF/HM/CPU%d/SwitchToGC", i);
465 AssertRC(rc);
466 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 1",
467 "/PROF/HM/CPU%d/SwitchFromGC_1", i);
468 AssertRC(rc);
469 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of VMXR0RunGuestCode exit part 2",
470 "/PROF/HM/CPU%d/SwitchFromGC_2", i);
471 AssertRC(rc);
472# if 1 /* temporary for tracking down darwin holdup. */
473 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - I/O",
474 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub1", i);
475 AssertRC(rc);
476 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - CRx RWs",
477 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub2", i);
478 AssertRC(rc);
479 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Temporary - Exceptions",
480 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub3", i);
481 AssertRC(rc);
482# endif
483 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of vmlaunch",
484 "/PROF/HM/CPU%d/InGC", i);
485 AssertRC(rc);
486
487# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
488 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
489 "/PROF/HM/CPU%d/Switcher3264", i);
490 AssertRC(rc);
491# endif
492
493# define HM_REG_COUNTER(a, b) \
494 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
495 AssertRC(rc);
496
497 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
498 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
499 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
500 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
501 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
502 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
503 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
504 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
505 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
506 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
507 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
508 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
509 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
510 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
511 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
512 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
513 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
514 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
515 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
516 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
517 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
518 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
519 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
520 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
521 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
522 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
523 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
524 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCLTS, "/HM/CPU%d/Exit/Instr/CLTS");
525 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLMSW, "/HM/CPU%d/Exit/Instr/LMSW");
526 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
527 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
528 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
529 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
530 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
531 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIrqWindow, "/HM/CPU%d/Exit/IrqWindow");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptPending, "/HM/CPU%d/Exit/PreemptPending");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMTF, "/HM/CPU%d/Exit/MonitorTrapFlag");
541
542 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchToR3, "/HM/CPU%d/Switch/ToR3");
544
545 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
548
549 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
551 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
552 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTLB, "/HM/CPU%d/Flush/TLB");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTLBManual, "/HM/CPU%d/Flush/TLB/Manual");
554 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTLBCRxChange, "/HM/CPU%d/Flush/TLB/CRx");
555 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageInvlpg, "/HM/CPU%d/Flush/Page/Invlpg");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTLBWorldSwitch, "/HM/CPU%d/Flush/TLB/Switch");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTLBWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
558 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushASID, "/HM/CPU%d/Flush/TLB/ASID");
559 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNP, "/HM/CPU%d/Flush/TLB/NP");
560 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTLBInvlpga, "/HM/CPU%d/Flush/TLB/PhysInvl");
561 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
562 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
563
564 HM_REG_COUNTER(&pVCpu->hm.s.StatTSCOffset, "/HM/CPU%d/TSC/Offset");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatTSCIntercept, "/HM/CPU%d/TSC/Intercept");
566 HM_REG_COUNTER(&pVCpu->hm.s.StatTSCInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
567
568 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIOCheck, "/HM/CPU%d/Debug/IOCheck");
571
572 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
573 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
574
575#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
576 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
577 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
578#endif
579
580 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
581 {
582 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx writes",
583 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
584 AssertRC(rc);
585 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Profiling of CRx reads",
586 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
587 AssertRC(rc);
588 }
589
590#undef HM_REG_COUNTER
591
592 pVCpu->hm.s.paStatExitReason = NULL;
593
594 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatExitReason);
595 AssertRC(rc);
596 if (RT_SUCCESS(rc))
597 {
598 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
599 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
600 {
601 if (papszDesc[j])
602 {
603 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
604 papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
605 AssertRC(rc);
606 }
607 }
608 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNPF, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
609 AssertRC(rc);
610 }
611 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
612# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
613 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
614# else
615 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
616# endif
617
618 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
619 AssertRCReturn(rc, rc);
620 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
621# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
622 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
623# else
624 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
625# endif
626 for (unsigned j = 0; j < 255; j++)
627 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES, "Forwarded interrupts.",
628 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
629
630 }
631#endif /* VBOX_WITH_STATISTICS */
632
633#ifdef VBOX_WITH_CRASHDUMP_MAGIC
634 /* Magic marker for searching in crash dumps. */
635 for (VMCPUID i = 0; i < pVM->cCpus; i++)
636 {
637 PVMCPU pVCpu = &pVM->aCpus[i];
638
639 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
640 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
641 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
642 }
643#endif
644 return VINF_SUCCESS;
645}
646
647
648/**
649 * Called when a init phase has completed.
650 *
651 * @returns VBox status code.
652 * @param pVM The VM.
653 * @param enmWhat The phase that completed.
654 */
655VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
656{
657 switch (enmWhat)
658 {
659 case VMINITCOMPLETED_RING3:
660 return hmR3InitCPU(pVM);
661 case VMINITCOMPLETED_RING0:
662 return hmR3InitFinalizeR0(pVM);
663 default:
664 return VINF_SUCCESS;
665 }
666}
667
668
669/**
670 * Turns off normal raw mode features.
671 *
672 * @param pVM Pointer to the VM.
673 */
674static void hmR3DisableRawMode(PVM pVM)
675{
676 /* Disable PATM & CSAM. */
677 PATMR3AllowPatching(pVM, false);
678 CSAMDisableScanning(pVM);
679
680 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
681 SELMR3DisableMonitoring(pVM);
682 TRPMR3DisableMonitoring(pVM);
683
684 /* Disable the switcher code (safety precaution). */
685 VMMR3DisableSwitcher(pVM);
686
687 /* Disable mapping of the hypervisor into the shadow page table. */
688 PGMR3MappingsDisable(pVM);
689
690 /* Disable the switcher */
691 VMMR3DisableSwitcher(pVM);
692
693 /* Reinit the paging mode to force the new shadow mode. */
694 for (VMCPUID i = 0; i < pVM->cCpus; i++)
695 {
696 PVMCPU pVCpu = &pVM->aCpus[i];
697
698 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
699 }
700}
701
702
703/**
704 * Initialize VT-x or AMD-V.
705 *
706 * @returns VBox status code.
707 * @param pVM Pointer to the VM.
708 */
709static int hmR3InitFinalizeR0(PVM pVM)
710{
711 int rc;
712
713 /*
714 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
715 * is already using AMD-V.
716 */
717 if ( !pVM->hm.s.vmx.fSupported
718 && !pVM->hm.s.svm.fSupported
719 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
720 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
721 {
722 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
723 pVM->hm.s.svm.fSupported = true;
724 pVM->hm.s.svm.fIgnoreInUseError = true;
725 }
726 else
727 if ( !pVM->hm.s.vmx.fSupported
728 && !pVM->hm.s.svm.fSupported)
729 {
730 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
731 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
732
733 if (VMMIsHwVirtExtForced(pVM))
734 {
735 switch (pVM->hm.s.lLastError)
736 {
737 case VERR_VMX_NO_VMX:
738 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
739 case VERR_VMX_IN_VMX_ROOT_MODE:
740 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
741 case VERR_SVM_IN_USE:
742 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
743 case VERR_SVM_NO_SVM:
744 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
745 case VERR_SVM_DISABLED:
746 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
747 default:
748 return pVM->hm.s.lLastError;
749 }
750 }
751 return VINF_SUCCESS;
752 }
753
754 if (pVM->hm.s.vmx.fSupported)
755 {
756 rc = SUPR3QueryVTxSupported();
757 if (RT_FAILURE(rc))
758 {
759#ifdef RT_OS_LINUX
760 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
761#else
762 LogRel(("HM: The host kernel does not support VT-x!\n"));
763#endif
764 if ( pVM->cCpus > 1
765 || VMMIsHwVirtExtForced(pVM))
766 return rc;
767
768 /* silently fall back to raw mode */
769 return VINF_SUCCESS;
770 }
771 }
772
773 if (!pVM->hm.s.fAllowed)
774 return VINF_SUCCESS; /* nothing to do */
775
776 /* Enable VT-x or AMD-V on all host CPUs. */
777 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
778 if (RT_FAILURE(rc))
779 {
780 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
781 return rc;
782 }
783 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
784
785 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
786 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
787 if (!pVM->hm.s.fHasIoApic)
788 {
789 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
790 pVM->hm.s.fTRPPatchingAllowed = false;
791 }
792
793 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
794 if (pVM->hm.s.vmx.fSupported)
795 {
796 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
797
798 if ( pVM->hm.s.fInitialized == false
799 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
800 {
801 uint64_t val;
802 RTGCPHYS GCPhys = 0;
803
804 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
805 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
806 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
807 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
808 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
809 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
810 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
811 LogRel(("HM: Dual monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
812
813 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
814 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
815 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
816 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT\n"));
817 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
818 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT\n"));
819 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
820 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI\n"));
821 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
822 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER\n"));
823 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
824 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT)
825 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT *must* be set\n"));
826 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT)
827 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT *must* be set\n"));
828 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI)
829 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI *must* be set\n"));
830 if (val & VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER)
831 LogRel(("HM: VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER *must* be set\n"));
832
833 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
834 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
835 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
836 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT\n"));
837 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
838 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET\n"));
839 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
840 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT\n"));
841 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
842 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT\n"));
843 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
844 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT\n"));
845 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
846 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT\n"));
847 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
848 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT\n"));
849 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
850 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT\n"));
851 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
852 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT\n"));
853 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
854 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT\n"));
855 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
856 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT\n"));
857 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
858 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW\n"));
859 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
860 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT\n"));
861 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
862 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT\n"));
863 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
864 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT\n"));
865 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
866 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS\n"));
867 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
868 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG\n"));
869 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
870 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS\n"));
871 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
872 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT\n"));
873 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
874 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT\n"));
875 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
876 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL\n"));
877
878 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
879 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT)
880 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_IRQ_WINDOW_EXIT *must* be set\n"));
881 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET)
882 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET *must* be set\n"));
883 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT)
884 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT *must* be set\n"));
885 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT)
886 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT *must* be set\n"));
887 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT)
888 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT *must* be set\n"));
889 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT)
890 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT *must* be set\n"));
891 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT)
892 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT *must* be set\n"));
893 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT)
894 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT *must* be set\n"));
895 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT)
896 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT *must* be set\n"));
897 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT)
898 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT *must* be set\n"));
899 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT)
900 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT *must* be set\n"));
901 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW)
902 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW *must* be set\n"));
903 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT)
904 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT *must* be set\n"));
905 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT)
906 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT *must* be set\n"));
907 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT)
908 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT *must* be set\n"));
909 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS)
910 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS *must* be set\n"));
911 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG)
912 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG *must* be set\n"));
913 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS)
914 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS *must* be set\n"));
915 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT)
916 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT *must* be set\n"));
917 if (val & VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT)
918 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT *must* be set\n"));
919 if (val & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
920 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL *must* be set\n"));
921
922 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
923 {
924 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
925 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
926 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
927 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC\n"));
928 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
929 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_EPT\n"));
930 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
931 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT\n"));
932 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
933 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP\n"));
934 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
935 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC\n"));
936 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
937 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VPID\n"));
938 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
939 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT\n"));
940 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
941 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE\n"));
942 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
943 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT\n"));
944
945 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
946 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC)
947 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC *must* be set\n"));
948 if (val & VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT)
949 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_INSTR_EXIT *must* be set\n"));
950 if (val & VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP)
951 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP *must* be set\n"));
952 if (val & VMX_VMCS_CTRL_PROC_EXEC2_X2APIC)
953 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_X2APIC *must* be set\n"));
954 if (val & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
955 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_EPT *must* be set\n"));
956 if (val & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
957 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_VPID *must* be set\n"));
958 if (val & VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT)
959 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT *must* be set\n"));
960 if (val & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE)
961 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE *must* be set\n"));
962 if (val & VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT)
963 LogRel(("HM: VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT *must* be set\n"));
964 }
965
966 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
967 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
968 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
969 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG\n"));
970 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
971 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE\n"));
972 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
973 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM\n"));
974 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
975 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON\n"));
976 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
977 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR\n"));
978 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
979 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR\n"));
980 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
981 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR\n"));
982 val = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
983 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG)
984 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG *must* be set\n"));
985 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE)
986 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_IA64_MODE *must* be set\n"));
987 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM)
988 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM *must* be set\n"));
989 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON)
990 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON *must* be set\n"));
991 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR)
992 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR *must* be set\n"));
993 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR)
994 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR *must* be set\n"));
995 if (val & VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR)
996 LogRel(("HM: VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR *must* be set\n"));
997
998 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
999 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
1000 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1001 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG\n"));
1002 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1003 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64\n"));
1004 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1005 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ\n"));
1006 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1007 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR\n"));
1008 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1009 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR\n"));
1010 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1011 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR\n"));
1012 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1013 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR\n"));
1014 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1015 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER\n"));
1016 val = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
1017 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG)
1018 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG *must* be set\n"));
1019 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64)
1020 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_AMD64 *must* be set\n"));
1021 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ)
1022 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXTERNAL_IRQ *must* be set\n"));
1023 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR)
1024 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR *must* be set\n"));
1025 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR)
1026 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR *must* be set\n"));
1027 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR)
1028 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR *must* be set\n"));
1029 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR)
1030 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR *must* be set\n"));
1031 if (val & VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER)
1032 LogRel(("HM: VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER *must* be set\n"));
1033
1034 if (pVM->hm.s.vmx.msr.vmx_eptcaps)
1035 {
1036 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAPS = %RX64\n", pVM->hm.s.vmx.msr.vmx_eptcaps));
1037
1038 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY)
1039 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_X_ONLY\n"));
1040 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY)
1041 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_W_ONLY\n"));
1042 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY)
1043 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_RWX_WX_ONLY\n"));
1044 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS)
1045 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_21_BITS\n"));
1046 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS)
1047 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_30_BITS\n"));
1048 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS)
1049 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_39_BITS\n"));
1050 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS)
1051 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_48_BITS\n"));
1052 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS)
1053 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_GAW_57_BITS\n"));
1054 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_UC)
1055 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_UC\n"));
1056 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WC)
1057 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WC\n"));
1058 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WT)
1059 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WT\n"));
1060 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WP)
1061 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WP\n"));
1062 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_EMT_WB)
1063 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_EMT_WB\n"));
1064 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_21_BITS)
1065 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_21_BITS\n"));
1066 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_30_BITS)
1067 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_30_BITS\n"));
1068 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_39_BITS)
1069 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_39_BITS\n"));
1070 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_SP_48_BITS)
1071 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_SP_48_BITS\n"));
1072 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT)
1073 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT\n"));
1074 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT)
1075 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_SINGLE_CONTEXT\n"));
1076 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS)
1077 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVEPT_CAPS_ALL_CONTEXTS\n"));
1078 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID)
1079 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID\n"));
1080 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR)
1081 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_INDIV_ADDR\n"));
1082 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT)
1083 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT\n"));
1084 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS)
1085 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_ALL_CONTEXTS\n"));
1086 if (pVM->hm.s.vmx.msr.vmx_eptcaps & MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS)
1087 LogRel(("HM: MSR_IA32_VMX_EPT_CAPS_INVVPID_CAPS_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1088 }
1089
1090 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
1091 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1092 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
1093 else
1094 {
1095 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT %x - erratum detected, using %x instead\n",
1096 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
1097 }
1098 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
1099 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
1100 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
1101 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
1102
1103 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
1104 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
1105 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1106 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1107 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1108
1109 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1110
1111 /* Paranoia */
1112 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1113
1114 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1115 {
1116 LogRel(("HM: VCPU%d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1117 LogRel(("HM: VCPU%d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVMCS));
1118 }
1119
1120 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1121 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1122
1123 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1124 pVM->hm.s.vmx.fVPID = pVM->hm.s.vmx.fAllowVPID;
1125
1126 /*
1127 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1128 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1129 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1130 */
1131 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1132 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1133 {
1134 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1135 }
1136
1137 /* Unrestricted guest execution relies on EPT. */
1138 if ( pVM->hm.s.fNestedPaging
1139 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_REAL_MODE))
1140 {
1141 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1142 }
1143
1144 /* Only try once. */
1145 pVM->hm.s.fInitialized = true;
1146
1147 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1148 {
1149 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1150 rc = PDMR3VMMDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1151 if (RT_SUCCESS(rc))
1152 {
1153 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1154 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1155 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1156 /* Bit set to 0 means redirection enabled. */
1157 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0x0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1158 /* Allow all port IO, so the VT-x IO intercepts do their job. */
1159 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE*2);
1160 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1161
1162 /*
1163 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1164 * real and protected mode without paging with EPT.
1165 */
1166 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1167 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1168 {
1169 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1170 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS | X86_PDE4M_G;
1171 }
1172
1173 /* We convert it here every time as pci regions could be reconfigured. */
1174 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1175 AssertRC(rc);
1176 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1177
1178 rc = PDMVMMDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1179 AssertRC(rc);
1180 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1181 }
1182 else
1183 {
1184 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1185 pVM->hm.s.vmx.pRealModeTSS = NULL;
1186 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1187 }
1188 }
1189
1190 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1191 AssertRC(rc);
1192 if (rc == VINF_SUCCESS)
1193 {
1194 pVM->fHMEnabled = true;
1195 pVM->hm.s.vmx.fEnabled = true;
1196 hmR3DisableRawMode(pVM);
1197
1198 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1199#ifdef VBOX_ENABLE_64_BITS_GUESTS
1200 if (pVM->hm.s.fAllow64BitGuests)
1201 {
1202 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1203 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1204 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1205 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1206 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1207 }
1208 else
1209 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1210 /* Todo: this needs to be fixed properly!! */
1211 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1212 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1213 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1214
1215 LogRel((pVM->hm.s.fAllow64BitGuests
1216 ? "HM: 32-bit and 64-bit guests supported.\n"
1217 : "HM: 32-bit guests supported.\n"));
1218#else
1219 LogRel(("HM: 32-bit guests supported.\n"));
1220#endif
1221 LogRel(("HM: VMX enabled!\n"));
1222 if (pVM->hm.s.fNestedPaging)
1223 {
1224 LogRel(("HM: Enabled nested paging\n"));
1225 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1226 if (pVM->hm.s.vmx.enmFlushEPT == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1227 LogRel(("HM: enmFlushEPT = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1228 else if (pVM->hm.s.vmx.enmFlushEPT == VMX_FLUSH_EPT_ALL_CONTEXTS)
1229 LogRel(("HM: enmFlushEPT = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1230 else if (pVM->hm.s.vmx.enmFlushEPT == VMX_FLUSH_EPT_NOT_SUPPORTED)
1231 LogRel(("HM: enmFlushEPT = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1232 else
1233 LogRel(("HM: enmFlushEPT = %d\n", pVM->hm.s.vmx.enmFlushEPT));
1234
1235 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1236 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1237
1238#if HC_ARCH_BITS == 64
1239 if (pVM->hm.s.fLargePages)
1240 {
1241 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1242 PGMSetLargePageUsage(pVM, true);
1243 LogRel(("HM: Large page support enabled!\n"));
1244 }
1245#endif
1246 }
1247 else
1248 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1249
1250 if (pVM->hm.s.vmx.fVPID)
1251 {
1252 LogRel(("HM: Enabled VPID\n"));
1253 if (pVM->hm.s.vmx.enmFlushVPID == VMX_FLUSH_VPID_INDIV_ADDR)
1254 LogRel(("HM: enmFlushVPID = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1255 else if (pVM->hm.s.vmx.enmFlushVPID == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1256 LogRel(("HM: enmFlushVPID = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1257 else if (pVM->hm.s.vmx.enmFlushVPID == VMX_FLUSH_VPID_ALL_CONTEXTS)
1258 LogRel(("HM: enmFlushVPID = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1259 else if (pVM->hm.s.vmx.enmFlushVPID == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1260 LogRel(("HM: enmFlushVPID = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1261 else
1262 LogRel(("HM: enmFlushVPID = %d\n", pVM->hm.s.vmx.enmFlushVPID));
1263 }
1264 else if (pVM->hm.s.vmx.enmFlushVPID == VMX_FLUSH_VPID_NOT_SUPPORTED)
1265 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1266
1267 /* TPR patching status logging. */
1268 if (pVM->hm.s.fTRPPatchingAllowed)
1269 {
1270 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1271 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1272 {
1273 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1274 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1275 }
1276 else
1277 {
1278 uint32_t u32Eax, u32Dummy;
1279
1280 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1281 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1282 if ( u32Eax < 0x80000001
1283 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1284 {
1285 pVM->hm.s.fTRPPatchingAllowed = false;
1286 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1287 }
1288 }
1289 }
1290 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1291
1292 /*
1293 * Check for preemption timer config override and log the state of it.
1294 */
1295 if (pVM->hm.s.vmx.fUsePreemptTimer)
1296 {
1297 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1298 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1299 AssertLogRelRC(rc2);
1300 }
1301 if (pVM->hm.s.vmx.fUsePreemptTimer)
1302 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1303 }
1304 else
1305 {
1306 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1307 LogRel(("HM: Last instruction error %x\n", pVM->aCpus[0].hm.s.vmx.lasterror.ulInstrError));
1308 pVM->fHMEnabled = false;
1309 }
1310 }
1311 }
1312 else
1313 if (pVM->hm.s.svm.fSupported)
1314 {
1315 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1316
1317 if (pVM->hm.s.fInitialized == false)
1318 {
1319 /* Erratum 170 which requires a forced TLB flush for each world switch:
1320 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1321 *
1322 * All BH-G1/2 and DH-G1/2 models include a fix:
1323 * Athlon X2: 0x6b 1/2
1324 * 0x68 1/2
1325 * Athlon 64: 0x7f 1
1326 * 0x6f 2
1327 * Sempron: 0x7f 1/2
1328 * 0x6f 2
1329 * 0x6c 2
1330 * 0x7c 2
1331 * Turion 64: 0x68 2
1332 *
1333 */
1334 uint32_t u32Dummy;
1335 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1336 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1337 u32BaseFamily= (u32Version >> 8) & 0xf;
1338 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1339 u32Model = ((u32Version >> 4) & 0xf);
1340 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1341 u32Stepping = u32Version & 0xf;
1342 if ( u32Family == 0xf
1343 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1344 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1345 {
1346 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1347 }
1348
1349 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1350 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1351 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHWCR));
1352 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1353 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxASID));
1354 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1355 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1356 {
1357#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1358 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1359 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1360 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1361 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1362 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1363 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1364 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1365 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1366 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1367 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1368 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1369#undef FLAG_NAME
1370 };
1371 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1372 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1373 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1374 {
1375 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1376 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1377 }
1378 if (fSvmFeatures)
1379 for (unsigned iBit = 0; iBit < 32; iBit++)
1380 if (RT_BIT_32(iBit) & fSvmFeatures)
1381 LogRel(("HM: Reserved bit %u\n", iBit));
1382
1383 /* Only try once. */
1384 pVM->hm.s.fInitialized = true;
1385
1386 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1387 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1388
1389 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1390 AssertRC(rc);
1391 if (rc == VINF_SUCCESS)
1392 {
1393 pVM->fHMEnabled = true;
1394 pVM->hm.s.svm.fEnabled = true;
1395
1396 if (pVM->hm.s.fNestedPaging)
1397 {
1398 LogRel(("HM: Enabled nested paging\n"));
1399#if HC_ARCH_BITS == 64
1400 if (pVM->hm.s.fLargePages)
1401 {
1402 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1403 PGMSetLargePageUsage(pVM, true);
1404 LogRel(("HM: Large page support enabled!\n"));
1405 }
1406#endif
1407 }
1408
1409 hmR3DisableRawMode(pVM);
1410 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1411 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1412#ifdef VBOX_ENABLE_64_BITS_GUESTS
1413 if (pVM->hm.s.fAllow64BitGuests)
1414 {
1415 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1416 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1417 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1418 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1419 }
1420 else
1421 /* Turn on NXE if PAE has been enabled. */
1422 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1423 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1424#endif
1425
1426 LogRel((pVM->hm.s.fAllow64BitGuests
1427 ? "HM: 32-bit and 64-bit guest supported.\n"
1428 : "HM: 32-bit guest supported.\n"));
1429
1430 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1431 }
1432 else
1433 {
1434 pVM->fHMEnabled = false;
1435 }
1436 }
1437 }
1438 if (pVM->fHMEnabled)
1439 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1440 RTLogRelSetBuffering(fOldBuffered);
1441 return VINF_SUCCESS;
1442}
1443
1444
1445/**
1446 * Applies relocations to data and code managed by this
1447 * component. This function will be called at init and
1448 * whenever the VMM need to relocate it self inside the GC.
1449 *
1450 * @param pVM The VM.
1451 */
1452VMMR3DECL(void) HMR3Relocate(PVM pVM)
1453{
1454 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1455
1456 /* Fetch the current paging mode during the relocate callback during state loading. */
1457 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1458 {
1459 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1460 {
1461 PVMCPU pVCpu = &pVM->aCpus[i];
1462
1463 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1464 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1465 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1466 }
1467 }
1468#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1469 if (pVM->fHMEnabled)
1470 {
1471 int rc;
1472 switch (PGMGetHostMode(pVM))
1473 {
1474 case PGMMODE_32_BIT:
1475 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1476 break;
1477
1478 case PGMMODE_PAE:
1479 case PGMMODE_PAE_NX:
1480 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1481 break;
1482
1483 default:
1484 AssertFailed();
1485 break;
1486 }
1487 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1488 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1489
1490 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1491 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1492
1493 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1494 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1495
1496 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1497 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1498
1499# ifdef DEBUG
1500 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1501 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1502# endif
1503 }
1504#endif
1505 return;
1506}
1507
1508
1509/**
1510 * Checks if hardware accelerated raw mode is allowed.
1511 *
1512 * @returns true if hardware acceleration is allowed, otherwise false.
1513 * @param pVM Pointer to the VM.
1514 */
1515VMMR3DECL(bool) HMR3IsAllowed(PVM pVM)
1516{
1517 return pVM->hm.s.fAllowed;
1518}
1519
1520
1521/**
1522 * Notification callback which is called whenever there is a chance that a CR3
1523 * value might have changed.
1524 *
1525 * This is called by PGM.
1526 *
1527 * @param pVM Pointer to the VM.
1528 * @param pVCpu Pointer to the VMCPU.
1529 * @param enmShadowMode New shadow paging mode.
1530 * @param enmGuestMode New guest paging mode.
1531 */
1532VMMR3DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1533{
1534 /* Ignore page mode changes during state loading. */
1535 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1536 return;
1537
1538 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1539
1540 if ( pVM->hm.s.vmx.fEnabled
1541 && pVM->fHMEnabled)
1542 {
1543 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1544 && enmGuestMode >= PGMMODE_PROTECTED)
1545 {
1546 PCPUMCTX pCtx;
1547
1548 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1549
1550 /* After a real mode switch to protected mode we must force
1551 CPL to 0. Our real mode emulation had to set it to 3. */
1552 pCtx->ss.Attr.n.u2Dpl = 0;
1553 }
1554 }
1555
1556 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1557 {
1558 /* Keep track of paging mode changes. */
1559 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1560 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1561
1562 /* Did we miss a change, because all code was executed in the recompiler? */
1563 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1564 {
1565 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1566 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1567 }
1568 }
1569
1570 /* Reset the contents of the read cache. */
1571 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1572 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1573 pCache->Read.aFieldVal[j] = 0;
1574}
1575
1576
1577/**
1578 * Terminates the HM.
1579 *
1580 * Termination means cleaning up and freeing all resources,
1581 * the VM itself is, at this point, powered off or suspended.
1582 *
1583 * @returns VBox status code.
1584 * @param pVM Pointer to the VM.
1585 */
1586VMMR3DECL(int) HMR3Term(PVM pVM)
1587{
1588 if (pVM->hm.s.vmx.pRealModeTSS)
1589 {
1590 PDMR3VMMDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1591 pVM->hm.s.vmx.pRealModeTSS = 0;
1592 }
1593 hmR3TermCPU(pVM);
1594 return 0;
1595}
1596
1597
1598/**
1599 * Terminates the per-VCPU HM.
1600 *
1601 * @returns VBox status code.
1602 * @param pVM Pointer to the VM.
1603 */
1604static int hmR3TermCPU(PVM pVM)
1605{
1606 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1607 {
1608 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1609
1610#ifdef VBOX_WITH_STATISTICS
1611 if (pVCpu->hm.s.paStatExitReason)
1612 {
1613 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1614 pVCpu->hm.s.paStatExitReason = NULL;
1615 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1616 }
1617 if (pVCpu->hm.s.paStatInjectedIrqs)
1618 {
1619 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1620 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1621 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1622 }
1623#endif
1624
1625#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1626 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1627 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1628 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1629#endif
1630 }
1631 return 0;
1632}
1633
1634
1635/**
1636 * Resets a virtual CPU.
1637 *
1638 * Used by HMR3Reset and CPU hot plugging.
1639 *
1640 * @param pVCpu The CPU to reset.
1641 */
1642VMMR3DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1643{
1644 /* On first entry we'll sync everything. */
1645 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1646
1647 pVCpu->hm.s.vmx.cr0_mask = 0;
1648 pVCpu->hm.s.vmx.cr4_mask = 0;
1649
1650 pVCpu->hm.s.fActive = false;
1651 pVCpu->hm.s.Event.fPending = false;
1652
1653 /* Reset state information for real-mode emulation in VT-x. */
1654 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1655 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1656 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1657
1658 /* Reset the contents of the read cache. */
1659 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1660 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1661 pCache->Read.aFieldVal[j] = 0;
1662
1663#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1664 /* Magic marker for searching in crash dumps. */
1665 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1666 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1667#endif
1668}
1669
1670
1671/**
1672 * The VM is being reset.
1673 *
1674 * For the HM component this means that any GDT/LDT/TSS monitors
1675 * needs to be removed.
1676 *
1677 * @param pVM Pointer to the VM.
1678 */
1679VMMR3DECL(void) HMR3Reset(PVM pVM)
1680{
1681 LogFlow(("HMR3Reset:\n"));
1682
1683 if (pVM->fHMEnabled)
1684 hmR3DisableRawMode(pVM);
1685
1686 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1687 {
1688 PVMCPU pVCpu = &pVM->aCpus[i];
1689
1690 HMR3ResetCpu(pVCpu);
1691 }
1692
1693 /* Clear all patch information. */
1694 pVM->hm.s.pGuestPatchMem = 0;
1695 pVM->hm.s.pFreeGuestPatchMem = 0;
1696 pVM->hm.s.cbGuestPatchMem = 0;
1697 pVM->hm.s.cPatches = 0;
1698 pVM->hm.s.PatchTree = 0;
1699 pVM->hm.s.fTPRPatchingActive = false;
1700 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1701}
1702
1703
1704/**
1705 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1706 *
1707 * @returns VBox strict status code.
1708 * @param pVM Pointer to the VM.
1709 * @param pVCpu The VMCPU for the EMT we're being called on.
1710 * @param pvUser Unused.
1711 */
1712DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1713{
1714 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1715
1716 /* Only execute the handler on the VCPU the original patch request was issued. */
1717 if (pVCpu->idCpu != idCpu)
1718 return VINF_SUCCESS;
1719
1720 Log(("hmR3RemovePatches\n"));
1721 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1722 {
1723 uint8_t abInstr[15];
1724 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1725 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1726 int rc;
1727
1728#ifdef LOG_ENABLED
1729 char szOutput[256];
1730
1731 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1732 szOutput, sizeof(szOutput), NULL);
1733 if (RT_SUCCESS(rc))
1734 Log(("Patched instr: %s\n", szOutput));
1735#endif
1736
1737 /* Check if the instruction is still the same. */
1738 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1739 if (rc != VINF_SUCCESS)
1740 {
1741 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1742 continue; /* swapped out or otherwise removed; skip it. */
1743 }
1744
1745 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1746 {
1747 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1748 continue; /* skip it. */
1749 }
1750
1751 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1752 AssertRC(rc);
1753
1754#ifdef LOG_ENABLED
1755 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1756 szOutput, sizeof(szOutput), NULL);
1757 if (RT_SUCCESS(rc))
1758 Log(("Original instr: %s\n", szOutput));
1759#endif
1760 }
1761 pVM->hm.s.cPatches = 0;
1762 pVM->hm.s.PatchTree = 0;
1763 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1764 pVM->hm.s.fTPRPatchingActive = false;
1765 return VINF_SUCCESS;
1766}
1767
1768
1769/**
1770 * Worker for enabling patching in a VT-x/AMD-V guest.
1771 *
1772 * @returns VBox status code.
1773 * @param pVM Pointer to the VM.
1774 * @param idCpu VCPU to execute hmR3RemovePatches on.
1775 * @param pPatchMem Patch memory range.
1776 * @param cbPatchMem Size of the memory range.
1777 */
1778static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1779{
1780 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1781 AssertRC(rc);
1782
1783 pVM->hm.s.pGuestPatchMem = pPatchMem;
1784 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1785 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1786 return VINF_SUCCESS;
1787}
1788
1789
1790/**
1791 * Enable patching in a VT-x/AMD-V guest
1792 *
1793 * @returns VBox status code.
1794 * @param pVM Pointer to the VM.
1795 * @param pPatchMem Patch memory range.
1796 * @param cbPatchMem Size of the memory range.
1797 */
1798VMMR3DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1799{
1800 VM_ASSERT_EMT(pVM);
1801 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1802 if (pVM->cCpus > 1)
1803 {
1804 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1805 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1806 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1807 AssertRC(rc);
1808 return rc;
1809 }
1810 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1811}
1812
1813
1814/**
1815 * Disable patching in a VT-x/AMD-V guest.
1816 *
1817 * @returns VBox status code.
1818 * @param pVM Pointer to the VM.
1819 * @param pPatchMem Patch memory range.
1820 * @param cbPatchMem Size of the memory range.
1821 */
1822VMMR3DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1823{
1824 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1825
1826 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1827 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1828
1829 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1830 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)VMMGetCpuId(pVM));
1831 AssertRC(rc);
1832
1833 pVM->hm.s.pGuestPatchMem = 0;
1834 pVM->hm.s.pFreeGuestPatchMem = 0;
1835 pVM->hm.s.cbGuestPatchMem = 0;
1836 pVM->hm.s.fTPRPatchingActive = false;
1837 return VINF_SUCCESS;
1838}
1839
1840
1841/**
1842 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1843 *
1844 * @returns VBox strict status code.
1845 * @param pVM Pointer to the VM.
1846 * @param pVCpu The VMCPU for the EMT we're being called on.
1847 * @param pvUser User specified CPU context.
1848 *
1849 */
1850DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1851{
1852 /*
1853 * Only execute the handler on the VCPU the original patch request was
1854 * issued. (The other CPU(s) might not yet have switched to protected
1855 * mode, nor have the correct memory context.)
1856 */
1857 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1858 if (pVCpu->idCpu != idCpu)
1859 return VINF_SUCCESS;
1860
1861 /*
1862 * We're racing other VCPUs here, so don't try patch the instruction twice
1863 * and make sure there is still room for our patch record.
1864 */
1865 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1866 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1867 if (pPatch)
1868 {
1869 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1870 return VINF_SUCCESS;
1871 }
1872 uint32_t const idx = pVM->hm.s.cPatches;
1873 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1874 {
1875 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1876 return VINF_SUCCESS;
1877 }
1878 pPatch = &pVM->hm.s.aPatches[idx];
1879
1880 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1881
1882 /*
1883 * Disassembler the instruction and get cracking.
1884 */
1885 DBGFR3DisasInstrCurrentLog(pVCpu, "hmR3ReplaceTprInstr");
1886 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1887 uint32_t cbOp;
1888 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1889 AssertRC(rc);
1890 if ( rc == VINF_SUCCESS
1891 && pDis->pCurInstr->uOpcode == OP_MOV
1892 && cbOp >= 3)
1893 {
1894 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1895
1896 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1897 AssertRC(rc);
1898
1899 pPatch->cbOp = cbOp;
1900
1901 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1902 {
1903 /* write. */
1904 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1905 {
1906 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1907 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1908 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1909 }
1910 else
1911 {
1912 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1913 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1914 pPatch->uSrcOperand = pDis->Param2.uValue;
1915 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1916 }
1917 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1918 AssertRC(rc);
1919
1920 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1921 pPatch->cbNewOp = sizeof(s_abVMMCall);
1922 }
1923 else
1924 {
1925 /*
1926 * TPR Read.
1927 *
1928 * Found:
1929 * mov eax, dword [fffe0080] (5 bytes)
1930 * Check if next instruction is:
1931 * shr eax, 4
1932 */
1933 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1934
1935 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1936 uint8_t const cbOpMmio = cbOp;
1937 uint64_t const uSavedRip = pCtx->rip;
1938
1939 pCtx->rip += cbOp;
1940 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1941 DBGFR3DisasInstrCurrentLog(pVCpu, "Following read");
1942 pCtx->rip = uSavedRip;
1943
1944 if ( rc == VINF_SUCCESS
1945 && pDis->pCurInstr->uOpcode == OP_SHR
1946 && pDis->Param1.fUse == DISUSE_REG_GEN32
1947 && pDis->Param1.Base.idxGenReg == idxMmioReg
1948 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1949 && pDis->Param2.uValue == 4
1950 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1951 {
1952 uint8_t abInstr[15];
1953
1954 /* Replacing two instructions now. */
1955 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1956 AssertRC(rc);
1957
1958 pPatch->cbOp = cbOpMmio + cbOp;
1959
1960 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1961 abInstr[0] = 0xF0;
1962 abInstr[1] = 0x0F;
1963 abInstr[2] = 0x20;
1964 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1965 for (unsigned i = 4; i < pPatch->cbOp; i++)
1966 abInstr[i] = 0x90; /* nop */
1967
1968 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1969 AssertRC(rc);
1970
1971 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1972 pPatch->cbNewOp = pPatch->cbOp;
1973
1974 Log(("Acceptable read/shr candidate!\n"));
1975 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1976 }
1977 else
1978 {
1979 pPatch->enmType = HMTPRINSTR_READ;
1980 pPatch->uDstOperand = idxMmioReg;
1981
1982 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1983 AssertRC(rc);
1984
1985 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1986 pPatch->cbNewOp = sizeof(s_abVMMCall);
1987 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1988 }
1989 }
1990
1991 pPatch->Core.Key = pCtx->eip;
1992 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1993 AssertRC(rc);
1994
1995 pVM->hm.s.cPatches++;
1996 STAM_COUNTER_INC(&pVM->hm.s.StatTPRReplaceSuccess);
1997 return VINF_SUCCESS;
1998 }
1999
2000 /*
2001 * Save invalid patch, so we will not try again.
2002 */
2003 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2004 pPatch->Core.Key = pCtx->eip;
2005 pPatch->enmType = HMTPRINSTR_INVALID;
2006 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2007 AssertRC(rc);
2008 pVM->hm.s.cPatches++;
2009 STAM_COUNTER_INC(&pVM->hm.s.StatTPRReplaceFailure);
2010 return VINF_SUCCESS;
2011}
2012
2013
2014/**
2015 * Callback to patch a TPR instruction (jump to generated code).
2016 *
2017 * @returns VBox strict status code.
2018 * @param pVM Pointer to the VM.
2019 * @param pVCpu The VMCPU for the EMT we're being called on.
2020 * @param pvUser User specified CPU context.
2021 *
2022 */
2023DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2024{
2025 /*
2026 * Only execute the handler on the VCPU the original patch request was
2027 * issued. (The other CPU(s) might not yet have switched to protected
2028 * mode, nor have the correct memory context.)
2029 */
2030 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2031 if (pVCpu->idCpu != idCpu)
2032 return VINF_SUCCESS;
2033
2034 /*
2035 * We're racing other VCPUs here, so don't try patch the instruction twice
2036 * and make sure there is still room for our patch record.
2037 */
2038 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2039 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2040 if (pPatch)
2041 {
2042 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2043 return VINF_SUCCESS;
2044 }
2045 uint32_t const idx = pVM->hm.s.cPatches;
2046 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2047 {
2048 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2049 return VINF_SUCCESS;
2050 }
2051 pPatch = &pVM->hm.s.aPatches[idx];
2052
2053 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2054 DBGFR3DisasInstrCurrentLog(pVCpu, "hmR3PatchTprInstr");
2055
2056 /*
2057 * Disassemble the instruction and get cracking.
2058 */
2059 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2060 uint32_t cbOp;
2061 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2062 AssertRC(rc);
2063 if ( rc == VINF_SUCCESS
2064 && pDis->pCurInstr->uOpcode == OP_MOV
2065 && cbOp >= 5)
2066 {
2067 uint8_t aPatch[64];
2068 uint32_t off = 0;
2069
2070 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2071 AssertRC(rc);
2072
2073 pPatch->cbOp = cbOp;
2074 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2075
2076 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2077 {
2078 /*
2079 * TPR write:
2080 *
2081 * push ECX [51]
2082 * push EDX [52]
2083 * push EAX [50]
2084 * xor EDX,EDX [31 D2]
2085 * mov EAX,EAX [89 C0]
2086 * or
2087 * mov EAX,0000000CCh [B8 CC 00 00 00]
2088 * mov ECX,0C0000082h [B9 82 00 00 C0]
2089 * wrmsr [0F 30]
2090 * pop EAX [58]
2091 * pop EDX [5A]
2092 * pop ECX [59]
2093 * jmp return_address [E9 return_address]
2094 *
2095 */
2096 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2097
2098 aPatch[off++] = 0x51; /* push ecx */
2099 aPatch[off++] = 0x52; /* push edx */
2100 if (!fUsesEax)
2101 aPatch[off++] = 0x50; /* push eax */
2102 aPatch[off++] = 0x31; /* xor edx, edx */
2103 aPatch[off++] = 0xD2;
2104 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2105 {
2106 if (!fUsesEax)
2107 {
2108 aPatch[off++] = 0x89; /* mov eax, src_reg */
2109 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2110 }
2111 }
2112 else
2113 {
2114 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2115 aPatch[off++] = 0xB8; /* mov eax, immediate */
2116 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2117 off += sizeof(uint32_t);
2118 }
2119 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2120 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2121 off += sizeof(uint32_t);
2122
2123 aPatch[off++] = 0x0F; /* wrmsr */
2124 aPatch[off++] = 0x30;
2125 if (!fUsesEax)
2126 aPatch[off++] = 0x58; /* pop eax */
2127 aPatch[off++] = 0x5A; /* pop edx */
2128 aPatch[off++] = 0x59; /* pop ecx */
2129 }
2130 else
2131 {
2132 /*
2133 * TPR read:
2134 *
2135 * push ECX [51]
2136 * push EDX [52]
2137 * push EAX [50]
2138 * mov ECX,0C0000082h [B9 82 00 00 C0]
2139 * rdmsr [0F 32]
2140 * mov EAX,EAX [89 C0]
2141 * pop EAX [58]
2142 * pop EDX [5A]
2143 * pop ECX [59]
2144 * jmp return_address [E9 return_address]
2145 *
2146 */
2147 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2148
2149 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2150 aPatch[off++] = 0x51; /* push ecx */
2151 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2152 aPatch[off++] = 0x52; /* push edx */
2153 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2154 aPatch[off++] = 0x50; /* push eax */
2155
2156 aPatch[off++] = 0x31; /* xor edx, edx */
2157 aPatch[off++] = 0xD2;
2158
2159 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2160 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2161 off += sizeof(uint32_t);
2162
2163 aPatch[off++] = 0x0F; /* rdmsr */
2164 aPatch[off++] = 0x32;
2165
2166 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2167 {
2168 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2169 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2170 }
2171
2172 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2173 aPatch[off++] = 0x58; /* pop eax */
2174 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2175 aPatch[off++] = 0x5A; /* pop edx */
2176 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2177 aPatch[off++] = 0x59; /* pop ecx */
2178 }
2179 aPatch[off++] = 0xE9; /* jmp return_address */
2180 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2181 off += sizeof(RTRCUINTPTR);
2182
2183 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2184 {
2185 /* Write new code to the patch buffer. */
2186 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2187 AssertRC(rc);
2188
2189#ifdef LOG_ENABLED
2190 uint32_t cbCurInstr;
2191 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2192 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2193 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2194 {
2195 char szOutput[256];
2196 rc = DBGFR3DisasInstrEx(pVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2197 szOutput, sizeof(szOutput), &cbCurInstr);
2198 if (RT_SUCCESS(rc))
2199 Log(("Patch instr %s\n", szOutput));
2200 else
2201 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2202 }
2203#endif
2204
2205 pPatch->aNewOpcode[0] = 0xE9;
2206 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2207
2208 /* Overwrite the TPR instruction with a jump. */
2209 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2210 AssertRC(rc);
2211
2212 DBGFR3DisasInstrCurrentLog(pVCpu, "Jump");
2213
2214 pVM->hm.s.pFreeGuestPatchMem += off;
2215 pPatch->cbNewOp = 5;
2216
2217 pPatch->Core.Key = pCtx->eip;
2218 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2219 AssertRC(rc);
2220
2221 pVM->hm.s.cPatches++;
2222 pVM->hm.s.fTPRPatchingActive = true;
2223 STAM_COUNTER_INC(&pVM->hm.s.StatTPRPatchSuccess);
2224 return VINF_SUCCESS;
2225 }
2226
2227 Log(("Ran out of space in our patch buffer!\n"));
2228 }
2229 else
2230 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2231
2232
2233 /*
2234 * Save invalid patch, so we will not try again.
2235 */
2236 pPatch = &pVM->hm.s.aPatches[idx];
2237 pPatch->Core.Key = pCtx->eip;
2238 pPatch->enmType = HMTPRINSTR_INVALID;
2239 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2240 AssertRC(rc);
2241 pVM->hm.s.cPatches++;
2242 STAM_COUNTER_INC(&pVM->hm.s.StatTPRPatchFailure);
2243 return VINF_SUCCESS;
2244}
2245
2246
2247/**
2248 * Attempt to patch TPR mmio instructions.
2249 *
2250 * @returns VBox status code.
2251 * @param pVM Pointer to the VM.
2252 * @param pVCpu Pointer to the VMCPU.
2253 * @param pCtx Pointer to the guest CPU context.
2254 */
2255VMMR3DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2256{
2257 NOREF(pCtx);
2258 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2259 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2260 (void *)(uintptr_t)pVCpu->idCpu);
2261 AssertRC(rc);
2262 return rc;
2263}
2264
2265
2266/**
2267 * Force execution of the current IO code in the recompiler.
2268 *
2269 * @returns VBox status code.
2270 * @param pVM Pointer to the VM.
2271 * @param pCtx Partial VM execution context.
2272 */
2273VMMR3DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2274{
2275 PVMCPU pVCpu = VMMGetCpu(pVM);
2276
2277 Assert(pVM->fHMEnabled);
2278 Log(("HMR3EmulateIoBlock\n"));
2279
2280 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2281 if (HMCanEmulateIoBlockEx(pCtx))
2282 {
2283 Log(("HMR3EmulateIoBlock -> enabled\n"));
2284 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2285 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2286 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2287 return VINF_EM_RESCHEDULE_REM;
2288 }
2289 return VINF_SUCCESS;
2290}
2291
2292
2293/**
2294 * Checks if we can currently use hardware accelerated raw mode.
2295 *
2296 * @returns true if we can currently use hardware acceleration, otherwise false.
2297 * @param pVM Pointer to the VM.
2298 * @param pCtx Partial VM execution context.
2299 */
2300VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2301{
2302 PVMCPU pVCpu = VMMGetCpu(pVM);
2303
2304 Assert(pVM->fHMEnabled);
2305
2306 /* If we're still executing the IO code, then return false. */
2307 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2308 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2309 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2310 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2311 return false;
2312
2313 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2314
2315 /* AMD-V supports real & protected mode with or without paging. */
2316 if (pVM->hm.s.svm.fEnabled)
2317 {
2318 pVCpu->hm.s.fActive = true;
2319 return true;
2320 }
2321
2322 pVCpu->hm.s.fActive = false;
2323
2324 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2325 Assert((pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS) || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2326
2327 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVMMDevHeapIsEnabled(pVM);
2328 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2329 {
2330 /*
2331 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2332 * guest execution feature i missing (VT-x only).
2333 */
2334 if (fSupportsRealMode)
2335 {
2336 if (CPUMIsGuestInRealModeEx(pCtx))
2337 {
2338 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2339 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2340 * If this is not true, we cannot execute real mode as V86 and have to fall
2341 * back to emulation.
2342 */
2343 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2344 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2345 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2346 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2347 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2348 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2349 || (pCtx->cs.u32Limit != 0xffff)
2350 || (pCtx->ds.u32Limit != 0xffff)
2351 || (pCtx->es.u32Limit != 0xffff)
2352 || (pCtx->ss.u32Limit != 0xffff)
2353 || (pCtx->fs.u32Limit != 0xffff)
2354 || (pCtx->gs.u32Limit != 0xffff))
2355 {
2356 return false;
2357 }
2358 }
2359 else
2360 {
2361 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2362 /* Verify the requirements for executing code in protected
2363 mode. VT-x can't handle the CPU state right after a switch
2364 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2365 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2366 && enmGuestMode >= PGMMODE_PROTECTED)
2367 {
2368 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2369 || (pCtx->ds.Sel & X86_SEL_RPL)
2370 || (pCtx->es.Sel & X86_SEL_RPL)
2371 || (pCtx->fs.Sel & X86_SEL_RPL)
2372 || (pCtx->gs.Sel & X86_SEL_RPL)
2373 || (pCtx->ss.Sel & X86_SEL_RPL))
2374 {
2375 return false;
2376 }
2377 }
2378 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2379 if ( pCtx->gdtr.cbGdt
2380 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2381 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2382 {
2383 return false;
2384 }
2385 }
2386 }
2387 else
2388 {
2389 if ( !CPUMIsGuestInLongModeEx(pCtx)
2390 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2391 {
2392 /** @todo This should (probably) be set on every excursion to the REM,
2393 * however it's too risky right now. So, only apply it when we go
2394 * back to REM for real mode execution. (The XP hack below doesn't
2395 * work reliably without this.)
2396 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2397 pVM->aCpus[0].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2398
2399 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap*/
2400 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2401 return false;
2402
2403 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2404 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2405 return false;
2406
2407 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2408 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2409 * hidden registers (possible recompiler bug; see load_seg_vm) */
2410 if (pCtx->cs.Attr.n.u1Present == 0)
2411 return false;
2412 if (pCtx->ss.Attr.n.u1Present == 0)
2413 return false;
2414
2415 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2416 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2417 /** @todo This check is actually wrong, it doesn't take the direction of the
2418 * stack segment into account. But, it does the job for now. */
2419 if (pCtx->rsp >= pCtx->ss.u32Limit)
2420 return false;
2421#if 0
2422 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2423 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2424 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2425 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2426 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2427 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2428 return false;
2429#endif
2430 }
2431 }
2432 }
2433
2434 if (pVM->hm.s.vmx.fEnabled)
2435 {
2436 uint32_t mask;
2437
2438 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2439 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2440 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2441 mask &= ~X86_CR0_NE;
2442
2443 if (fSupportsRealMode)
2444 {
2445 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2446 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2447 }
2448 else
2449 {
2450 /* We support protected mode without paging using identity mapping. */
2451 mask &= ~X86_CR0_PG;
2452 }
2453 if ((pCtx->cr0 & mask) != mask)
2454 return false;
2455
2456 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2457 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2458 if ((pCtx->cr0 & mask) != 0)
2459 return false;
2460
2461 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2462 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2463 mask &= ~X86_CR4_VMXE;
2464 if ((pCtx->cr4 & mask) != mask)
2465 return false;
2466
2467 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2468 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2469 if ((pCtx->cr4 & mask) != 0)
2470 return false;
2471
2472 pVCpu->hm.s.fActive = true;
2473 return true;
2474 }
2475
2476 return false;
2477}
2478
2479
2480/**
2481 * Checks if we need to reschedule due to VMM device heap changes.
2482 *
2483 * @returns true if a reschedule is required, otherwise false.
2484 * @param pVM Pointer to the VM.
2485 * @param pCtx VM execution context.
2486 */
2487VMMR3DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2488{
2489 /*
2490 * The VMM device heap is a requirement for emulating real mode or protected mode without paging
2491 * when the unrestricted guest execution feature is missing (VT-x only).
2492 */
2493 if ( pVM->hm.s.vmx.fEnabled
2494 && !pVM->hm.s.vmx.fUnrestrictedGuest
2495 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2496 && !PDMVMMDevHeapIsEnabled(pVM)
2497 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2498 return true;
2499
2500 return false;
2501}
2502
2503
2504/**
2505 * Notification from EM about a rescheduling into hardware assisted execution
2506 * mode.
2507 *
2508 * @param pVCpu Pointer to the current VMCPU.
2509 */
2510VMMR3DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2511{
2512 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2513}
2514
2515
2516/**
2517 * Notification from EM about returning from instruction emulation (REM / EM).
2518 *
2519 * @param pVCpu Pointer to the VMCPU.
2520 */
2521VMMR3DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2522{
2523 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2524}
2525
2526
2527/**
2528 * Checks if we are currently using hardware accelerated raw mode.
2529 *
2530 * @returns true if hardware acceleration is being used, otherwise false.
2531 * @param pVCpu Pointer to the VMCPU.
2532 */
2533VMMR3DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2534{
2535 return pVCpu->hm.s.fActive;
2536}
2537
2538
2539/**
2540 * Checks if we are currently using nested paging.
2541 *
2542 * @returns true if nested paging is being used, otherwise false.
2543 * @param pVM Pointer to the VM.
2544 */
2545VMMR3DECL(bool) HMR3IsNestedPagingActive(PVM pVM)
2546{
2547 return pVM->hm.s.fNestedPaging;
2548}
2549
2550
2551/**
2552 * Checks if we are currently using VPID in VT-x mode.
2553 *
2554 * @returns true if VPID is being used, otherwise false.
2555 * @param pVM Pointer to the VM.
2556 */
2557VMMR3DECL(bool) HMR3IsVPIDActive(PVM pVM)
2558{
2559 return pVM->hm.s.vmx.fVPID;
2560}
2561
2562
2563/**
2564 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2565 *
2566 * @returns true if an internal event is pending, otherwise false.
2567 * @param pVM Pointer to the VM.
2568 */
2569VMMR3DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2570{
2571 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2572}
2573
2574
2575/**
2576 * Checks if the VMX-preemption timer is being used.
2577 *
2578 * @returns true if the VMX-preemption timer is being used, otherwise false.
2579 * @param pVM Pointer to the VM.
2580 */
2581VMMR3DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2582{
2583 return HMIsEnabled(pVM)
2584 && pVM->hm.s.vmx.fEnabled
2585 && pVM->hm.s.vmx.fUsePreemptTimer;
2586}
2587
2588
2589/**
2590 * Restart an I/O instruction that was refused in ring-0
2591 *
2592 * @returns Strict VBox status code. Informational status codes other than the one documented
2593 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2594 * @retval VINF_SUCCESS Success.
2595 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2596 * status code must be passed on to EM.
2597 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2598 *
2599 * @param pVM Pointer to the VM.
2600 * @param pVCpu Pointer to the VMCPU.
2601 * @param pCtx Pointer to the guest CPU context.
2602 */
2603VMMR3DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2604{
2605 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2606
2607 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2608
2609 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2610 || enmType == HMPENDINGIO_INVALID)
2611 return VERR_NOT_FOUND;
2612
2613 VBOXSTRICTRC rcStrict;
2614 switch (enmType)
2615 {
2616 case HMPENDINGIO_PORT_READ:
2617 {
2618 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2619 uint32_t u32Val = 0;
2620
2621 rcStrict = IOMIOPortRead(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2622 &u32Val,
2623 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2624 if (IOM_SUCCESS(rcStrict))
2625 {
2626 /* Write back to the EAX register. */
2627 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2628 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2629 }
2630 break;
2631 }
2632
2633 case HMPENDINGIO_PORT_WRITE:
2634 rcStrict = IOMIOPortWrite(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2635 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2636 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2637 if (IOM_SUCCESS(rcStrict))
2638 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2639 break;
2640
2641 default:
2642 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2643 }
2644
2645 return rcStrict;
2646}
2647
2648
2649/**
2650 * Inject an NMI into a running VM (only VCPU 0!)
2651 *
2652 * @returns boolean
2653 * @param pVM Pointer to the VM.
2654 */
2655VMMR3DECL(int) HMR3InjectNMI(PVM pVM)
2656{
2657 VMCPU_FF_SET(&pVM->aCpus[0], VMCPU_FF_INTERRUPT_NMI);
2658 return VINF_SUCCESS;
2659}
2660
2661
2662/**
2663 * Check fatal VT-x/AMD-V error and produce some meaningful
2664 * log release message.
2665 *
2666 * @param pVM Pointer to the VM.
2667 * @param iStatusCode VBox status code.
2668 */
2669VMMR3DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2670{
2671 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2672 {
2673 switch (iStatusCode)
2674 {
2675 case VERR_VMX_INVALID_VMCS_FIELD:
2676 break;
2677
2678 case VERR_VMX_INVALID_VMCS_PTR:
2679 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVMCS));
2680 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulVMCSRevision));
2681 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2682 LogRel(("VERR_VMX_INVALID_VMCS_PTR: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2683 break;
2684
2685 case VERR_VMX_UNABLE_TO_START_VM:
2686 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulInstrError));
2687 LogRel(("VERR_VMX_UNABLE_TO_START_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulExitReason));
2688 if (pVM->aCpus[i].hm.s.vmx.lasterror.ulInstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2689 {
2690 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2691#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2692 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2693 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2694 LogRel(("VERR_VMX_UNABLE_TO_START_VM: Cpu%d Cached MSRs %x\n", i, pVM->aCpus[i].hm.s.vmx.cCachedMsrs));
2695#endif
2696 }
2697 /** @todo Log VM-entry event injection control fields
2698 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2699 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2700 break;
2701
2702 case VERR_VMX_UNABLE_TO_RESUME_VM:
2703 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulInstrError));
2704 LogRel(("VERR_VMX_UNABLE_TO_RESUME_VM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.ulExitReason));
2705 break;
2706
2707 case VERR_VMX_INVALID_VMXON_PTR:
2708 break;
2709 }
2710 }
2711
2712 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2713 {
2714 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2715 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2716 }
2717}
2718
2719
2720/**
2721 * Execute state save operation.
2722 *
2723 * @returns VBox status code.
2724 * @param pVM Pointer to the VM.
2725 * @param pSSM SSM operation handle.
2726 */
2727static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2728{
2729 int rc;
2730
2731 Log(("hmR3Save:\n"));
2732
2733 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2734 {
2735 /*
2736 * Save the basic bits - fortunately all the other things can be resynced on load.
2737 */
2738 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2739 AssertRCReturn(rc, rc);
2740 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.errCode);
2741 AssertRCReturn(rc, rc);
2742 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.intInfo);
2743 AssertRCReturn(rc, rc);
2744
2745 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2746 AssertRCReturn(rc, rc);
2747 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2748 AssertRCReturn(rc, rc);
2749 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2750 AssertRCReturn(rc, rc);
2751 }
2752#ifdef VBOX_HM_WITH_GUEST_PATCHING
2753 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2754 AssertRCReturn(rc, rc);
2755 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2756 AssertRCReturn(rc, rc);
2757 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2758 AssertRCReturn(rc, rc);
2759
2760 /* Store all the guest patch records too. */
2761 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2762 AssertRCReturn(rc, rc);
2763
2764 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2765 {
2766 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2767
2768 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2769 AssertRCReturn(rc, rc);
2770
2771 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2772 AssertRCReturn(rc, rc);
2773
2774 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2775 AssertRCReturn(rc, rc);
2776
2777 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2778 AssertRCReturn(rc, rc);
2779
2780 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2781 AssertRCReturn(rc, rc);
2782
2783 AssertCompileSize(HMTPRINSTR, 4);
2784 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2785 AssertRCReturn(rc, rc);
2786
2787 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2788 AssertRCReturn(rc, rc);
2789
2790 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2791 AssertRCReturn(rc, rc);
2792
2793 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2794 AssertRCReturn(rc, rc);
2795
2796 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2797 AssertRCReturn(rc, rc);
2798 }
2799#endif
2800 return VINF_SUCCESS;
2801}
2802
2803
2804/**
2805 * Execute state load operation.
2806 *
2807 * @returns VBox status code.
2808 * @param pVM Pointer to the VM.
2809 * @param pSSM SSM operation handle.
2810 * @param uVersion Data layout version.
2811 * @param uPass The data pass.
2812 */
2813static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2814{
2815 int rc;
2816
2817 Log(("hmR3Load:\n"));
2818 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2819
2820 /*
2821 * Validate version.
2822 */
2823 if ( uVersion != HM_SSM_VERSION
2824 && uVersion != HM_SSM_VERSION_NO_PATCHING
2825 && uVersion != HM_SSM_VERSION_2_0_X)
2826 {
2827 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2828 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2829 }
2830 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2831 {
2832 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2833 AssertRCReturn(rc, rc);
2834 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.errCode);
2835 AssertRCReturn(rc, rc);
2836 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.intInfo);
2837 AssertRCReturn(rc, rc);
2838
2839 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2840 {
2841 uint32_t val;
2842
2843 rc = SSMR3GetU32(pSSM, &val);
2844 AssertRCReturn(rc, rc);
2845 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2846
2847 rc = SSMR3GetU32(pSSM, &val);
2848 AssertRCReturn(rc, rc);
2849 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2850
2851 rc = SSMR3GetU32(pSSM, &val);
2852 AssertRCReturn(rc, rc);
2853 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2854 }
2855 }
2856#ifdef VBOX_HM_WITH_GUEST_PATCHING
2857 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2858 {
2859 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2860 AssertRCReturn(rc, rc);
2861 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2862 AssertRCReturn(rc, rc);
2863 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2864 AssertRCReturn(rc, rc);
2865
2866 /* Fetch all TPR patch records. */
2867 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2868 AssertRCReturn(rc, rc);
2869
2870 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2871 {
2872 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2873
2874 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2875 AssertRCReturn(rc, rc);
2876
2877 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2878 AssertRCReturn(rc, rc);
2879
2880 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2881 AssertRCReturn(rc, rc);
2882
2883 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2884 AssertRCReturn(rc, rc);
2885
2886 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2887 AssertRCReturn(rc, rc);
2888
2889 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2890 AssertRCReturn(rc, rc);
2891
2892 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2893 pVM->hm.s.fTPRPatchingActive = true;
2894
2895 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2896
2897 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2898 AssertRCReturn(rc, rc);
2899
2900 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2901 AssertRCReturn(rc, rc);
2902
2903 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2904 AssertRCReturn(rc, rc);
2905
2906 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2907 AssertRCReturn(rc, rc);
2908
2909 Log(("hmR3Load: patch %d\n", i));
2910 Log(("Key = %x\n", pPatch->Core.Key));
2911 Log(("cbOp = %d\n", pPatch->cbOp));
2912 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2913 Log(("type = %d\n", pPatch->enmType));
2914 Log(("srcop = %d\n", pPatch->uSrcOperand));
2915 Log(("dstop = %d\n", pPatch->uDstOperand));
2916 Log(("cFaults = %d\n", pPatch->cFaults));
2917 Log(("target = %x\n", pPatch->pJumpTarget));
2918 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2919 AssertRC(rc);
2920 }
2921 }
2922#endif
2923
2924 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2925 if (HMIsEnabled(pVM))
2926 {
2927 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2928 {
2929 PVMCPU pVCpu = &pVM->aCpus[i];
2930
2931 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2932 }
2933 }
2934 return VINF_SUCCESS;
2935}
2936
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