VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 45214

Last change on this file since 45214 was 45214, checked in by vboxsync, 12 years ago

VMMR3/HM: release log tidying.
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  • Property svn:keywords set to Id Revision
File size: 128.6 KB
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1/* $Id: HM.cpp 45214 2013-03-27 18:29:52Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/vmm/uvm.h>
42#include <VBox/err.h>
43#include <VBox/param.h>
44
45#include <iprt/assert.h>
46#include <VBox/log.h>
47#include <iprt/asm.h>
48#include <iprt/asm-amd64-x86.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
114 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL()
119};
120/** Exit reason descriptions for AMD-V, used to describe statistics. */
121static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
122{
123 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
124 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
125 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
126 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
127 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
128 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
129 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
130 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
131 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
132 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
133 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
134 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
135 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
136 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
137 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
138 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
139 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
140 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
141 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
155 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
156 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
157 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
158 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
159 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
160 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
161 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
162 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
163 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
164 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
165 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
166 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
167 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
168 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
169 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
170 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
171 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
172 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
173 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
187 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
188 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
189 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
219 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
220 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
221 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
222 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
223 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
224 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
225 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
226 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
227 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
228 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
229 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
230 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
232 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
233 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
234 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
235 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
236 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
237 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
238 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
239 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
240 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
241 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
242 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
243 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
244 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
245 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
246 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
247 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
248 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
249 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
250 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
251 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
252 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
253 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
254 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
255 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
256 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
257 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
258 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
259 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
260 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
261 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
262 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
263 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
264 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
265 EXIT_REASON_NIL()
266};
267# undef EXIT_REASON
268# undef EXIT_REASON_NIL
269#endif /* VBOX_WITH_STATISTICS */
270
271#define VMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
272 do { \
273 if ((allowed1) & (featflag)) \
274 LogRel(("HM: " #featflag "\n")); \
275 else \
276 LogRel(("HM: " #featflag " *must* be cleared\n")); \
277 if ((disallowed0) & (featflag)) \
278 LogRel(("HM: " #featflag " *must* be set\n")); \
279 } while(0)
280
281
282/*******************************************************************************
283* Internal Functions *
284*******************************************************************************/
285static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
286static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
287static int hmR3InitCPU(PVM pVM);
288static int hmR3InitFinalizeR0(PVM pVM);
289static int hmR3TermCPU(PVM pVM);
290
291
292/**
293 * Initializes the HM.
294 *
295 * @returns VBox status code.
296 * @param pVM Pointer to the VM.
297 */
298VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
299{
300 LogFlow(("HMR3Init\n"));
301
302 /*
303 * Assert alignment and sizes.
304 */
305 AssertCompileMemberAlignment(VM, hm.s, 32);
306 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
307
308 /* Some structure checks. */
309 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
310 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
311 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
312
313 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
314 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
315 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
316 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
317 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
318 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
319 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
320 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
321 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
322 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
323 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
324
325 /*
326 * Register the saved state data unit.
327 */
328 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
329 NULL, NULL, NULL,
330 NULL, hmR3Save, NULL,
331 NULL, hmR3Load, NULL);
332 if (RT_FAILURE(rc))
333 return rc;
334
335 /* Misc initialisation. */
336 pVM->hm.s.vmx.fSupported = false;
337 pVM->hm.s.svm.fSupported = false;
338 pVM->hm.s.vmx.fEnabled = false;
339 pVM->hm.s.svm.fEnabled = false;
340
341 pVM->hm.s.fNestedPaging = false;
342 pVM->hm.s.fLargePages = false;
343
344 /* Disabled by default. */
345 pVM->fHMEnabled = false;
346
347 /*
348 * Check CFGM options.
349 */
350 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
351 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
352 /* Nested paging: disabled by default. */
353 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
354 AssertRC(rc);
355
356 /* Large pages: disabled by default. */
357 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
358 AssertRC(rc);
359
360 /* VT-x VPID: disabled by default. */
361 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
362 AssertRC(rc);
363
364 /* HM support must be explicitely enabled in the configuration file. */
365 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
366 AssertRC(rc);
367
368 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
369 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
370 AssertRC(rc);
371
372#ifdef RT_OS_DARWIN
373 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
374#else
375 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
376#endif
377 {
378 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
379 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
380 return VERR_HM_CONFIG_MISMATCH;
381 }
382
383 if (VMMIsHwVirtExtForced(pVM))
384 pVM->fHMEnabled = true;
385
386#if HC_ARCH_BITS == 32
387 /*
388 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
389 * (To use the default, don't set 64bitEnabled in CFGM.)
390 */
391 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
392 AssertLogRelRCReturn(rc, rc);
393 if (pVM->hm.s.fAllow64BitGuests)
394 {
395# ifdef RT_OS_DARWIN
396 if (!VMMIsHwVirtExtForced(pVM))
397# else
398 if (!pVM->hm.s.fAllowed)
399# endif
400 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
401 }
402#else
403 /*
404 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
405 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
406 */
407 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
408 AssertLogRelRCReturn(rc, rc);
409#endif
410
411
412 /*
413 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
414 * or local init each time we wish to execute guest code.
415 *
416 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
417 */
418 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
419#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
420 false
421#else
422 true
423#endif
424 );
425
426 /* Max number of resume loops. */
427 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
428 AssertRC(rc);
429
430 return rc;
431}
432
433
434/**
435 * Initializes the per-VCPU HM.
436 *
437 * @returns VBox status code.
438 * @param pVM Pointer to the VM.
439 */
440static int hmR3InitCPU(PVM pVM)
441{
442 LogFlow(("HMR3InitCPU\n"));
443
444 for (VMCPUID i = 0; i < pVM->cCpus; i++)
445 {
446 PVMCPU pVCpu = &pVM->aCpus[i];
447
448 pVCpu->hm.s.fActive = false;
449 }
450
451#ifdef VBOX_WITH_STATISTICS
452 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
453 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
454 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
455 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
456
457 /*
458 * Statistics.
459 */
460 for (VMCPUID i = 0; i < pVM->cCpus; i++)
461 {
462 PVMCPU pVCpu = &pVM->aCpus[i];
463 int rc;
464
465 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
466 "Profiling of RTMpPokeCpu",
467 "/PROF/HM/CPU%d/Poke", i);
468 AssertRC(rc);
469 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
470 "Profiling of poke wait",
471 "/PROF/HM/CPU%d/PokeWait", i);
472 AssertRC(rc);
473 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
474 "Profiling of poke wait when RTMpPokeCpu fails",
475 "/PROF/HM/CPU%d/PokeWaitFailed", i);
476 AssertRC(rc);
477 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
478 "Profiling of VMXR0RunGuestCode entry",
479 "/PROF/HM/CPU%d/SwitchToGC", i);
480 AssertRC(rc);
481 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
482 "Profiling of VMXR0RunGuestCode exit part 1",
483 "/PROF/HM/CPU%d/SwitchFromGC_1", i);
484 AssertRC(rc);
485 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
486 "Profiling of VMXR0RunGuestCode exit part 2",
487 "/PROF/HM/CPU%d/SwitchFromGC_2", i);
488 AssertRC(rc);
489# if 1 /* temporary for tracking down darwin holdup. */
490 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
491 "Temporary - I/O",
492 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub1", i);
493 AssertRC(rc);
494 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
495 "Temporary - CRx RWs",
496 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub2", i);
497 AssertRC(rc);
498 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
499 "Temporary - Exceptions",
500 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub3", i);
501 AssertRC(rc);
502# endif
503 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
504 "Profiling of vmlaunch",
505 "/PROF/HM/CPU%d/InGC", i);
506 AssertRC(rc);
507
508# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
509 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
510 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
511 "/PROF/HM/CPU%d/Switcher3264", i);
512 AssertRC(rc);
513# endif
514
515# define HM_REG_COUNTER(a, b) \
516 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
517 AssertRC(rc);
518
519 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
520 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
521 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
522 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
523 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
524 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
525 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
526 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
527 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
528 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
529 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
530 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
531 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
541 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
542 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
544 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
545 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
548 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
549 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW");
551 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
552 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
554 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
555 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
558 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess");
559 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
560 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
561 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
562 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
563 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow");
564 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptPending, "/HM/CPU%d/Exit/PreemptPending");
566 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer");
567 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold");
568 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess");
571
572 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
573 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchToR3, "/HM/CPU%d/Switch/ToR3");
574
575 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
576 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
577 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
578
579 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
580 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
581 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
582 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
583 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
584 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbCRxChange, "/HM/CPU%d/Flush/TLB/CRx");
585 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageInvlpg, "/HM/CPU%d/Flush/Page/Invlpg");
586 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Switch");
587 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
588 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
589 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
590 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpga, "/HM/CPU%d/Flush/TLB/PhysInvl");
591 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
592 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
593
594 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
595 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
596 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
597
598 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
599 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
600 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
601
602 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
603 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
604
605#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
606 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
607 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
608#endif
609
610 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
611 {
612 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
613 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
614 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
615 AssertRC(rc);
616 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
617 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
618 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
619 AssertRC(rc);
620 }
621
622#undef HM_REG_COUNTER
623
624 pVCpu->hm.s.paStatExitReason = NULL;
625
626 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
627 (void **)&pVCpu->hm.s.paStatExitReason);
628 AssertRC(rc);
629 if (RT_SUCCESS(rc))
630 {
631 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
632 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
633 {
634 if (papszDesc[j])
635 {
636 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
637 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
638 AssertRC(rc);
639 }
640 }
641 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
642 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
643 AssertRC(rc);
644 }
645 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
646# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
647 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
648# else
649 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
650# endif
651
652 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
653 AssertRCReturn(rc, rc);
654 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
655# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
656 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
657# else
658 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
659# endif
660 for (unsigned j = 0; j < 255; j++)
661 {
662 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
663 "Forwarded interrupts.",
664 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
665 }
666
667 }
668#endif /* VBOX_WITH_STATISTICS */
669
670#ifdef VBOX_WITH_CRASHDUMP_MAGIC
671 /* Magic marker for searching in crash dumps. */
672 for (VMCPUID i = 0; i < pVM->cCpus; i++)
673 {
674 PVMCPU pVCpu = &pVM->aCpus[i];
675
676 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
677 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
678 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
679 }
680#endif
681 return VINF_SUCCESS;
682}
683
684
685/**
686 * Called when a init phase has completed.
687 *
688 * @returns VBox status code.
689 * @param pVM The VM.
690 * @param enmWhat The phase that completed.
691 */
692VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
693{
694 switch (enmWhat)
695 {
696 case VMINITCOMPLETED_RING3:
697 return hmR3InitCPU(pVM);
698 case VMINITCOMPLETED_RING0:
699 return hmR3InitFinalizeR0(pVM);
700 default:
701 return VINF_SUCCESS;
702 }
703}
704
705
706/**
707 * Turns off normal raw mode features.
708 *
709 * @param pVM Pointer to the VM.
710 */
711static void hmR3DisableRawMode(PVM pVM)
712{
713 /* Disable PATM & CSAM. */
714 PATMR3AllowPatching(pVM->pUVM, false);
715 CSAMDisableScanning(pVM);
716
717 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
718 SELMR3DisableMonitoring(pVM);
719 TRPMR3DisableMonitoring(pVM);
720
721 /* Disable the switcher code (safety precaution). */
722 VMMR3DisableSwitcher(pVM);
723
724 /* Disable mapping of the hypervisor into the shadow page table. */
725 PGMR3MappingsDisable(pVM);
726
727 /* Disable the switcher */
728 VMMR3DisableSwitcher(pVM);
729
730 /* Reinit the paging mode to force the new shadow mode. */
731 for (VMCPUID i = 0; i < pVM->cCpus; i++)
732 {
733 PVMCPU pVCpu = &pVM->aCpus[i];
734
735 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
736 }
737}
738
739
740/**
741 * Initialize VT-x or AMD-V.
742 *
743 * @returns VBox status code.
744 * @param pVM Pointer to the VM.
745 */
746static int hmR3InitFinalizeR0(PVM pVM)
747{
748 int rc;
749
750 /*
751 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
752 * is already using AMD-V.
753 */
754 if ( !pVM->hm.s.vmx.fSupported
755 && !pVM->hm.s.svm.fSupported
756 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
757 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
758 {
759 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
760 pVM->hm.s.svm.fSupported = true;
761 pVM->hm.s.svm.fIgnoreInUseError = true;
762 }
763 else
764 if ( !pVM->hm.s.vmx.fSupported
765 && !pVM->hm.s.svm.fSupported)
766 {
767 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
768 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
769
770 if (VMMIsHwVirtExtForced(pVM))
771 {
772 switch (pVM->hm.s.lLastError)
773 {
774 case VERR_VMX_NO_VMX:
775 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
776 case VERR_VMX_IN_VMX_ROOT_MODE:
777 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
778 case VERR_SVM_IN_USE:
779 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
780 case VERR_SVM_NO_SVM:
781 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
782 case VERR_SVM_DISABLED:
783 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
784 default:
785 return pVM->hm.s.lLastError;
786 }
787 }
788 return VINF_SUCCESS;
789 }
790
791 if (pVM->hm.s.vmx.fSupported)
792 {
793 rc = SUPR3QueryVTxSupported();
794 if (RT_FAILURE(rc))
795 {
796#ifdef RT_OS_LINUX
797 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
798#else
799 LogRel(("HM: The host kernel does not support VT-x!\n"));
800#endif
801 if ( pVM->cCpus > 1
802 || VMMIsHwVirtExtForced(pVM))
803 return rc;
804
805 /* silently fall back to raw mode */
806 return VINF_SUCCESS;
807 }
808 }
809
810 if (!pVM->hm.s.fAllowed)
811 return VINF_SUCCESS; /* nothing to do */
812
813 /* Enable VT-x or AMD-V on all host CPUs. */
814 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
815 if (RT_FAILURE(rc))
816 {
817 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
818 return rc;
819 }
820 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
821
822 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
823 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
824 if (!pVM->hm.s.fHasIoApic)
825 {
826 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
827 pVM->hm.s.fTRPPatchingAllowed = false;
828 }
829
830 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
831 if (pVM->hm.s.vmx.fSupported)
832 {
833 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
834
835 if ( pVM->hm.s.fInitialized == false
836 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
837 {
838 uint64_t val;
839 uint64_t zap;
840 RTGCPHYS GCPhys = 0;
841
842 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
843 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
844 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
845 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
846 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
847 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
848 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
849 LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
850 LogRel(("HM: Max resume loops = %RX32\n", pVM->hm.s.cMaxResumeLoops));
851
852 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
853 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
854 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
855 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT);
856 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT);
857 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI);
858 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER);
859
860 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
861 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
862 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
863 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT);
864 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_TSC_OFFSET);
865 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT);
866 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT);
867 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT);
868 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT);
869 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT);
870 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT);
871 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
872 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT);
873 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT);
874 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW);
875 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT);
876 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
877 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT);
878 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS);
879 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG);
880 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS);
881 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT);
882 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT);
883 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
884 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
885 {
886 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
887 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
888 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
889 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
890 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
891 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
892 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
893 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
894 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
895 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
896 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
897 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
898 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
899 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
900 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
901 }
902
903 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
904 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
905 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
906 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG);
907 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST);
908 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM);
909 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON);
910 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR);
911 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR);
912 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR);
913
914 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
915 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
916 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
917 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG);
918 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE);
919 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR);
920 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT);
921 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR);
922 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR);
923 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR);
924 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR);
925 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER);
926
927 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
928 {
929 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", pVM->hm.s.vmx.msr.vmx_ept_vpid_caps));
930
931 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY)
932 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY\n"));
933 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY)
934 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY\n"));
935 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY)
936 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY\n"));
937 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS)
938 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS\n"));
939 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS)
940 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS\n"));
941 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS)
942 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS\n"));
943 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS)
944 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS\n"));
945 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS)
946 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS\n"));
947 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC)
948 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC\n"));
949 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC)
950 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC\n"));
951 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT)
952 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT\n"));
953 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP)
954 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP\n"));
955 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB)
956 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB\n"));
957 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS)
958 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS\n"));
959 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS)
960 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS\n"));
961 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS)
962 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS\n"));
963 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS)
964 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS\n"));
965 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT)
966 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT\n"));
967 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT)
968 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT\n"));
969 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS)
970 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS\n"));
971 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID)
972 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID\n"));
973 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR)
974 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR\n"));
975 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT)
976 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT\n"));
977 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS)
978 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS\n"));
979 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps & MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
980 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
981 }
982
983 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
984 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
985 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
986 else
987 {
988 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
989 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
990 }
991
992 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
993 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
994 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
995 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
996
997 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
998 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
999 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1000 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1001 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1002
1003 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1004
1005 /* Paranoia */
1006 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1007
1008 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1009 {
1010 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1011 LogRel(("HM: VCPU%3d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1012 }
1013
1014 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1015 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1016
1017 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1018 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1019
1020 /*
1021 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1022 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1023 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1024 */
1025 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1026 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1027 {
1028 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1029 LogRel(("HM: Disabled RDTSCP\n"));
1030 }
1031
1032 /* Unrestricted guest execution relies on EPT. */
1033 if ( pVM->hm.s.fNestedPaging
1034 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1035 {
1036 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1037 }
1038
1039 /* Only try once. */
1040 pVM->hm.s.fInitialized = true;
1041
1042 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1043 {
1044 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1045 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1046 if (RT_SUCCESS(rc))
1047 {
1048 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1049 /* Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode" esp. Figure 20-5.*/
1050 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1051 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1052 /* Bit set to 0 means software interrupts are redirected to the 8086 program interrupt handler rather than
1053 switching to protected-mode handler. */
1054 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1055 /* Allow all port IO, so that port IO instructions do not cause exceptions and would instead
1056 cause a VM-exit (based on VT-x's IO bitmap which we currently configure to always cause an exit). */
1057 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1058 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1059
1060 /*
1061 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1062 * real and protected mode without paging with EPT.
1063 */
1064 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1065 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1066 {
1067 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1068 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1069 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1070 | X86_PDE4M_G;
1071 }
1072
1073 /* We convert it here every time as pci regions could be reconfigured. */
1074 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1075 AssertRC(rc);
1076 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1077
1078 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1079 AssertRC(rc);
1080 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1081 }
1082 else
1083 {
1084 /** @todo This cannot possibly work, there are other places which assumes
1085 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1086 * a failure case. */
1087 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1088 pVM->hm.s.vmx.pRealModeTSS = NULL;
1089 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1090 }
1091 }
1092
1093 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1094 AssertRC(rc);
1095 if (rc == VINF_SUCCESS)
1096 {
1097 pVM->fHMEnabled = true;
1098 pVM->hm.s.vmx.fEnabled = true;
1099 hmR3DisableRawMode(pVM);
1100
1101 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1102#ifdef VBOX_ENABLE_64_BITS_GUESTS
1103 if (pVM->hm.s.fAllow64BitGuests)
1104 {
1105 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1106 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1107 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1108 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1109 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1110# if RT_ARCH_X86
1111 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1112 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1113 LogRel(("NX is only supported for 64-bit guests!\n"));
1114# endif
1115 }
1116 else
1117 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1118 /* Todo: this needs to be fixed properly!! */
1119 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1120 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1121 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1122 else
1123 LogRel(("HM: NX not supported by the host\n"));
1124
1125 LogRel((pVM->hm.s.fAllow64BitGuests
1126 ? "HM: 32-bit and 64-bit guests supported.\n"
1127 : "HM: 32-bit guests supported.\n"));
1128#else
1129 LogRel(("HM: 32-bit guests supported.\n"));
1130#endif
1131 LogRel(("HM: VMX enabled!\n"));
1132 if (pVM->hm.s.fNestedPaging)
1133 {
1134 LogRel(("HM: Nested paging enabled!\n"));
1135 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1136 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1137 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1138 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1139 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1140 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1141 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1142 else
1143 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1144
1145 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1146 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1147
1148#if HC_ARCH_BITS == 64
1149 if (pVM->hm.s.fLargePages)
1150 {
1151 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1152 PGMSetLargePageUsage(pVM, true);
1153 LogRel(("HM: Large page support enabled!\n"));
1154 }
1155#endif
1156 }
1157 else
1158 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1159
1160 if (pVM->hm.s.vmx.fVpid)
1161 {
1162 LogRel(("HM: VPID enabled!\n"));
1163 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1164 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1165 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1166 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1167 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1168 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1169 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1170 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1171 else
1172 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1173 }
1174 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1175 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1176
1177 /* TPR patching status logging. */
1178 if (pVM->hm.s.fTRPPatchingAllowed)
1179 {
1180 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1181 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1182 {
1183 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1184 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1185 }
1186 else
1187 {
1188 uint32_t u32Eax, u32Dummy;
1189
1190 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1191 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1192 if ( u32Eax < 0x80000001
1193 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1194 {
1195 pVM->hm.s.fTRPPatchingAllowed = false;
1196 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1197 }
1198 }
1199 }
1200 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1201
1202 /*
1203 * Check for preemption timer config override and log the state of it.
1204 */
1205 if (pVM->hm.s.vmx.fUsePreemptTimer)
1206 {
1207 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1208 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1209 AssertLogRelRC(rc2);
1210 }
1211 if (pVM->hm.s.vmx.fUsePreemptTimer)
1212 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1213 }
1214 else
1215 {
1216 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1217 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1218 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1219 pVM->fHMEnabled = false;
1220 }
1221 }
1222 }
1223 else
1224 if (pVM->hm.s.svm.fSupported)
1225 {
1226 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1227
1228 if (pVM->hm.s.fInitialized == false)
1229 {
1230 /* Erratum 170 which requires a forced TLB flush for each world switch:
1231 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1232 *
1233 * All BH-G1/2 and DH-G1/2 models include a fix:
1234 * Athlon X2: 0x6b 1/2
1235 * 0x68 1/2
1236 * Athlon 64: 0x7f 1
1237 * 0x6f 2
1238 * Sempron: 0x7f 1/2
1239 * 0x6f 2
1240 * 0x6c 2
1241 * 0x7c 2
1242 * Turion 64: 0x68 2
1243 *
1244 */
1245 uint32_t u32Dummy;
1246 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1247 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1248 u32BaseFamily= (u32Version >> 8) & 0xf;
1249 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1250 u32Model = ((u32Version >> 4) & 0xf);
1251 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1252 u32Stepping = u32Version & 0xf;
1253 if ( u32Family == 0xf
1254 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1255 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1256 {
1257 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1258 }
1259
1260 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1261 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1262 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1263 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1264 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1265 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1266 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1267 {
1268#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1269 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1270 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1271 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1272 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1273 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1274 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1275 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1276 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1277 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1278 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1279 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1280#undef FLAG_NAME
1281 };
1282 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1283 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1284 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1285 {
1286 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1287 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1288 }
1289 if (fSvmFeatures)
1290 for (unsigned iBit = 0; iBit < 32; iBit++)
1291 if (RT_BIT_32(iBit) & fSvmFeatures)
1292 LogRel(("HM: Reserved bit %u\n", iBit));
1293
1294 /* Only try once. */
1295 pVM->hm.s.fInitialized = true;
1296
1297 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1298 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1299
1300 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1301 AssertRC(rc);
1302 if (rc == VINF_SUCCESS)
1303 {
1304 pVM->fHMEnabled = true;
1305 pVM->hm.s.svm.fEnabled = true;
1306
1307 if (pVM->hm.s.fNestedPaging)
1308 {
1309 LogRel(("HM: Enabled nested paging!\n"));
1310#if HC_ARCH_BITS == 64
1311 if (pVM->hm.s.fLargePages)
1312 {
1313 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1314 PGMSetLargePageUsage(pVM, true);
1315 LogRel(("HM: Large page support enabled!\n"));
1316 }
1317#endif
1318 }
1319
1320 hmR3DisableRawMode(pVM);
1321 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1322 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1323#ifdef VBOX_ENABLE_64_BITS_GUESTS
1324 if (pVM->hm.s.fAllow64BitGuests)
1325 {
1326 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1327 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1328 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1329 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1330 }
1331 else
1332 /* Turn on NXE if PAE has been enabled. */
1333 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1334 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1335#endif
1336
1337 LogRel((pVM->hm.s.fAllow64BitGuests
1338 ? "HM: 32-bit and 64-bit guest supported.\n"
1339 : "HM: 32-bit guest supported.\n"));
1340
1341 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1342 }
1343 else
1344 {
1345 pVM->fHMEnabled = false;
1346 }
1347 }
1348 }
1349 if (pVM->fHMEnabled)
1350 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1351 RTLogRelSetBuffering(fOldBuffered);
1352 return VINF_SUCCESS;
1353}
1354
1355
1356/**
1357 * Applies relocations to data and code managed by this
1358 * component. This function will be called at init and
1359 * whenever the VMM need to relocate it self inside the GC.
1360 *
1361 * @param pVM The VM.
1362 */
1363VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1364{
1365 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1366
1367 /* Fetch the current paging mode during the relocate callback during state loading. */
1368 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1369 {
1370 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1371 {
1372 PVMCPU pVCpu = &pVM->aCpus[i];
1373
1374 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1375 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1376 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1377 }
1378 }
1379#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1380 if (pVM->fHMEnabled)
1381 {
1382 int rc;
1383 switch (PGMGetHostMode(pVM))
1384 {
1385 case PGMMODE_32_BIT:
1386 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1387 break;
1388
1389 case PGMMODE_PAE:
1390 case PGMMODE_PAE_NX:
1391 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1392 break;
1393
1394 default:
1395 AssertFailed();
1396 break;
1397 }
1398 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1399 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1400
1401 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1402 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1403
1404 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1405 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1406
1407 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1408 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1409
1410# ifdef DEBUG
1411 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1412 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1413# endif
1414 }
1415#endif
1416 return;
1417}
1418
1419
1420/**
1421 * Checks if hardware accelerated raw mode is allowed.
1422 *
1423 * @returns true if hardware acceleration is allowed, otherwise false.
1424 * @param pVM Pointer to the VM.
1425 */
1426VMMR3_INT_DECL(bool) HMR3IsAllowed(PVM pVM)
1427{
1428 return pVM->hm.s.fAllowed;
1429}
1430
1431
1432/**
1433 * Notification callback which is called whenever there is a chance that a CR3
1434 * value might have changed.
1435 *
1436 * This is called by PGM.
1437 *
1438 * @param pVM Pointer to the VM.
1439 * @param pVCpu Pointer to the VMCPU.
1440 * @param enmShadowMode New shadow paging mode.
1441 * @param enmGuestMode New guest paging mode.
1442 */
1443VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1444{
1445 /* Ignore page mode changes during state loading. */
1446 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1447 return;
1448
1449 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1450
1451#ifdef VBOX_WITH_OLD_VTX_CODE
1452 if ( pVM->hm.s.vmx.fEnabled
1453 && pVM->fHMEnabled)
1454 {
1455 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1456 && enmGuestMode >= PGMMODE_PROTECTED)
1457 {
1458 PCPUMCTX pCtx;
1459
1460 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1461
1462 /* After a real mode switch to protected mode we must force
1463 CPL to 0. Our real mode emulation had to set it to 3. */
1464 pCtx->ss.Attr.n.u2Dpl = 0;
1465 }
1466 }
1467#endif
1468
1469 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1470 {
1471 /* Keep track of paging mode changes. */
1472 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1473 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1474
1475 /* Did we miss a change, because all code was executed in the recompiler? */
1476 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1477 {
1478 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1479 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1480 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1481 }
1482 }
1483
1484 /** @todo r=ramshankar: Why do we need to do this? Most likely
1485 * VBOX_WITH_OLD_VTX_CODE only. */
1486 /* Reset the contents of the read cache. */
1487 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1488 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1489 pCache->Read.aFieldVal[j] = 0;
1490}
1491
1492
1493/**
1494 * Terminates the HM.
1495 *
1496 * Termination means cleaning up and freeing all resources,
1497 * the VM itself is, at this point, powered off or suspended.
1498 *
1499 * @returns VBox status code.
1500 * @param pVM Pointer to the VM.
1501 */
1502VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1503{
1504 if (pVM->hm.s.vmx.pRealModeTSS)
1505 {
1506 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1507 pVM->hm.s.vmx.pRealModeTSS = 0;
1508 }
1509 hmR3TermCPU(pVM);
1510 return 0;
1511}
1512
1513
1514/**
1515 * Terminates the per-VCPU HM.
1516 *
1517 * @returns VBox status code.
1518 * @param pVM Pointer to the VM.
1519 */
1520static int hmR3TermCPU(PVM pVM)
1521{
1522 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1523 {
1524 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1525
1526#ifdef VBOX_WITH_STATISTICS
1527 if (pVCpu->hm.s.paStatExitReason)
1528 {
1529 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1530 pVCpu->hm.s.paStatExitReason = NULL;
1531 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1532 }
1533 if (pVCpu->hm.s.paStatInjectedIrqs)
1534 {
1535 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1536 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1537 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1538 }
1539#endif
1540
1541#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1542 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1543 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1544 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1545#endif
1546 }
1547 return 0;
1548}
1549
1550
1551/**
1552 * Resets a virtual CPU.
1553 *
1554 * Used by HMR3Reset and CPU hot plugging.
1555 *
1556 * @param pVCpu The CPU to reset.
1557 */
1558VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1559{
1560 /* On first entry we'll sync everything. */
1561 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1562
1563 pVCpu->hm.s.vmx.cr0_mask = 0;
1564 pVCpu->hm.s.vmx.cr4_mask = 0;
1565
1566 pVCpu->hm.s.fActive = false;
1567 pVCpu->hm.s.Event.fPending = false;
1568
1569 /* Reset state information for real-mode emulation in VT-x. */
1570 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1571 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1572 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1573
1574 /* Reset the contents of the read cache. */
1575 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1576 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1577 pCache->Read.aFieldVal[j] = 0;
1578
1579#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1580 /* Magic marker for searching in crash dumps. */
1581 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1582 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1583#endif
1584}
1585
1586
1587/**
1588 * The VM is being reset.
1589 *
1590 * For the HM component this means that any GDT/LDT/TSS monitors
1591 * needs to be removed.
1592 *
1593 * @param pVM Pointer to the VM.
1594 */
1595VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1596{
1597 LogFlow(("HMR3Reset:\n"));
1598
1599 if (pVM->fHMEnabled)
1600 hmR3DisableRawMode(pVM);
1601
1602 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1603 {
1604 PVMCPU pVCpu = &pVM->aCpus[i];
1605
1606 HMR3ResetCpu(pVCpu);
1607 }
1608
1609 /* Clear all patch information. */
1610 pVM->hm.s.pGuestPatchMem = 0;
1611 pVM->hm.s.pFreeGuestPatchMem = 0;
1612 pVM->hm.s.cbGuestPatchMem = 0;
1613 pVM->hm.s.cPatches = 0;
1614 pVM->hm.s.PatchTree = 0;
1615 pVM->hm.s.fTPRPatchingActive = false;
1616 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1617}
1618
1619
1620/**
1621 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1622 *
1623 * @returns VBox strict status code.
1624 * @param pVM Pointer to the VM.
1625 * @param pVCpu The VMCPU for the EMT we're being called on.
1626 * @param pvUser Unused.
1627 */
1628DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1629{
1630 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1631
1632 /* Only execute the handler on the VCPU the original patch request was issued. */
1633 if (pVCpu->idCpu != idCpu)
1634 return VINF_SUCCESS;
1635
1636 Log(("hmR3RemovePatches\n"));
1637 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1638 {
1639 uint8_t abInstr[15];
1640 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1641 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1642 int rc;
1643
1644#ifdef LOG_ENABLED
1645 char szOutput[256];
1646
1647 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1648 szOutput, sizeof(szOutput), NULL);
1649 if (RT_SUCCESS(rc))
1650 Log(("Patched instr: %s\n", szOutput));
1651#endif
1652
1653 /* Check if the instruction is still the same. */
1654 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1655 if (rc != VINF_SUCCESS)
1656 {
1657 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1658 continue; /* swapped out or otherwise removed; skip it. */
1659 }
1660
1661 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1662 {
1663 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1664 continue; /* skip it. */
1665 }
1666
1667 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1668 AssertRC(rc);
1669
1670#ifdef LOG_ENABLED
1671 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1672 szOutput, sizeof(szOutput), NULL);
1673 if (RT_SUCCESS(rc))
1674 Log(("Original instr: %s\n", szOutput));
1675#endif
1676 }
1677 pVM->hm.s.cPatches = 0;
1678 pVM->hm.s.PatchTree = 0;
1679 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1680 pVM->hm.s.fTPRPatchingActive = false;
1681 return VINF_SUCCESS;
1682}
1683
1684
1685/**
1686 * Worker for enabling patching in a VT-x/AMD-V guest.
1687 *
1688 * @returns VBox status code.
1689 * @param pVM Pointer to the VM.
1690 * @param idCpu VCPU to execute hmR3RemovePatches on.
1691 * @param pPatchMem Patch memory range.
1692 * @param cbPatchMem Size of the memory range.
1693 */
1694static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1695{
1696 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1697 AssertRC(rc);
1698
1699 pVM->hm.s.pGuestPatchMem = pPatchMem;
1700 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1701 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1702 return VINF_SUCCESS;
1703}
1704
1705
1706/**
1707 * Enable patching in a VT-x/AMD-V guest
1708 *
1709 * @returns VBox status code.
1710 * @param pVM Pointer to the VM.
1711 * @param pPatchMem Patch memory range.
1712 * @param cbPatchMem Size of the memory range.
1713 */
1714VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1715{
1716 VM_ASSERT_EMT(pVM);
1717 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1718 if (pVM->cCpus > 1)
1719 {
1720 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1721 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1722 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1723 AssertRC(rc);
1724 return rc;
1725 }
1726 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1727}
1728
1729
1730/**
1731 * Disable patching in a VT-x/AMD-V guest.
1732 *
1733 * @returns VBox status code.
1734 * @param pVM Pointer to the VM.
1735 * @param pPatchMem Patch memory range.
1736 * @param cbPatchMem Size of the memory range.
1737 */
1738VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1739{
1740 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1741
1742 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1743 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1744
1745 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1746 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1747 (void *)(uintptr_t)VMMGetCpuId(pVM));
1748 AssertRC(rc);
1749
1750 pVM->hm.s.pGuestPatchMem = 0;
1751 pVM->hm.s.pFreeGuestPatchMem = 0;
1752 pVM->hm.s.cbGuestPatchMem = 0;
1753 pVM->hm.s.fTPRPatchingActive = false;
1754 return VINF_SUCCESS;
1755}
1756
1757
1758/**
1759 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1760 *
1761 * @returns VBox strict status code.
1762 * @param pVM Pointer to the VM.
1763 * @param pVCpu The VMCPU for the EMT we're being called on.
1764 * @param pvUser User specified CPU context.
1765 *
1766 */
1767DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1768{
1769 /*
1770 * Only execute the handler on the VCPU the original patch request was
1771 * issued. (The other CPU(s) might not yet have switched to protected
1772 * mode, nor have the correct memory context.)
1773 */
1774 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1775 if (pVCpu->idCpu != idCpu)
1776 return VINF_SUCCESS;
1777
1778 /*
1779 * We're racing other VCPUs here, so don't try patch the instruction twice
1780 * and make sure there is still room for our patch record.
1781 */
1782 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1783 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1784 if (pPatch)
1785 {
1786 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1787 return VINF_SUCCESS;
1788 }
1789 uint32_t const idx = pVM->hm.s.cPatches;
1790 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1791 {
1792 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1793 return VINF_SUCCESS;
1794 }
1795 pPatch = &pVM->hm.s.aPatches[idx];
1796
1797 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1798
1799 /*
1800 * Disassembler the instruction and get cracking.
1801 */
1802 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1803 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1804 uint32_t cbOp;
1805 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1806 AssertRC(rc);
1807 if ( rc == VINF_SUCCESS
1808 && pDis->pCurInstr->uOpcode == OP_MOV
1809 && cbOp >= 3)
1810 {
1811 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1812
1813 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1814 AssertRC(rc);
1815
1816 pPatch->cbOp = cbOp;
1817
1818 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1819 {
1820 /* write. */
1821 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1822 {
1823 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1824 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1825 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1826 }
1827 else
1828 {
1829 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1830 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1831 pPatch->uSrcOperand = pDis->Param2.uValue;
1832 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1833 }
1834 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1835 AssertRC(rc);
1836
1837 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1838 pPatch->cbNewOp = sizeof(s_abVMMCall);
1839 }
1840 else
1841 {
1842 /*
1843 * TPR Read.
1844 *
1845 * Found:
1846 * mov eax, dword [fffe0080] (5 bytes)
1847 * Check if next instruction is:
1848 * shr eax, 4
1849 */
1850 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1851
1852 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1853 uint8_t const cbOpMmio = cbOp;
1854 uint64_t const uSavedRip = pCtx->rip;
1855
1856 pCtx->rip += cbOp;
1857 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1858 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1859 pCtx->rip = uSavedRip;
1860
1861 if ( rc == VINF_SUCCESS
1862 && pDis->pCurInstr->uOpcode == OP_SHR
1863 && pDis->Param1.fUse == DISUSE_REG_GEN32
1864 && pDis->Param1.Base.idxGenReg == idxMmioReg
1865 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1866 && pDis->Param2.uValue == 4
1867 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1868 {
1869 uint8_t abInstr[15];
1870
1871 /* Replacing two instructions now. */
1872 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1873 AssertRC(rc);
1874
1875 pPatch->cbOp = cbOpMmio + cbOp;
1876
1877 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1878 abInstr[0] = 0xF0;
1879 abInstr[1] = 0x0F;
1880 abInstr[2] = 0x20;
1881 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1882 for (unsigned i = 4; i < pPatch->cbOp; i++)
1883 abInstr[i] = 0x90; /* nop */
1884
1885 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1886 AssertRC(rc);
1887
1888 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1889 pPatch->cbNewOp = pPatch->cbOp;
1890
1891 Log(("Acceptable read/shr candidate!\n"));
1892 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1893 }
1894 else
1895 {
1896 pPatch->enmType = HMTPRINSTR_READ;
1897 pPatch->uDstOperand = idxMmioReg;
1898
1899 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1900 AssertRC(rc);
1901
1902 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1903 pPatch->cbNewOp = sizeof(s_abVMMCall);
1904 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1905 }
1906 }
1907
1908 pPatch->Core.Key = pCtx->eip;
1909 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1910 AssertRC(rc);
1911
1912 pVM->hm.s.cPatches++;
1913 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1914 return VINF_SUCCESS;
1915 }
1916
1917 /*
1918 * Save invalid patch, so we will not try again.
1919 */
1920 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1921 pPatch->Core.Key = pCtx->eip;
1922 pPatch->enmType = HMTPRINSTR_INVALID;
1923 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1924 AssertRC(rc);
1925 pVM->hm.s.cPatches++;
1926 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1927 return VINF_SUCCESS;
1928}
1929
1930
1931/**
1932 * Callback to patch a TPR instruction (jump to generated code).
1933 *
1934 * @returns VBox strict status code.
1935 * @param pVM Pointer to the VM.
1936 * @param pVCpu The VMCPU for the EMT we're being called on.
1937 * @param pvUser User specified CPU context.
1938 *
1939 */
1940DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1941{
1942 /*
1943 * Only execute the handler on the VCPU the original patch request was
1944 * issued. (The other CPU(s) might not yet have switched to protected
1945 * mode, nor have the correct memory context.)
1946 */
1947 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1948 if (pVCpu->idCpu != idCpu)
1949 return VINF_SUCCESS;
1950
1951 /*
1952 * We're racing other VCPUs here, so don't try patch the instruction twice
1953 * and make sure there is still room for our patch record.
1954 */
1955 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1956 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1957 if (pPatch)
1958 {
1959 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1960 return VINF_SUCCESS;
1961 }
1962 uint32_t const idx = pVM->hm.s.cPatches;
1963 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1964 {
1965 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1966 return VINF_SUCCESS;
1967 }
1968 pPatch = &pVM->hm.s.aPatches[idx];
1969
1970 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1971 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
1972
1973 /*
1974 * Disassemble the instruction and get cracking.
1975 */
1976 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1977 uint32_t cbOp;
1978 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1979 AssertRC(rc);
1980 if ( rc == VINF_SUCCESS
1981 && pDis->pCurInstr->uOpcode == OP_MOV
1982 && cbOp >= 5)
1983 {
1984 uint8_t aPatch[64];
1985 uint32_t off = 0;
1986
1987 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1988 AssertRC(rc);
1989
1990 pPatch->cbOp = cbOp;
1991 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
1992
1993 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1994 {
1995 /*
1996 * TPR write:
1997 *
1998 * push ECX [51]
1999 * push EDX [52]
2000 * push EAX [50]
2001 * xor EDX,EDX [31 D2]
2002 * mov EAX,EAX [89 C0]
2003 * or
2004 * mov EAX,0000000CCh [B8 CC 00 00 00]
2005 * mov ECX,0C0000082h [B9 82 00 00 C0]
2006 * wrmsr [0F 30]
2007 * pop EAX [58]
2008 * pop EDX [5A]
2009 * pop ECX [59]
2010 * jmp return_address [E9 return_address]
2011 *
2012 */
2013 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2014
2015 aPatch[off++] = 0x51; /* push ecx */
2016 aPatch[off++] = 0x52; /* push edx */
2017 if (!fUsesEax)
2018 aPatch[off++] = 0x50; /* push eax */
2019 aPatch[off++] = 0x31; /* xor edx, edx */
2020 aPatch[off++] = 0xD2;
2021 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2022 {
2023 if (!fUsesEax)
2024 {
2025 aPatch[off++] = 0x89; /* mov eax, src_reg */
2026 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2027 }
2028 }
2029 else
2030 {
2031 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2032 aPatch[off++] = 0xB8; /* mov eax, immediate */
2033 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2034 off += sizeof(uint32_t);
2035 }
2036 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2037 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2038 off += sizeof(uint32_t);
2039
2040 aPatch[off++] = 0x0F; /* wrmsr */
2041 aPatch[off++] = 0x30;
2042 if (!fUsesEax)
2043 aPatch[off++] = 0x58; /* pop eax */
2044 aPatch[off++] = 0x5A; /* pop edx */
2045 aPatch[off++] = 0x59; /* pop ecx */
2046 }
2047 else
2048 {
2049 /*
2050 * TPR read:
2051 *
2052 * push ECX [51]
2053 * push EDX [52]
2054 * push EAX [50]
2055 * mov ECX,0C0000082h [B9 82 00 00 C0]
2056 * rdmsr [0F 32]
2057 * mov EAX,EAX [89 C0]
2058 * pop EAX [58]
2059 * pop EDX [5A]
2060 * pop ECX [59]
2061 * jmp return_address [E9 return_address]
2062 *
2063 */
2064 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2065
2066 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2067 aPatch[off++] = 0x51; /* push ecx */
2068 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2069 aPatch[off++] = 0x52; /* push edx */
2070 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2071 aPatch[off++] = 0x50; /* push eax */
2072
2073 aPatch[off++] = 0x31; /* xor edx, edx */
2074 aPatch[off++] = 0xD2;
2075
2076 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2077 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2078 off += sizeof(uint32_t);
2079
2080 aPatch[off++] = 0x0F; /* rdmsr */
2081 aPatch[off++] = 0x32;
2082
2083 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2084 {
2085 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2086 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2087 }
2088
2089 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2090 aPatch[off++] = 0x58; /* pop eax */
2091 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2092 aPatch[off++] = 0x5A; /* pop edx */
2093 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2094 aPatch[off++] = 0x59; /* pop ecx */
2095 }
2096 aPatch[off++] = 0xE9; /* jmp return_address */
2097 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2098 off += sizeof(RTRCUINTPTR);
2099
2100 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2101 {
2102 /* Write new code to the patch buffer. */
2103 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2104 AssertRC(rc);
2105
2106#ifdef LOG_ENABLED
2107 uint32_t cbCurInstr;
2108 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2109 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2110 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2111 {
2112 char szOutput[256];
2113 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2114 szOutput, sizeof(szOutput), &cbCurInstr);
2115 if (RT_SUCCESS(rc))
2116 Log(("Patch instr %s\n", szOutput));
2117 else
2118 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2119 }
2120#endif
2121
2122 pPatch->aNewOpcode[0] = 0xE9;
2123 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2124
2125 /* Overwrite the TPR instruction with a jump. */
2126 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2127 AssertRC(rc);
2128
2129 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2130
2131 pVM->hm.s.pFreeGuestPatchMem += off;
2132 pPatch->cbNewOp = 5;
2133
2134 pPatch->Core.Key = pCtx->eip;
2135 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2136 AssertRC(rc);
2137
2138 pVM->hm.s.cPatches++;
2139 pVM->hm.s.fTPRPatchingActive = true;
2140 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2141 return VINF_SUCCESS;
2142 }
2143
2144 Log(("Ran out of space in our patch buffer!\n"));
2145 }
2146 else
2147 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2148
2149
2150 /*
2151 * Save invalid patch, so we will not try again.
2152 */
2153 pPatch = &pVM->hm.s.aPatches[idx];
2154 pPatch->Core.Key = pCtx->eip;
2155 pPatch->enmType = HMTPRINSTR_INVALID;
2156 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2157 AssertRC(rc);
2158 pVM->hm.s.cPatches++;
2159 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2160 return VINF_SUCCESS;
2161}
2162
2163
2164/**
2165 * Attempt to patch TPR mmio instructions.
2166 *
2167 * @returns VBox status code.
2168 * @param pVM Pointer to the VM.
2169 * @param pVCpu Pointer to the VMCPU.
2170 * @param pCtx Pointer to the guest CPU context.
2171 */
2172VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2173{
2174 NOREF(pCtx);
2175 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2176 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2177 (void *)(uintptr_t)pVCpu->idCpu);
2178 AssertRC(rc);
2179 return rc;
2180}
2181
2182
2183/**
2184 * Force execution of the current IO code in the recompiler.
2185 *
2186 * @returns VBox status code.
2187 * @param pVM Pointer to the VM.
2188 * @param pCtx Partial VM execution context.
2189 */
2190VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2191{
2192 PVMCPU pVCpu = VMMGetCpu(pVM);
2193
2194 Assert(pVM->fHMEnabled);
2195 Log(("HMR3EmulateIoBlock\n"));
2196
2197 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2198 if (HMCanEmulateIoBlockEx(pCtx))
2199 {
2200 Log(("HMR3EmulateIoBlock -> enabled\n"));
2201 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2202 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2203 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2204 return VINF_EM_RESCHEDULE_REM;
2205 }
2206 return VINF_SUCCESS;
2207}
2208
2209
2210/**
2211 * Checks if we can currently use hardware accelerated raw mode.
2212 *
2213 * @returns true if we can currently use hardware acceleration, otherwise false.
2214 * @param pVM Pointer to the VM.
2215 * @param pCtx Partial VM execution context.
2216 */
2217VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2218{
2219 PVMCPU pVCpu = VMMGetCpu(pVM);
2220
2221 Assert(pVM->fHMEnabled);
2222
2223 /* If we're still executing the IO code, then return false. */
2224 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2225 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2226 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2227 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2228 return false;
2229
2230 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2231
2232 /* AMD-V supports real & protected mode with or without paging. */
2233 if (pVM->hm.s.svm.fEnabled)
2234 {
2235 pVCpu->hm.s.fActive = true;
2236 return true;
2237 }
2238
2239 pVCpu->hm.s.fActive = false;
2240
2241 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2242 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2243 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2244
2245 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2246 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2247 {
2248 /*
2249 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2250 * guest execution feature i missing (VT-x only).
2251 */
2252 if (fSupportsRealMode)
2253 {
2254 if (CPUMIsGuestInRealModeEx(pCtx))
2255 {
2256 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2257 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2258 * If this is not true, we cannot execute real mode as V86 and have to fall
2259 * back to emulation.
2260 */
2261 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2262 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2263 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2264 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2265 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2266 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2267 || (pCtx->cs.u32Limit != 0xffff)
2268 || (pCtx->ds.u32Limit != 0xffff)
2269 || (pCtx->es.u32Limit != 0xffff)
2270 || (pCtx->ss.u32Limit != 0xffff)
2271 || (pCtx->fs.u32Limit != 0xffff)
2272 || (pCtx->gs.u32Limit != 0xffff))
2273 {
2274 return false;
2275 }
2276 }
2277 else
2278 {
2279 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2280 /* Verify the requirements for executing code in protected
2281 mode. VT-x can't handle the CPU state right after a switch
2282 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2283 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2284 && enmGuestMode >= PGMMODE_PROTECTED)
2285 {
2286 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2287 || (pCtx->ds.Sel & X86_SEL_RPL)
2288 || (pCtx->es.Sel & X86_SEL_RPL)
2289 || (pCtx->fs.Sel & X86_SEL_RPL)
2290 || (pCtx->gs.Sel & X86_SEL_RPL)
2291 || (pCtx->ss.Sel & X86_SEL_RPL))
2292 {
2293 return false;
2294 }
2295 }
2296 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2297 if ( pCtx->gdtr.cbGdt
2298 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2299 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2300 {
2301 return false;
2302 }
2303 }
2304 }
2305 else
2306 {
2307 if ( !CPUMIsGuestInLongModeEx(pCtx)
2308 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2309 {
2310 /** @todo This should (probably) be set on every excursion to the REM,
2311 * however it's too risky right now. So, only apply it when we go
2312 * back to REM for real mode execution. (The XP hack below doesn't
2313 * work reliably without this.)
2314 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2315 for (uint32_t i = 0; i < pVM->cCpus; i++)
2316 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2317
2318 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2319 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2320 return false;
2321
2322 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2323 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2324 return false;
2325
2326 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2327 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2328 * hidden registers (possible recompiler bug; see load_seg_vm) */
2329 if (pCtx->cs.Attr.n.u1Present == 0)
2330 return false;
2331 if (pCtx->ss.Attr.n.u1Present == 0)
2332 return false;
2333
2334 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2335 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2336 /** @todo This check is actually wrong, it doesn't take the direction of the
2337 * stack segment into account. But, it does the job for now. */
2338 if (pCtx->rsp >= pCtx->ss.u32Limit)
2339 return false;
2340#if 0
2341 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2342 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2343 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2344 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2345 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2346 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2347 return false;
2348#endif
2349 }
2350 }
2351 }
2352
2353 if (pVM->hm.s.vmx.fEnabled)
2354 {
2355 uint32_t mask;
2356
2357 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2358 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2359 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2360 mask &= ~X86_CR0_NE;
2361
2362 if (fSupportsRealMode)
2363 {
2364 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2365 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2366 }
2367 else
2368 {
2369 /* We support protected mode without paging using identity mapping. */
2370 mask &= ~X86_CR0_PG;
2371 }
2372 if ((pCtx->cr0 & mask) != mask)
2373 return false;
2374
2375 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2376 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2377 if ((pCtx->cr0 & mask) != 0)
2378 return false;
2379
2380 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2381 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2382 mask &= ~X86_CR4_VMXE;
2383 if ((pCtx->cr4 & mask) != mask)
2384 return false;
2385
2386 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2387 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2388 if ((pCtx->cr4 & mask) != 0)
2389 return false;
2390
2391 pVCpu->hm.s.fActive = true;
2392 return true;
2393 }
2394
2395 return false;
2396}
2397
2398
2399/**
2400 * Checks if we need to reschedule due to VMM device heap changes.
2401 *
2402 * @returns true if a reschedule is required, otherwise false.
2403 * @param pVM Pointer to the VM.
2404 * @param pCtx VM execution context.
2405 */
2406VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2407{
2408 /*
2409 * The VMM device heap is a requirement for emulating real mode or protected mode without paging
2410 * when the unrestricted guest execution feature is missing (VT-x only).
2411 */
2412 if ( pVM->hm.s.vmx.fEnabled
2413 && !pVM->hm.s.vmx.fUnrestrictedGuest
2414 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2415 && !PDMVmmDevHeapIsEnabled(pVM)
2416 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2417 return true;
2418
2419 return false;
2420}
2421
2422
2423/**
2424 * Notification from EM about a rescheduling into hardware assisted execution
2425 * mode.
2426 *
2427 * @param pVCpu Pointer to the current VMCPU.
2428 */
2429VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2430{
2431 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2432}
2433
2434
2435/**
2436 * Notification from EM about returning from instruction emulation (REM / EM).
2437 *
2438 * @param pVCpu Pointer to the VMCPU.
2439 */
2440VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2441{
2442 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2443}
2444
2445
2446/**
2447 * Checks if we are currently using hardware accelerated raw mode.
2448 *
2449 * @returns true if hardware acceleration is being used, otherwise false.
2450 * @param pVCpu Pointer to the VMCPU.
2451 */
2452VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2453{
2454 return pVCpu->hm.s.fActive;
2455}
2456
2457
2458/**
2459 * Checks if we are currently using nested paging.
2460 *
2461 * @returns true if nested paging is being used, otherwise false.
2462 * @param pUVM The user mode VM handle.
2463 */
2464VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2465{
2466 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2467 PVM pVM = pUVM->pVM;
2468 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2469 return HMIsEnabled(pVM);
2470}
2471
2472
2473/**
2474 * Checks if we are currently using nested paging.
2475 *
2476 * @returns true if nested paging is being used, otherwise false.
2477 * @param pUVM The user mode VM handle.
2478 */
2479VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2480{
2481 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2482 PVM pVM = pUVM->pVM;
2483 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2484 return pVM->hm.s.fNestedPaging;
2485}
2486
2487
2488/**
2489 * Checks if we are currently using VPID in VT-x mode.
2490 *
2491 * @returns true if VPID is being used, otherwise false.
2492 * @param pUVM The user mode VM handle.
2493 */
2494VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2495{
2496 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2497 PVM pVM = pUVM->pVM;
2498 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2499 return pVM->hm.s.vmx.fVpid;
2500}
2501
2502
2503/**
2504 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2505 *
2506 * @returns true if an internal event is pending, otherwise false.
2507 * @param pVM Pointer to the VM.
2508 */
2509VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2510{
2511 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2512}
2513
2514
2515/**
2516 * Checks if the VMX-preemption timer is being used.
2517 *
2518 * @returns true if the VMX-preemption timer is being used, otherwise false.
2519 * @param pVM Pointer to the VM.
2520 */
2521VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2522{
2523 return HMIsEnabled(pVM)
2524 && pVM->hm.s.vmx.fEnabled
2525 && pVM->hm.s.vmx.fUsePreemptTimer;
2526}
2527
2528
2529/**
2530 * Restart an I/O instruction that was refused in ring-0
2531 *
2532 * @returns Strict VBox status code. Informational status codes other than the one documented
2533 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2534 * @retval VINF_SUCCESS Success.
2535 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2536 * status code must be passed on to EM.
2537 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2538 *
2539 * @param pVM Pointer to the VM.
2540 * @param pVCpu Pointer to the VMCPU.
2541 * @param pCtx Pointer to the guest CPU context.
2542 */
2543VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2544{
2545 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2546
2547 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2548
2549 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2550 || enmType == HMPENDINGIO_INVALID)
2551 return VERR_NOT_FOUND;
2552
2553 VBOXSTRICTRC rcStrict;
2554 switch (enmType)
2555 {
2556 case HMPENDINGIO_PORT_READ:
2557 {
2558 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2559 uint32_t u32Val = 0;
2560
2561 rcStrict = IOMIOPortRead(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2562 &u32Val,
2563 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2564 if (IOM_SUCCESS(rcStrict))
2565 {
2566 /* Write back to the EAX register. */
2567 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2568 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2569 }
2570 break;
2571 }
2572
2573 case HMPENDINGIO_PORT_WRITE:
2574 rcStrict = IOMIOPortWrite(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2575 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2576 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2577 if (IOM_SUCCESS(rcStrict))
2578 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2579 break;
2580
2581 default:
2582 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2583 }
2584
2585 return rcStrict;
2586}
2587
2588
2589/**
2590 * Check fatal VT-x/AMD-V error and produce some meaningful
2591 * log release message.
2592 *
2593 * @param pVM Pointer to the VM.
2594 * @param iStatusCode VBox status code.
2595 */
2596VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2597{
2598 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2599 {
2600 switch (iStatusCode)
2601 {
2602 case VERR_VMX_INVALID_VMCS_FIELD:
2603 break;
2604
2605 case VERR_VMX_INVALID_VMCS_PTR:
2606 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2607 LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2608 LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2609 LogRel(("HM: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2610 LogRel(("HM: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2611 break;
2612
2613 case VERR_VMX_UNABLE_TO_START_VM:
2614 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2615 LogRel(("HM: CPU%d instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2616 LogRel(("HM: CPU%d exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2617 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2618 {
2619 LogRel(("HM: Cpu%d PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2620 LogRel(("HM: Cpu%d ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2621 LogRel(("HM: Cpu%d ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2622 LogRel(("HM: Cpu%d EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2623 LogRel(("HM: Cpu%d ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2624 LogRel(("HM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2625#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2626 LogRel(("HM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2627 LogRel(("HM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2628 LogRel(("HM: Cpu%d cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2629#endif
2630 }
2631 /** @todo Log VM-entry event injection control fields
2632 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2633 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2634 break;
2635
2636 case VERR_VMX_UNABLE_TO_RESUME_VM:
2637 LogRel(("HM: VERR_VMX_UNABLE_TO_RESUME_VM:\n"));
2638 LogRel(("HM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2639 LogRel(("HM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2640 break;
2641
2642 case VERR_VMX_INVALID_VMXON_PTR:
2643 break;
2644 }
2645 }
2646
2647 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2648 {
2649 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2650 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2651 }
2652}
2653
2654
2655/**
2656 * Execute state save operation.
2657 *
2658 * @returns VBox status code.
2659 * @param pVM Pointer to the VM.
2660 * @param pSSM SSM operation handle.
2661 */
2662static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2663{
2664 int rc;
2665
2666 Log(("hmR3Save:\n"));
2667
2668 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2669 {
2670 /*
2671 * Save the basic bits - fortunately all the other things can be resynced on load.
2672 */
2673 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2674 AssertRCReturn(rc, rc);
2675 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2676 AssertRCReturn(rc, rc);
2677 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2678 AssertRCReturn(rc, rc);
2679
2680 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2681 AssertRCReturn(rc, rc);
2682 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2683 AssertRCReturn(rc, rc);
2684 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2685 AssertRCReturn(rc, rc);
2686 }
2687#ifdef VBOX_HM_WITH_GUEST_PATCHING
2688 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2689 AssertRCReturn(rc, rc);
2690 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2691 AssertRCReturn(rc, rc);
2692 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2693 AssertRCReturn(rc, rc);
2694
2695 /* Store all the guest patch records too. */
2696 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2697 AssertRCReturn(rc, rc);
2698
2699 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2700 {
2701 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2702
2703 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2704 AssertRCReturn(rc, rc);
2705
2706 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2707 AssertRCReturn(rc, rc);
2708
2709 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2710 AssertRCReturn(rc, rc);
2711
2712 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2713 AssertRCReturn(rc, rc);
2714
2715 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2716 AssertRCReturn(rc, rc);
2717
2718 AssertCompileSize(HMTPRINSTR, 4);
2719 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2720 AssertRCReturn(rc, rc);
2721
2722 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2723 AssertRCReturn(rc, rc);
2724
2725 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2726 AssertRCReturn(rc, rc);
2727
2728 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2729 AssertRCReturn(rc, rc);
2730
2731 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2732 AssertRCReturn(rc, rc);
2733 }
2734#endif
2735 return VINF_SUCCESS;
2736}
2737
2738
2739/**
2740 * Execute state load operation.
2741 *
2742 * @returns VBox status code.
2743 * @param pVM Pointer to the VM.
2744 * @param pSSM SSM operation handle.
2745 * @param uVersion Data layout version.
2746 * @param uPass The data pass.
2747 */
2748static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2749{
2750 int rc;
2751
2752 Log(("hmR3Load:\n"));
2753 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2754
2755 /*
2756 * Validate version.
2757 */
2758 if ( uVersion != HM_SSM_VERSION
2759 && uVersion != HM_SSM_VERSION_NO_PATCHING
2760 && uVersion != HM_SSM_VERSION_2_0_X)
2761 {
2762 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2763 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2764 }
2765 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2766 {
2767 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2768 AssertRCReturn(rc, rc);
2769 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
2770 AssertRCReturn(rc, rc);
2771 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2772 AssertRCReturn(rc, rc);
2773
2774 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2775 {
2776 uint32_t val;
2777
2778 rc = SSMR3GetU32(pSSM, &val);
2779 AssertRCReturn(rc, rc);
2780 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2781
2782 rc = SSMR3GetU32(pSSM, &val);
2783 AssertRCReturn(rc, rc);
2784 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2785
2786 rc = SSMR3GetU32(pSSM, &val);
2787 AssertRCReturn(rc, rc);
2788 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2789 }
2790 }
2791#ifdef VBOX_HM_WITH_GUEST_PATCHING
2792 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2793 {
2794 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2795 AssertRCReturn(rc, rc);
2796 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2797 AssertRCReturn(rc, rc);
2798 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2799 AssertRCReturn(rc, rc);
2800
2801 /* Fetch all TPR patch records. */
2802 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2803 AssertRCReturn(rc, rc);
2804
2805 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2806 {
2807 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2808
2809 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2810 AssertRCReturn(rc, rc);
2811
2812 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2813 AssertRCReturn(rc, rc);
2814
2815 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2816 AssertRCReturn(rc, rc);
2817
2818 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2819 AssertRCReturn(rc, rc);
2820
2821 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2822 AssertRCReturn(rc, rc);
2823
2824 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2825 AssertRCReturn(rc, rc);
2826
2827 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2828 pVM->hm.s.fTPRPatchingActive = true;
2829
2830 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2831
2832 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2833 AssertRCReturn(rc, rc);
2834
2835 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2836 AssertRCReturn(rc, rc);
2837
2838 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2839 AssertRCReturn(rc, rc);
2840
2841 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2842 AssertRCReturn(rc, rc);
2843
2844 Log(("hmR3Load: patch %d\n", i));
2845 Log(("Key = %x\n", pPatch->Core.Key));
2846 Log(("cbOp = %d\n", pPatch->cbOp));
2847 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2848 Log(("type = %d\n", pPatch->enmType));
2849 Log(("srcop = %d\n", pPatch->uSrcOperand));
2850 Log(("dstop = %d\n", pPatch->uDstOperand));
2851 Log(("cFaults = %d\n", pPatch->cFaults));
2852 Log(("target = %x\n", pPatch->pJumpTarget));
2853 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2854 AssertRC(rc);
2855 }
2856 }
2857#endif
2858
2859 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2860 if (HMIsEnabled(pVM))
2861 {
2862 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2863 {
2864 PVMCPU pVCpu = &pVM->aCpus[i];
2865
2866 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2867 }
2868 }
2869 return VINF_SUCCESS;
2870}
2871
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