VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 45237

Last change on this file since 45237 was 45235, checked in by vboxsync, 12 years ago

VMM: Flush page and tlb STAM counter cleanup.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 126.7 KB
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1/* $Id: HM.cpp 45235 2013-03-28 14:36:52Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/vmm/uvm.h>
42#include <VBox/err.h>
43#include <VBox/param.h>
44
45#include <iprt/assert.h>
46#include <VBox/log.h>
47#include <iprt/asm.h>
48#include <iprt/asm-amd64-x86.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
114 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL(),
119 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND. Guest software attempted to execute RDRAND."),
120 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID. Guest software attempted to execute INVPCID."),
121 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC. Guest software attempted to execute VMFUNC.")
122};
123/** Exit reason descriptions for AMD-V, used to describe statistics. */
124static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
125{
126 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
127 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
128 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
129 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
130 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
131 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
132 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
133 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
134 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
135 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
136 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
137 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
138 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
139 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
140 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
141 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
158 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
159 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
160 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
161 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
162 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
163 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
164 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
165 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
166 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
167 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
168 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
169 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
170 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
171 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
172 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
173 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
222 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
223 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
224 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
225 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
226 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
227 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
228 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
229 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
230 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
232 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
236 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
237 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
238 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
239 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
240 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
241 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
242 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
243 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
244 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
245 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
246 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
247 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
248 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
249 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
250 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
251 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
252 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
253 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
254 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
255 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
256 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
257 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
258 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
259 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
260 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
261 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
262 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
263 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
264 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
265 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
266 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
267 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
268 EXIT_REASON_NIL()
269};
270# undef EXIT_REASON
271# undef EXIT_REASON_NIL
272#endif /* VBOX_WITH_STATISTICS */
273
274#define VMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
275 do { \
276 if ((allowed1) & (featflag)) \
277 LogRel(("HM: " #featflag "\n")); \
278 else \
279 LogRel(("HM: " #featflag " *must* be cleared\n")); \
280 if ((disallowed0) & (featflag)) \
281 LogRel(("HM: " #featflag " *must* be set\n")); \
282 } while(0)
283
284#define VMX_REPORT_CAPABILITY(msrcaps, cap) \
285 do { \
286 if ((msrcaps) & (cap)) \
287 LogRel(("HM: " #cap "\n")); \
288 } while(0)
289
290/*******************************************************************************
291* Internal Functions *
292*******************************************************************************/
293static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
294static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
295static int hmR3InitCPU(PVM pVM);
296static int hmR3InitFinalizeR0(PVM pVM);
297static int hmR3TermCPU(PVM pVM);
298
299
300/**
301 * Initializes the HM.
302 *
303 * @returns VBox status code.
304 * @param pVM Pointer to the VM.
305 */
306VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
307{
308 LogFlow(("HMR3Init\n"));
309
310 /*
311 * Assert alignment and sizes.
312 */
313 AssertCompileMemberAlignment(VM, hm.s, 32);
314 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
315
316 /* Some structure checks. */
317 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
318 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
319 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
320
321 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
322 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
323 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
324 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
325 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
326 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
327 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
328 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
329 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
330 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
331 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
332
333 /*
334 * Register the saved state data unit.
335 */
336 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
337 NULL, NULL, NULL,
338 NULL, hmR3Save, NULL,
339 NULL, hmR3Load, NULL);
340 if (RT_FAILURE(rc))
341 return rc;
342
343 /* Misc initialisation. */
344 pVM->hm.s.vmx.fSupported = false;
345 pVM->hm.s.svm.fSupported = false;
346 pVM->hm.s.vmx.fEnabled = false;
347 pVM->hm.s.svm.fEnabled = false;
348
349 pVM->hm.s.fNestedPaging = false;
350 pVM->hm.s.fLargePages = false;
351
352 /* Disabled by default. */
353 pVM->fHMEnabled = false;
354
355 /*
356 * Check CFGM options.
357 */
358 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
359 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
360 /* Nested paging: disabled by default. */
361 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
362 AssertRC(rc);
363
364 /* Large pages: disabled by default. */
365 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
366 AssertRC(rc);
367
368 /* VT-x VPID: disabled by default. */
369 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
370 AssertRC(rc);
371
372 /* HM support must be explicitely enabled in the configuration file. */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
374 AssertRC(rc);
375
376 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
377 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
378 AssertRC(rc);
379
380#ifdef RT_OS_DARWIN
381 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
382#else
383 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
384#endif
385 {
386 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
387 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
388 return VERR_HM_CONFIG_MISMATCH;
389 }
390
391 if (VMMIsHwVirtExtForced(pVM))
392 pVM->fHMEnabled = true;
393
394#if HC_ARCH_BITS == 32
395 /*
396 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
397 * (To use the default, don't set 64bitEnabled in CFGM.)
398 */
399 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
400 AssertLogRelRCReturn(rc, rc);
401 if (pVM->hm.s.fAllow64BitGuests)
402 {
403# ifdef RT_OS_DARWIN
404 if (!VMMIsHwVirtExtForced(pVM))
405# else
406 if (!pVM->hm.s.fAllowed)
407# endif
408 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
409 }
410#else
411 /*
412 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
413 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
414 */
415 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
416 AssertLogRelRCReturn(rc, rc);
417#endif
418
419
420 /*
421 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
422 * or local init each time we wish to execute guest code.
423 *
424 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
425 */
426 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
427#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
428 false
429#else
430 true
431#endif
432 );
433
434 /* Max number of resume loops. */
435 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
436 AssertRC(rc);
437
438 return rc;
439}
440
441
442/**
443 * Initializes the per-VCPU HM.
444 *
445 * @returns VBox status code.
446 * @param pVM Pointer to the VM.
447 */
448static int hmR3InitCPU(PVM pVM)
449{
450 LogFlow(("HMR3InitCPU\n"));
451
452 for (VMCPUID i = 0; i < pVM->cCpus; i++)
453 {
454 PVMCPU pVCpu = &pVM->aCpus[i];
455
456 pVCpu->hm.s.fActive = false;
457 }
458
459#ifdef VBOX_WITH_STATISTICS
460 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
461 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
462 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
463 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
464
465 /*
466 * Statistics.
467 */
468 for (VMCPUID i = 0; i < pVM->cCpus; i++)
469 {
470 PVMCPU pVCpu = &pVM->aCpus[i];
471 int rc;
472
473 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
474 "Profiling of RTMpPokeCpu",
475 "/PROF/HM/CPU%d/Poke", i);
476 AssertRC(rc);
477 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
478 "Profiling of poke wait",
479 "/PROF/HM/CPU%d/PokeWait", i);
480 AssertRC(rc);
481 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
482 "Profiling of poke wait when RTMpPokeCpu fails",
483 "/PROF/HM/CPU%d/PokeWaitFailed", i);
484 AssertRC(rc);
485 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
486 "Profiling of VMXR0RunGuestCode entry",
487 "/PROF/HM/CPU%d/SwitchToGC", i);
488 AssertRC(rc);
489 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
490 "Profiling of VMXR0RunGuestCode exit part 1",
491 "/PROF/HM/CPU%d/SwitchFromGC_1", i);
492 AssertRC(rc);
493 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
494 "Profiling of VMXR0RunGuestCode exit part 2",
495 "/PROF/HM/CPU%d/SwitchFromGC_2", i);
496 AssertRC(rc);
497# if 1 /* temporary for tracking down darwin holdup. */
498 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
499 "Temporary - I/O",
500 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub1", i);
501 AssertRC(rc);
502 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
503 "Temporary - CRx RWs",
504 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub2", i);
505 AssertRC(rc);
506 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
507 "Temporary - Exceptions",
508 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub3", i);
509 AssertRC(rc);
510# endif
511 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
512 "Profiling of vmlaunch",
513 "/PROF/HM/CPU%d/InGC", i);
514 AssertRC(rc);
515
516# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
517 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
518 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
519 "/PROF/HM/CPU%d/Switcher3264", i);
520 AssertRC(rc);
521# endif
522
523# define HM_REG_COUNTER(a, b) \
524 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
525 AssertRC(rc);
526
527 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
528 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
529 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
530 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
531 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
541 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
542 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
544 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd");
545 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
548 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
549 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand");
551 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
552 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
554 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
555 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
558 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW");
559 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
560 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
561 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
562 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
563 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
564 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
566 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess");
567 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
568 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
571 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow");
572 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
573 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptPending, "/HM/CPU%d/Exit/PreemptPending");
574 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer");
575 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold");
576 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch");
577 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
578 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess");
579
580 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
581 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF");
582 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchToR3, "/HM/CPU%d/Switch/ToR3");
583
584 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
585 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
586 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
587
588 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
589 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
590 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
591 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
592 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
593 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Switch");
594 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
595 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
596 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
597 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt");
598 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys");
599 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
600 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
601
602 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
603 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
604 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
605
606 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
607 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
608 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
609
610 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
611 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
612
613#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
614 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
615 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
616#endif
617
618 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
619 {
620 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
621 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
622 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
623 AssertRC(rc);
624 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
625 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
626 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
627 AssertRC(rc);
628 }
629
630#undef HM_REG_COUNTER
631
632 pVCpu->hm.s.paStatExitReason = NULL;
633
634 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
635 (void **)&pVCpu->hm.s.paStatExitReason);
636 AssertRC(rc);
637 if (RT_SUCCESS(rc))
638 {
639 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
640 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
641 {
642 if (papszDesc[j])
643 {
644 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
645 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
646 AssertRC(rc);
647 }
648 }
649 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
650 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
651 AssertRC(rc);
652 }
653 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
654# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
655 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
656# else
657 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
658# endif
659
660 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
661 AssertRCReturn(rc, rc);
662 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
663# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
664 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
665# else
666 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
667# endif
668 for (unsigned j = 0; j < 255; j++)
669 {
670 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
671 "Forwarded interrupts.",
672 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
673 }
674
675 }
676#endif /* VBOX_WITH_STATISTICS */
677
678#ifdef VBOX_WITH_CRASHDUMP_MAGIC
679 /* Magic marker for searching in crash dumps. */
680 for (VMCPUID i = 0; i < pVM->cCpus; i++)
681 {
682 PVMCPU pVCpu = &pVM->aCpus[i];
683
684 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
685 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
686 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
687 }
688#endif
689 return VINF_SUCCESS;
690}
691
692
693/**
694 * Called when a init phase has completed.
695 *
696 * @returns VBox status code.
697 * @param pVM The VM.
698 * @param enmWhat The phase that completed.
699 */
700VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
701{
702 switch (enmWhat)
703 {
704 case VMINITCOMPLETED_RING3:
705 return hmR3InitCPU(pVM);
706 case VMINITCOMPLETED_RING0:
707 return hmR3InitFinalizeR0(pVM);
708 default:
709 return VINF_SUCCESS;
710 }
711}
712
713
714/**
715 * Turns off normal raw mode features.
716 *
717 * @param pVM Pointer to the VM.
718 */
719static void hmR3DisableRawMode(PVM pVM)
720{
721 /* Disable PATM & CSAM. */
722 PATMR3AllowPatching(pVM->pUVM, false);
723 CSAMDisableScanning(pVM);
724
725 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
726 SELMR3DisableMonitoring(pVM);
727 TRPMR3DisableMonitoring(pVM);
728
729 /* Disable the switcher code (safety precaution). */
730 VMMR3DisableSwitcher(pVM);
731
732 /* Disable mapping of the hypervisor into the shadow page table. */
733 PGMR3MappingsDisable(pVM);
734
735 /* Disable the switcher */
736 VMMR3DisableSwitcher(pVM);
737
738 /* Reinit the paging mode to force the new shadow mode. */
739 for (VMCPUID i = 0; i < pVM->cCpus; i++)
740 {
741 PVMCPU pVCpu = &pVM->aCpus[i];
742
743 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
744 }
745}
746
747
748/**
749 * Initialize VT-x or AMD-V.
750 *
751 * @returns VBox status code.
752 * @param pVM Pointer to the VM.
753 */
754static int hmR3InitFinalizeR0(PVM pVM)
755{
756 int rc;
757
758 /*
759 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
760 * is already using AMD-V.
761 */
762 if ( !pVM->hm.s.vmx.fSupported
763 && !pVM->hm.s.svm.fSupported
764 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
765 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
766 {
767 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
768 pVM->hm.s.svm.fSupported = true;
769 pVM->hm.s.svm.fIgnoreInUseError = true;
770 }
771 else
772 if ( !pVM->hm.s.vmx.fSupported
773 && !pVM->hm.s.svm.fSupported)
774 {
775 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
776 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
777
778 if (VMMIsHwVirtExtForced(pVM))
779 {
780 switch (pVM->hm.s.lLastError)
781 {
782 case VERR_VMX_NO_VMX:
783 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
784 case VERR_VMX_IN_VMX_ROOT_MODE:
785 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
786 case VERR_SVM_IN_USE:
787 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
788 case VERR_SVM_NO_SVM:
789 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
790 case VERR_SVM_DISABLED:
791 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
792 default:
793 return pVM->hm.s.lLastError;
794 }
795 }
796 return VINF_SUCCESS;
797 }
798
799 if (pVM->hm.s.vmx.fSupported)
800 {
801 rc = SUPR3QueryVTxSupported();
802 if (RT_FAILURE(rc))
803 {
804#ifdef RT_OS_LINUX
805 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
806#else
807 LogRel(("HM: The host kernel does not support VT-x!\n"));
808#endif
809 if ( pVM->cCpus > 1
810 || VMMIsHwVirtExtForced(pVM))
811 return rc;
812
813 /* silently fall back to raw mode */
814 return VINF_SUCCESS;
815 }
816 }
817
818 if (!pVM->hm.s.fAllowed)
819 return VINF_SUCCESS; /* nothing to do */
820
821 /* Enable VT-x or AMD-V on all host CPUs. */
822 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
823 if (RT_FAILURE(rc))
824 {
825 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
826 return rc;
827 }
828 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
829
830 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
831 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
832 if (!pVM->hm.s.fHasIoApic)
833 {
834 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
835 pVM->hm.s.fTRPPatchingAllowed = false;
836 }
837
838 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
839 if (pVM->hm.s.vmx.fSupported)
840 {
841 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
842
843 if ( pVM->hm.s.fInitialized == false
844 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
845 {
846 uint64_t val;
847 uint64_t zap;
848 RTGCPHYS GCPhys = 0;
849
850 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
851 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
852 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
853 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
854 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
855 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
856 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
857 LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
858 LogRel(("HM: Max resume loops = %RX32\n", pVM->hm.s.cMaxResumeLoops));
859
860 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
861 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
862 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
863 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT);
864 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT);
865 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI);
866 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER);
867
868 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
869 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
870 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
871 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT);
872 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TSC_OFFSETTING);
873 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT);
874 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT);
875 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT);
876 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT);
877 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT);
878 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT);
879 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
880 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT);
881 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT);
882 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW);
883 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT);
884 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
885 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT);
886 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS);
887 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG);
888 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS);
889 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT);
890 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT);
891 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
892 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
893 {
894 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
895 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
896 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
897 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
898 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
899 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
900 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
901 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
902 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
903 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
904 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
905 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
906 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
907 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
908 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
909 }
910
911 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
912 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
913 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
914 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG);
915 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST);
916 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM);
917 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON);
918 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR);
919 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR);
920 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR);
921
922 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
923 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
924 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
925 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG);
926 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE);
927 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR);
928 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT);
929 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR);
930 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR);
931 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR);
932 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR);
933 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER);
934
935 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
936 {
937 val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
938 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", val));
939 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
940 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
941 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
942 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
943 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
944 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
945 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
946 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
947 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
948 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
949 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
950 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
951 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
952 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
953 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
954 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
955 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
956 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
957 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
958 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
959 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
960 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
961 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
962 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
963 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
964 }
965
966 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
967 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
968 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
969 else
970 {
971 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
972 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
973 }
974
975 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
976 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
977 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
978 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
979
980 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
981 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
982 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
983 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
984 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
985
986 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
987
988 /* Paranoia */
989 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
990
991 for (VMCPUID i = 0; i < pVM->cCpus; i++)
992 {
993 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
994 LogRel(("HM: VCPU%3d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
995 }
996
997 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
998 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
999
1000 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1001 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1002
1003 /*
1004 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1005 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1006 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1007 */
1008 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1009 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1010 {
1011 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1012 LogRel(("HM: Disabled RDTSCP\n"));
1013 }
1014
1015 /* Unrestricted guest execution relies on EPT. */
1016 if ( pVM->hm.s.fNestedPaging
1017 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1018 {
1019 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1020 }
1021
1022 /* Only try once. */
1023 pVM->hm.s.fInitialized = true;
1024
1025 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1026 {
1027 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1028 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1029 if (RT_SUCCESS(rc))
1030 {
1031 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1032 /* Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode" esp. Figure 20-5.*/
1033 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1034 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1035 /* Bit set to 0 means software interrupts are redirected to the 8086 program interrupt handler rather than
1036 switching to protected-mode handler. */
1037 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1038 /* Allow all port IO, so that port IO instructions do not cause exceptions and would instead
1039 cause a VM-exit (based on VT-x's IO bitmap which we currently configure to always cause an exit). */
1040 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1041 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1042
1043 /*
1044 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1045 * real and protected mode without paging with EPT.
1046 */
1047 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1048 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1049 {
1050 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1051 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1052 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1053 | X86_PDE4M_G;
1054 }
1055
1056 /* We convert it here every time as pci regions could be reconfigured. */
1057 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1058 AssertRC(rc);
1059 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1060
1061 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1062 AssertRC(rc);
1063 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1064 }
1065 else
1066 {
1067 /** @todo This cannot possibly work, there are other places which assumes
1068 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1069 * a failure case. */
1070 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1071 pVM->hm.s.vmx.pRealModeTSS = NULL;
1072 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1073 }
1074 }
1075
1076 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1077 AssertRC(rc);
1078 if (rc == VINF_SUCCESS)
1079 {
1080 pVM->fHMEnabled = true;
1081 pVM->hm.s.vmx.fEnabled = true;
1082 hmR3DisableRawMode(pVM);
1083
1084 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1085#ifdef VBOX_ENABLE_64_BITS_GUESTS
1086 if (pVM->hm.s.fAllow64BitGuests)
1087 {
1088 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1089 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1090 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1091 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1092 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1093# if RT_ARCH_X86
1094 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1095 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1096 LogRel(("NX is only supported for 64-bit guests!\n"));
1097# endif
1098 }
1099 else
1100 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1101 /* Todo: this needs to be fixed properly!! */
1102 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1103 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1104 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1105 else
1106 LogRel(("HM: NX not supported by the host\n"));
1107
1108 LogRel((pVM->hm.s.fAllow64BitGuests
1109 ? "HM: 32-bit and 64-bit guests supported.\n"
1110 : "HM: 32-bit guests supported.\n"));
1111#else
1112 LogRel(("HM: 32-bit guests supported.\n"));
1113#endif
1114 LogRel(("HM: VMX enabled!\n"));
1115 if (pVM->hm.s.fNestedPaging)
1116 {
1117 LogRel(("HM: Nested paging enabled!\n"));
1118 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1119 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1120 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1121 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1122 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1123 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1124 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1125 else
1126 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1127
1128 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1129 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1130
1131#if HC_ARCH_BITS == 64
1132 if (pVM->hm.s.fLargePages)
1133 {
1134 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1135 PGMSetLargePageUsage(pVM, true);
1136 LogRel(("HM: Large page support enabled!\n"));
1137 }
1138#endif
1139 }
1140 else
1141 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1142
1143 if (pVM->hm.s.vmx.fVpid)
1144 {
1145 LogRel(("HM: VPID enabled!\n"));
1146 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1147 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1148 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1149 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1150 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1151 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1152 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1153 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1154 else
1155 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1156 }
1157 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1158 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1159
1160 /* TPR patching status logging. */
1161 if (pVM->hm.s.fTRPPatchingAllowed)
1162 {
1163 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1164 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1165 {
1166 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1167 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1168 }
1169 else
1170 {
1171 uint32_t u32Eax, u32Dummy;
1172
1173 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1174 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1175 if ( u32Eax < 0x80000001
1176 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1177 {
1178 pVM->hm.s.fTRPPatchingAllowed = false;
1179 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1180 }
1181 }
1182 }
1183 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1184
1185 /*
1186 * Check for preemption timer config override and log the state of it.
1187 */
1188 if (pVM->hm.s.vmx.fUsePreemptTimer)
1189 {
1190 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1191 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1192 AssertLogRelRC(rc2);
1193 }
1194 if (pVM->hm.s.vmx.fUsePreemptTimer)
1195 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1196 }
1197 else
1198 {
1199 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1200 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1201 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1202 pVM->fHMEnabled = false;
1203 }
1204 }
1205 }
1206 else
1207 if (pVM->hm.s.svm.fSupported)
1208 {
1209 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1210
1211 if (pVM->hm.s.fInitialized == false)
1212 {
1213 /* Erratum 170 which requires a forced TLB flush for each world switch:
1214 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1215 *
1216 * All BH-G1/2 and DH-G1/2 models include a fix:
1217 * Athlon X2: 0x6b 1/2
1218 * 0x68 1/2
1219 * Athlon 64: 0x7f 1
1220 * 0x6f 2
1221 * Sempron: 0x7f 1/2
1222 * 0x6f 2
1223 * 0x6c 2
1224 * 0x7c 2
1225 * Turion 64: 0x68 2
1226 *
1227 */
1228 uint32_t u32Dummy;
1229 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1230 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1231 u32BaseFamily= (u32Version >> 8) & 0xf;
1232 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1233 u32Model = ((u32Version >> 4) & 0xf);
1234 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1235 u32Stepping = u32Version & 0xf;
1236 if ( u32Family == 0xf
1237 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1238 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1239 {
1240 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1241 }
1242
1243 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1244 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1245 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1246 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1247 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1248 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1249 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1250 {
1251#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1252 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1253 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1254 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1255 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1256 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1257 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1258 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1259 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1260 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1261 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1262 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1263#undef FLAG_NAME
1264 };
1265 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1266 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1267 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1268 {
1269 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1270 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1271 }
1272 if (fSvmFeatures)
1273 for (unsigned iBit = 0; iBit < 32; iBit++)
1274 if (RT_BIT_32(iBit) & fSvmFeatures)
1275 LogRel(("HM: Reserved bit %u\n", iBit));
1276
1277 /* Only try once. */
1278 pVM->hm.s.fInitialized = true;
1279
1280 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1281 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1282
1283 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1284 AssertRC(rc);
1285 if (rc == VINF_SUCCESS)
1286 {
1287 pVM->fHMEnabled = true;
1288 pVM->hm.s.svm.fEnabled = true;
1289
1290 if (pVM->hm.s.fNestedPaging)
1291 {
1292 LogRel(("HM: Enabled nested paging!\n"));
1293#if HC_ARCH_BITS == 64
1294 if (pVM->hm.s.fLargePages)
1295 {
1296 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1297 PGMSetLargePageUsage(pVM, true);
1298 LogRel(("HM: Large page support enabled!\n"));
1299 }
1300#endif
1301 }
1302
1303 hmR3DisableRawMode(pVM);
1304 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1305 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1306#ifdef VBOX_ENABLE_64_BITS_GUESTS
1307 if (pVM->hm.s.fAllow64BitGuests)
1308 {
1309 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1310 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1311 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1312 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1313 }
1314 else
1315 /* Turn on NXE if PAE has been enabled. */
1316 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1317 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1318#endif
1319
1320 LogRel((pVM->hm.s.fAllow64BitGuests
1321 ? "HM: 32-bit and 64-bit guest supported.\n"
1322 : "HM: 32-bit guest supported.\n"));
1323
1324 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1325 }
1326 else
1327 {
1328 pVM->fHMEnabled = false;
1329 }
1330 }
1331 }
1332 if (pVM->fHMEnabled)
1333 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1334 RTLogRelSetBuffering(fOldBuffered);
1335 return VINF_SUCCESS;
1336}
1337
1338
1339/**
1340 * Applies relocations to data and code managed by this
1341 * component. This function will be called at init and
1342 * whenever the VMM need to relocate it self inside the GC.
1343 *
1344 * @param pVM The VM.
1345 */
1346VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1347{
1348 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1349
1350 /* Fetch the current paging mode during the relocate callback during state loading. */
1351 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1352 {
1353 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1354 {
1355 PVMCPU pVCpu = &pVM->aCpus[i];
1356
1357 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1358 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1359 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1360 }
1361 }
1362#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1363 if (pVM->fHMEnabled)
1364 {
1365 int rc;
1366 switch (PGMGetHostMode(pVM))
1367 {
1368 case PGMMODE_32_BIT:
1369 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1370 break;
1371
1372 case PGMMODE_PAE:
1373 case PGMMODE_PAE_NX:
1374 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1375 break;
1376
1377 default:
1378 AssertFailed();
1379 break;
1380 }
1381 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1382 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1383
1384 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1385 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1386
1387 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1388 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1389
1390 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1391 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1392
1393# ifdef DEBUG
1394 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1395 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1396# endif
1397 }
1398#endif
1399 return;
1400}
1401
1402
1403/**
1404 * Checks if hardware accelerated raw mode is allowed.
1405 *
1406 * @returns true if hardware acceleration is allowed, otherwise false.
1407 * @param pVM Pointer to the VM.
1408 */
1409VMMR3_INT_DECL(bool) HMR3IsAllowed(PVM pVM)
1410{
1411 return pVM->hm.s.fAllowed;
1412}
1413
1414
1415/**
1416 * Notification callback which is called whenever there is a chance that a CR3
1417 * value might have changed.
1418 *
1419 * This is called by PGM.
1420 *
1421 * @param pVM Pointer to the VM.
1422 * @param pVCpu Pointer to the VMCPU.
1423 * @param enmShadowMode New shadow paging mode.
1424 * @param enmGuestMode New guest paging mode.
1425 */
1426VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1427{
1428 /* Ignore page mode changes during state loading. */
1429 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1430 return;
1431
1432 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1433
1434#ifdef VBOX_WITH_OLD_VTX_CODE
1435 if ( pVM->hm.s.vmx.fEnabled
1436 && pVM->fHMEnabled)
1437 {
1438 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1439 && enmGuestMode >= PGMMODE_PROTECTED)
1440 {
1441 PCPUMCTX pCtx;
1442
1443 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1444
1445 /* After a real mode switch to protected mode we must force
1446 CPL to 0. Our real mode emulation had to set it to 3. */
1447 pCtx->ss.Attr.n.u2Dpl = 0;
1448 }
1449 }
1450#endif
1451
1452 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1453 {
1454 /* Keep track of paging mode changes. */
1455 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1456 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1457
1458 /* Did we miss a change, because all code was executed in the recompiler? */
1459 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1460 {
1461 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1462 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1463 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1464 }
1465 }
1466
1467 /** @todo r=ramshankar: Why do we need to do this? Most likely
1468 * VBOX_WITH_OLD_VTX_CODE only. */
1469 /* Reset the contents of the read cache. */
1470 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1471 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1472 pCache->Read.aFieldVal[j] = 0;
1473}
1474
1475
1476/**
1477 * Terminates the HM.
1478 *
1479 * Termination means cleaning up and freeing all resources,
1480 * the VM itself is, at this point, powered off or suspended.
1481 *
1482 * @returns VBox status code.
1483 * @param pVM Pointer to the VM.
1484 */
1485VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1486{
1487 if (pVM->hm.s.vmx.pRealModeTSS)
1488 {
1489 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1490 pVM->hm.s.vmx.pRealModeTSS = 0;
1491 }
1492 hmR3TermCPU(pVM);
1493 return 0;
1494}
1495
1496
1497/**
1498 * Terminates the per-VCPU HM.
1499 *
1500 * @returns VBox status code.
1501 * @param pVM Pointer to the VM.
1502 */
1503static int hmR3TermCPU(PVM pVM)
1504{
1505 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1506 {
1507 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1508
1509#ifdef VBOX_WITH_STATISTICS
1510 if (pVCpu->hm.s.paStatExitReason)
1511 {
1512 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1513 pVCpu->hm.s.paStatExitReason = NULL;
1514 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1515 }
1516 if (pVCpu->hm.s.paStatInjectedIrqs)
1517 {
1518 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1519 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1520 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1521 }
1522#endif
1523
1524#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1525 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1526 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1527 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1528#endif
1529 }
1530 return 0;
1531}
1532
1533
1534/**
1535 * Resets a virtual CPU.
1536 *
1537 * Used by HMR3Reset and CPU hot plugging.
1538 *
1539 * @param pVCpu The CPU to reset.
1540 */
1541VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1542{
1543 /* On first entry we'll sync everything. */
1544 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1545
1546 pVCpu->hm.s.vmx.cr0_mask = 0;
1547 pVCpu->hm.s.vmx.cr4_mask = 0;
1548
1549 pVCpu->hm.s.fActive = false;
1550 pVCpu->hm.s.Event.fPending = false;
1551
1552 /* Reset state information for real-mode emulation in VT-x. */
1553 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1554 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1555 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1556
1557 /* Reset the contents of the read cache. */
1558 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1559 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1560 pCache->Read.aFieldVal[j] = 0;
1561
1562#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1563 /* Magic marker for searching in crash dumps. */
1564 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1565 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1566#endif
1567}
1568
1569
1570/**
1571 * The VM is being reset.
1572 *
1573 * For the HM component this means that any GDT/LDT/TSS monitors
1574 * needs to be removed.
1575 *
1576 * @param pVM Pointer to the VM.
1577 */
1578VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1579{
1580 LogFlow(("HMR3Reset:\n"));
1581
1582 if (pVM->fHMEnabled)
1583 hmR3DisableRawMode(pVM);
1584
1585 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1586 {
1587 PVMCPU pVCpu = &pVM->aCpus[i];
1588
1589 HMR3ResetCpu(pVCpu);
1590 }
1591
1592 /* Clear all patch information. */
1593 pVM->hm.s.pGuestPatchMem = 0;
1594 pVM->hm.s.pFreeGuestPatchMem = 0;
1595 pVM->hm.s.cbGuestPatchMem = 0;
1596 pVM->hm.s.cPatches = 0;
1597 pVM->hm.s.PatchTree = 0;
1598 pVM->hm.s.fTPRPatchingActive = false;
1599 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1600}
1601
1602
1603/**
1604 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1605 *
1606 * @returns VBox strict status code.
1607 * @param pVM Pointer to the VM.
1608 * @param pVCpu The VMCPU for the EMT we're being called on.
1609 * @param pvUser Unused.
1610 */
1611DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1612{
1613 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1614
1615 /* Only execute the handler on the VCPU the original patch request was issued. */
1616 if (pVCpu->idCpu != idCpu)
1617 return VINF_SUCCESS;
1618
1619 Log(("hmR3RemovePatches\n"));
1620 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1621 {
1622 uint8_t abInstr[15];
1623 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1624 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1625 int rc;
1626
1627#ifdef LOG_ENABLED
1628 char szOutput[256];
1629
1630 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1631 szOutput, sizeof(szOutput), NULL);
1632 if (RT_SUCCESS(rc))
1633 Log(("Patched instr: %s\n", szOutput));
1634#endif
1635
1636 /* Check if the instruction is still the same. */
1637 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1638 if (rc != VINF_SUCCESS)
1639 {
1640 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1641 continue; /* swapped out or otherwise removed; skip it. */
1642 }
1643
1644 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1645 {
1646 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1647 continue; /* skip it. */
1648 }
1649
1650 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1651 AssertRC(rc);
1652
1653#ifdef LOG_ENABLED
1654 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1655 szOutput, sizeof(szOutput), NULL);
1656 if (RT_SUCCESS(rc))
1657 Log(("Original instr: %s\n", szOutput));
1658#endif
1659 }
1660 pVM->hm.s.cPatches = 0;
1661 pVM->hm.s.PatchTree = 0;
1662 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1663 pVM->hm.s.fTPRPatchingActive = false;
1664 return VINF_SUCCESS;
1665}
1666
1667
1668/**
1669 * Worker for enabling patching in a VT-x/AMD-V guest.
1670 *
1671 * @returns VBox status code.
1672 * @param pVM Pointer to the VM.
1673 * @param idCpu VCPU to execute hmR3RemovePatches on.
1674 * @param pPatchMem Patch memory range.
1675 * @param cbPatchMem Size of the memory range.
1676 */
1677static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1678{
1679 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1680 AssertRC(rc);
1681
1682 pVM->hm.s.pGuestPatchMem = pPatchMem;
1683 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1684 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1685 return VINF_SUCCESS;
1686}
1687
1688
1689/**
1690 * Enable patching in a VT-x/AMD-V guest
1691 *
1692 * @returns VBox status code.
1693 * @param pVM Pointer to the VM.
1694 * @param pPatchMem Patch memory range.
1695 * @param cbPatchMem Size of the memory range.
1696 */
1697VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1698{
1699 VM_ASSERT_EMT(pVM);
1700 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1701 if (pVM->cCpus > 1)
1702 {
1703 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1704 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1705 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1706 AssertRC(rc);
1707 return rc;
1708 }
1709 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1710}
1711
1712
1713/**
1714 * Disable patching in a VT-x/AMD-V guest.
1715 *
1716 * @returns VBox status code.
1717 * @param pVM Pointer to the VM.
1718 * @param pPatchMem Patch memory range.
1719 * @param cbPatchMem Size of the memory range.
1720 */
1721VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1722{
1723 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1724
1725 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1726 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1727
1728 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1729 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1730 (void *)(uintptr_t)VMMGetCpuId(pVM));
1731 AssertRC(rc);
1732
1733 pVM->hm.s.pGuestPatchMem = 0;
1734 pVM->hm.s.pFreeGuestPatchMem = 0;
1735 pVM->hm.s.cbGuestPatchMem = 0;
1736 pVM->hm.s.fTPRPatchingActive = false;
1737 return VINF_SUCCESS;
1738}
1739
1740
1741/**
1742 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1743 *
1744 * @returns VBox strict status code.
1745 * @param pVM Pointer to the VM.
1746 * @param pVCpu The VMCPU for the EMT we're being called on.
1747 * @param pvUser User specified CPU context.
1748 *
1749 */
1750DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1751{
1752 /*
1753 * Only execute the handler on the VCPU the original patch request was
1754 * issued. (The other CPU(s) might not yet have switched to protected
1755 * mode, nor have the correct memory context.)
1756 */
1757 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1758 if (pVCpu->idCpu != idCpu)
1759 return VINF_SUCCESS;
1760
1761 /*
1762 * We're racing other VCPUs here, so don't try patch the instruction twice
1763 * and make sure there is still room for our patch record.
1764 */
1765 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1766 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1767 if (pPatch)
1768 {
1769 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1770 return VINF_SUCCESS;
1771 }
1772 uint32_t const idx = pVM->hm.s.cPatches;
1773 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1774 {
1775 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1776 return VINF_SUCCESS;
1777 }
1778 pPatch = &pVM->hm.s.aPatches[idx];
1779
1780 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1781
1782 /*
1783 * Disassembler the instruction and get cracking.
1784 */
1785 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1786 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1787 uint32_t cbOp;
1788 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1789 AssertRC(rc);
1790 if ( rc == VINF_SUCCESS
1791 && pDis->pCurInstr->uOpcode == OP_MOV
1792 && cbOp >= 3)
1793 {
1794 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1795
1796 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1797 AssertRC(rc);
1798
1799 pPatch->cbOp = cbOp;
1800
1801 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1802 {
1803 /* write. */
1804 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1805 {
1806 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1807 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1808 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1809 }
1810 else
1811 {
1812 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1813 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1814 pPatch->uSrcOperand = pDis->Param2.uValue;
1815 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1816 }
1817 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1818 AssertRC(rc);
1819
1820 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1821 pPatch->cbNewOp = sizeof(s_abVMMCall);
1822 }
1823 else
1824 {
1825 /*
1826 * TPR Read.
1827 *
1828 * Found:
1829 * mov eax, dword [fffe0080] (5 bytes)
1830 * Check if next instruction is:
1831 * shr eax, 4
1832 */
1833 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1834
1835 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1836 uint8_t const cbOpMmio = cbOp;
1837 uint64_t const uSavedRip = pCtx->rip;
1838
1839 pCtx->rip += cbOp;
1840 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1841 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1842 pCtx->rip = uSavedRip;
1843
1844 if ( rc == VINF_SUCCESS
1845 && pDis->pCurInstr->uOpcode == OP_SHR
1846 && pDis->Param1.fUse == DISUSE_REG_GEN32
1847 && pDis->Param1.Base.idxGenReg == idxMmioReg
1848 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1849 && pDis->Param2.uValue == 4
1850 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1851 {
1852 uint8_t abInstr[15];
1853
1854 /* Replacing two instructions now. */
1855 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1856 AssertRC(rc);
1857
1858 pPatch->cbOp = cbOpMmio + cbOp;
1859
1860 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1861 abInstr[0] = 0xF0;
1862 abInstr[1] = 0x0F;
1863 abInstr[2] = 0x20;
1864 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1865 for (unsigned i = 4; i < pPatch->cbOp; i++)
1866 abInstr[i] = 0x90; /* nop */
1867
1868 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1869 AssertRC(rc);
1870
1871 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1872 pPatch->cbNewOp = pPatch->cbOp;
1873
1874 Log(("Acceptable read/shr candidate!\n"));
1875 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1876 }
1877 else
1878 {
1879 pPatch->enmType = HMTPRINSTR_READ;
1880 pPatch->uDstOperand = idxMmioReg;
1881
1882 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1883 AssertRC(rc);
1884
1885 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1886 pPatch->cbNewOp = sizeof(s_abVMMCall);
1887 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1888 }
1889 }
1890
1891 pPatch->Core.Key = pCtx->eip;
1892 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1893 AssertRC(rc);
1894
1895 pVM->hm.s.cPatches++;
1896 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1897 return VINF_SUCCESS;
1898 }
1899
1900 /*
1901 * Save invalid patch, so we will not try again.
1902 */
1903 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1904 pPatch->Core.Key = pCtx->eip;
1905 pPatch->enmType = HMTPRINSTR_INVALID;
1906 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1907 AssertRC(rc);
1908 pVM->hm.s.cPatches++;
1909 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1910 return VINF_SUCCESS;
1911}
1912
1913
1914/**
1915 * Callback to patch a TPR instruction (jump to generated code).
1916 *
1917 * @returns VBox strict status code.
1918 * @param pVM Pointer to the VM.
1919 * @param pVCpu The VMCPU for the EMT we're being called on.
1920 * @param pvUser User specified CPU context.
1921 *
1922 */
1923DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1924{
1925 /*
1926 * Only execute the handler on the VCPU the original patch request was
1927 * issued. (The other CPU(s) might not yet have switched to protected
1928 * mode, nor have the correct memory context.)
1929 */
1930 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1931 if (pVCpu->idCpu != idCpu)
1932 return VINF_SUCCESS;
1933
1934 /*
1935 * We're racing other VCPUs here, so don't try patch the instruction twice
1936 * and make sure there is still room for our patch record.
1937 */
1938 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1939 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1940 if (pPatch)
1941 {
1942 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1943 return VINF_SUCCESS;
1944 }
1945 uint32_t const idx = pVM->hm.s.cPatches;
1946 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1947 {
1948 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1949 return VINF_SUCCESS;
1950 }
1951 pPatch = &pVM->hm.s.aPatches[idx];
1952
1953 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1954 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
1955
1956 /*
1957 * Disassemble the instruction and get cracking.
1958 */
1959 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1960 uint32_t cbOp;
1961 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1962 AssertRC(rc);
1963 if ( rc == VINF_SUCCESS
1964 && pDis->pCurInstr->uOpcode == OP_MOV
1965 && cbOp >= 5)
1966 {
1967 uint8_t aPatch[64];
1968 uint32_t off = 0;
1969
1970 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1971 AssertRC(rc);
1972
1973 pPatch->cbOp = cbOp;
1974 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
1975
1976 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1977 {
1978 /*
1979 * TPR write:
1980 *
1981 * push ECX [51]
1982 * push EDX [52]
1983 * push EAX [50]
1984 * xor EDX,EDX [31 D2]
1985 * mov EAX,EAX [89 C0]
1986 * or
1987 * mov EAX,0000000CCh [B8 CC 00 00 00]
1988 * mov ECX,0C0000082h [B9 82 00 00 C0]
1989 * wrmsr [0F 30]
1990 * pop EAX [58]
1991 * pop EDX [5A]
1992 * pop ECX [59]
1993 * jmp return_address [E9 return_address]
1994 *
1995 */
1996 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
1997
1998 aPatch[off++] = 0x51; /* push ecx */
1999 aPatch[off++] = 0x52; /* push edx */
2000 if (!fUsesEax)
2001 aPatch[off++] = 0x50; /* push eax */
2002 aPatch[off++] = 0x31; /* xor edx, edx */
2003 aPatch[off++] = 0xD2;
2004 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2005 {
2006 if (!fUsesEax)
2007 {
2008 aPatch[off++] = 0x89; /* mov eax, src_reg */
2009 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2010 }
2011 }
2012 else
2013 {
2014 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2015 aPatch[off++] = 0xB8; /* mov eax, immediate */
2016 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2017 off += sizeof(uint32_t);
2018 }
2019 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2020 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2021 off += sizeof(uint32_t);
2022
2023 aPatch[off++] = 0x0F; /* wrmsr */
2024 aPatch[off++] = 0x30;
2025 if (!fUsesEax)
2026 aPatch[off++] = 0x58; /* pop eax */
2027 aPatch[off++] = 0x5A; /* pop edx */
2028 aPatch[off++] = 0x59; /* pop ecx */
2029 }
2030 else
2031 {
2032 /*
2033 * TPR read:
2034 *
2035 * push ECX [51]
2036 * push EDX [52]
2037 * push EAX [50]
2038 * mov ECX,0C0000082h [B9 82 00 00 C0]
2039 * rdmsr [0F 32]
2040 * mov EAX,EAX [89 C0]
2041 * pop EAX [58]
2042 * pop EDX [5A]
2043 * pop ECX [59]
2044 * jmp return_address [E9 return_address]
2045 *
2046 */
2047 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2048
2049 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2050 aPatch[off++] = 0x51; /* push ecx */
2051 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2052 aPatch[off++] = 0x52; /* push edx */
2053 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2054 aPatch[off++] = 0x50; /* push eax */
2055
2056 aPatch[off++] = 0x31; /* xor edx, edx */
2057 aPatch[off++] = 0xD2;
2058
2059 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2060 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2061 off += sizeof(uint32_t);
2062
2063 aPatch[off++] = 0x0F; /* rdmsr */
2064 aPatch[off++] = 0x32;
2065
2066 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2067 {
2068 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2069 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2070 }
2071
2072 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2073 aPatch[off++] = 0x58; /* pop eax */
2074 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2075 aPatch[off++] = 0x5A; /* pop edx */
2076 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2077 aPatch[off++] = 0x59; /* pop ecx */
2078 }
2079 aPatch[off++] = 0xE9; /* jmp return_address */
2080 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2081 off += sizeof(RTRCUINTPTR);
2082
2083 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2084 {
2085 /* Write new code to the patch buffer. */
2086 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2087 AssertRC(rc);
2088
2089#ifdef LOG_ENABLED
2090 uint32_t cbCurInstr;
2091 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2092 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2093 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2094 {
2095 char szOutput[256];
2096 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2097 szOutput, sizeof(szOutput), &cbCurInstr);
2098 if (RT_SUCCESS(rc))
2099 Log(("Patch instr %s\n", szOutput));
2100 else
2101 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2102 }
2103#endif
2104
2105 pPatch->aNewOpcode[0] = 0xE9;
2106 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2107
2108 /* Overwrite the TPR instruction with a jump. */
2109 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2110 AssertRC(rc);
2111
2112 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2113
2114 pVM->hm.s.pFreeGuestPatchMem += off;
2115 pPatch->cbNewOp = 5;
2116
2117 pPatch->Core.Key = pCtx->eip;
2118 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2119 AssertRC(rc);
2120
2121 pVM->hm.s.cPatches++;
2122 pVM->hm.s.fTPRPatchingActive = true;
2123 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2124 return VINF_SUCCESS;
2125 }
2126
2127 Log(("Ran out of space in our patch buffer!\n"));
2128 }
2129 else
2130 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2131
2132
2133 /*
2134 * Save invalid patch, so we will not try again.
2135 */
2136 pPatch = &pVM->hm.s.aPatches[idx];
2137 pPatch->Core.Key = pCtx->eip;
2138 pPatch->enmType = HMTPRINSTR_INVALID;
2139 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2140 AssertRC(rc);
2141 pVM->hm.s.cPatches++;
2142 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2143 return VINF_SUCCESS;
2144}
2145
2146
2147/**
2148 * Attempt to patch TPR mmio instructions.
2149 *
2150 * @returns VBox status code.
2151 * @param pVM Pointer to the VM.
2152 * @param pVCpu Pointer to the VMCPU.
2153 * @param pCtx Pointer to the guest CPU context.
2154 */
2155VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2156{
2157 NOREF(pCtx);
2158 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2159 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2160 (void *)(uintptr_t)pVCpu->idCpu);
2161 AssertRC(rc);
2162 return rc;
2163}
2164
2165
2166/**
2167 * Force execution of the current IO code in the recompiler.
2168 *
2169 * @returns VBox status code.
2170 * @param pVM Pointer to the VM.
2171 * @param pCtx Partial VM execution context.
2172 */
2173VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2174{
2175 PVMCPU pVCpu = VMMGetCpu(pVM);
2176
2177 Assert(pVM->fHMEnabled);
2178 Log(("HMR3EmulateIoBlock\n"));
2179
2180 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2181 if (HMCanEmulateIoBlockEx(pCtx))
2182 {
2183 Log(("HMR3EmulateIoBlock -> enabled\n"));
2184 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2185 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2186 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2187 return VINF_EM_RESCHEDULE_REM;
2188 }
2189 return VINF_SUCCESS;
2190}
2191
2192
2193/**
2194 * Checks if we can currently use hardware accelerated raw mode.
2195 *
2196 * @returns true if we can currently use hardware acceleration, otherwise false.
2197 * @param pVM Pointer to the VM.
2198 * @param pCtx Partial VM execution context.
2199 */
2200VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2201{
2202 PVMCPU pVCpu = VMMGetCpu(pVM);
2203
2204 Assert(pVM->fHMEnabled);
2205
2206 /* If we're still executing the IO code, then return false. */
2207 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2208 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2209 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2210 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2211 return false;
2212
2213 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2214
2215 /* AMD-V supports real & protected mode with or without paging. */
2216 if (pVM->hm.s.svm.fEnabled)
2217 {
2218 pVCpu->hm.s.fActive = true;
2219 return true;
2220 }
2221
2222 pVCpu->hm.s.fActive = false;
2223
2224 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2225 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2226 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2227
2228 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2229 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2230 {
2231 /*
2232 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2233 * guest execution feature i missing (VT-x only).
2234 */
2235 if (fSupportsRealMode)
2236 {
2237 if (CPUMIsGuestInRealModeEx(pCtx))
2238 {
2239 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2240 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2241 * If this is not true, we cannot execute real mode as V86 and have to fall
2242 * back to emulation.
2243 */
2244 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2245 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2246 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2247 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2248 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2249 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2250 || (pCtx->cs.u32Limit != 0xffff)
2251 || (pCtx->ds.u32Limit != 0xffff)
2252 || (pCtx->es.u32Limit != 0xffff)
2253 || (pCtx->ss.u32Limit != 0xffff)
2254 || (pCtx->fs.u32Limit != 0xffff)
2255 || (pCtx->gs.u32Limit != 0xffff))
2256 {
2257 return false;
2258 }
2259 }
2260 else
2261 {
2262 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2263 /* Verify the requirements for executing code in protected
2264 mode. VT-x can't handle the CPU state right after a switch
2265 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2266 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2267 && enmGuestMode >= PGMMODE_PROTECTED)
2268 {
2269 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2270 || (pCtx->ds.Sel & X86_SEL_RPL)
2271 || (pCtx->es.Sel & X86_SEL_RPL)
2272 || (pCtx->fs.Sel & X86_SEL_RPL)
2273 || (pCtx->gs.Sel & X86_SEL_RPL)
2274 || (pCtx->ss.Sel & X86_SEL_RPL))
2275 {
2276 return false;
2277 }
2278 }
2279 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2280 if ( pCtx->gdtr.cbGdt
2281 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2282 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2283 {
2284 return false;
2285 }
2286 }
2287 }
2288 else
2289 {
2290 if ( !CPUMIsGuestInLongModeEx(pCtx)
2291 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2292 {
2293 /** @todo This should (probably) be set on every excursion to the REM,
2294 * however it's too risky right now. So, only apply it when we go
2295 * back to REM for real mode execution. (The XP hack below doesn't
2296 * work reliably without this.)
2297 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2298 for (uint32_t i = 0; i < pVM->cCpus; i++)
2299 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2300
2301 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2302 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2303 return false;
2304
2305 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2306 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2307 return false;
2308
2309 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2310 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2311 * hidden registers (possible recompiler bug; see load_seg_vm) */
2312 if (pCtx->cs.Attr.n.u1Present == 0)
2313 return false;
2314 if (pCtx->ss.Attr.n.u1Present == 0)
2315 return false;
2316
2317 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2318 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2319 /** @todo This check is actually wrong, it doesn't take the direction of the
2320 * stack segment into account. But, it does the job for now. */
2321 if (pCtx->rsp >= pCtx->ss.u32Limit)
2322 return false;
2323#if 0
2324 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2325 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2326 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2327 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2328 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2329 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2330 return false;
2331#endif
2332 }
2333 }
2334 }
2335
2336 if (pVM->hm.s.vmx.fEnabled)
2337 {
2338 uint32_t mask;
2339
2340 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2341 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2342 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2343 mask &= ~X86_CR0_NE;
2344
2345 if (fSupportsRealMode)
2346 {
2347 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2348 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2349 }
2350 else
2351 {
2352 /* We support protected mode without paging using identity mapping. */
2353 mask &= ~X86_CR0_PG;
2354 }
2355 if ((pCtx->cr0 & mask) != mask)
2356 return false;
2357
2358 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2359 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2360 if ((pCtx->cr0 & mask) != 0)
2361 return false;
2362
2363 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2364 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2365 mask &= ~X86_CR4_VMXE;
2366 if ((pCtx->cr4 & mask) != mask)
2367 return false;
2368
2369 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2370 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2371 if ((pCtx->cr4 & mask) != 0)
2372 return false;
2373
2374 pVCpu->hm.s.fActive = true;
2375 return true;
2376 }
2377
2378 return false;
2379}
2380
2381
2382/**
2383 * Checks if we need to reschedule due to VMM device heap changes.
2384 *
2385 * @returns true if a reschedule is required, otherwise false.
2386 * @param pVM Pointer to the VM.
2387 * @param pCtx VM execution context.
2388 */
2389VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2390{
2391 /*
2392 * The VMM device heap is a requirement for emulating real mode or protected mode without paging
2393 * when the unrestricted guest execution feature is missing (VT-x only).
2394 */
2395 if ( pVM->hm.s.vmx.fEnabled
2396 && !pVM->hm.s.vmx.fUnrestrictedGuest
2397 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2398 && !PDMVmmDevHeapIsEnabled(pVM)
2399 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2400 return true;
2401
2402 return false;
2403}
2404
2405
2406/**
2407 * Notification from EM about a rescheduling into hardware assisted execution
2408 * mode.
2409 *
2410 * @param pVCpu Pointer to the current VMCPU.
2411 */
2412VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2413{
2414 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2415}
2416
2417
2418/**
2419 * Notification from EM about returning from instruction emulation (REM / EM).
2420 *
2421 * @param pVCpu Pointer to the VMCPU.
2422 */
2423VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2424{
2425 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2426}
2427
2428
2429/**
2430 * Checks if we are currently using hardware accelerated raw mode.
2431 *
2432 * @returns true if hardware acceleration is being used, otherwise false.
2433 * @param pVCpu Pointer to the VMCPU.
2434 */
2435VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2436{
2437 return pVCpu->hm.s.fActive;
2438}
2439
2440
2441/**
2442 * Checks if we are currently using nested paging.
2443 *
2444 * @returns true if nested paging is being used, otherwise false.
2445 * @param pUVM The user mode VM handle.
2446 */
2447VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2448{
2449 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2450 PVM pVM = pUVM->pVM;
2451 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2452 return HMIsEnabled(pVM);
2453}
2454
2455
2456/**
2457 * Checks if we are currently using nested paging.
2458 *
2459 * @returns true if nested paging is being used, otherwise false.
2460 * @param pUVM The user mode VM handle.
2461 */
2462VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2463{
2464 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2465 PVM pVM = pUVM->pVM;
2466 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2467 return pVM->hm.s.fNestedPaging;
2468}
2469
2470
2471/**
2472 * Checks if we are currently using VPID in VT-x mode.
2473 *
2474 * @returns true if VPID is being used, otherwise false.
2475 * @param pUVM The user mode VM handle.
2476 */
2477VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2478{
2479 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2480 PVM pVM = pUVM->pVM;
2481 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2482 return pVM->hm.s.vmx.fVpid;
2483}
2484
2485
2486/**
2487 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2488 *
2489 * @returns true if an internal event is pending, otherwise false.
2490 * @param pVM Pointer to the VM.
2491 */
2492VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2493{
2494 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2495}
2496
2497
2498/**
2499 * Checks if the VMX-preemption timer is being used.
2500 *
2501 * @returns true if the VMX-preemption timer is being used, otherwise false.
2502 * @param pVM Pointer to the VM.
2503 */
2504VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2505{
2506 return HMIsEnabled(pVM)
2507 && pVM->hm.s.vmx.fEnabled
2508 && pVM->hm.s.vmx.fUsePreemptTimer;
2509}
2510
2511
2512/**
2513 * Restart an I/O instruction that was refused in ring-0
2514 *
2515 * @returns Strict VBox status code. Informational status codes other than the one documented
2516 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2517 * @retval VINF_SUCCESS Success.
2518 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2519 * status code must be passed on to EM.
2520 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2521 *
2522 * @param pVM Pointer to the VM.
2523 * @param pVCpu Pointer to the VMCPU.
2524 * @param pCtx Pointer to the guest CPU context.
2525 */
2526VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2527{
2528 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2529
2530 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2531
2532 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2533 || enmType == HMPENDINGIO_INVALID)
2534 return VERR_NOT_FOUND;
2535
2536 VBOXSTRICTRC rcStrict;
2537 switch (enmType)
2538 {
2539 case HMPENDINGIO_PORT_READ:
2540 {
2541 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2542 uint32_t u32Val = 0;
2543
2544 rcStrict = IOMIOPortRead(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2545 &u32Val,
2546 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2547 if (IOM_SUCCESS(rcStrict))
2548 {
2549 /* Write back to the EAX register. */
2550 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2551 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2552 }
2553 break;
2554 }
2555
2556 case HMPENDINGIO_PORT_WRITE:
2557 rcStrict = IOMIOPortWrite(pVM, pVCpu->hm.s.PendingIO.s.Port.uPort,
2558 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2559 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2560 if (IOM_SUCCESS(rcStrict))
2561 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2562 break;
2563
2564 default:
2565 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2566 }
2567
2568 return rcStrict;
2569}
2570
2571
2572/**
2573 * Check fatal VT-x/AMD-V error and produce some meaningful
2574 * log release message.
2575 *
2576 * @param pVM Pointer to the VM.
2577 * @param iStatusCode VBox status code.
2578 */
2579VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2580{
2581 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2582 {
2583 switch (iStatusCode)
2584 {
2585 case VERR_VMX_INVALID_VMCS_FIELD:
2586 break;
2587
2588 case VERR_VMX_INVALID_VMCS_PTR:
2589 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2590 LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2591 LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2592 LogRel(("HM: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2593 LogRel(("HM: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2594 break;
2595
2596 case VERR_VMX_UNABLE_TO_START_VM:
2597 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2598 LogRel(("HM: CPU%d instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2599 LogRel(("HM: CPU%d exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2600 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2601 {
2602 LogRel(("HM: Cpu%d PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2603 LogRel(("HM: Cpu%d ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2604 LogRel(("HM: Cpu%d ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2605 LogRel(("HM: Cpu%d EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2606 LogRel(("HM: Cpu%d ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2607 LogRel(("HM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2608#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2609 LogRel(("HM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2610 LogRel(("HM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2611 LogRel(("HM: Cpu%d cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2612#endif
2613 }
2614 /** @todo Log VM-entry event injection control fields
2615 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2616 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2617 break;
2618
2619 case VERR_VMX_UNABLE_TO_RESUME_VM:
2620 LogRel(("HM: VERR_VMX_UNABLE_TO_RESUME_VM:\n"));
2621 LogRel(("HM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2622 LogRel(("HM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2623 break;
2624
2625 case VERR_VMX_INVALID_VMXON_PTR:
2626 break;
2627 }
2628 }
2629
2630 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2631 {
2632 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2633 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2634 }
2635}
2636
2637
2638/**
2639 * Execute state save operation.
2640 *
2641 * @returns VBox status code.
2642 * @param pVM Pointer to the VM.
2643 * @param pSSM SSM operation handle.
2644 */
2645static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2646{
2647 int rc;
2648
2649 Log(("hmR3Save:\n"));
2650
2651 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2652 {
2653 /*
2654 * Save the basic bits - fortunately all the other things can be resynced on load.
2655 */
2656 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2657 AssertRCReturn(rc, rc);
2658 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2659 AssertRCReturn(rc, rc);
2660 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2661 AssertRCReturn(rc, rc);
2662
2663 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2664 AssertRCReturn(rc, rc);
2665 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2666 AssertRCReturn(rc, rc);
2667 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2668 AssertRCReturn(rc, rc);
2669 }
2670#ifdef VBOX_HM_WITH_GUEST_PATCHING
2671 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2672 AssertRCReturn(rc, rc);
2673 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2674 AssertRCReturn(rc, rc);
2675 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2676 AssertRCReturn(rc, rc);
2677
2678 /* Store all the guest patch records too. */
2679 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2680 AssertRCReturn(rc, rc);
2681
2682 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2683 {
2684 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2685
2686 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2687 AssertRCReturn(rc, rc);
2688
2689 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2690 AssertRCReturn(rc, rc);
2691
2692 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2693 AssertRCReturn(rc, rc);
2694
2695 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2696 AssertRCReturn(rc, rc);
2697
2698 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2699 AssertRCReturn(rc, rc);
2700
2701 AssertCompileSize(HMTPRINSTR, 4);
2702 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2703 AssertRCReturn(rc, rc);
2704
2705 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2706 AssertRCReturn(rc, rc);
2707
2708 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2709 AssertRCReturn(rc, rc);
2710
2711 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2712 AssertRCReturn(rc, rc);
2713
2714 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2715 AssertRCReturn(rc, rc);
2716 }
2717#endif
2718 return VINF_SUCCESS;
2719}
2720
2721
2722/**
2723 * Execute state load operation.
2724 *
2725 * @returns VBox status code.
2726 * @param pVM Pointer to the VM.
2727 * @param pSSM SSM operation handle.
2728 * @param uVersion Data layout version.
2729 * @param uPass The data pass.
2730 */
2731static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2732{
2733 int rc;
2734
2735 Log(("hmR3Load:\n"));
2736 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2737
2738 /*
2739 * Validate version.
2740 */
2741 if ( uVersion != HM_SSM_VERSION
2742 && uVersion != HM_SSM_VERSION_NO_PATCHING
2743 && uVersion != HM_SSM_VERSION_2_0_X)
2744 {
2745 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2746 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2747 }
2748 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2749 {
2750 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2751 AssertRCReturn(rc, rc);
2752 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
2753 AssertRCReturn(rc, rc);
2754 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2755 AssertRCReturn(rc, rc);
2756
2757 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2758 {
2759 uint32_t val;
2760
2761 rc = SSMR3GetU32(pSSM, &val);
2762 AssertRCReturn(rc, rc);
2763 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2764
2765 rc = SSMR3GetU32(pSSM, &val);
2766 AssertRCReturn(rc, rc);
2767 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2768
2769 rc = SSMR3GetU32(pSSM, &val);
2770 AssertRCReturn(rc, rc);
2771 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2772 }
2773 }
2774#ifdef VBOX_HM_WITH_GUEST_PATCHING
2775 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2776 {
2777 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2778 AssertRCReturn(rc, rc);
2779 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2780 AssertRCReturn(rc, rc);
2781 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2782 AssertRCReturn(rc, rc);
2783
2784 /* Fetch all TPR patch records. */
2785 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2786 AssertRCReturn(rc, rc);
2787
2788 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2789 {
2790 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2791
2792 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2793 AssertRCReturn(rc, rc);
2794
2795 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2796 AssertRCReturn(rc, rc);
2797
2798 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2799 AssertRCReturn(rc, rc);
2800
2801 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2802 AssertRCReturn(rc, rc);
2803
2804 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2805 AssertRCReturn(rc, rc);
2806
2807 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2808 AssertRCReturn(rc, rc);
2809
2810 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2811 pVM->hm.s.fTPRPatchingActive = true;
2812
2813 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2814
2815 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2816 AssertRCReturn(rc, rc);
2817
2818 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2819 AssertRCReturn(rc, rc);
2820
2821 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2822 AssertRCReturn(rc, rc);
2823
2824 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2825 AssertRCReturn(rc, rc);
2826
2827 Log(("hmR3Load: patch %d\n", i));
2828 Log(("Key = %x\n", pPatch->Core.Key));
2829 Log(("cbOp = %d\n", pPatch->cbOp));
2830 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2831 Log(("type = %d\n", pPatch->enmType));
2832 Log(("srcop = %d\n", pPatch->uSrcOperand));
2833 Log(("dstop = %d\n", pPatch->uDstOperand));
2834 Log(("cFaults = %d\n", pPatch->cFaults));
2835 Log(("target = %x\n", pPatch->pJumpTarget));
2836 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2837 AssertRC(rc);
2838 }
2839 }
2840#endif
2841
2842 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2843 if (HMIsEnabled(pVM))
2844 {
2845 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2846 {
2847 PVMCPU pVCpu = &pVM->aCpus[i];
2848
2849 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2850 }
2851 }
2852 return VINF_SUCCESS;
2853}
2854
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