VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 45357

Last change on this file since 45357 was 45349, checked in by vboxsync, 12 years ago

VMM/VMMR0: Very important stats.
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1/* $Id: HM.cpp 45349 2013-04-04 19:51:49Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/vmm/uvm.h>
42#include <VBox/err.h>
43#include <VBox/param.h>
44
45#include <iprt/assert.h>
46#include <VBox/log.h>
47#include <iprt/asm.h>
48#include <iprt/asm-amd64-x86.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
114 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL(),
119 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND. Guest software attempted to execute RDRAND."),
120 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID. Guest software attempted to execute INVPCID."),
121 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC. Guest software attempted to execute VMFUNC.")
122};
123/** Exit reason descriptions for AMD-V, used to describe statistics. */
124static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
125{
126 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
127 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
128 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
129 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
130 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
131 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
132 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
133 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
134 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
135 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
136 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
137 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
138 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
139 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
140 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
141 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
158 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
159 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
160 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
161 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
162 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
163 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
164 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
165 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
166 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
167 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
168 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
169 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
170 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
171 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
172 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
173 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
222 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
223 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
224 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
225 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
226 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
227 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
228 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
229 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
230 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
232 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
236 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
237 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
238 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
239 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
240 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
241 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
242 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
243 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
244 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
245 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
246 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
247 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
248 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
249 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
250 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
251 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
252 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
253 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
254 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
255 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
256 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
257 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
258 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
259 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
260 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
261 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
262 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
263 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
264 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
265 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
266 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
267 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
268 EXIT_REASON_NIL()
269};
270# undef EXIT_REASON
271# undef EXIT_REASON_NIL
272#endif /* VBOX_WITH_STATISTICS */
273
274#define VMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
275 do { \
276 if ((allowed1) & (featflag)) \
277 LogRel(("HM: " #featflag "\n")); \
278 else \
279 LogRel(("HM: " #featflag " *must* be cleared\n")); \
280 if ((disallowed0) & (featflag)) \
281 LogRel(("HM: " #featflag " *must* be set\n")); \
282 } while(0)
283
284#define VMX_REPORT_CAPABILITY(msrcaps, cap) \
285 do { \
286 if ((msrcaps) & (cap)) \
287 LogRel(("HM: " #cap "\n")); \
288 } while(0)
289
290/*******************************************************************************
291* Internal Functions *
292*******************************************************************************/
293static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
294static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
295static int hmR3InitCPU(PVM pVM);
296static int hmR3InitFinalizeR0(PVM pVM);
297static int hmR3TermCPU(PVM pVM);
298
299
300/**
301 * Initializes the HM.
302 *
303 * @returns VBox status code.
304 * @param pVM Pointer to the VM.
305 */
306VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
307{
308 LogFlow(("HMR3Init\n"));
309
310 /*
311 * Assert alignment and sizes.
312 */
313 AssertCompileMemberAlignment(VM, hm.s, 32);
314 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
315
316 /* Some structure checks. */
317 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
318 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
319 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
320
321 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
322 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
323 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
324 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
325 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
326 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
327 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
328 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
329 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
330 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
331 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
332
333 /*
334 * Register the saved state data unit.
335 */
336 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
337 NULL, NULL, NULL,
338 NULL, hmR3Save, NULL,
339 NULL, hmR3Load, NULL);
340 if (RT_FAILURE(rc))
341 return rc;
342
343 /* Misc initialisation. */
344 pVM->hm.s.vmx.fSupported = false;
345 pVM->hm.s.svm.fSupported = false;
346 pVM->hm.s.vmx.fEnabled = false;
347 pVM->hm.s.svm.fEnabled = false;
348
349 pVM->hm.s.fNestedPaging = false;
350 pVM->hm.s.fLargePages = false;
351
352 /* Disabled by default. */
353 pVM->fHMEnabled = false;
354
355 /*
356 * Check CFGM options.
357 */
358 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
359 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
360 /* Nested paging: disabled by default. */
361 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
362 AssertRC(rc);
363
364 /* Large pages: disabled by default. */
365 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
366 AssertRC(rc);
367
368 /* VT-x VPID: disabled by default. */
369 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
370 AssertRC(rc);
371
372 /* HM support must be explicitely enabled in the configuration file. */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
374 AssertRC(rc);
375
376 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
377 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
378 AssertRC(rc);
379
380#ifdef RT_OS_DARWIN
381 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
382#else
383 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
384#endif
385 {
386 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
387 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
388 return VERR_HM_CONFIG_MISMATCH;
389 }
390
391 if (VMMIsHwVirtExtForced(pVM))
392 pVM->fHMEnabled = true;
393
394#if HC_ARCH_BITS == 32
395 /*
396 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
397 * (To use the default, don't set 64bitEnabled in CFGM.)
398 */
399 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
400 AssertLogRelRCReturn(rc, rc);
401 if (pVM->hm.s.fAllow64BitGuests)
402 {
403# ifdef RT_OS_DARWIN
404 if (!VMMIsHwVirtExtForced(pVM))
405# else
406 if (!pVM->hm.s.fAllowed)
407# endif
408 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
409 }
410#else
411 /*
412 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
413 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
414 */
415 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
416 AssertLogRelRCReturn(rc, rc);
417#endif
418
419
420 /*
421 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
422 * or local init each time we wish to execute guest code.
423 *
424 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
425 */
426 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
427#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
428 false
429#else
430 true
431#endif
432 );
433
434 /* Max number of resume loops. */
435 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
436 AssertRC(rc);
437
438 return rc;
439}
440
441
442/**
443 * Initializes the per-VCPU HM.
444 *
445 * @returns VBox status code.
446 * @param pVM Pointer to the VM.
447 */
448static int hmR3InitCPU(PVM pVM)
449{
450 LogFlow(("HMR3InitCPU\n"));
451
452 for (VMCPUID i = 0; i < pVM->cCpus; i++)
453 {
454 PVMCPU pVCpu = &pVM->aCpus[i];
455
456 pVCpu->hm.s.fActive = false;
457 }
458
459#ifdef VBOX_WITH_STATISTICS
460 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
461 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
462 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
463 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
464
465 /*
466 * Statistics.
467 */
468 for (VMCPUID i = 0; i < pVM->cCpus; i++)
469 {
470 PVMCPU pVCpu = &pVM->aCpus[i];
471 int rc;
472
473 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
474 "Profiling of RTMpPokeCpu",
475 "/PROF/HM/CPU%d/Poke", i);
476 AssertRC(rc);
477 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
478 "Profiling of poke wait",
479 "/PROF/HM/CPU%d/PokeWait", i);
480 AssertRC(rc);
481 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
482 "Profiling of poke wait when RTMpPokeCpu fails",
483 "/PROF/HM/CPU%d/PokeWaitFailed", i);
484 AssertRC(rc);
485 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
486 "Profiling of VMXR0RunGuestCode entry",
487 "/PROF/HM/CPU%d/StatEntry", i);
488 AssertRC(rc);
489 /** @todo r=ramshankar: should be sorted out for the new-code which doesn't
490 * have 2 exit parts. */
491 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
492 "Profiling of VMXR0RunGuestCode exit part 1",
493 "/PROF/HM/CPU%d/SwitchFromGC_1", i);
494 AssertRC(rc);
495 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
496 "Profiling of VMXR0RunGuestCode exit part 2",
497 "/PROF/HM/CPU%d/SwitchFromGC_2", i);
498 AssertRC(rc);
499# if 1 /* temporary for tracking down darwin holdup. */
500 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
501 "Temporary - I/O",
502 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub1", i);
503 AssertRC(rc);
504 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
505 "Temporary - CRx RWs",
506 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub2", i);
507 AssertRC(rc);
508 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
509 "Temporary - Exceptions",
510 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub3", i);
511 AssertRC(rc);
512# endif
513 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
514 "Profiling of vmlaunch",
515 "/PROF/HM/CPU%d/InGC", i);
516 AssertRC(rc);
517
518# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
519 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
520 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
521 "/PROF/HM/CPU%d/Switcher3264", i);
522 AssertRC(rc);
523# endif
524
525# define HM_REG_COUNTER(a, b) \
526 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
527 AssertRC(rc);
528
529 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
530 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
531 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
541 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
542 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
544 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
545 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause");
548 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
549 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
551 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
552 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
554 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
555 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
558 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
559 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
560 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW");
561 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
562 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
563 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
564 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
566 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
567 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
568 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
571 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
572 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
573 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow");
574 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
575 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptPending, "/HM/CPU%d/Exit/PreemptPending");
576 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer");
577 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold");
578 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch");
579 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
580 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess");
581
582 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
583 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF");
584 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3");
585 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3");
586
587 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
588 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
589 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
590
591 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
592 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
593 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
594 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
595 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
596 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Switch");
597 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
598 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
599 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
600 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt");
601 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys");
602 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
603 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
604
605 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
606 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
607 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
608
609 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
610 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
611 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
612
613 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
614 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
615
616#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
617 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
618 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
619#endif
620
621 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
622 {
623 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
624 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
625 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
626 AssertRC(rc);
627 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
628 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
629 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
630 AssertRC(rc);
631 }
632
633#undef HM_REG_COUNTER
634
635 pVCpu->hm.s.paStatExitReason = NULL;
636
637 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
638 (void **)&pVCpu->hm.s.paStatExitReason);
639 AssertRC(rc);
640 if (RT_SUCCESS(rc))
641 {
642 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
643 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
644 {
645 if (papszDesc[j])
646 {
647 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
648 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
649 AssertRC(rc);
650 }
651 }
652 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
653 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
654 AssertRC(rc);
655 }
656 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
657# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
658 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
659# else
660 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
661# endif
662
663 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
664 AssertRCReturn(rc, rc);
665 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
666# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
667 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
668# else
669 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
670# endif
671 for (unsigned j = 0; j < 255; j++)
672 {
673 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
674 "Forwarded interrupts.",
675 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
676 }
677
678 }
679#endif /* VBOX_WITH_STATISTICS */
680
681#ifdef VBOX_WITH_CRASHDUMP_MAGIC
682 /* Magic marker for searching in crash dumps. */
683 for (VMCPUID i = 0; i < pVM->cCpus; i++)
684 {
685 PVMCPU pVCpu = &pVM->aCpus[i];
686
687 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
688 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
689 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
690 }
691#endif
692 return VINF_SUCCESS;
693}
694
695
696/**
697 * Called when a init phase has completed.
698 *
699 * @returns VBox status code.
700 * @param pVM The VM.
701 * @param enmWhat The phase that completed.
702 */
703VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
704{
705 switch (enmWhat)
706 {
707 case VMINITCOMPLETED_RING3:
708 return hmR3InitCPU(pVM);
709 case VMINITCOMPLETED_RING0:
710 return hmR3InitFinalizeR0(pVM);
711 default:
712 return VINF_SUCCESS;
713 }
714}
715
716
717/**
718 * Turns off normal raw mode features.
719 *
720 * @param pVM Pointer to the VM.
721 */
722static void hmR3DisableRawMode(PVM pVM)
723{
724 /* Disable PATM & CSAM. */
725 PATMR3AllowPatching(pVM->pUVM, false);
726 CSAMDisableScanning(pVM);
727
728 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
729 SELMR3DisableMonitoring(pVM);
730 TRPMR3DisableMonitoring(pVM);
731
732 /* Disable the switcher code (safety precaution). */
733 VMMR3DisableSwitcher(pVM);
734
735 /* Disable mapping of the hypervisor into the shadow page table. */
736 PGMR3MappingsDisable(pVM);
737
738 /* Disable the switcher */
739 VMMR3DisableSwitcher(pVM);
740
741 /* Reinit the paging mode to force the new shadow mode. */
742 for (VMCPUID i = 0; i < pVM->cCpus; i++)
743 {
744 PVMCPU pVCpu = &pVM->aCpus[i];
745
746 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
747 }
748}
749
750
751/**
752 * Initialize VT-x or AMD-V.
753 *
754 * @returns VBox status code.
755 * @param pVM Pointer to the VM.
756 */
757static int hmR3InitFinalizeR0(PVM pVM)
758{
759 int rc;
760
761 /*
762 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
763 * is already using AMD-V.
764 */
765 if ( !pVM->hm.s.vmx.fSupported
766 && !pVM->hm.s.svm.fSupported
767 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
768 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
769 {
770 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
771 pVM->hm.s.svm.fSupported = true;
772 pVM->hm.s.svm.fIgnoreInUseError = true;
773 }
774 else
775 if ( !pVM->hm.s.vmx.fSupported
776 && !pVM->hm.s.svm.fSupported)
777 {
778 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
779 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
780
781 if (VMMIsHwVirtExtForced(pVM))
782 {
783 switch (pVM->hm.s.lLastError)
784 {
785 case VERR_VMX_NO_VMX:
786 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
787 case VERR_VMX_IN_VMX_ROOT_MODE:
788 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
789 case VERR_SVM_IN_USE:
790 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
791 case VERR_SVM_NO_SVM:
792 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
793 case VERR_SVM_DISABLED:
794 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
795 default:
796 return pVM->hm.s.lLastError;
797 }
798 }
799 return VINF_SUCCESS;
800 }
801
802 if (pVM->hm.s.vmx.fSupported)
803 {
804 rc = SUPR3QueryVTxSupported();
805 if (RT_FAILURE(rc))
806 {
807#ifdef RT_OS_LINUX
808 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
809#else
810 LogRel(("HM: The host kernel does not support VT-x!\n"));
811#endif
812 if ( pVM->cCpus > 1
813 || VMMIsHwVirtExtForced(pVM))
814 return rc;
815
816 /* silently fall back to raw mode */
817 return VINF_SUCCESS;
818 }
819 }
820
821 if (!pVM->hm.s.fAllowed)
822 return VINF_SUCCESS; /* nothing to do */
823
824 /* Enable VT-x or AMD-V on all host CPUs. */
825 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
826 if (RT_FAILURE(rc))
827 {
828 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
829 return rc;
830 }
831 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
832
833 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
834 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
835 if (!pVM->hm.s.fHasIoApic)
836 {
837 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
838 pVM->hm.s.fTRPPatchingAllowed = false;
839 }
840
841 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
842 if (pVM->hm.s.vmx.fSupported)
843 {
844 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
845
846 if ( pVM->hm.s.fInitialized == false
847 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
848 {
849 uint64_t val;
850 uint64_t zap;
851 RTGCPHYS GCPhys = 0;
852
853 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
854 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
855 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
856 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
857 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
858 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
859 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
860 LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
861 LogRel(("HM: Max resume loops = %RX32\n", pVM->hm.s.cMaxResumeLoops));
862
863 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
864 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
865 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
866 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT);
867 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT);
868 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI);
869 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER);
870
871 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
872 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
873 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
874 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT);
875 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TSC_OFFSETTING);
876 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT);
877 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT);
878 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT);
879 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT);
880 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT);
881 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT);
882 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
883 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT);
884 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT);
885 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW);
886 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT);
887 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
888 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT);
889 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS);
890 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG);
891 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS);
892 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT);
893 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT);
894 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
895 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
896 {
897 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
898 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
899 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
900 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
901 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
902 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
903 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
904 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
905 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
906 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
907 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
908 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
909 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
910 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
911 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
912 }
913
914 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
915 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
916 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
917 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG);
918 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST);
919 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM);
920 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON);
921 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR);
922 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR);
923 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR);
924
925 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
926 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
927 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
928 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG);
929 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE);
930 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR);
931 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT);
932 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR);
933 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR);
934 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR);
935 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR);
936 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER);
937
938 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
939 {
940 val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
941 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", val));
942 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
943 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
944 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
945 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
946 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
947 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
948 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
949 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
950 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
951 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
952 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
953 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
954 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
955 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
956 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
957 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
958 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
959 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
960 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
961 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
962 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
963 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
964 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
965 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
966 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
967 }
968
969 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
970 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
971 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
972 else
973 {
974 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
975 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
976 }
977
978 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
979 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
980 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
981 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
982
983 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
984 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
985 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
986 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
987 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
988
989 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
990
991 /* Paranoia */
992 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
993
994 for (VMCPUID i = 0; i < pVM->cCpus; i++)
995 {
996 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
997 LogRel(("HM: VCPU%3d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
998 }
999
1000 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1001 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1002
1003 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1004 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1005
1006 /*
1007 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1008 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1009 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1010 */
1011 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1012 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1013 {
1014 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1015 LogRel(("HM: Disabled RDTSCP\n"));
1016 }
1017
1018 /* Unrestricted guest execution relies on EPT. */
1019 if ( pVM->hm.s.fNestedPaging
1020 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1021 {
1022 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1023 }
1024
1025 /* Only try once. */
1026 pVM->hm.s.fInitialized = true;
1027
1028 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1029 {
1030 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1031 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1032 if (RT_SUCCESS(rc))
1033 {
1034 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1035 /* Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode" esp. Figure 20-5.*/
1036 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1037 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1038 /* Bit set to 0 means software interrupts are redirected to the 8086 program interrupt handler rather than
1039 switching to protected-mode handler. */
1040 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1041 /* Allow all port IO, so that port IO instructions do not cause exceptions and would instead
1042 cause a VM-exit (based on VT-x's IO bitmap which we currently configure to always cause an exit). */
1043 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1044 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1045
1046 /*
1047 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1048 * real and protected mode without paging with EPT.
1049 */
1050 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1051 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1052 {
1053 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1054 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1055 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1056 | X86_PDE4M_G;
1057 }
1058
1059 /* We convert it here every time as pci regions could be reconfigured. */
1060 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1061 AssertRC(rc);
1062 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1063
1064 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1065 AssertRC(rc);
1066 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1067 }
1068 else
1069 {
1070 /** @todo This cannot possibly work, there are other places which assumes
1071 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1072 * a failure case. */
1073 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1074 pVM->hm.s.vmx.pRealModeTSS = NULL;
1075 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1076 }
1077 }
1078
1079 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1080 AssertRC(rc);
1081 if (rc == VINF_SUCCESS)
1082 {
1083 pVM->fHMEnabled = true;
1084 pVM->hm.s.vmx.fEnabled = true;
1085 hmR3DisableRawMode(pVM);
1086
1087 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1088#ifdef VBOX_ENABLE_64_BITS_GUESTS
1089 if (pVM->hm.s.fAllow64BitGuests)
1090 {
1091 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1092 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1093 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1094 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1095 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1096# if RT_ARCH_X86
1097 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1098 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1099 LogRel(("NX is only supported for 64-bit guests!\n"));
1100# endif
1101 }
1102 else
1103 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1104 /* Todo: this needs to be fixed properly!! */
1105 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1106 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1107 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1108 else
1109 LogRel(("HM: NX not supported by the host\n"));
1110
1111 LogRel((pVM->hm.s.fAllow64BitGuests
1112 ? "HM: 32-bit and 64-bit guests supported.\n"
1113 : "HM: 32-bit guests supported.\n"));
1114#else
1115 LogRel(("HM: 32-bit guests supported.\n"));
1116#endif
1117 LogRel(("HM: VMX enabled!\n"));
1118 if (pVM->hm.s.fNestedPaging)
1119 {
1120 LogRel(("HM: Nested paging enabled!\n"));
1121 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1122 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1123 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1124 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1125 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1126 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1127 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1128 else
1129 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1130
1131 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1132 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1133
1134#if HC_ARCH_BITS == 64
1135 if (pVM->hm.s.fLargePages)
1136 {
1137 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1138 PGMSetLargePageUsage(pVM, true);
1139 LogRel(("HM: Large page support enabled!\n"));
1140 }
1141#endif
1142 }
1143 else
1144 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1145
1146 if (pVM->hm.s.vmx.fVpid)
1147 {
1148 LogRel(("HM: VPID enabled!\n"));
1149 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1150 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1151 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1152 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1153 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1154 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1155 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1156 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1157 else
1158 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1159 }
1160 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1161 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1162
1163 /* TPR patching status logging. */
1164 if (pVM->hm.s.fTRPPatchingAllowed)
1165 {
1166 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1167 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1168 {
1169 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1170 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1171 }
1172 else
1173 {
1174 uint32_t u32Eax, u32Dummy;
1175
1176 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1177 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1178 if ( u32Eax < 0x80000001
1179 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1180 {
1181 pVM->hm.s.fTRPPatchingAllowed = false;
1182 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1183 }
1184 }
1185 }
1186 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1187
1188 /*
1189 * Check for preemption timer config override and log the state of it.
1190 */
1191 if (pVM->hm.s.vmx.fUsePreemptTimer)
1192 {
1193 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1194 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1195 AssertLogRelRC(rc2);
1196 }
1197 if (pVM->hm.s.vmx.fUsePreemptTimer)
1198 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1199 }
1200 else
1201 {
1202 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1203 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1204 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1205 pVM->fHMEnabled = false;
1206 }
1207 }
1208 }
1209 else
1210 if (pVM->hm.s.svm.fSupported)
1211 {
1212 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1213
1214 if (pVM->hm.s.fInitialized == false)
1215 {
1216 /* Erratum 170 which requires a forced TLB flush for each world switch:
1217 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1218 *
1219 * All BH-G1/2 and DH-G1/2 models include a fix:
1220 * Athlon X2: 0x6b 1/2
1221 * 0x68 1/2
1222 * Athlon 64: 0x7f 1
1223 * 0x6f 2
1224 * Sempron: 0x7f 1/2
1225 * 0x6f 2
1226 * 0x6c 2
1227 * 0x7c 2
1228 * Turion 64: 0x68 2
1229 *
1230 */
1231 uint32_t u32Dummy;
1232 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1233 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1234 u32BaseFamily= (u32Version >> 8) & 0xf;
1235 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1236 u32Model = ((u32Version >> 4) & 0xf);
1237 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1238 u32Stepping = u32Version & 0xf;
1239 if ( u32Family == 0xf
1240 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1241 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1242 {
1243 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1244 }
1245
1246 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1247 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1248 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1249 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1250 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1251 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1252 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1253 {
1254#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1255 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1256 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1257 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1258 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1259 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1260 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1261 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1262 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1263 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1264 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1265 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1266#undef FLAG_NAME
1267 };
1268 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1269 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1270 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1271 {
1272 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1273 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1274 }
1275 if (fSvmFeatures)
1276 for (unsigned iBit = 0; iBit < 32; iBit++)
1277 if (RT_BIT_32(iBit) & fSvmFeatures)
1278 LogRel(("HM: Reserved bit %u\n", iBit));
1279
1280 /* Only try once. */
1281 pVM->hm.s.fInitialized = true;
1282
1283 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1284 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1285
1286 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1287 AssertRC(rc);
1288 if (rc == VINF_SUCCESS)
1289 {
1290 pVM->fHMEnabled = true;
1291 pVM->hm.s.svm.fEnabled = true;
1292
1293 if (pVM->hm.s.fNestedPaging)
1294 {
1295 LogRel(("HM: Enabled nested paging!\n"));
1296#if HC_ARCH_BITS == 64
1297 if (pVM->hm.s.fLargePages)
1298 {
1299 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1300 PGMSetLargePageUsage(pVM, true);
1301 LogRel(("HM: Large page support enabled!\n"));
1302 }
1303#endif
1304 }
1305
1306 hmR3DisableRawMode(pVM);
1307 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1308 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1309#ifdef VBOX_ENABLE_64_BITS_GUESTS
1310 if (pVM->hm.s.fAllow64BitGuests)
1311 {
1312 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1313 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1314 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1315 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1316 }
1317 else
1318 /* Turn on NXE if PAE has been enabled. */
1319 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1320 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1321#endif
1322
1323 LogRel((pVM->hm.s.fAllow64BitGuests
1324 ? "HM: 32-bit and 64-bit guest supported.\n"
1325 : "HM: 32-bit guest supported.\n"));
1326
1327 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1328 }
1329 else
1330 {
1331 pVM->fHMEnabled = false;
1332 }
1333 }
1334 }
1335 if (pVM->fHMEnabled)
1336 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1337 RTLogRelSetBuffering(fOldBuffered);
1338 return VINF_SUCCESS;
1339}
1340
1341
1342/**
1343 * Applies relocations to data and code managed by this
1344 * component. This function will be called at init and
1345 * whenever the VMM need to relocate it self inside the GC.
1346 *
1347 * @param pVM The VM.
1348 */
1349VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1350{
1351 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1352
1353 /* Fetch the current paging mode during the relocate callback during state loading. */
1354 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1355 {
1356 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1357 {
1358 PVMCPU pVCpu = &pVM->aCpus[i];
1359
1360 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1361 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1362 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1363 }
1364 }
1365#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1366 if (pVM->fHMEnabled)
1367 {
1368 int rc;
1369 switch (PGMGetHostMode(pVM))
1370 {
1371 case PGMMODE_32_BIT:
1372 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1373 break;
1374
1375 case PGMMODE_PAE:
1376 case PGMMODE_PAE_NX:
1377 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1378 break;
1379
1380 default:
1381 AssertFailed();
1382 break;
1383 }
1384 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1385 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1386
1387 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1388 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1389
1390 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1391 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1392
1393 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1394 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1395
1396# ifdef DEBUG
1397 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1398 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1399# endif
1400 }
1401#endif
1402 return;
1403}
1404
1405
1406/**
1407 * Checks if hardware accelerated raw mode is allowed.
1408 *
1409 * @returns true if hardware acceleration is allowed, otherwise false.
1410 * @param pVM Pointer to the VM.
1411 */
1412VMMR3_INT_DECL(bool) HMR3IsAllowed(PVM pVM)
1413{
1414 return pVM->hm.s.fAllowed;
1415}
1416
1417
1418/**
1419 * Notification callback which is called whenever there is a chance that a CR3
1420 * value might have changed.
1421 *
1422 * This is called by PGM.
1423 *
1424 * @param pVM Pointer to the VM.
1425 * @param pVCpu Pointer to the VMCPU.
1426 * @param enmShadowMode New shadow paging mode.
1427 * @param enmGuestMode New guest paging mode.
1428 */
1429VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1430{
1431 /* Ignore page mode changes during state loading. */
1432 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1433 return;
1434
1435 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1436
1437#ifdef VBOX_WITH_OLD_VTX_CODE
1438 if ( pVM->hm.s.vmx.fEnabled
1439 && pVM->fHMEnabled)
1440 {
1441 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1442 && enmGuestMode >= PGMMODE_PROTECTED)
1443 {
1444 PCPUMCTX pCtx;
1445
1446 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1447
1448 /* After a real mode switch to protected mode we must force
1449 CPL to 0. Our real mode emulation had to set it to 3. */
1450 pCtx->ss.Attr.n.u2Dpl = 0;
1451 }
1452 }
1453#endif
1454
1455 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1456 {
1457 /* Keep track of paging mode changes. */
1458 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1459 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1460
1461 /* Did we miss a change, because all code was executed in the recompiler? */
1462 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1463 {
1464 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1465 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1466 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1467 }
1468 }
1469
1470 /** @todo r=ramshankar: Why do we need to do this? Most likely
1471 * VBOX_WITH_OLD_VTX_CODE only. */
1472 /* Reset the contents of the read cache. */
1473 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1474 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1475 pCache->Read.aFieldVal[j] = 0;
1476}
1477
1478
1479/**
1480 * Terminates the HM.
1481 *
1482 * Termination means cleaning up and freeing all resources,
1483 * the VM itself is, at this point, powered off or suspended.
1484 *
1485 * @returns VBox status code.
1486 * @param pVM Pointer to the VM.
1487 */
1488VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1489{
1490 if (pVM->hm.s.vmx.pRealModeTSS)
1491 {
1492 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1493 pVM->hm.s.vmx.pRealModeTSS = 0;
1494 }
1495 hmR3TermCPU(pVM);
1496 return 0;
1497}
1498
1499
1500/**
1501 * Terminates the per-VCPU HM.
1502 *
1503 * @returns VBox status code.
1504 * @param pVM Pointer to the VM.
1505 */
1506static int hmR3TermCPU(PVM pVM)
1507{
1508 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1509 {
1510 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1511
1512#ifdef VBOX_WITH_STATISTICS
1513 if (pVCpu->hm.s.paStatExitReason)
1514 {
1515 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1516 pVCpu->hm.s.paStatExitReason = NULL;
1517 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1518 }
1519 if (pVCpu->hm.s.paStatInjectedIrqs)
1520 {
1521 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1522 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1523 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1524 }
1525#endif
1526
1527#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1528 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1529 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1530 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1531#endif
1532 }
1533 return 0;
1534}
1535
1536
1537/**
1538 * Resets a virtual CPU.
1539 *
1540 * Used by HMR3Reset and CPU hot plugging.
1541 *
1542 * @param pVCpu The CPU to reset.
1543 */
1544VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1545{
1546 /* On first entry we'll sync everything. */
1547 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1548
1549 pVCpu->hm.s.vmx.cr0_mask = 0;
1550 pVCpu->hm.s.vmx.cr4_mask = 0;
1551
1552 pVCpu->hm.s.fActive = false;
1553 pVCpu->hm.s.Event.fPending = false;
1554
1555 /* Reset state information for real-mode emulation in VT-x. */
1556 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1557 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1558 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1559
1560 /* Reset the contents of the read cache. */
1561 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1562 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1563 pCache->Read.aFieldVal[j] = 0;
1564
1565#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1566 /* Magic marker for searching in crash dumps. */
1567 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1568 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1569#endif
1570}
1571
1572
1573/**
1574 * The VM is being reset.
1575 *
1576 * For the HM component this means that any GDT/LDT/TSS monitors
1577 * needs to be removed.
1578 *
1579 * @param pVM Pointer to the VM.
1580 */
1581VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1582{
1583 LogFlow(("HMR3Reset:\n"));
1584
1585 if (pVM->fHMEnabled)
1586 hmR3DisableRawMode(pVM);
1587
1588 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1589 {
1590 PVMCPU pVCpu = &pVM->aCpus[i];
1591
1592 HMR3ResetCpu(pVCpu);
1593 }
1594
1595 /* Clear all patch information. */
1596 pVM->hm.s.pGuestPatchMem = 0;
1597 pVM->hm.s.pFreeGuestPatchMem = 0;
1598 pVM->hm.s.cbGuestPatchMem = 0;
1599 pVM->hm.s.cPatches = 0;
1600 pVM->hm.s.PatchTree = 0;
1601 pVM->hm.s.fTPRPatchingActive = false;
1602 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1603}
1604
1605
1606/**
1607 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1608 *
1609 * @returns VBox strict status code.
1610 * @param pVM Pointer to the VM.
1611 * @param pVCpu The VMCPU for the EMT we're being called on.
1612 * @param pvUser Unused.
1613 */
1614DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1615{
1616 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1617
1618 /* Only execute the handler on the VCPU the original patch request was issued. */
1619 if (pVCpu->idCpu != idCpu)
1620 return VINF_SUCCESS;
1621
1622 Log(("hmR3RemovePatches\n"));
1623 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1624 {
1625 uint8_t abInstr[15];
1626 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1627 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1628 int rc;
1629
1630#ifdef LOG_ENABLED
1631 char szOutput[256];
1632
1633 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1634 szOutput, sizeof(szOutput), NULL);
1635 if (RT_SUCCESS(rc))
1636 Log(("Patched instr: %s\n", szOutput));
1637#endif
1638
1639 /* Check if the instruction is still the same. */
1640 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1641 if (rc != VINF_SUCCESS)
1642 {
1643 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1644 continue; /* swapped out or otherwise removed; skip it. */
1645 }
1646
1647 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1648 {
1649 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1650 continue; /* skip it. */
1651 }
1652
1653 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1654 AssertRC(rc);
1655
1656#ifdef LOG_ENABLED
1657 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1658 szOutput, sizeof(szOutput), NULL);
1659 if (RT_SUCCESS(rc))
1660 Log(("Original instr: %s\n", szOutput));
1661#endif
1662 }
1663 pVM->hm.s.cPatches = 0;
1664 pVM->hm.s.PatchTree = 0;
1665 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1666 pVM->hm.s.fTPRPatchingActive = false;
1667 return VINF_SUCCESS;
1668}
1669
1670
1671/**
1672 * Worker for enabling patching in a VT-x/AMD-V guest.
1673 *
1674 * @returns VBox status code.
1675 * @param pVM Pointer to the VM.
1676 * @param idCpu VCPU to execute hmR3RemovePatches on.
1677 * @param pPatchMem Patch memory range.
1678 * @param cbPatchMem Size of the memory range.
1679 */
1680static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1681{
1682 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1683 AssertRC(rc);
1684
1685 pVM->hm.s.pGuestPatchMem = pPatchMem;
1686 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1687 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1688 return VINF_SUCCESS;
1689}
1690
1691
1692/**
1693 * Enable patching in a VT-x/AMD-V guest
1694 *
1695 * @returns VBox status code.
1696 * @param pVM Pointer to the VM.
1697 * @param pPatchMem Patch memory range.
1698 * @param cbPatchMem Size of the memory range.
1699 */
1700VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1701{
1702 VM_ASSERT_EMT(pVM);
1703 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1704 if (pVM->cCpus > 1)
1705 {
1706 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1707 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1708 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1709 AssertRC(rc);
1710 return rc;
1711 }
1712 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1713}
1714
1715
1716/**
1717 * Disable patching in a VT-x/AMD-V guest.
1718 *
1719 * @returns VBox status code.
1720 * @param pVM Pointer to the VM.
1721 * @param pPatchMem Patch memory range.
1722 * @param cbPatchMem Size of the memory range.
1723 */
1724VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1725{
1726 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1727
1728 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1729 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1730
1731 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1732 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1733 (void *)(uintptr_t)VMMGetCpuId(pVM));
1734 AssertRC(rc);
1735
1736 pVM->hm.s.pGuestPatchMem = 0;
1737 pVM->hm.s.pFreeGuestPatchMem = 0;
1738 pVM->hm.s.cbGuestPatchMem = 0;
1739 pVM->hm.s.fTPRPatchingActive = false;
1740 return VINF_SUCCESS;
1741}
1742
1743
1744/**
1745 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1746 *
1747 * @returns VBox strict status code.
1748 * @param pVM Pointer to the VM.
1749 * @param pVCpu The VMCPU for the EMT we're being called on.
1750 * @param pvUser User specified CPU context.
1751 *
1752 */
1753DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1754{
1755 /*
1756 * Only execute the handler on the VCPU the original patch request was
1757 * issued. (The other CPU(s) might not yet have switched to protected
1758 * mode, nor have the correct memory context.)
1759 */
1760 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1761 if (pVCpu->idCpu != idCpu)
1762 return VINF_SUCCESS;
1763
1764 /*
1765 * We're racing other VCPUs here, so don't try patch the instruction twice
1766 * and make sure there is still room for our patch record.
1767 */
1768 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1769 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1770 if (pPatch)
1771 {
1772 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1773 return VINF_SUCCESS;
1774 }
1775 uint32_t const idx = pVM->hm.s.cPatches;
1776 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1777 {
1778 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1779 return VINF_SUCCESS;
1780 }
1781 pPatch = &pVM->hm.s.aPatches[idx];
1782
1783 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1784
1785 /*
1786 * Disassembler the instruction and get cracking.
1787 */
1788 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1789 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1790 uint32_t cbOp;
1791 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1792 AssertRC(rc);
1793 if ( rc == VINF_SUCCESS
1794 && pDis->pCurInstr->uOpcode == OP_MOV
1795 && cbOp >= 3)
1796 {
1797 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1798
1799 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1800 AssertRC(rc);
1801
1802 pPatch->cbOp = cbOp;
1803
1804 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1805 {
1806 /* write. */
1807 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1808 {
1809 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1810 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1811 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1812 }
1813 else
1814 {
1815 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1816 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1817 pPatch->uSrcOperand = pDis->Param2.uValue;
1818 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1819 }
1820 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1821 AssertRC(rc);
1822
1823 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1824 pPatch->cbNewOp = sizeof(s_abVMMCall);
1825 }
1826 else
1827 {
1828 /*
1829 * TPR Read.
1830 *
1831 * Found:
1832 * mov eax, dword [fffe0080] (5 bytes)
1833 * Check if next instruction is:
1834 * shr eax, 4
1835 */
1836 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1837
1838 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1839 uint8_t const cbOpMmio = cbOp;
1840 uint64_t const uSavedRip = pCtx->rip;
1841
1842 pCtx->rip += cbOp;
1843 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1844 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1845 pCtx->rip = uSavedRip;
1846
1847 if ( rc == VINF_SUCCESS
1848 && pDis->pCurInstr->uOpcode == OP_SHR
1849 && pDis->Param1.fUse == DISUSE_REG_GEN32
1850 && pDis->Param1.Base.idxGenReg == idxMmioReg
1851 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1852 && pDis->Param2.uValue == 4
1853 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1854 {
1855 uint8_t abInstr[15];
1856
1857 /* Replacing two instructions now. */
1858 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1859 AssertRC(rc);
1860
1861 pPatch->cbOp = cbOpMmio + cbOp;
1862
1863 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1864 abInstr[0] = 0xF0;
1865 abInstr[1] = 0x0F;
1866 abInstr[2] = 0x20;
1867 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1868 for (unsigned i = 4; i < pPatch->cbOp; i++)
1869 abInstr[i] = 0x90; /* nop */
1870
1871 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1872 AssertRC(rc);
1873
1874 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1875 pPatch->cbNewOp = pPatch->cbOp;
1876
1877 Log(("Acceptable read/shr candidate!\n"));
1878 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1879 }
1880 else
1881 {
1882 pPatch->enmType = HMTPRINSTR_READ;
1883 pPatch->uDstOperand = idxMmioReg;
1884
1885 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1886 AssertRC(rc);
1887
1888 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1889 pPatch->cbNewOp = sizeof(s_abVMMCall);
1890 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1891 }
1892 }
1893
1894 pPatch->Core.Key = pCtx->eip;
1895 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1896 AssertRC(rc);
1897
1898 pVM->hm.s.cPatches++;
1899 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1900 return VINF_SUCCESS;
1901 }
1902
1903 /*
1904 * Save invalid patch, so we will not try again.
1905 */
1906 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1907 pPatch->Core.Key = pCtx->eip;
1908 pPatch->enmType = HMTPRINSTR_INVALID;
1909 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1910 AssertRC(rc);
1911 pVM->hm.s.cPatches++;
1912 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1913 return VINF_SUCCESS;
1914}
1915
1916
1917/**
1918 * Callback to patch a TPR instruction (jump to generated code).
1919 *
1920 * @returns VBox strict status code.
1921 * @param pVM Pointer to the VM.
1922 * @param pVCpu The VMCPU for the EMT we're being called on.
1923 * @param pvUser User specified CPU context.
1924 *
1925 */
1926DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1927{
1928 /*
1929 * Only execute the handler on the VCPU the original patch request was
1930 * issued. (The other CPU(s) might not yet have switched to protected
1931 * mode, nor have the correct memory context.)
1932 */
1933 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1934 if (pVCpu->idCpu != idCpu)
1935 return VINF_SUCCESS;
1936
1937 /*
1938 * We're racing other VCPUs here, so don't try patch the instruction twice
1939 * and make sure there is still room for our patch record.
1940 */
1941 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1942 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1943 if (pPatch)
1944 {
1945 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1946 return VINF_SUCCESS;
1947 }
1948 uint32_t const idx = pVM->hm.s.cPatches;
1949 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1950 {
1951 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1952 return VINF_SUCCESS;
1953 }
1954 pPatch = &pVM->hm.s.aPatches[idx];
1955
1956 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1957 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
1958
1959 /*
1960 * Disassemble the instruction and get cracking.
1961 */
1962 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1963 uint32_t cbOp;
1964 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1965 AssertRC(rc);
1966 if ( rc == VINF_SUCCESS
1967 && pDis->pCurInstr->uOpcode == OP_MOV
1968 && cbOp >= 5)
1969 {
1970 uint8_t aPatch[64];
1971 uint32_t off = 0;
1972
1973 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1974 AssertRC(rc);
1975
1976 pPatch->cbOp = cbOp;
1977 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
1978
1979 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1980 {
1981 /*
1982 * TPR write:
1983 *
1984 * push ECX [51]
1985 * push EDX [52]
1986 * push EAX [50]
1987 * xor EDX,EDX [31 D2]
1988 * mov EAX,EAX [89 C0]
1989 * or
1990 * mov EAX,0000000CCh [B8 CC 00 00 00]
1991 * mov ECX,0C0000082h [B9 82 00 00 C0]
1992 * wrmsr [0F 30]
1993 * pop EAX [58]
1994 * pop EDX [5A]
1995 * pop ECX [59]
1996 * jmp return_address [E9 return_address]
1997 *
1998 */
1999 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2000
2001 aPatch[off++] = 0x51; /* push ecx */
2002 aPatch[off++] = 0x52; /* push edx */
2003 if (!fUsesEax)
2004 aPatch[off++] = 0x50; /* push eax */
2005 aPatch[off++] = 0x31; /* xor edx, edx */
2006 aPatch[off++] = 0xD2;
2007 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2008 {
2009 if (!fUsesEax)
2010 {
2011 aPatch[off++] = 0x89; /* mov eax, src_reg */
2012 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2013 }
2014 }
2015 else
2016 {
2017 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2018 aPatch[off++] = 0xB8; /* mov eax, immediate */
2019 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2020 off += sizeof(uint32_t);
2021 }
2022 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2023 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2024 off += sizeof(uint32_t);
2025
2026 aPatch[off++] = 0x0F; /* wrmsr */
2027 aPatch[off++] = 0x30;
2028 if (!fUsesEax)
2029 aPatch[off++] = 0x58; /* pop eax */
2030 aPatch[off++] = 0x5A; /* pop edx */
2031 aPatch[off++] = 0x59; /* pop ecx */
2032 }
2033 else
2034 {
2035 /*
2036 * TPR read:
2037 *
2038 * push ECX [51]
2039 * push EDX [52]
2040 * push EAX [50]
2041 * mov ECX,0C0000082h [B9 82 00 00 C0]
2042 * rdmsr [0F 32]
2043 * mov EAX,EAX [89 C0]
2044 * pop EAX [58]
2045 * pop EDX [5A]
2046 * pop ECX [59]
2047 * jmp return_address [E9 return_address]
2048 *
2049 */
2050 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2051
2052 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2053 aPatch[off++] = 0x51; /* push ecx */
2054 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2055 aPatch[off++] = 0x52; /* push edx */
2056 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2057 aPatch[off++] = 0x50; /* push eax */
2058
2059 aPatch[off++] = 0x31; /* xor edx, edx */
2060 aPatch[off++] = 0xD2;
2061
2062 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2063 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2064 off += sizeof(uint32_t);
2065
2066 aPatch[off++] = 0x0F; /* rdmsr */
2067 aPatch[off++] = 0x32;
2068
2069 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2070 {
2071 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2072 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2073 }
2074
2075 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2076 aPatch[off++] = 0x58; /* pop eax */
2077 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2078 aPatch[off++] = 0x5A; /* pop edx */
2079 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2080 aPatch[off++] = 0x59; /* pop ecx */
2081 }
2082 aPatch[off++] = 0xE9; /* jmp return_address */
2083 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2084 off += sizeof(RTRCUINTPTR);
2085
2086 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2087 {
2088 /* Write new code to the patch buffer. */
2089 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2090 AssertRC(rc);
2091
2092#ifdef LOG_ENABLED
2093 uint32_t cbCurInstr;
2094 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2095 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2096 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2097 {
2098 char szOutput[256];
2099 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2100 szOutput, sizeof(szOutput), &cbCurInstr);
2101 if (RT_SUCCESS(rc))
2102 Log(("Patch instr %s\n", szOutput));
2103 else
2104 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2105 }
2106#endif
2107
2108 pPatch->aNewOpcode[0] = 0xE9;
2109 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2110
2111 /* Overwrite the TPR instruction with a jump. */
2112 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2113 AssertRC(rc);
2114
2115 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2116
2117 pVM->hm.s.pFreeGuestPatchMem += off;
2118 pPatch->cbNewOp = 5;
2119
2120 pPatch->Core.Key = pCtx->eip;
2121 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2122 AssertRC(rc);
2123
2124 pVM->hm.s.cPatches++;
2125 pVM->hm.s.fTPRPatchingActive = true;
2126 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2127 return VINF_SUCCESS;
2128 }
2129
2130 Log(("Ran out of space in our patch buffer!\n"));
2131 }
2132 else
2133 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2134
2135
2136 /*
2137 * Save invalid patch, so we will not try again.
2138 */
2139 pPatch = &pVM->hm.s.aPatches[idx];
2140 pPatch->Core.Key = pCtx->eip;
2141 pPatch->enmType = HMTPRINSTR_INVALID;
2142 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2143 AssertRC(rc);
2144 pVM->hm.s.cPatches++;
2145 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2146 return VINF_SUCCESS;
2147}
2148
2149
2150/**
2151 * Attempt to patch TPR mmio instructions.
2152 *
2153 * @returns VBox status code.
2154 * @param pVM Pointer to the VM.
2155 * @param pVCpu Pointer to the VMCPU.
2156 * @param pCtx Pointer to the guest CPU context.
2157 */
2158VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2159{
2160 NOREF(pCtx);
2161 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2162 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2163 (void *)(uintptr_t)pVCpu->idCpu);
2164 AssertRC(rc);
2165 return rc;
2166}
2167
2168
2169/**
2170 * Force execution of the current IO code in the recompiler.
2171 *
2172 * @returns VBox status code.
2173 * @param pVM Pointer to the VM.
2174 * @param pCtx Partial VM execution context.
2175 */
2176VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2177{
2178 PVMCPU pVCpu = VMMGetCpu(pVM);
2179
2180 Assert(pVM->fHMEnabled);
2181 Log(("HMR3EmulateIoBlock\n"));
2182
2183 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2184 if (HMCanEmulateIoBlockEx(pCtx))
2185 {
2186 Log(("HMR3EmulateIoBlock -> enabled\n"));
2187 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2188 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2189 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2190 return VINF_EM_RESCHEDULE_REM;
2191 }
2192 return VINF_SUCCESS;
2193}
2194
2195
2196/**
2197 * Checks if we can currently use hardware accelerated raw mode.
2198 *
2199 * @returns true if we can currently use hardware acceleration, otherwise false.
2200 * @param pVM Pointer to the VM.
2201 * @param pCtx Partial VM execution context.
2202 */
2203VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2204{
2205 PVMCPU pVCpu = VMMGetCpu(pVM);
2206
2207 Assert(pVM->fHMEnabled);
2208
2209 /* If we're still executing the IO code, then return false. */
2210 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2211 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2212 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2213 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2214 return false;
2215
2216 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2217
2218 /* AMD-V supports real & protected mode with or without paging. */
2219 if (pVM->hm.s.svm.fEnabled)
2220 {
2221 pVCpu->hm.s.fActive = true;
2222 return true;
2223 }
2224
2225 pVCpu->hm.s.fActive = false;
2226
2227 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2228 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2229 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2230
2231 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2232 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2233 {
2234 /*
2235 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2236 * guest execution feature i missing (VT-x only).
2237 */
2238 if (fSupportsRealMode)
2239 {
2240 if (CPUMIsGuestInRealModeEx(pCtx))
2241 {
2242 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2243 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2244 * If this is not true, we cannot execute real mode as V86 and have to fall
2245 * back to emulation.
2246 */
2247 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2248 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2249 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2250 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2251 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2252 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2253 || (pCtx->cs.u32Limit != 0xffff)
2254 || (pCtx->ds.u32Limit != 0xffff)
2255 || (pCtx->es.u32Limit != 0xffff)
2256 || (pCtx->ss.u32Limit != 0xffff)
2257 || (pCtx->fs.u32Limit != 0xffff)
2258 || (pCtx->gs.u32Limit != 0xffff))
2259 {
2260 return false;
2261 }
2262 }
2263 else
2264 {
2265 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2266 /* Verify the requirements for executing code in protected
2267 mode. VT-x can't handle the CPU state right after a switch
2268 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2269 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2270 && enmGuestMode >= PGMMODE_PROTECTED)
2271 {
2272 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2273 || (pCtx->ds.Sel & X86_SEL_RPL)
2274 || (pCtx->es.Sel & X86_SEL_RPL)
2275 || (pCtx->fs.Sel & X86_SEL_RPL)
2276 || (pCtx->gs.Sel & X86_SEL_RPL)
2277 || (pCtx->ss.Sel & X86_SEL_RPL))
2278 {
2279 return false;
2280 }
2281 }
2282 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2283 if ( pCtx->gdtr.cbGdt
2284 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2285 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2286 {
2287 return false;
2288 }
2289 }
2290 }
2291 else
2292 {
2293 if ( !CPUMIsGuestInLongModeEx(pCtx)
2294 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2295 {
2296 /** @todo This should (probably) be set on every excursion to the REM,
2297 * however it's too risky right now. So, only apply it when we go
2298 * back to REM for real mode execution. (The XP hack below doesn't
2299 * work reliably without this.)
2300 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2301 for (uint32_t i = 0; i < pVM->cCpus; i++)
2302 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2303
2304 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2305 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2306 return false;
2307
2308 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2309 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2310 return false;
2311
2312 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2313 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2314 * hidden registers (possible recompiler bug; see load_seg_vm) */
2315 if (pCtx->cs.Attr.n.u1Present == 0)
2316 return false;
2317 if (pCtx->ss.Attr.n.u1Present == 0)
2318 return false;
2319
2320 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2321 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2322 /** @todo This check is actually wrong, it doesn't take the direction of the
2323 * stack segment into account. But, it does the job for now. */
2324 if (pCtx->rsp >= pCtx->ss.u32Limit)
2325 return false;
2326#if 0
2327 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2328 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2329 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2330 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2331 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2332 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2333 return false;
2334#endif
2335 }
2336 }
2337 }
2338
2339 if (pVM->hm.s.vmx.fEnabled)
2340 {
2341 uint32_t mask;
2342
2343 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2344 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2345 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2346 mask &= ~X86_CR0_NE;
2347
2348 if (fSupportsRealMode)
2349 {
2350 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2351 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2352 }
2353 else
2354 {
2355 /* We support protected mode without paging using identity mapping. */
2356 mask &= ~X86_CR0_PG;
2357 }
2358 if ((pCtx->cr0 & mask) != mask)
2359 return false;
2360
2361 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2362 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2363 if ((pCtx->cr0 & mask) != 0)
2364 return false;
2365
2366 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2367 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2368 mask &= ~X86_CR4_VMXE;
2369 if ((pCtx->cr4 & mask) != mask)
2370 return false;
2371
2372 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2373 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2374 if ((pCtx->cr4 & mask) != 0)
2375 return false;
2376
2377 pVCpu->hm.s.fActive = true;
2378 return true;
2379 }
2380
2381 return false;
2382}
2383
2384
2385/**
2386 * Checks if we need to reschedule due to VMM device heap changes.
2387 *
2388 * @returns true if a reschedule is required, otherwise false.
2389 * @param pVM Pointer to the VM.
2390 * @param pCtx VM execution context.
2391 */
2392VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2393{
2394 /*
2395 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2396 * when the unrestricted guest execution feature is missing (VT-x only).
2397 */
2398#ifdef VBOX_WITH_OLD_VTX_CODE
2399 if ( pVM->hm.s.vmx.fEnabled
2400 && !pVM->hm.s.vmx.fUnrestrictedGuest
2401 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2402 && !PDMVmmDevHeapIsEnabled(pVM)
2403 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2404 return true;
2405#else
2406 if ( pVM->hm.s.vmx.fEnabled
2407 && !pVM->hm.s.vmx.fUnrestrictedGuest
2408 && CPUMIsGuestInRealModeEx(pCtx)
2409 && !PDMVmmDevHeapIsEnabled(pVM))
2410 return true;
2411#endif
2412
2413 return false;
2414}
2415
2416
2417/**
2418 * Notification from EM about a rescheduling into hardware assisted execution
2419 * mode.
2420 *
2421 * @param pVCpu Pointer to the current VMCPU.
2422 */
2423VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2424{
2425 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2426}
2427
2428
2429/**
2430 * Notification from EM about returning from instruction emulation (REM / EM).
2431 *
2432 * @param pVCpu Pointer to the VMCPU.
2433 */
2434VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2435{
2436 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2437}
2438
2439
2440/**
2441 * Checks if we are currently using hardware accelerated raw mode.
2442 *
2443 * @returns true if hardware acceleration is being used, otherwise false.
2444 * @param pVCpu Pointer to the VMCPU.
2445 */
2446VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2447{
2448 return pVCpu->hm.s.fActive;
2449}
2450
2451
2452/**
2453 * Checks if we are currently using nested paging.
2454 *
2455 * @returns true if nested paging is being used, otherwise false.
2456 * @param pUVM The user mode VM handle.
2457 */
2458VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2459{
2460 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2461 PVM pVM = pUVM->pVM;
2462 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2463 return HMIsEnabled(pVM);
2464}
2465
2466
2467/**
2468 * Checks if we are currently using nested paging.
2469 *
2470 * @returns true if nested paging is being used, otherwise false.
2471 * @param pUVM The user mode VM handle.
2472 */
2473VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2474{
2475 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2476 PVM pVM = pUVM->pVM;
2477 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2478 return pVM->hm.s.fNestedPaging;
2479}
2480
2481
2482/**
2483 * Checks if we are currently using VPID in VT-x mode.
2484 *
2485 * @returns true if VPID is being used, otherwise false.
2486 * @param pUVM The user mode VM handle.
2487 */
2488VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2489{
2490 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2491 PVM pVM = pUVM->pVM;
2492 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2493 return pVM->hm.s.vmx.fVpid;
2494}
2495
2496
2497/**
2498 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2499 *
2500 * @returns true if an internal event is pending, otherwise false.
2501 * @param pVM Pointer to the VM.
2502 */
2503VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2504{
2505 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2506}
2507
2508
2509/**
2510 * Checks if the VMX-preemption timer is being used.
2511 *
2512 * @returns true if the VMX-preemption timer is being used, otherwise false.
2513 * @param pVM Pointer to the VM.
2514 */
2515VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2516{
2517 return HMIsEnabled(pVM)
2518 && pVM->hm.s.vmx.fEnabled
2519 && pVM->hm.s.vmx.fUsePreemptTimer;
2520}
2521
2522
2523/**
2524 * Restart an I/O instruction that was refused in ring-0
2525 *
2526 * @returns Strict VBox status code. Informational status codes other than the one documented
2527 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2528 * @retval VINF_SUCCESS Success.
2529 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2530 * status code must be passed on to EM.
2531 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2532 *
2533 * @param pVM Pointer to the VM.
2534 * @param pVCpu Pointer to the VMCPU.
2535 * @param pCtx Pointer to the guest CPU context.
2536 */
2537VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2538{
2539 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2540
2541 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2542
2543 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2544 || enmType == HMPENDINGIO_INVALID)
2545 return VERR_NOT_FOUND;
2546
2547 VBOXSTRICTRC rcStrict;
2548 switch (enmType)
2549 {
2550 case HMPENDINGIO_PORT_READ:
2551 {
2552 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2553 uint32_t u32Val = 0;
2554
2555 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2556 &u32Val,
2557 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2558 if (IOM_SUCCESS(rcStrict))
2559 {
2560 /* Write back to the EAX register. */
2561 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2562 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2563 }
2564 break;
2565 }
2566
2567 case HMPENDINGIO_PORT_WRITE:
2568 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2569 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2570 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2571 if (IOM_SUCCESS(rcStrict))
2572 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2573 break;
2574
2575 default:
2576 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2577 }
2578
2579 return rcStrict;
2580}
2581
2582
2583/**
2584 * Check fatal VT-x/AMD-V error and produce some meaningful
2585 * log release message.
2586 *
2587 * @param pVM Pointer to the VM.
2588 * @param iStatusCode VBox status code.
2589 */
2590VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2591{
2592 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2593 {
2594 switch (iStatusCode)
2595 {
2596 case VERR_VMX_INVALID_VMCS_FIELD:
2597 break;
2598
2599 case VERR_VMX_INVALID_VMCS_PTR:
2600 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2601 LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2602 LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2603 LogRel(("HM: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2604 LogRel(("HM: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2605 break;
2606
2607 case VERR_VMX_UNABLE_TO_START_VM:
2608 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2609 LogRel(("HM: CPU%d instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2610 LogRel(("HM: CPU%d exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2611 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2612 {
2613 LogRel(("HM: Cpu%d PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2614 LogRel(("HM: Cpu%d ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2615 LogRel(("HM: Cpu%d ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2616 LogRel(("HM: Cpu%d EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2617 LogRel(("HM: Cpu%d ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2618 LogRel(("HM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2619#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2620 LogRel(("HM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2621 LogRel(("HM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2622 LogRel(("HM: Cpu%d cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2623#endif
2624 }
2625 /** @todo Log VM-entry event injection control fields
2626 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2627 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2628 break;
2629
2630 case VERR_VMX_UNABLE_TO_RESUME_VM:
2631 LogRel(("HM: VERR_VMX_UNABLE_TO_RESUME_VM:\n"));
2632 LogRel(("HM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2633 LogRel(("HM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2634 break;
2635
2636 case VERR_VMX_INVALID_VMXON_PTR:
2637 break;
2638 }
2639 }
2640
2641 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2642 {
2643 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2644 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2645 }
2646}
2647
2648
2649/**
2650 * Execute state save operation.
2651 *
2652 * @returns VBox status code.
2653 * @param pVM Pointer to the VM.
2654 * @param pSSM SSM operation handle.
2655 */
2656static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2657{
2658 int rc;
2659
2660 Log(("hmR3Save:\n"));
2661
2662 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2663 {
2664 /*
2665 * Save the basic bits - fortunately all the other things can be resynced on load.
2666 */
2667 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2668 AssertRCReturn(rc, rc);
2669 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2670 AssertRCReturn(rc, rc);
2671 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2672 AssertRCReturn(rc, rc);
2673
2674 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2675 AssertRCReturn(rc, rc);
2676 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2677 AssertRCReturn(rc, rc);
2678 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2679 AssertRCReturn(rc, rc);
2680 }
2681#ifdef VBOX_HM_WITH_GUEST_PATCHING
2682 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2683 AssertRCReturn(rc, rc);
2684 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2685 AssertRCReturn(rc, rc);
2686 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2687 AssertRCReturn(rc, rc);
2688
2689 /* Store all the guest patch records too. */
2690 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2691 AssertRCReturn(rc, rc);
2692
2693 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2694 {
2695 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2696
2697 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2698 AssertRCReturn(rc, rc);
2699
2700 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2701 AssertRCReturn(rc, rc);
2702
2703 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2704 AssertRCReturn(rc, rc);
2705
2706 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2707 AssertRCReturn(rc, rc);
2708
2709 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2710 AssertRCReturn(rc, rc);
2711
2712 AssertCompileSize(HMTPRINSTR, 4);
2713 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2714 AssertRCReturn(rc, rc);
2715
2716 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2717 AssertRCReturn(rc, rc);
2718
2719 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2720 AssertRCReturn(rc, rc);
2721
2722 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2723 AssertRCReturn(rc, rc);
2724
2725 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2726 AssertRCReturn(rc, rc);
2727 }
2728#endif
2729 return VINF_SUCCESS;
2730}
2731
2732
2733/**
2734 * Execute state load operation.
2735 *
2736 * @returns VBox status code.
2737 * @param pVM Pointer to the VM.
2738 * @param pSSM SSM operation handle.
2739 * @param uVersion Data layout version.
2740 * @param uPass The data pass.
2741 */
2742static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2743{
2744 int rc;
2745
2746 Log(("hmR3Load:\n"));
2747 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2748
2749 /*
2750 * Validate version.
2751 */
2752 if ( uVersion != HM_SSM_VERSION
2753 && uVersion != HM_SSM_VERSION_NO_PATCHING
2754 && uVersion != HM_SSM_VERSION_2_0_X)
2755 {
2756 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2757 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2758 }
2759 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2760 {
2761 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2762 AssertRCReturn(rc, rc);
2763 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
2764 AssertRCReturn(rc, rc);
2765 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2766 AssertRCReturn(rc, rc);
2767
2768 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2769 {
2770 uint32_t val;
2771
2772 rc = SSMR3GetU32(pSSM, &val);
2773 AssertRCReturn(rc, rc);
2774 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2775
2776 rc = SSMR3GetU32(pSSM, &val);
2777 AssertRCReturn(rc, rc);
2778 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2779
2780 rc = SSMR3GetU32(pSSM, &val);
2781 AssertRCReturn(rc, rc);
2782 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2783 }
2784 }
2785#ifdef VBOX_HM_WITH_GUEST_PATCHING
2786 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2787 {
2788 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2789 AssertRCReturn(rc, rc);
2790 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2791 AssertRCReturn(rc, rc);
2792 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2793 AssertRCReturn(rc, rc);
2794
2795 /* Fetch all TPR patch records. */
2796 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2797 AssertRCReturn(rc, rc);
2798
2799 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2800 {
2801 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2802
2803 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2804 AssertRCReturn(rc, rc);
2805
2806 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2807 AssertRCReturn(rc, rc);
2808
2809 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2810 AssertRCReturn(rc, rc);
2811
2812 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2813 AssertRCReturn(rc, rc);
2814
2815 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2816 AssertRCReturn(rc, rc);
2817
2818 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2819 AssertRCReturn(rc, rc);
2820
2821 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2822 pVM->hm.s.fTPRPatchingActive = true;
2823
2824 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2825
2826 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2827 AssertRCReturn(rc, rc);
2828
2829 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2830 AssertRCReturn(rc, rc);
2831
2832 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2833 AssertRCReturn(rc, rc);
2834
2835 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2836 AssertRCReturn(rc, rc);
2837
2838 Log(("hmR3Load: patch %d\n", i));
2839 Log(("Key = %x\n", pPatch->Core.Key));
2840 Log(("cbOp = %d\n", pPatch->cbOp));
2841 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2842 Log(("type = %d\n", pPatch->enmType));
2843 Log(("srcop = %d\n", pPatch->uSrcOperand));
2844 Log(("dstop = %d\n", pPatch->uDstOperand));
2845 Log(("cFaults = %d\n", pPatch->cFaults));
2846 Log(("target = %x\n", pPatch->pJumpTarget));
2847 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2848 AssertRC(rc);
2849 }
2850 }
2851#endif
2852
2853 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2854 if (HMIsEnabled(pVM))
2855 {
2856 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2857 {
2858 PVMCPU pVCpu = &pVM->aCpus[i];
2859
2860 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2861 }
2862 }
2863 return VINF_SUCCESS;
2864}
2865
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