VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 45388

Last change on this file since 45388 was 45387, checked in by vboxsync, 12 years ago

VMM/VMMR0: HM bits.
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1/* $Id: HM.cpp 45387 2013-04-05 21:37:40Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/*******************************************************************************
19* Header Files *
20*******************************************************************************/
21#define LOG_GROUP LOG_GROUP_HM
22#include <VBox/vmm/cpum.h>
23#include <VBox/vmm/stam.h>
24#include <VBox/vmm/mm.h>
25#include <VBox/vmm/pdmapi.h>
26#include <VBox/vmm/pgm.h>
27#include <VBox/vmm/ssm.h>
28#include <VBox/vmm/trpm.h>
29#include <VBox/vmm/dbgf.h>
30#include <VBox/vmm/iom.h>
31#include <VBox/vmm/patm.h>
32#include <VBox/vmm/csam.h>
33#include <VBox/vmm/selm.h>
34#ifdef VBOX_WITH_REM
35# include <VBox/vmm/rem.h>
36#endif
37#include <VBox/vmm/hm_vmx.h>
38#include <VBox/vmm/hm_svm.h>
39#include "HMInternal.h"
40#include <VBox/vmm/vm.h>
41#include <VBox/vmm/uvm.h>
42#include <VBox/err.h>
43#include <VBox/param.h>
44
45#include <iprt/assert.h>
46#include <VBox/log.h>
47#include <iprt/asm.h>
48#include <iprt/asm-amd64-x86.h>
49#include <iprt/string.h>
50#include <iprt/env.h>
51#include <iprt/thread.h>
52
53/*******************************************************************************
54* Global Variables *
55*******************************************************************************/
56#ifdef VBOX_WITH_STATISTICS
57# define EXIT_REASON(def, val, str) #def " - " #val " - " str
58# define EXIT_REASON_NIL() NULL
59/** Exit reason descriptions for VT-x, used to describe statistics. */
60static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
61{
62 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
63 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
64 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
65 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
66 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
67 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
68 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
69 EXIT_REASON(VMX_EXIT_IRQ_WINDOW , 7, "Interrupt window."),
70 EXIT_REASON_NIL(),
71 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
72 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
73 EXIT_REASON_NIL(),
74 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
75 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
76 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
77 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
78 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
79 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
80 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
81 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
82 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
83 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
84 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
85 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
86 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
87 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
88 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
89 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
90 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
91 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
92 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
93 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
94 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
95 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
96 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
97 EXIT_REASON_NIL(),
98 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
99 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
100 EXIT_REASON_NIL(),
101 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
102 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
103 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
104 EXIT_REASON_NIL(),
105 EXIT_REASON(VMX_EXIT_TPR , 43, "TPR below threshold. Guest software executed MOV to CR8."),
106 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
107 EXIT_REASON_NIL(),
108 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
109 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
110 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
111 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
112 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
113 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest software attempted to execute RDTSCP."),
114 EXIT_REASON(VMX_EXIT_PREEMPTION_TIMER , 52, "VMX-preemption timer expired. The preemption timer counted down to zero."),
115 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
116 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
117 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
118 EXIT_REASON_NIL(),
119 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND. Guest software attempted to execute RDRAND."),
120 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID. Guest software attempted to execute INVPCID."),
121 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC. Guest software attempted to execute VMFUNC.")
122};
123/** Exit reason descriptions for AMD-V, used to describe statistics. */
124static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
125{
126 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
127 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
128 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
129 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
130 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
131 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
132 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
133 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
134 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
135 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
136 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
137 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
138 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
139 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
140 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
141 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
142 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
143 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
158 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
159 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
160 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
161 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
162 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
163 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
164 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
165 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
166 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
167 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
168 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
169 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
170 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
171 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
172 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
173 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
174 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
175 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
190 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
191 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
222 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
223 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
224 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
225 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
226 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
227 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
228 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
229 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
230 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
231 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
232 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
236 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
237 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
238 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
239 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
240 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
241 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
242 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
243 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
244 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
245 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
246 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
247 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
248 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
249 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
250 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
251 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
252 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
253 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
254 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
255 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
256 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
257 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
258 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
259 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
260 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
261 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
262 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
263 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
264 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
265 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
266 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
267 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
268 EXIT_REASON_NIL()
269};
270# undef EXIT_REASON
271# undef EXIT_REASON_NIL
272#endif /* VBOX_WITH_STATISTICS */
273
274#define VMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
275 do { \
276 if ((allowed1) & (featflag)) \
277 LogRel(("HM: " #featflag "\n")); \
278 else \
279 LogRel(("HM: " #featflag " *must* be cleared\n")); \
280 if ((disallowed0) & (featflag)) \
281 LogRel(("HM: " #featflag " *must* be set\n")); \
282 } while(0)
283
284#define VMX_REPORT_CAPABILITY(msrcaps, cap) \
285 do { \
286 if ((msrcaps) & (cap)) \
287 LogRel(("HM: " #cap "\n")); \
288 } while(0)
289
290/*******************************************************************************
291* Internal Functions *
292*******************************************************************************/
293static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
294static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
295static int hmR3InitCPU(PVM pVM);
296static int hmR3InitFinalizeR0(PVM pVM);
297static int hmR3TermCPU(PVM pVM);
298
299
300/**
301 * Initializes the HM.
302 *
303 * @returns VBox status code.
304 * @param pVM Pointer to the VM.
305 */
306VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
307{
308 LogFlow(("HMR3Init\n"));
309
310 /*
311 * Assert alignment and sizes.
312 */
313 AssertCompileMemberAlignment(VM, hm.s, 32);
314 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
315
316 /* Some structure checks. */
317 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.EventInject) == 0xA8, ("ctrl.EventInject offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.EventInject)));
318 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo) == 0x88, ("ctrl.ExitIntInfo offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.ExitIntInfo)));
319 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl) == 0x58, ("ctrl.TLBCtrl offset = %x\n", RT_OFFSETOF(SVM_VMCB, ctrl.TLBCtrl)));
320
321 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest) == 0x400, ("guest offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest)));
322 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.TR) == 0x490, ("guest.TR offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.TR)));
323 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u8CPL) == 0x4CB, ("guest.u8CPL offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u8CPL)));
324 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64EFER) == 0x4D0, ("guest.u64EFER offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64EFER)));
325 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR4) == 0x548, ("guest.u64CR4 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR4)));
326 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RIP) == 0x578, ("guest.u64RIP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RIP)));
327 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64RSP) == 0x5D8, ("guest.u64RSP offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64RSP)));
328 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64CR2) == 0x640, ("guest.u64CR2 offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64CR2)));
329 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64GPAT) == 0x668, ("guest.u64GPAT offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64GPAT)));
330 AssertReleaseMsg(RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO) == 0x690, ("guest.u64LASTEXCPTO offset = %x\n", RT_OFFSETOF(SVM_VMCB, guest.u64LASTEXCPTO)));
331 AssertReleaseMsg(sizeof(SVM_VMCB) == 0x1000, ("SVM_VMCB size = %x\n", sizeof(SVM_VMCB)));
332
333 /*
334 * Register the saved state data unit.
335 */
336 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
337 NULL, NULL, NULL,
338 NULL, hmR3Save, NULL,
339 NULL, hmR3Load, NULL);
340 if (RT_FAILURE(rc))
341 return rc;
342
343 /* Misc initialisation. */
344 pVM->hm.s.vmx.fSupported = false;
345 pVM->hm.s.svm.fSupported = false;
346 pVM->hm.s.vmx.fEnabled = false;
347 pVM->hm.s.svm.fEnabled = false;
348
349 pVM->hm.s.fNestedPaging = false;
350 pVM->hm.s.fLargePages = false;
351
352 /* Disabled by default. */
353 pVM->fHMEnabled = false;
354
355 /*
356 * Check CFGM options.
357 */
358 PCFGMNODE pRoot = CFGMR3GetRoot(pVM);
359 PCFGMNODE pHWVirtExt = CFGMR3GetChild(pRoot, "HWVirtExt/");
360 /* Nested paging: disabled by default. */
361 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
362 AssertRC(rc);
363
364 /* Large pages: disabled by default. */
365 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableLargePages", &pVM->hm.s.fLargePages, false);
366 AssertRC(rc);
367
368 /* VT-x VPID: disabled by default. */
369 rc = CFGMR3QueryBoolDef(pHWVirtExt, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
370 AssertRC(rc);
371
372 /* HM support must be explicitely enabled in the configuration file. */
373 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Enabled", &pVM->hm.s.fAllowed, false);
374 AssertRC(rc);
375
376 /* TPR patching for 32 bits (Windows) guests with IO-APIC: disabled by default. */
377 rc = CFGMR3QueryBoolDef(pHWVirtExt, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
378 AssertRC(rc);
379
380#ifdef RT_OS_DARWIN
381 if (VMMIsHwVirtExtForced(pVM) != pVM->hm.s.fAllowed)
382#else
383 if (VMMIsHwVirtExtForced(pVM) && !pVM->hm.s.fAllowed)
384#endif
385 {
386 AssertLogRelMsgFailed(("VMMIsHwVirtExtForced=%RTbool fAllowed=%RTbool\n",
387 VMMIsHwVirtExtForced(pVM), pVM->hm.s.fAllowed));
388 return VERR_HM_CONFIG_MISMATCH;
389 }
390
391 if (VMMIsHwVirtExtForced(pVM))
392 pVM->fHMEnabled = true;
393
394#if HC_ARCH_BITS == 32
395 /*
396 * 64-bit mode is configurable and it depends on both the kernel mode and VT-x.
397 * (To use the default, don't set 64bitEnabled in CFGM.)
398 */
399 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, false);
400 AssertLogRelRCReturn(rc, rc);
401 if (pVM->hm.s.fAllow64BitGuests)
402 {
403# ifdef RT_OS_DARWIN
404 if (!VMMIsHwVirtExtForced(pVM))
405# else
406 if (!pVM->hm.s.fAllowed)
407# endif
408 return VM_SET_ERROR(pVM, VERR_INVALID_PARAMETER, "64-bit guest support was requested without also enabling HWVirtEx (VT-x/AMD-V).");
409 }
410#else
411 /*
412 * On 64-bit hosts 64-bit guest support is enabled by default, but allow this to be overridden
413 * via VBoxInternal/HWVirtExt/64bitEnabled=0. (ConsoleImpl2.cpp doesn't set this to false for 64-bit.)*
414 */
415 rc = CFGMR3QueryBoolDef(pHWVirtExt, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, true);
416 AssertLogRelRCReturn(rc, rc);
417#endif
418
419
420 /*
421 * Determine the init method for AMD-V and VT-x; either one global init for each host CPU
422 * or local init each time we wish to execute guest code.
423 *
424 * Default false for Mac OS X and Windows due to the higher risk of conflicts with other hypervisors.
425 */
426 rc = CFGMR3QueryBoolDef(pHWVirtExt, "Exclusive", &pVM->hm.s.fGlobalInit,
427#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
428 false
429#else
430 true
431#endif
432 );
433
434 /* Max number of resume loops. */
435 rc = CFGMR3QueryU32Def(pHWVirtExt, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
436 AssertRC(rc);
437
438 return rc;
439}
440
441
442/**
443 * Initializes the per-VCPU HM.
444 *
445 * @returns VBox status code.
446 * @param pVM Pointer to the VM.
447 */
448static int hmR3InitCPU(PVM pVM)
449{
450 LogFlow(("HMR3InitCPU\n"));
451
452 for (VMCPUID i = 0; i < pVM->cCpus; i++)
453 {
454 PVMCPU pVCpu = &pVM->aCpus[i];
455
456 pVCpu->hm.s.fActive = false;
457 }
458
459#ifdef VBOX_WITH_STATISTICS
460 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
461 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
462 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
463 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
464
465 /*
466 * Statistics.
467 */
468 for (VMCPUID i = 0; i < pVM->cCpus; i++)
469 {
470 PVMCPU pVCpu = &pVM->aCpus[i];
471 int rc;
472
473 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
474 "Profiling of RTMpPokeCpu",
475 "/PROF/HM/CPU%d/Poke", i);
476 AssertRC(rc);
477 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
478 "Profiling of poke wait",
479 "/PROF/HM/CPU%d/PokeWait", i);
480 AssertRC(rc);
481 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
482 "Profiling of poke wait when RTMpPokeCpu fails",
483 "/PROF/HM/CPU%d/PokeWaitFailed", i);
484 AssertRC(rc);
485 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
486 "Profiling of VMXR0RunGuestCode entry",
487 "/PROF/HM/CPU%d/StatEntry", i);
488 AssertRC(rc);
489 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
490 "Profiling of VMXR0RunGuestCode exit part 1",
491 "/PROF/HM/CPU%d/SwitchFromGC_1", i);
492 AssertRC(rc);
493 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
494 "Profiling of VMXR0RunGuestCode exit part 2",
495 "/PROF/HM/CPU%d/SwitchFromGC_2", i);
496 AssertRC(rc);
497# ifdef VBOX_WITH_OLD_VTX_CODE
498 /* temporary for tracking down darwin holdup. */
499 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
500 "Temporary - I/O",
501 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub1", i);
502 AssertRC(rc);
503 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
504 "Temporary - CRx RWs",
505 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub2", i);
506 AssertRC(rc);
507 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2Sub3, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
508 "Temporary - Exceptions",
509 "/PROF/HM/CPU%d/SwitchFromGC_2/Sub3", i);
510 AssertRC(rc);
511# endif
512 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
513 "Profiling of VMXR0LoadGuestState",
514 "/PROF/HM/CPU%d/StatLoadGuestState", i);
515 AssertRC(rc);
516 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
517 "Profiling of vmlaunch/vmresume",
518 "/PROF/HM/CPU%d/InGC", i);
519 AssertRC(rc);
520
521# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
522 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
523 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
524 "/PROF/HM/CPU%d/Switcher3264", i);
525 AssertRC(rc);
526# endif
527
528# define HM_REG_COUNTER(a, b) \
529 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of vmlaunch", b, i); \
530 AssertRC(rc);
531
532 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
533 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
534 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
535 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
536 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
537 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
538 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
539 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
540 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
541 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
542 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
543 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
544 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
545 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
546 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
547 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
548 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
549 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd");
550 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause");
551 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
552 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
553 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
554 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
555 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand");
556 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
557 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
558 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
559 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
560 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
561 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
562 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
563 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW");
564 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
565 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
566 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
567 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
568 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
569 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
570 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
571 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess");
572 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
573 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
574 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
575 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
576 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow");
577 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
578 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt");
579 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer");
580 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold");
581 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch");
582 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
583 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess");
584
585 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
586 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF");
587 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3");
588 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3");
589
590 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
591 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
592 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
593
594 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
595 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
596 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
597 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
598 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
599 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Switch");
600 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
601 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
602 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
603 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt");
604 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys");
605 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
606 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
607
608 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
609 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
610 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
611
612 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
613 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
614 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
615
616 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
617 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
618
619#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
620 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
621 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
622#endif
623
624 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
625 {
626 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
627 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
628 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
629 AssertRC(rc);
630 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
631 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
632 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
633 AssertRC(rc);
634 }
635
636#undef HM_REG_COUNTER
637
638 pVCpu->hm.s.paStatExitReason = NULL;
639
640 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
641 (void **)&pVCpu->hm.s.paStatExitReason);
642 AssertRC(rc);
643 if (RT_SUCCESS(rc))
644 {
645 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
646 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
647 {
648 if (papszDesc[j])
649 {
650 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
651 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
652 AssertRC(rc);
653 }
654 }
655 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
656 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
657 AssertRC(rc);
658 }
659 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
660# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
661 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
662# else
663 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
664# endif
665
666 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
667 AssertRCReturn(rc, rc);
668 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
669# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
670 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !VMMIsHwVirtExtForced(pVM));
671# else
672 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
673# endif
674 for (unsigned j = 0; j < 255; j++)
675 {
676 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
677 "Forwarded interrupts.",
678 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
679 }
680
681 }
682#endif /* VBOX_WITH_STATISTICS */
683
684#ifdef VBOX_WITH_CRASHDUMP_MAGIC
685 /* Magic marker for searching in crash dumps. */
686 for (VMCPUID i = 0; i < pVM->cCpus; i++)
687 {
688 PVMCPU pVCpu = &pVM->aCpus[i];
689
690 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
691 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
692 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
693 }
694#endif
695 return VINF_SUCCESS;
696}
697
698
699/**
700 * Called when a init phase has completed.
701 *
702 * @returns VBox status code.
703 * @param pVM The VM.
704 * @param enmWhat The phase that completed.
705 */
706VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
707{
708 switch (enmWhat)
709 {
710 case VMINITCOMPLETED_RING3:
711 return hmR3InitCPU(pVM);
712 case VMINITCOMPLETED_RING0:
713 return hmR3InitFinalizeR0(pVM);
714 default:
715 return VINF_SUCCESS;
716 }
717}
718
719
720/**
721 * Turns off normal raw mode features.
722 *
723 * @param pVM Pointer to the VM.
724 */
725static void hmR3DisableRawMode(PVM pVM)
726{
727 /* Disable PATM & CSAM. */
728 PATMR3AllowPatching(pVM->pUVM, false);
729 CSAMDisableScanning(pVM);
730
731 /* Turn off IDT/LDT/GDT and TSS monitoring and sycing. */
732 SELMR3DisableMonitoring(pVM);
733 TRPMR3DisableMonitoring(pVM);
734
735 /* Disable the switcher code (safety precaution). */
736 VMMR3DisableSwitcher(pVM);
737
738 /* Disable mapping of the hypervisor into the shadow page table. */
739 PGMR3MappingsDisable(pVM);
740
741 /* Disable the switcher */
742 VMMR3DisableSwitcher(pVM);
743
744 /* Reinit the paging mode to force the new shadow mode. */
745 for (VMCPUID i = 0; i < pVM->cCpus; i++)
746 {
747 PVMCPU pVCpu = &pVM->aCpus[i];
748
749 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
750 }
751}
752
753
754/**
755 * Initialize VT-x or AMD-V.
756 *
757 * @returns VBox status code.
758 * @param pVM Pointer to the VM.
759 */
760static int hmR3InitFinalizeR0(PVM pVM)
761{
762 int rc;
763
764 /*
765 * Hack to allow users to work around broken BIOSes that incorrectly set EFER.SVME, which makes us believe somebody else
766 * is already using AMD-V.
767 */
768 if ( !pVM->hm.s.vmx.fSupported
769 && !pVM->hm.s.svm.fSupported
770 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
771 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
772 {
773 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
774 pVM->hm.s.svm.fSupported = true;
775 pVM->hm.s.svm.fIgnoreInUseError = true;
776 }
777 else
778 if ( !pVM->hm.s.vmx.fSupported
779 && !pVM->hm.s.svm.fSupported)
780 {
781 LogRel(("HM: No VT-x or AMD-V CPU extension found. Reason %Rrc\n", pVM->hm.s.lLastError));
782 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
783
784 if (VMMIsHwVirtExtForced(pVM))
785 {
786 switch (pVM->hm.s.lLastError)
787 {
788 case VERR_VMX_NO_VMX:
789 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
790 case VERR_VMX_IN_VMX_ROOT_MODE:
791 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
792 case VERR_SVM_IN_USE:
793 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
794 case VERR_SVM_NO_SVM:
795 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
796 case VERR_SVM_DISABLED:
797 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
798 default:
799 return pVM->hm.s.lLastError;
800 }
801 }
802 return VINF_SUCCESS;
803 }
804
805 if (pVM->hm.s.vmx.fSupported)
806 {
807 rc = SUPR3QueryVTxSupported();
808 if (RT_FAILURE(rc))
809 {
810#ifdef RT_OS_LINUX
811 LogRel(("HM: The host kernel does not support VT-x -- Linux 2.6.13 or newer required!\n"));
812#else
813 LogRel(("HM: The host kernel does not support VT-x!\n"));
814#endif
815 if ( pVM->cCpus > 1
816 || VMMIsHwVirtExtForced(pVM))
817 return rc;
818
819 /* silently fall back to raw mode */
820 return VINF_SUCCESS;
821 }
822 }
823
824 if (!pVM->hm.s.fAllowed)
825 return VINF_SUCCESS; /* nothing to do */
826
827 /* Enable VT-x or AMD-V on all host CPUs. */
828 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
829 if (RT_FAILURE(rc))
830 {
831 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
832 return rc;
833 }
834 Assert(!pVM->fHMEnabled || VMMIsHwVirtExtForced(pVM));
835
836 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
837 /* No TPR patching is required when the IO-APIC is not enabled for this VM. (Main should have taken care of this already) */
838 if (!pVM->hm.s.fHasIoApic)
839 {
840 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
841 pVM->hm.s.fTRPPatchingAllowed = false;
842 }
843
844 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
845 if (pVM->hm.s.vmx.fSupported)
846 {
847 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
848
849 if ( pVM->hm.s.fInitialized == false
850 && pVM->hm.s.vmx.msr.feature_ctrl != 0)
851 {
852 uint64_t val;
853 uint64_t zap;
854 RTGCPHYS GCPhys = 0;
855
856 LogRel(("HM: Host CR4=%08X\n", pVM->hm.s.vmx.hostCR4));
857 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
858 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
859 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
860 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
861 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
862 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
863 LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
864 LogRel(("HM: Max resume loops = %RX32\n", pVM->hm.s.cMaxResumeLoops));
865
866 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
867 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
868 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
869 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT);
870 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT);
871 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI);
872 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER);
873
874 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
875 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
876 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
877 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT);
878 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TSC_OFFSETTING);
879 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT);
880 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT);
881 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT);
882 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT);
883 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT);
884 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT);
885 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
886 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT);
887 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT);
888 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW);
889 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT);
890 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
891 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT);
892 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS);
893 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG);
894 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS);
895 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT);
896 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT);
897 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
898 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
899 {
900 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
901 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
902 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
903 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
904 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
905 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
906 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
907 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
908 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
909 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
910 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
911 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
912 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
913 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
914 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
915 }
916
917 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
918 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
919 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
920 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG);
921 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST);
922 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM);
923 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON);
924 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR);
925 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR);
926 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR);
927
928 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
929 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
930 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
931 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG);
932 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE);
933 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR);
934 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT);
935 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR);
936 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR);
937 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR);
938 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR);
939 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER);
940
941 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
942 {
943 val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
944 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", val));
945 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
946 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
947 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
948 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
949 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
950 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
951 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
952 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
953 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
954 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
955 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
956 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
957 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
958 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
959 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
960 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
961 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
962 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
963 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
964 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
965 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
966 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
967 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
968 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
969 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
970 }
971
972 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
973 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
974 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
975 else
976 {
977 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
978 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
979 }
980
981 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
982 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
983 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
984 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
985
986 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
987 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
988 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
989 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
990 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
991
992 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
993
994 /* Paranoia */
995 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
996
997 for (VMCPUID i = 0; i < pVM->cCpus; i++)
998 {
999 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1000 LogRel(("HM: VCPU%3d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1001 }
1002
1003 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1004 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1005
1006 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1007 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1008
1009 /*
1010 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1011 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1012 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1013 */
1014 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1015 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1016 {
1017 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1018 LogRel(("HM: Disabled RDTSCP\n"));
1019 }
1020
1021 /* Unrestricted guest execution relies on EPT. */
1022 if ( pVM->hm.s.fNestedPaging
1023 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1024 {
1025 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1026 }
1027
1028 /* Only try once. */
1029 pVM->hm.s.fInitialized = true;
1030
1031 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1032 {
1033 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1034 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1035 if (RT_SUCCESS(rc))
1036 {
1037 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap. */
1038 /* Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode" esp. Figure 20-5.*/
1039 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1040 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1041 /* Bit set to 0 means software interrupts are redirected to the 8086 program interrupt handler rather than
1042 switching to protected-mode handler. */
1043 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1044 /* Allow all port IO, so that port IO instructions do not cause exceptions and would instead
1045 cause a VM-exit (based on VT-x's IO bitmap which we currently configure to always cause an exit). */
1046 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1047 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1048
1049 /*
1050 * Construct a 1024 element page directory with 4 MB pages for the identity mapped page table used in
1051 * real and protected mode without paging with EPT.
1052 */
1053 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1054 for (unsigned i = 0; i < X86_PG_ENTRIES; i++)
1055 {
1056 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1057 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1058 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1059 | X86_PDE4M_G;
1060 }
1061
1062 /* We convert it here every time as pci regions could be reconfigured. */
1063 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1064 AssertRC(rc);
1065 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1066
1067 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1068 AssertRC(rc);
1069 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1070 }
1071 else
1072 {
1073 /** @todo This cannot possibly work, there are other places which assumes
1074 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1075 * a failure case. */
1076 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1077 pVM->hm.s.vmx.pRealModeTSS = NULL;
1078 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1079 }
1080 }
1081
1082 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1083 AssertRC(rc);
1084 if (rc == VINF_SUCCESS)
1085 {
1086 pVM->fHMEnabled = true;
1087 pVM->hm.s.vmx.fEnabled = true;
1088 hmR3DisableRawMode(pVM);
1089
1090 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1091#ifdef VBOX_ENABLE_64_BITS_GUESTS
1092 if (pVM->hm.s.fAllow64BitGuests)
1093 {
1094 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1095 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1096 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1097 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1098 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1099# if RT_ARCH_X86
1100 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1101 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1102 LogRel(("NX is only supported for 64-bit guests!\n"));
1103# endif
1104 }
1105 else
1106 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE (we reuse the host EFER in the switcher) */
1107 /* Todo: this needs to be fixed properly!! */
1108 if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1109 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1110 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1111 else
1112 LogRel(("HM: NX not supported by the host\n"));
1113
1114 LogRel((pVM->hm.s.fAllow64BitGuests
1115 ? "HM: 32-bit and 64-bit guests supported.\n"
1116 : "HM: 32-bit guests supported.\n"));
1117#else
1118 LogRel(("HM: 32-bit guests supported.\n"));
1119#endif
1120 LogRel(("HM: VMX enabled!\n"));
1121 if (pVM->hm.s.fNestedPaging)
1122 {
1123 LogRel(("HM: Nested paging enabled!\n"));
1124 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1125 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1126 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1127 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1128 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1129 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1130 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1131 else
1132 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1133
1134 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1135 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1136
1137#if HC_ARCH_BITS == 64
1138 if (pVM->hm.s.fLargePages)
1139 {
1140 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1141 PGMSetLargePageUsage(pVM, true);
1142 LogRel(("HM: Large page support enabled!\n"));
1143 }
1144#endif
1145 }
1146 else
1147 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1148
1149 if (pVM->hm.s.vmx.fVpid)
1150 {
1151 LogRel(("HM: VPID enabled!\n"));
1152 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1153 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1154 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1155 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1156 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1157 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1158 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1159 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1160 else
1161 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1162 }
1163 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1164 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1165
1166 /* TPR patching status logging. */
1167 if (pVM->hm.s.fTRPPatchingAllowed)
1168 {
1169 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1170 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1171 {
1172 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1173 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1174 }
1175 else
1176 {
1177 uint32_t u32Eax, u32Dummy;
1178
1179 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1180 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1181 if ( u32Eax < 0x80000001
1182 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1183 {
1184 pVM->hm.s.fTRPPatchingAllowed = false;
1185 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1186 }
1187 }
1188 }
1189 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1190
1191 /*
1192 * Check for preemption timer config override and log the state of it.
1193 */
1194 if (pVM->hm.s.vmx.fUsePreemptTimer)
1195 {
1196 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1197 int rc2 = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1198 AssertLogRelRC(rc2);
1199 }
1200 if (pVM->hm.s.vmx.fUsePreemptTimer)
1201 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1202 }
1203 else
1204 {
1205 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1206 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1207 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1208 pVM->fHMEnabled = false;
1209 }
1210 }
1211 }
1212 else
1213 if (pVM->hm.s.svm.fSupported)
1214 {
1215 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1216
1217 if (pVM->hm.s.fInitialized == false)
1218 {
1219 /* Erratum 170 which requires a forced TLB flush for each world switch:
1220 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1221 *
1222 * All BH-G1/2 and DH-G1/2 models include a fix:
1223 * Athlon X2: 0x6b 1/2
1224 * 0x68 1/2
1225 * Athlon 64: 0x7f 1
1226 * 0x6f 2
1227 * Sempron: 0x7f 1/2
1228 * 0x6f 2
1229 * 0x6c 2
1230 * 0x7c 2
1231 * Turion 64: 0x68 2
1232 *
1233 */
1234 uint32_t u32Dummy;
1235 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1236 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1237 u32BaseFamily= (u32Version >> 8) & 0xf;
1238 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1239 u32Model = ((u32Version >> 4) & 0xf);
1240 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1241 u32Stepping = u32Version & 0xf;
1242 if ( u32Family == 0xf
1243 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1244 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1245 {
1246 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1247 }
1248
1249 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1250 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1251 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1252 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1253 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1254 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1255 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1256 {
1257#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1258 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1259 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1260 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1261 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1262 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1263 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1264 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1265 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1266 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1267 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1268 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1269#undef FLAG_NAME
1270 };
1271 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1272 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1273 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1274 {
1275 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1276 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1277 }
1278 if (fSvmFeatures)
1279 for (unsigned iBit = 0; iBit < 32; iBit++)
1280 if (RT_BIT_32(iBit) & fSvmFeatures)
1281 LogRel(("HM: Reserved bit %u\n", iBit));
1282
1283 /* Only try once. */
1284 pVM->hm.s.fInitialized = true;
1285
1286 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1287 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1288
1289 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1290 AssertRC(rc);
1291 if (rc == VINF_SUCCESS)
1292 {
1293 pVM->fHMEnabled = true;
1294 pVM->hm.s.svm.fEnabled = true;
1295
1296 if (pVM->hm.s.fNestedPaging)
1297 {
1298 LogRel(("HM: Enabled nested paging!\n"));
1299#if HC_ARCH_BITS == 64
1300 if (pVM->hm.s.fLargePages)
1301 {
1302 /* Use large (2 MB) pages for our nested paging PDEs where possible. */
1303 PGMSetLargePageUsage(pVM, true);
1304 LogRel(("HM: Large page support enabled!\n"));
1305 }
1306#endif
1307 }
1308
1309 hmR3DisableRawMode(pVM);
1310 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1311 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1312#ifdef VBOX_ENABLE_64_BITS_GUESTS
1313 if (pVM->hm.s.fAllow64BitGuests)
1314 {
1315 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1316 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1317 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1318 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1319 }
1320 else
1321 /* Turn on NXE if PAE has been enabled. */
1322 if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1323 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1324#endif
1325
1326 LogRel((pVM->hm.s.fAllow64BitGuests
1327 ? "HM: 32-bit and 64-bit guest supported.\n"
1328 : "HM: 32-bit guest supported.\n"));
1329
1330 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1331 }
1332 else
1333 {
1334 pVM->fHMEnabled = false;
1335 }
1336 }
1337 }
1338 if (pVM->fHMEnabled)
1339 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1340 RTLogRelSetBuffering(fOldBuffered);
1341 return VINF_SUCCESS;
1342}
1343
1344
1345/**
1346 * Applies relocations to data and code managed by this
1347 * component. This function will be called at init and
1348 * whenever the VMM need to relocate it self inside the GC.
1349 *
1350 * @param pVM The VM.
1351 */
1352VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1353{
1354 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1355
1356 /* Fetch the current paging mode during the relocate callback during state loading. */
1357 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1358 {
1359 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1360 {
1361 PVMCPU pVCpu = &pVM->aCpus[i];
1362
1363 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1364 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1365 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1366 }
1367 }
1368#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1369 if (pVM->fHMEnabled)
1370 {
1371 int rc;
1372 switch (PGMGetHostMode(pVM))
1373 {
1374 case PGMMODE_32_BIT:
1375 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1376 break;
1377
1378 case PGMMODE_PAE:
1379 case PGMMODE_PAE_NX:
1380 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1381 break;
1382
1383 default:
1384 AssertFailed();
1385 break;
1386 }
1387 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1388 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1389
1390 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1391 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1392
1393 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1394 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1395
1396 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1397 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1398
1399# ifdef DEBUG
1400 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1401 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1402# endif
1403 }
1404#endif
1405 return;
1406}
1407
1408
1409/**
1410 * Checks if hardware accelerated raw mode is allowed.
1411 *
1412 * @returns true if hardware acceleration is allowed, otherwise false.
1413 * @param pVM Pointer to the VM.
1414 */
1415VMMR3_INT_DECL(bool) HMR3IsAllowed(PVM pVM)
1416{
1417 return pVM->hm.s.fAllowed;
1418}
1419
1420
1421/**
1422 * Notification callback which is called whenever there is a chance that a CR3
1423 * value might have changed.
1424 *
1425 * This is called by PGM.
1426 *
1427 * @param pVM Pointer to the VM.
1428 * @param pVCpu Pointer to the VMCPU.
1429 * @param enmShadowMode New shadow paging mode.
1430 * @param enmGuestMode New guest paging mode.
1431 */
1432VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1433{
1434 /* Ignore page mode changes during state loading. */
1435 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1436 return;
1437
1438 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1439
1440#ifdef VBOX_WITH_OLD_VTX_CODE
1441 if ( pVM->hm.s.vmx.fEnabled
1442 && pVM->fHMEnabled)
1443 {
1444 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1445 && enmGuestMode >= PGMMODE_PROTECTED)
1446 {
1447 PCPUMCTX pCtx;
1448
1449 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1450
1451 /* After a real mode switch to protected mode we must force
1452 CPL to 0. Our real mode emulation had to set it to 3. */
1453 pCtx->ss.Attr.n.u2Dpl = 0;
1454 }
1455 }
1456#endif
1457
1458 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1459 {
1460 /* Keep track of paging mode changes. */
1461 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1462 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1463
1464 /* Did we miss a change, because all code was executed in the recompiler? */
1465 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1466 {
1467 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1468 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1469 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1470 }
1471 }
1472
1473 /** @todo r=ramshankar: Why do we need to do this? Most likely
1474 * VBOX_WITH_OLD_VTX_CODE only. */
1475 /* Reset the contents of the read cache. */
1476 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1477 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1478 pCache->Read.aFieldVal[j] = 0;
1479}
1480
1481
1482/**
1483 * Terminates the HM.
1484 *
1485 * Termination means cleaning up and freeing all resources,
1486 * the VM itself is, at this point, powered off or suspended.
1487 *
1488 * @returns VBox status code.
1489 * @param pVM Pointer to the VM.
1490 */
1491VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1492{
1493 if (pVM->hm.s.vmx.pRealModeTSS)
1494 {
1495 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1496 pVM->hm.s.vmx.pRealModeTSS = 0;
1497 }
1498 hmR3TermCPU(pVM);
1499 return 0;
1500}
1501
1502
1503/**
1504 * Terminates the per-VCPU HM.
1505 *
1506 * @returns VBox status code.
1507 * @param pVM Pointer to the VM.
1508 */
1509static int hmR3TermCPU(PVM pVM)
1510{
1511 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1512 {
1513 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1514
1515#ifdef VBOX_WITH_STATISTICS
1516 if (pVCpu->hm.s.paStatExitReason)
1517 {
1518 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1519 pVCpu->hm.s.paStatExitReason = NULL;
1520 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1521 }
1522 if (pVCpu->hm.s.paStatInjectedIrqs)
1523 {
1524 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1525 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1526 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1527 }
1528#endif
1529
1530#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1531 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1532 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1533 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1534#endif
1535 }
1536 return 0;
1537}
1538
1539
1540/**
1541 * Resets a virtual CPU.
1542 *
1543 * Used by HMR3Reset and CPU hot plugging.
1544 *
1545 * @param pVCpu The CPU to reset.
1546 */
1547VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1548{
1549 /* On first entry we'll sync everything. */
1550 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1551
1552 pVCpu->hm.s.vmx.cr0_mask = 0;
1553 pVCpu->hm.s.vmx.cr4_mask = 0;
1554
1555 pVCpu->hm.s.fActive = false;
1556 pVCpu->hm.s.Event.fPending = false;
1557
1558 /* Reset state information for real-mode emulation in VT-x. */
1559 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1560 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1561 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1562
1563 /* Reset the contents of the read cache. */
1564 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1565 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1566 pCache->Read.aFieldVal[j] = 0;
1567
1568#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1569 /* Magic marker for searching in crash dumps. */
1570 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1571 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1572#endif
1573}
1574
1575
1576/**
1577 * The VM is being reset.
1578 *
1579 * For the HM component this means that any GDT/LDT/TSS monitors
1580 * needs to be removed.
1581 *
1582 * @param pVM Pointer to the VM.
1583 */
1584VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1585{
1586 LogFlow(("HMR3Reset:\n"));
1587
1588 if (pVM->fHMEnabled)
1589 hmR3DisableRawMode(pVM);
1590
1591 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1592 {
1593 PVMCPU pVCpu = &pVM->aCpus[i];
1594
1595 HMR3ResetCpu(pVCpu);
1596 }
1597
1598 /* Clear all patch information. */
1599 pVM->hm.s.pGuestPatchMem = 0;
1600 pVM->hm.s.pFreeGuestPatchMem = 0;
1601 pVM->hm.s.cbGuestPatchMem = 0;
1602 pVM->hm.s.cPatches = 0;
1603 pVM->hm.s.PatchTree = 0;
1604 pVM->hm.s.fTPRPatchingActive = false;
1605 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1606}
1607
1608
1609/**
1610 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1611 *
1612 * @returns VBox strict status code.
1613 * @param pVM Pointer to the VM.
1614 * @param pVCpu The VMCPU for the EMT we're being called on.
1615 * @param pvUser Unused.
1616 */
1617DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1618{
1619 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1620
1621 /* Only execute the handler on the VCPU the original patch request was issued. */
1622 if (pVCpu->idCpu != idCpu)
1623 return VINF_SUCCESS;
1624
1625 Log(("hmR3RemovePatches\n"));
1626 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1627 {
1628 uint8_t abInstr[15];
1629 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1630 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1631 int rc;
1632
1633#ifdef LOG_ENABLED
1634 char szOutput[256];
1635
1636 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1637 szOutput, sizeof(szOutput), NULL);
1638 if (RT_SUCCESS(rc))
1639 Log(("Patched instr: %s\n", szOutput));
1640#endif
1641
1642 /* Check if the instruction is still the same. */
1643 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1644 if (rc != VINF_SUCCESS)
1645 {
1646 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1647 continue; /* swapped out or otherwise removed; skip it. */
1648 }
1649
1650 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1651 {
1652 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1653 continue; /* skip it. */
1654 }
1655
1656 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1657 AssertRC(rc);
1658
1659#ifdef LOG_ENABLED
1660 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1661 szOutput, sizeof(szOutput), NULL);
1662 if (RT_SUCCESS(rc))
1663 Log(("Original instr: %s\n", szOutput));
1664#endif
1665 }
1666 pVM->hm.s.cPatches = 0;
1667 pVM->hm.s.PatchTree = 0;
1668 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1669 pVM->hm.s.fTPRPatchingActive = false;
1670 return VINF_SUCCESS;
1671}
1672
1673
1674/**
1675 * Worker for enabling patching in a VT-x/AMD-V guest.
1676 *
1677 * @returns VBox status code.
1678 * @param pVM Pointer to the VM.
1679 * @param idCpu VCPU to execute hmR3RemovePatches on.
1680 * @param pPatchMem Patch memory range.
1681 * @param cbPatchMem Size of the memory range.
1682 */
1683static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1684{
1685 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1686 AssertRC(rc);
1687
1688 pVM->hm.s.pGuestPatchMem = pPatchMem;
1689 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1690 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1691 return VINF_SUCCESS;
1692}
1693
1694
1695/**
1696 * Enable patching in a VT-x/AMD-V guest
1697 *
1698 * @returns VBox status code.
1699 * @param pVM Pointer to the VM.
1700 * @param pPatchMem Patch memory range.
1701 * @param cbPatchMem Size of the memory range.
1702 */
1703VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1704{
1705 VM_ASSERT_EMT(pVM);
1706 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1707 if (pVM->cCpus > 1)
1708 {
1709 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1710 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1711 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1712 AssertRC(rc);
1713 return rc;
1714 }
1715 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1716}
1717
1718
1719/**
1720 * Disable patching in a VT-x/AMD-V guest.
1721 *
1722 * @returns VBox status code.
1723 * @param pVM Pointer to the VM.
1724 * @param pPatchMem Patch memory range.
1725 * @param cbPatchMem Size of the memory range.
1726 */
1727VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1728{
1729 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1730
1731 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1732 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1733
1734 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1735 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1736 (void *)(uintptr_t)VMMGetCpuId(pVM));
1737 AssertRC(rc);
1738
1739 pVM->hm.s.pGuestPatchMem = 0;
1740 pVM->hm.s.pFreeGuestPatchMem = 0;
1741 pVM->hm.s.cbGuestPatchMem = 0;
1742 pVM->hm.s.fTPRPatchingActive = false;
1743 return VINF_SUCCESS;
1744}
1745
1746
1747/**
1748 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1749 *
1750 * @returns VBox strict status code.
1751 * @param pVM Pointer to the VM.
1752 * @param pVCpu The VMCPU for the EMT we're being called on.
1753 * @param pvUser User specified CPU context.
1754 *
1755 */
1756DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1757{
1758 /*
1759 * Only execute the handler on the VCPU the original patch request was
1760 * issued. (The other CPU(s) might not yet have switched to protected
1761 * mode, nor have the correct memory context.)
1762 */
1763 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1764 if (pVCpu->idCpu != idCpu)
1765 return VINF_SUCCESS;
1766
1767 /*
1768 * We're racing other VCPUs here, so don't try patch the instruction twice
1769 * and make sure there is still room for our patch record.
1770 */
1771 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1772 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1773 if (pPatch)
1774 {
1775 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1776 return VINF_SUCCESS;
1777 }
1778 uint32_t const idx = pVM->hm.s.cPatches;
1779 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1780 {
1781 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1782 return VINF_SUCCESS;
1783 }
1784 pPatch = &pVM->hm.s.aPatches[idx];
1785
1786 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1787
1788 /*
1789 * Disassembler the instruction and get cracking.
1790 */
1791 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1792 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1793 uint32_t cbOp;
1794 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1795 AssertRC(rc);
1796 if ( rc == VINF_SUCCESS
1797 && pDis->pCurInstr->uOpcode == OP_MOV
1798 && cbOp >= 3)
1799 {
1800 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1801
1802 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1803 AssertRC(rc);
1804
1805 pPatch->cbOp = cbOp;
1806
1807 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1808 {
1809 /* write. */
1810 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1811 {
1812 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1813 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1814 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1815 }
1816 else
1817 {
1818 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1819 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1820 pPatch->uSrcOperand = pDis->Param2.uValue;
1821 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1822 }
1823 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1824 AssertRC(rc);
1825
1826 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1827 pPatch->cbNewOp = sizeof(s_abVMMCall);
1828 }
1829 else
1830 {
1831 /*
1832 * TPR Read.
1833 *
1834 * Found:
1835 * mov eax, dword [fffe0080] (5 bytes)
1836 * Check if next instruction is:
1837 * shr eax, 4
1838 */
1839 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1840
1841 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1842 uint8_t const cbOpMmio = cbOp;
1843 uint64_t const uSavedRip = pCtx->rip;
1844
1845 pCtx->rip += cbOp;
1846 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1847 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1848 pCtx->rip = uSavedRip;
1849
1850 if ( rc == VINF_SUCCESS
1851 && pDis->pCurInstr->uOpcode == OP_SHR
1852 && pDis->Param1.fUse == DISUSE_REG_GEN32
1853 && pDis->Param1.Base.idxGenReg == idxMmioReg
1854 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1855 && pDis->Param2.uValue == 4
1856 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1857 {
1858 uint8_t abInstr[15];
1859
1860 /* Replacing two instructions now. */
1861 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1862 AssertRC(rc);
1863
1864 pPatch->cbOp = cbOpMmio + cbOp;
1865
1866 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1867 abInstr[0] = 0xF0;
1868 abInstr[1] = 0x0F;
1869 abInstr[2] = 0x20;
1870 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1871 for (unsigned i = 4; i < pPatch->cbOp; i++)
1872 abInstr[i] = 0x90; /* nop */
1873
1874 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1875 AssertRC(rc);
1876
1877 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1878 pPatch->cbNewOp = pPatch->cbOp;
1879
1880 Log(("Acceptable read/shr candidate!\n"));
1881 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1882 }
1883 else
1884 {
1885 pPatch->enmType = HMTPRINSTR_READ;
1886 pPatch->uDstOperand = idxMmioReg;
1887
1888 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1889 AssertRC(rc);
1890
1891 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1892 pPatch->cbNewOp = sizeof(s_abVMMCall);
1893 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1894 }
1895 }
1896
1897 pPatch->Core.Key = pCtx->eip;
1898 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1899 AssertRC(rc);
1900
1901 pVM->hm.s.cPatches++;
1902 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1903 return VINF_SUCCESS;
1904 }
1905
1906 /*
1907 * Save invalid patch, so we will not try again.
1908 */
1909 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1910 pPatch->Core.Key = pCtx->eip;
1911 pPatch->enmType = HMTPRINSTR_INVALID;
1912 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1913 AssertRC(rc);
1914 pVM->hm.s.cPatches++;
1915 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1916 return VINF_SUCCESS;
1917}
1918
1919
1920/**
1921 * Callback to patch a TPR instruction (jump to generated code).
1922 *
1923 * @returns VBox strict status code.
1924 * @param pVM Pointer to the VM.
1925 * @param pVCpu The VMCPU for the EMT we're being called on.
1926 * @param pvUser User specified CPU context.
1927 *
1928 */
1929DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1930{
1931 /*
1932 * Only execute the handler on the VCPU the original patch request was
1933 * issued. (The other CPU(s) might not yet have switched to protected
1934 * mode, nor have the correct memory context.)
1935 */
1936 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1937 if (pVCpu->idCpu != idCpu)
1938 return VINF_SUCCESS;
1939
1940 /*
1941 * We're racing other VCPUs here, so don't try patch the instruction twice
1942 * and make sure there is still room for our patch record.
1943 */
1944 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1945 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1946 if (pPatch)
1947 {
1948 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
1949 return VINF_SUCCESS;
1950 }
1951 uint32_t const idx = pVM->hm.s.cPatches;
1952 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1953 {
1954 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1955 return VINF_SUCCESS;
1956 }
1957 pPatch = &pVM->hm.s.aPatches[idx];
1958
1959 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1960 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
1961
1962 /*
1963 * Disassemble the instruction and get cracking.
1964 */
1965 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1966 uint32_t cbOp;
1967 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1968 AssertRC(rc);
1969 if ( rc == VINF_SUCCESS
1970 && pDis->pCurInstr->uOpcode == OP_MOV
1971 && cbOp >= 5)
1972 {
1973 uint8_t aPatch[64];
1974 uint32_t off = 0;
1975
1976 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1977 AssertRC(rc);
1978
1979 pPatch->cbOp = cbOp;
1980 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
1981
1982 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1983 {
1984 /*
1985 * TPR write:
1986 *
1987 * push ECX [51]
1988 * push EDX [52]
1989 * push EAX [50]
1990 * xor EDX,EDX [31 D2]
1991 * mov EAX,EAX [89 C0]
1992 * or
1993 * mov EAX,0000000CCh [B8 CC 00 00 00]
1994 * mov ECX,0C0000082h [B9 82 00 00 C0]
1995 * wrmsr [0F 30]
1996 * pop EAX [58]
1997 * pop EDX [5A]
1998 * pop ECX [59]
1999 * jmp return_address [E9 return_address]
2000 *
2001 */
2002 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2003
2004 aPatch[off++] = 0x51; /* push ecx */
2005 aPatch[off++] = 0x52; /* push edx */
2006 if (!fUsesEax)
2007 aPatch[off++] = 0x50; /* push eax */
2008 aPatch[off++] = 0x31; /* xor edx, edx */
2009 aPatch[off++] = 0xD2;
2010 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2011 {
2012 if (!fUsesEax)
2013 {
2014 aPatch[off++] = 0x89; /* mov eax, src_reg */
2015 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2016 }
2017 }
2018 else
2019 {
2020 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2021 aPatch[off++] = 0xB8; /* mov eax, immediate */
2022 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2023 off += sizeof(uint32_t);
2024 }
2025 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2026 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2027 off += sizeof(uint32_t);
2028
2029 aPatch[off++] = 0x0F; /* wrmsr */
2030 aPatch[off++] = 0x30;
2031 if (!fUsesEax)
2032 aPatch[off++] = 0x58; /* pop eax */
2033 aPatch[off++] = 0x5A; /* pop edx */
2034 aPatch[off++] = 0x59; /* pop ecx */
2035 }
2036 else
2037 {
2038 /*
2039 * TPR read:
2040 *
2041 * push ECX [51]
2042 * push EDX [52]
2043 * push EAX [50]
2044 * mov ECX,0C0000082h [B9 82 00 00 C0]
2045 * rdmsr [0F 32]
2046 * mov EAX,EAX [89 C0]
2047 * pop EAX [58]
2048 * pop EDX [5A]
2049 * pop ECX [59]
2050 * jmp return_address [E9 return_address]
2051 *
2052 */
2053 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2054
2055 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2056 aPatch[off++] = 0x51; /* push ecx */
2057 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2058 aPatch[off++] = 0x52; /* push edx */
2059 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2060 aPatch[off++] = 0x50; /* push eax */
2061
2062 aPatch[off++] = 0x31; /* xor edx, edx */
2063 aPatch[off++] = 0xD2;
2064
2065 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2066 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2067 off += sizeof(uint32_t);
2068
2069 aPatch[off++] = 0x0F; /* rdmsr */
2070 aPatch[off++] = 0x32;
2071
2072 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2073 {
2074 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2075 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2076 }
2077
2078 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2079 aPatch[off++] = 0x58; /* pop eax */
2080 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2081 aPatch[off++] = 0x5A; /* pop edx */
2082 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2083 aPatch[off++] = 0x59; /* pop ecx */
2084 }
2085 aPatch[off++] = 0xE9; /* jmp return_address */
2086 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2087 off += sizeof(RTRCUINTPTR);
2088
2089 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2090 {
2091 /* Write new code to the patch buffer. */
2092 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2093 AssertRC(rc);
2094
2095#ifdef LOG_ENABLED
2096 uint32_t cbCurInstr;
2097 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2098 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2099 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2100 {
2101 char szOutput[256];
2102 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2103 szOutput, sizeof(szOutput), &cbCurInstr);
2104 if (RT_SUCCESS(rc))
2105 Log(("Patch instr %s\n", szOutput));
2106 else
2107 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2108 }
2109#endif
2110
2111 pPatch->aNewOpcode[0] = 0xE9;
2112 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2113
2114 /* Overwrite the TPR instruction with a jump. */
2115 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2116 AssertRC(rc);
2117
2118 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2119
2120 pVM->hm.s.pFreeGuestPatchMem += off;
2121 pPatch->cbNewOp = 5;
2122
2123 pPatch->Core.Key = pCtx->eip;
2124 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2125 AssertRC(rc);
2126
2127 pVM->hm.s.cPatches++;
2128 pVM->hm.s.fTPRPatchingActive = true;
2129 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2130 return VINF_SUCCESS;
2131 }
2132
2133 Log(("Ran out of space in our patch buffer!\n"));
2134 }
2135 else
2136 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2137
2138
2139 /*
2140 * Save invalid patch, so we will not try again.
2141 */
2142 pPatch = &pVM->hm.s.aPatches[idx];
2143 pPatch->Core.Key = pCtx->eip;
2144 pPatch->enmType = HMTPRINSTR_INVALID;
2145 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2146 AssertRC(rc);
2147 pVM->hm.s.cPatches++;
2148 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2149 return VINF_SUCCESS;
2150}
2151
2152
2153/**
2154 * Attempt to patch TPR mmio instructions.
2155 *
2156 * @returns VBox status code.
2157 * @param pVM Pointer to the VM.
2158 * @param pVCpu Pointer to the VMCPU.
2159 * @param pCtx Pointer to the guest CPU context.
2160 */
2161VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2162{
2163 NOREF(pCtx);
2164 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2165 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2166 (void *)(uintptr_t)pVCpu->idCpu);
2167 AssertRC(rc);
2168 return rc;
2169}
2170
2171
2172/**
2173 * Force execution of the current IO code in the recompiler.
2174 *
2175 * @returns VBox status code.
2176 * @param pVM Pointer to the VM.
2177 * @param pCtx Partial VM execution context.
2178 */
2179VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2180{
2181 PVMCPU pVCpu = VMMGetCpu(pVM);
2182
2183 Assert(pVM->fHMEnabled);
2184 Log(("HMR3EmulateIoBlock\n"));
2185
2186 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2187 if (HMCanEmulateIoBlockEx(pCtx))
2188 {
2189 Log(("HMR3EmulateIoBlock -> enabled\n"));
2190 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2191 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2192 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2193 return VINF_EM_RESCHEDULE_REM;
2194 }
2195 return VINF_SUCCESS;
2196}
2197
2198
2199/**
2200 * Checks if we can currently use hardware accelerated raw mode.
2201 *
2202 * @returns true if we can currently use hardware acceleration, otherwise false.
2203 * @param pVM Pointer to the VM.
2204 * @param pCtx Partial VM execution context.
2205 */
2206VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2207{
2208 PVMCPU pVCpu = VMMGetCpu(pVM);
2209
2210 Assert(pVM->fHMEnabled);
2211
2212 /* If we're still executing the IO code, then return false. */
2213 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2214 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2215 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2216 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2217 return false;
2218
2219 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2220
2221 /* AMD-V supports real & protected mode with or without paging. */
2222 if (pVM->hm.s.svm.fEnabled)
2223 {
2224 pVCpu->hm.s.fActive = true;
2225 return true;
2226 }
2227
2228 pVCpu->hm.s.fActive = false;
2229
2230 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2231 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2232 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2233
2234 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2235 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2236 {
2237 /*
2238 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2239 * guest execution feature i missing (VT-x only).
2240 */
2241 if (fSupportsRealMode)
2242 {
2243 if (CPUMIsGuestInRealModeEx(pCtx))
2244 {
2245 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2246 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2247 * If this is not true, we cannot execute real mode as V86 and have to fall
2248 * back to emulation.
2249 */
2250 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2251 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2252 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2253 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2254 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2255 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2256 || (pCtx->cs.u32Limit != 0xffff)
2257 || (pCtx->ds.u32Limit != 0xffff)
2258 || (pCtx->es.u32Limit != 0xffff)
2259 || (pCtx->ss.u32Limit != 0xffff)
2260 || (pCtx->fs.u32Limit != 0xffff)
2261 || (pCtx->gs.u32Limit != 0xffff))
2262 {
2263 return false;
2264 }
2265 }
2266 else
2267 {
2268 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2269 /* Verify the requirements for executing code in protected
2270 mode. VT-x can't handle the CPU state right after a switch
2271 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2272 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2273 && enmGuestMode >= PGMMODE_PROTECTED)
2274 {
2275 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2276 || (pCtx->ds.Sel & X86_SEL_RPL)
2277 || (pCtx->es.Sel & X86_SEL_RPL)
2278 || (pCtx->fs.Sel & X86_SEL_RPL)
2279 || (pCtx->gs.Sel & X86_SEL_RPL)
2280 || (pCtx->ss.Sel & X86_SEL_RPL))
2281 {
2282 return false;
2283 }
2284 }
2285 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2286 if ( pCtx->gdtr.cbGdt
2287 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2288 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2289 {
2290 return false;
2291 }
2292 }
2293 }
2294 else
2295 {
2296 if ( !CPUMIsGuestInLongModeEx(pCtx)
2297 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2298 {
2299 /** @todo This should (probably) be set on every excursion to the REM,
2300 * however it's too risky right now. So, only apply it when we go
2301 * back to REM for real mode execution. (The XP hack below doesn't
2302 * work reliably without this.)
2303 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2304 for (uint32_t i = 0; i < pVM->cCpus; i++)
2305 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2306
2307 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2308 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2309 return false;
2310
2311 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2312 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2313 return false;
2314
2315 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2316 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2317 * hidden registers (possible recompiler bug; see load_seg_vm) */
2318 if (pCtx->cs.Attr.n.u1Present == 0)
2319 return false;
2320 if (pCtx->ss.Attr.n.u1Present == 0)
2321 return false;
2322
2323 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2324 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2325 /** @todo This check is actually wrong, it doesn't take the direction of the
2326 * stack segment into account. But, it does the job for now. */
2327 if (pCtx->rsp >= pCtx->ss.u32Limit)
2328 return false;
2329#if 0
2330 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2331 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2332 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2333 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2334 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2335 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2336 return false;
2337#endif
2338 }
2339 }
2340 }
2341
2342 if (pVM->hm.s.vmx.fEnabled)
2343 {
2344 uint32_t mask;
2345
2346 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2347 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2348 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2349 mask &= ~X86_CR0_NE;
2350
2351 if (fSupportsRealMode)
2352 {
2353 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2354 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2355 }
2356 else
2357 {
2358 /* We support protected mode without paging using identity mapping. */
2359 mask &= ~X86_CR0_PG;
2360 }
2361 if ((pCtx->cr0 & mask) != mask)
2362 return false;
2363
2364 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2365 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2366 if ((pCtx->cr0 & mask) != 0)
2367 return false;
2368
2369 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2370 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2371 mask &= ~X86_CR4_VMXE;
2372 if ((pCtx->cr4 & mask) != mask)
2373 return false;
2374
2375 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2376 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2377 if ((pCtx->cr4 & mask) != 0)
2378 return false;
2379
2380 pVCpu->hm.s.fActive = true;
2381 return true;
2382 }
2383
2384 return false;
2385}
2386
2387
2388/**
2389 * Checks if we need to reschedule due to VMM device heap changes.
2390 *
2391 * @returns true if a reschedule is required, otherwise false.
2392 * @param pVM Pointer to the VM.
2393 * @param pCtx VM execution context.
2394 */
2395VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2396{
2397 /*
2398 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2399 * when the unrestricted guest execution feature is missing (VT-x only).
2400 */
2401#ifdef VBOX_WITH_OLD_VTX_CODE
2402 if ( pVM->hm.s.vmx.fEnabled
2403 && !pVM->hm.s.vmx.fUnrestrictedGuest
2404 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2405 && !PDMVmmDevHeapIsEnabled(pVM)
2406 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2407 return true;
2408#else
2409 if ( pVM->hm.s.vmx.fEnabled
2410 && !pVM->hm.s.vmx.fUnrestrictedGuest
2411 && CPUMIsGuestInRealModeEx(pCtx)
2412 && !PDMVmmDevHeapIsEnabled(pVM))
2413 return true;
2414#endif
2415
2416 return false;
2417}
2418
2419
2420/**
2421 * Notification from EM about a rescheduling into hardware assisted execution
2422 * mode.
2423 *
2424 * @param pVCpu Pointer to the current VMCPU.
2425 */
2426VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2427{
2428 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2429}
2430
2431
2432/**
2433 * Notification from EM about returning from instruction emulation (REM / EM).
2434 *
2435 * @param pVCpu Pointer to the VMCPU.
2436 */
2437VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2438{
2439 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2440}
2441
2442
2443/**
2444 * Checks if we are currently using hardware accelerated raw mode.
2445 *
2446 * @returns true if hardware acceleration is being used, otherwise false.
2447 * @param pVCpu Pointer to the VMCPU.
2448 */
2449VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2450{
2451 return pVCpu->hm.s.fActive;
2452}
2453
2454
2455/**
2456 * Checks if we are currently using nested paging.
2457 *
2458 * @returns true if nested paging is being used, otherwise false.
2459 * @param pUVM The user mode VM handle.
2460 */
2461VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2462{
2463 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2464 PVM pVM = pUVM->pVM;
2465 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2466 return HMIsEnabled(pVM);
2467}
2468
2469
2470/**
2471 * Checks if we are currently using nested paging.
2472 *
2473 * @returns true if nested paging is being used, otherwise false.
2474 * @param pUVM The user mode VM handle.
2475 */
2476VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2477{
2478 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2479 PVM pVM = pUVM->pVM;
2480 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2481 return pVM->hm.s.fNestedPaging;
2482}
2483
2484
2485/**
2486 * Checks if we are currently using VPID in VT-x mode.
2487 *
2488 * @returns true if VPID is being used, otherwise false.
2489 * @param pUVM The user mode VM handle.
2490 */
2491VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2492{
2493 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2494 PVM pVM = pUVM->pVM;
2495 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2496 return pVM->hm.s.vmx.fVpid;
2497}
2498
2499
2500/**
2501 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2502 *
2503 * @returns true if an internal event is pending, otherwise false.
2504 * @param pVM Pointer to the VM.
2505 */
2506VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2507{
2508 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2509}
2510
2511
2512/**
2513 * Checks if the VMX-preemption timer is being used.
2514 *
2515 * @returns true if the VMX-preemption timer is being used, otherwise false.
2516 * @param pVM Pointer to the VM.
2517 */
2518VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2519{
2520 return HMIsEnabled(pVM)
2521 && pVM->hm.s.vmx.fEnabled
2522 && pVM->hm.s.vmx.fUsePreemptTimer;
2523}
2524
2525
2526/**
2527 * Restart an I/O instruction that was refused in ring-0
2528 *
2529 * @returns Strict VBox status code. Informational status codes other than the one documented
2530 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2531 * @retval VINF_SUCCESS Success.
2532 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2533 * status code must be passed on to EM.
2534 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2535 *
2536 * @param pVM Pointer to the VM.
2537 * @param pVCpu Pointer to the VMCPU.
2538 * @param pCtx Pointer to the guest CPU context.
2539 */
2540VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2541{
2542 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2543
2544 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2545
2546 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2547 || enmType == HMPENDINGIO_INVALID)
2548 return VERR_NOT_FOUND;
2549
2550 VBOXSTRICTRC rcStrict;
2551 switch (enmType)
2552 {
2553 case HMPENDINGIO_PORT_READ:
2554 {
2555 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2556 uint32_t u32Val = 0;
2557
2558 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2559 &u32Val,
2560 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2561 if (IOM_SUCCESS(rcStrict))
2562 {
2563 /* Write back to the EAX register. */
2564 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2565 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2566 }
2567 break;
2568 }
2569
2570 case HMPENDINGIO_PORT_WRITE:
2571 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2572 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2573 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2574 if (IOM_SUCCESS(rcStrict))
2575 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2576 break;
2577
2578 default:
2579 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2580 }
2581
2582 return rcStrict;
2583}
2584
2585
2586/**
2587 * Check fatal VT-x/AMD-V error and produce some meaningful
2588 * log release message.
2589 *
2590 * @param pVM Pointer to the VM.
2591 * @param iStatusCode VBox status code.
2592 */
2593VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2594{
2595 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2596 {
2597 switch (iStatusCode)
2598 {
2599 case VERR_VMX_INVALID_VMCS_FIELD:
2600 break;
2601
2602 case VERR_VMX_INVALID_VMCS_PTR:
2603 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2604 LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2605 LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2606 LogRel(("HM: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2607 LogRel(("HM: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2608 break;
2609
2610 case VERR_VMX_UNABLE_TO_START_VM:
2611 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2612 LogRel(("HM: CPU%d instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2613 LogRel(("HM: CPU%d exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2614 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2615 {
2616 LogRel(("HM: Cpu%d PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2617 LogRel(("HM: Cpu%d ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2618 LogRel(("HM: Cpu%d ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2619 LogRel(("HM: Cpu%d EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2620 LogRel(("HM: Cpu%d ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2621 LogRel(("HM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2622#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2623 LogRel(("HM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2624 LogRel(("HM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2625 LogRel(("HM: Cpu%d cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2626#endif
2627 }
2628 /** @todo Log VM-entry event injection control fields
2629 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2630 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2631 break;
2632
2633 case VERR_VMX_UNABLE_TO_RESUME_VM:
2634 LogRel(("HM: VERR_VMX_UNABLE_TO_RESUME_VM:\n"));
2635 LogRel(("HM: CPU%d instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2636 LogRel(("HM: CPU%d exit reason %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2637 break;
2638
2639 case VERR_VMX_INVALID_VMXON_PTR:
2640 break;
2641 }
2642 }
2643
2644 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2645 {
2646 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2647 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2648 }
2649}
2650
2651
2652/**
2653 * Execute state save operation.
2654 *
2655 * @returns VBox status code.
2656 * @param pVM Pointer to the VM.
2657 * @param pSSM SSM operation handle.
2658 */
2659static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2660{
2661 int rc;
2662
2663 Log(("hmR3Save:\n"));
2664
2665 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2666 {
2667 /*
2668 * Save the basic bits - fortunately all the other things can be resynced on load.
2669 */
2670 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2671 AssertRCReturn(rc, rc);
2672 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2673 AssertRCReturn(rc, rc);
2674 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2675 AssertRCReturn(rc, rc);
2676
2677 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2678 AssertRCReturn(rc, rc);
2679 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2680 AssertRCReturn(rc, rc);
2681 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2682 AssertRCReturn(rc, rc);
2683 }
2684#ifdef VBOX_HM_WITH_GUEST_PATCHING
2685 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2686 AssertRCReturn(rc, rc);
2687 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2688 AssertRCReturn(rc, rc);
2689 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2690 AssertRCReturn(rc, rc);
2691
2692 /* Store all the guest patch records too. */
2693 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2694 AssertRCReturn(rc, rc);
2695
2696 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2697 {
2698 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2699
2700 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2701 AssertRCReturn(rc, rc);
2702
2703 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2704 AssertRCReturn(rc, rc);
2705
2706 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2707 AssertRCReturn(rc, rc);
2708
2709 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2710 AssertRCReturn(rc, rc);
2711
2712 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2713 AssertRCReturn(rc, rc);
2714
2715 AssertCompileSize(HMTPRINSTR, 4);
2716 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2717 AssertRCReturn(rc, rc);
2718
2719 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2720 AssertRCReturn(rc, rc);
2721
2722 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2723 AssertRCReturn(rc, rc);
2724
2725 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2726 AssertRCReturn(rc, rc);
2727
2728 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2729 AssertRCReturn(rc, rc);
2730 }
2731#endif
2732 return VINF_SUCCESS;
2733}
2734
2735
2736/**
2737 * Execute state load operation.
2738 *
2739 * @returns VBox status code.
2740 * @param pVM Pointer to the VM.
2741 * @param pSSM SSM operation handle.
2742 * @param uVersion Data layout version.
2743 * @param uPass The data pass.
2744 */
2745static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2746{
2747 int rc;
2748
2749 Log(("hmR3Load:\n"));
2750 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2751
2752 /*
2753 * Validate version.
2754 */
2755 if ( uVersion != HM_SSM_VERSION
2756 && uVersion != HM_SSM_VERSION_NO_PATCHING
2757 && uVersion != HM_SSM_VERSION_2_0_X)
2758 {
2759 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2760 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2761 }
2762 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2763 {
2764 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2765 AssertRCReturn(rc, rc);
2766 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
2767 AssertRCReturn(rc, rc);
2768 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2769 AssertRCReturn(rc, rc);
2770
2771 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2772 {
2773 uint32_t val;
2774
2775 rc = SSMR3GetU32(pSSM, &val);
2776 AssertRCReturn(rc, rc);
2777 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2778
2779 rc = SSMR3GetU32(pSSM, &val);
2780 AssertRCReturn(rc, rc);
2781 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2782
2783 rc = SSMR3GetU32(pSSM, &val);
2784 AssertRCReturn(rc, rc);
2785 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2786 }
2787 }
2788#ifdef VBOX_HM_WITH_GUEST_PATCHING
2789 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2790 {
2791 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2792 AssertRCReturn(rc, rc);
2793 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2794 AssertRCReturn(rc, rc);
2795 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2796 AssertRCReturn(rc, rc);
2797
2798 /* Fetch all TPR patch records. */
2799 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2800 AssertRCReturn(rc, rc);
2801
2802 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2803 {
2804 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2805
2806 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2807 AssertRCReturn(rc, rc);
2808
2809 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2810 AssertRCReturn(rc, rc);
2811
2812 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2813 AssertRCReturn(rc, rc);
2814
2815 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2816 AssertRCReturn(rc, rc);
2817
2818 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2819 AssertRCReturn(rc, rc);
2820
2821 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2822 AssertRCReturn(rc, rc);
2823
2824 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2825 pVM->hm.s.fTPRPatchingActive = true;
2826
2827 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2828
2829 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2830 AssertRCReturn(rc, rc);
2831
2832 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2833 AssertRCReturn(rc, rc);
2834
2835 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2836 AssertRCReturn(rc, rc);
2837
2838 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2839 AssertRCReturn(rc, rc);
2840
2841 Log(("hmR3Load: patch %d\n", i));
2842 Log(("Key = %x\n", pPatch->Core.Key));
2843 Log(("cbOp = %d\n", pPatch->cbOp));
2844 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2845 Log(("type = %d\n", pPatch->enmType));
2846 Log(("srcop = %d\n", pPatch->uSrcOperand));
2847 Log(("dstop = %d\n", pPatch->uDstOperand));
2848 Log(("cFaults = %d\n", pPatch->cFaults));
2849 Log(("target = %x\n", pPatch->pJumpTarget));
2850 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2851 AssertRC(rc);
2852 }
2853 }
2854#endif
2855
2856 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2857 if (HMIsEnabled(pVM))
2858 {
2859 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2860 {
2861 PVMCPU pVCpu = &pVM->aCpus[i];
2862
2863 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2864 }
2865 }
2866 return VINF_SUCCESS;
2867}
2868
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