VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 45741

Last change on this file since 45741 was 45739, checked in by vboxsync, 12 years ago

VMM: First part of HMIsEnabled() and PGMMap*.
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File size: 127.1 KB
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1/* $Id: HM.cpp 45739 2013-04-25 19:44:05Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/ssm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/csam.h>
34#include <VBox/vmm/selm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/uvm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/asm-amd64-x86.h>
50#include <iprt/string.h>
51#include <iprt/env.h>
52#include <iprt/thread.h>
53
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58#ifdef VBOX_WITH_STATISTICS
59# define EXIT_REASON(def, val, str) #def " - " #val " - " str
60# define EXIT_REASON_NIL() NULL
61/** Exit reason descriptions for VT-x, used to describe statistics. */
62static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
63{
64 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
65 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
66 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
67 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
68 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
69 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
70 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
71 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
74 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest software attempted to execute CPUID."),
75 EXIT_REASON_NIL(),
76 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest software attempted to execute HLT."),
77 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest software attempted to execute INVD."),
78 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest software attempted to execute INVLPG."),
79 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest software attempted to execute RDPMC."),
80 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest software attempted to execute RDTSC."),
81 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest software attempted to execute RSM in SMM."),
82 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest software executed VMCALL."),
83 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest software executed VMCLEAR."),
84 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest software executed VMLAUNCH."),
85 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest software executed VMPTRLD."),
86 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest software executed VMPTRST."),
87 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest software executed VMREAD."),
88 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest software executed VMRESUME."),
89 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest software executed VMWRITE."),
90 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest software executed VMXOFF."),
91 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest software executed VMXON."),
92 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
93 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
94 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
95 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR. Guest software attempted to execute RDMSR."),
96 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR. Guest software attempted to execute WRMSR."),
97 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
98 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest software executed MWAIT."),
101 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest software attempted to execute MONITOR."),
104 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest software attempted to execute PAUSE."),
105 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest software executed MOV to CR8."),
108 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest software attempted to access memory at a physical address on the APIC-access page."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest software attempted to execute LGDT, LIDT, SGDT, or SIDT."),
111 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest software attempted to execute LLDT, LTR, SLDT, or STR."),
112 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
113 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
114 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT. Guest software attempted to execute INVEPT."),
115 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP. Guest software attempted to execute RDTSCP."),
116 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
117 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID. Guest software attempted to execute INVVPID."),
118 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD. Guest software attempted to execute WBINVD."),
119 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV. Guest software attempted to execute XSETBV."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND. Guest software attempted to execute RDRAND."),
122 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID. Guest software attempted to execute INVPCID."),
123 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC. Guest software attempted to execute VMFUNC.")
124};
125/** Exit reason descriptions for AMD-V, used to describe statistics. */
126static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
231 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
232 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
252 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
270 EXIT_REASON_NIL()
271};
272# undef EXIT_REASON
273# undef EXIT_REASON_NIL
274#endif /* VBOX_WITH_STATISTICS */
275
276#define VMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
277 do { \
278 if ((allowed1) & (featflag)) \
279 LogRel(("HM: " #featflag "\n")); \
280 else \
281 LogRel(("HM: " #featflag " *must* be cleared\n")); \
282 if ((disallowed0) & (featflag)) \
283 LogRel(("HM: " #featflag " *must* be set\n")); \
284 } while (0)
285
286#define VMX_REPORT_CAPABILITY(msrcaps, cap) \
287 do { \
288 if ((msrcaps) & (cap)) \
289 LogRel(("HM: " #cap "\n")); \
290 } while (0)
291
292
293/*******************************************************************************
294* Internal Functions *
295*******************************************************************************/
296static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
297static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
298static int hmR3InitCPU(PVM pVM);
299static int hmR3InitFinalizeR0(PVM pVM);
300static int hmR3InitFinalizeR0Intel(PVM pVM);
301static int hmR3InitFinalizeR0Amd(PVM pVM);
302static int hmR3TermCPU(PVM pVM);
303
304
305
306/**
307 * Initializes the HM.
308 *
309 * This reads the config and check whether VT-x or AMD-V hardware is available
310 * if configured to use it. This is one of the very first components to be
311 * initialized after CFGM, so that we can fall back to raw-mode early in the
312 * initialization process.
313 *
314 * Note that a lot of the set up work is done in ring-0 and thus postponed till
315 * the ring-3 and ring-0 callback to HMR3InitCompleted.
316 *
317 * @returns VBox status code.
318 * @param pVM Pointer to the VM.
319 *
320 * @remarks Be careful with what we call here, since most of the VMM components
321 * are uninitialized.
322 */
323VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
324{
325 LogFlow(("HMR3Init\n"));
326
327 /*
328 * Assert alignment and sizes.
329 */
330 AssertCompileMemberAlignment(VM, hm.s, 32);
331 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
332
333 /* Some structure checks. */
334 AssertCompileMemberOffset(SVM_VMCB, ctrl.EventInject, 0xA8);
335 AssertCompileMemberOffset(SVM_VMCB, ctrl.ExitIntInfo, 0x88);
336 AssertCompileMemberOffset(SVM_VMCB, ctrl.TLBCtrl, 0x58);
337
338 AssertCompileMemberOffset(SVM_VMCB, guest, 0x400);
339 AssertCompileMemberOffset(SVM_VMCB, guest.TR, 0x490);
340 AssertCompileMemberOffset(SVM_VMCB, guest.u8CPL, 0x4CB);
341 AssertCompileMemberOffset(SVM_VMCB, guest.u64EFER, 0x4D0);
342 AssertCompileMemberOffset(SVM_VMCB, guest.u64CR4, 0x548);
343 AssertCompileMemberOffset(SVM_VMCB, guest.u64RIP, 0x578);
344 AssertCompileMemberOffset(SVM_VMCB, guest.u64RSP, 0x5D8);
345 AssertCompileMemberOffset(SVM_VMCB, guest.u64CR2, 0x640);
346 AssertCompileMemberOffset(SVM_VMCB, guest.u64GPAT, 0x668);
347 AssertCompileMemberOffset(SVM_VMCB, guest.u64LASTEXCPTO,0x690);
348 AssertCompileSize(SVM_VMCB, 0x1000);
349
350 /*
351 * Register the saved state data unit.
352 */
353 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
354 NULL, NULL, NULL,
355 NULL, hmR3Save, NULL,
356 NULL, hmR3Load, NULL);
357 if (RT_FAILURE(rc))
358 return rc;
359
360 /*
361 * Misc initialisation.
362 */
363 //pVM->hm.s.vmx.fSupported = false;
364 //pVM->hm.s.svm.fSupported = false;
365 //pVM->hm.s.vmx.fEnabled = false;
366 //pVM->hm.s.svm.fEnabled = false;
367 //pVM->hm.s.fNestedPaging = false;
368
369
370 /*
371 * Read configuration.
372 */
373 PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
374
375 /** @cfgm{/HM/HMForced, bool, false}
376 * Forces hardware virtualization, no falling back on raw-mode. HM must be
377 * enabled, i.e. /HMEnabled must be true. */
378 bool fHMForced;
379#ifdef VBOX_WITH_RAW_MODE
380 rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
381 AssertRCReturn(rc, rc);
382 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
383 VERR_INVALID_PARAMETER);
384# if defined(RT_OS_DARWIN)
385 if (pVM->fHMEnabled)
386 fHMForced = true;
387# endif
388 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
389 VERR_INVALID_PARAMETER);
390 if (pVM->cCpus > 1)
391 fHMForced = true;
392#else /* !VBOX_WITH_RAW_MODE */
393 AssertRelease(pVM->fHMEnabled);
394 fHMForced = true;
395#endif /* !VBOX_WITH_RAW_MODE */
396
397 /** @cfgm{/HM/EnableNestedPaging, bool, false}
398 * Enables nested paging (aka extended page tables). */
399 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
400 AssertRCReturn(rc, rc);
401
402 /** @cfgm{/HM/EnableLargePages, bool, false}
403 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
404 * page table walking and maybe better TLB hit rate in some cases. */
405 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
406 AssertRCReturn(rc, rc);
407
408 /** @cfgm{/HM/EnableVPID, bool, false}
409 * Enables the VT-x VPID feature. */
410 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
411 AssertRCReturn(rc, rc);
412
413 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
414 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
415 rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
416 AssertRCReturn(rc, rc);
417
418 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
419 * Enables AMD64 cpu features.
420 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
421 * already have the support. */
422#ifdef VBOX_ENABLE_64_BITS_GUESTS
423 rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
424 AssertLogRelRCReturn(rc, rc);
425#else
426 pVM->hm.s.fAllow64BitGuests = false;
427#endif
428
429 /** @cfgm{/HM/Exclusive, bool}
430 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
431 * global init for each host CPU. If false, we do local init each time we wish
432 * to execute guest code.
433 *
434 * Default is false for Mac OS X and Windows due to the higher risk of conflicts
435 * with other hypervisors.
436 */
437 rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
438#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
439 false
440#else
441 true
442#endif
443 );
444 AssertLogRelRCReturn(rc, rc);
445
446 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
447 * The number of times to resume guest execution before we forcibly return to
448 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
449 * determins the default value. */
450 rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
451 AssertLogRelRCReturn(rc, rc);
452
453 /*
454 * Check if VT-x or AMD-v support according to the users wishes.
455 */
456 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
457 * VERR_SVM_IN_USE. */
458 if (pVM->fHMEnabled)
459 {
460 uint32_t fCaps;
461 rc = SUPR3QueryVTCaps(&fCaps);
462 if (RT_SUCCESS(rc))
463 {
464 if (fCaps & SUPVTCAPS_AMD_V)
465 LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
466 else if (fCaps & SUPVTCAPS_VT_X)
467 {
468 rc = SUPR3QueryVTxSupported();
469 if (RT_SUCCESS(rc))
470 LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
471 else
472 {
473#ifdef RT_OS_LINUX
474 const char *pszMinReq = " Linux 2.6.13 or newer required!";
475#else
476 const char *pszMinReq = "";
477#endif
478 if (fHMForced)
479 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
480
481 /* Fall back to raw-mode. */
482 LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
483 pVM->fHMEnabled = false;
484 }
485 }
486 else
487 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
488 VERR_INTERNAL_ERROR_5);
489
490 /*
491 * Do we require a little bit or raw-mode for 64-bit guest execution?
492 */
493 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
494 && pVM->fHMEnabled
495 && pVM->hm.s.fAllow64BitGuests;
496 }
497 else
498 {
499 const char *pszMsg;
500 switch (rc)
501 {
502 case VERR_UNSUPPORTED_CPU:
503 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
504 break;
505
506 case VERR_VMX_NO_VMX:
507 pszMsg = "VT-x is not available.";
508 break;
509
510 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
511 pszMsg = "VT-x is disabled in the BIOS (or by the host OS).";
512 break;
513
514 case VERR_SVM_NO_SVM:
515 pszMsg = "AMD-V is not available.";
516 break;
517
518 case VERR_SVM_DISABLED:
519 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
520 break;
521
522 default:
523 pszMsg = NULL;
524 break;
525 }
526 if (fHMForced && pszMsg)
527 return VM_SET_ERROR(pVM, rc, pszMsg);
528 if (!pszMsg)
529 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
530
531 /* Fall back to raw-mode. */
532 LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
533 pVM->fHMEnabled = false;
534 }
535 }
536
537 /* It's now OK to use the predicate function. */
538 pVM->fHMEnabledFixed = true;
539 return VINF_SUCCESS;
540}
541
542
543/**
544 * Initializes the per-VCPU HM.
545 *
546 * @returns VBox status code.
547 * @param pVM Pointer to the VM.
548 */
549static int hmR3InitCPU(PVM pVM)
550{
551 LogFlow(("HMR3InitCPU\n"));
552
553 if (!HMIsEnabled(pVM))
554 return VINF_SUCCESS;
555
556 for (VMCPUID i = 0; i < pVM->cCpus; i++)
557 {
558 PVMCPU pVCpu = &pVM->aCpus[i];
559 pVCpu->hm.s.fActive = false;
560 }
561
562#ifdef VBOX_WITH_STATISTICS
563 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
564 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
565 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
566 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
567
568 /*
569 * Statistics.
570 */
571 for (VMCPUID i = 0; i < pVM->cCpus; i++)
572 {
573 PVMCPU pVCpu = &pVM->aCpus[i];
574 int rc;
575
576 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
577 "Profiling of RTMpPokeCpu",
578 "/PROF/CPU%d/HM/Poke", i);
579 AssertRC(rc);
580 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
581 "Profiling of poke wait",
582 "/PROF/CPU%d/HM/PokeWait", i);
583 AssertRC(rc);
584 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
585 "Profiling of poke wait when RTMpPokeCpu fails",
586 "/PROF/CPU%d/HM/PokeWaitFailed", i);
587 AssertRC(rc);
588 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
589 "Profiling of VMXR0RunGuestCode entry",
590 "/PROF/CPU%d/HM/StatEntry", i);
591 AssertRC(rc);
592 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
593 "Profiling of VMXR0RunGuestCode exit part 1",
594 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
595 AssertRC(rc);
596 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
597 "Profiling of VMXR0RunGuestCode exit part 2",
598 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
599 AssertRC(rc);
600
601 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
602 "I/O",
603 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
604 AssertRC(rc);
605 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
606 "MOV CRx",
607 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
608 AssertRC(rc);
609 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
610 "Exceptions, NMIs",
611 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
612 AssertRC(rc);
613
614 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
615 "Profiling of VMXR0LoadGuestState",
616 "/PROF/CPU%d/HM/StatLoadGuestState", i);
617 AssertRC(rc);
618 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
619 "Profiling of vmlaunch/vmresume",
620 "/PROF/CPU%d/HM/InGC", i);
621 AssertRC(rc);
622
623# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
624 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
625 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher",
626 "/PROF/CPU%d/HM/Switcher3264", i);
627 AssertRC(rc);
628# endif
629
630# ifdef HM_PROFILE_EXIT_DISPATCH
631 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
632 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers",
633 "/PROF/CPU%d/HM/ExitDispatch", i);
634 AssertRC(rc);
635# endif
636
637# define HM_REG_COUNTER(a, b) \
638 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, "Profiling of HM", b, i); \
639 AssertRC(rc);
640
641 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM");
642 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM");
643 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF");
644 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM");
645 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF");
646 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD");
647 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS");
648 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP");
649 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP");
650 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF");
651 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE");
652 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB");
653 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP");
654 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF");
655 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other");
656 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg");
657 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd");
658 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd");
659 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause");
660 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid");
661 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc");
662 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp");
663 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc");
664 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand");
665 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr");
666 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr");
667 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait");
668 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor");
669 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write");
670 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read");
671 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS");
672 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW");
673 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli");
674 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti");
675 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf");
676 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf");
677 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret");
678 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int");
679 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt");
680 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess");
681 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write");
682 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read");
683 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString");
684 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString");
685 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow");
686 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume");
687 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt");
688 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer");
689 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold");
690 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch");
691 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag");
692 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess");
693
694 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending");
695 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF");
696 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3");
697 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3");
698
699 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject");
700 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject");
701 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost");
702
703 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page");
704 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt");
705 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys");
706 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB");
707 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual");
708 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch");
709 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped");
710 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID");
711 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging");
712 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt");
713 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys");
714 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page");
715 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB");
716
717 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset");
718 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept");
719 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow");
720
721 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed");
722 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck");
724
725 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal");
726 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full");
727
728#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
729 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu");
730 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug");
731#endif
732
733 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
734 {
735 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
736 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
737 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
738 AssertRC(rc);
739 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
740 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
741 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
742 AssertRC(rc);
743 }
744
745#undef HM_REG_COUNTER
746
747 pVCpu->hm.s.paStatExitReason = NULL;
748
749 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
750 (void **)&pVCpu->hm.s.paStatExitReason);
751 AssertRC(rc);
752 if (RT_SUCCESS(rc))
753 {
754 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
755 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
756 {
757 if (papszDesc[j])
758 {
759 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
760 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
761 AssertRC(rc);
762 }
763 }
764 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
765 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
766 AssertRC(rc);
767 }
768 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
769# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
770 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
771# else
772 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
773# endif
774
775 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
776 AssertRCReturn(rc, rc);
777 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
778# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
779 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
780# else
781 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
782# endif
783 for (unsigned j = 0; j < 255; j++)
784 {
785 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
786 "Forwarded interrupts.",
787 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
788 }
789
790 }
791#endif /* VBOX_WITH_STATISTICS */
792
793#ifdef VBOX_WITH_CRASHDUMP_MAGIC
794 /*
795 * Magic marker for searching in crash dumps.
796 */
797 for (VMCPUID i = 0; i < pVM->cCpus; i++)
798 {
799 PVMCPU pVCpu = &pVM->aCpus[i];
800
801 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
802 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
803 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
804 }
805#endif
806
807 return VINF_SUCCESS;
808}
809
810
811/**
812 * Called when a init phase has completed.
813 *
814 * @returns VBox status code.
815 * @param pVM The VM.
816 * @param enmWhat The phase that completed.
817 */
818VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
819{
820 switch (enmWhat)
821 {
822 case VMINITCOMPLETED_RING3:
823 return hmR3InitCPU(pVM);
824 case VMINITCOMPLETED_RING0:
825 return hmR3InitFinalizeR0(pVM);
826 default:
827 return VINF_SUCCESS;
828 }
829}
830
831
832/**
833 * Turns off normal raw mode features.
834 *
835 * @param pVM Pointer to the VM.
836 */
837static void hmR3DisableRawMode(PVM pVM)
838{
839 /* Reinit the paging mode to force the new shadow mode. */
840 for (VMCPUID i = 0; i < pVM->cCpus; i++)
841 {
842 PVMCPU pVCpu = &pVM->aCpus[i];
843
844 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
845 }
846}
847
848
849/**
850 * Initialize VT-x or AMD-V.
851 *
852 * @returns VBox status code.
853 * @param pVM Pointer to the VM.
854 */
855static int hmR3InitFinalizeR0(PVM pVM)
856{
857 int rc;
858
859 if (!HMIsEnabled(pVM))
860 return VINF_SUCCESS;
861
862 /*
863 * Hack to allow users to work around broken BIOSes that incorrectly set
864 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
865 */
866 if ( !pVM->hm.s.vmx.fSupported
867 && !pVM->hm.s.svm.fSupported
868 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
869 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
870 {
871 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
872 pVM->hm.s.svm.fSupported = true;
873 pVM->hm.s.svm.fIgnoreInUseError = true;
874 pVM->hm.s.lLastError = VINF_SUCCESS;
875 }
876
877 /*
878 * Report ring-0 init errors.
879 */
880 if ( !pVM->hm.s.vmx.fSupported
881 && !pVM->hm.s.svm.fSupported)
882 {
883 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
884 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
885 switch (pVM->hm.s.lLastError)
886 {
887 case VERR_VMX_IN_VMX_ROOT_MODE:
888 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
889 case VERR_VMX_NO_VMX:
890 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
891 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
892 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS (or by the host OS).");
893
894 case VERR_SVM_IN_USE:
895 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
896 case VERR_SVM_NO_SVM:
897 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
898 case VERR_SVM_DISABLED:
899 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
900 }
901 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
902 }
903
904 /*
905 * Enable VT-x or AMD-V on all host CPUs.
906 */
907 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
908 if (RT_FAILURE(rc))
909 {
910 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
911 return rc;
912 }
913
914 /*
915 * No TPR patching is required when the IO-APIC is not enabled for this VM.
916 * (Main should have taken care of this already)
917 */
918 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
919 if (!pVM->hm.s.fHasIoApic)
920 {
921 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
922 pVM->hm.s.fTRPPatchingAllowed = false;
923 }
924
925 /*
926 * Do the vendor specific initalization .
927 * .
928 * Note! We disable release log buffering here since we're doing relatively .
929 * lot of logging and doesn't want to hit the disk with each LogRel .
930 * statement.
931 */
932 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
933 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
934 if (pVM->hm.s.vmx.fSupported)
935 rc = hmR3InitFinalizeR0Intel(pVM);
936 else
937 rc = hmR3InitFinalizeR0Amd(pVM);
938 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
939 RTLogRelSetBuffering(fOldBuffered);
940 pVM->hm.s.fInitialized = true;
941
942 return rc;
943}
944
945
946/**
947 * Finish VT-x initialization (after ring-0 init).
948 *
949 * @returns VBox status code.
950 * @param pVM The cross context VM structure.
951 */
952static int hmR3InitFinalizeR0Intel(PVM pVM)
953{
954 int rc;
955
956 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
957 AssertLogRelReturn(pVM->hm.s.vmx.msr.feature_ctrl != 0, VERR_HM_IPE_4);
958
959 uint64_t val;
960 uint64_t zap;
961 RTGCPHYS GCPhys = 0;
962
963#ifndef VBOX_WITH_OLD_VTX_CODE
964 LogRel(("HM: Using VT-x implementation 2.0!\n"));
965#endif
966 LogRel(("HM: Host CR4 = %08X\n", pVM->hm.s.vmx.hostCR4));
967 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
968 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
969 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
970 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
971 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
972 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
973 LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
974 LogRel(("HM: Max resume loops = %RX32\n", pVM->hm.s.cMaxResumeLoops));
975
976 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
977 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
978 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
979 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_EXT_INT_EXIT);
980 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_NMI_EXIT);
981 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_VIRTUAL_NMI);
982 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_CONTROLS_PREEMPT_TIMER);
983
984 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
985 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
986 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
987 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INT_WINDOW_EXIT);
988 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TSC_OFFSETTING);
989 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_HLT_EXIT);
990 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_INVLPG_EXIT);
991 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MWAIT_EXIT);
992 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDPMC_EXIT);
993 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_RDTSC_EXIT);
994 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_LOAD_EXIT);
995 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR3_STORE_EXIT);
996 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_LOAD_EXIT);
997 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_CR8_STORE_EXIT);
998 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_TPR_SHADOW);
999 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_NMI_WINDOW_EXIT);
1000 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MOV_DR_EXIT);
1001 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_UNCOND_IO_EXIT);
1002 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_IO_BITMAPS);
1003 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_TRAP_FLAG);
1004 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_USE_MSR_BITMAPS);
1005 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_MONITOR_EXIT);
1006 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CONTROLS_PAUSE_EXIT);
1007 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1008 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1009 {
1010 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
1011 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
1012 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
1013 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1014 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1015 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1016 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1017 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1018 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1019 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1020 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1021 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1022 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1023 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1024 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1025 }
1026
1027 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
1028 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
1029 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
1030 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_DEBUG);
1031 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_IA32E_MODE_GUEST);
1032 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_ENTRY_SMM);
1033 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_DEACTIVATE_DUALMON);
1034 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PERF_MSR);
1035 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_PAT_MSR);
1036 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_CONTROLS_LOAD_GUEST_EFER_MSR);
1037
1038 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
1039 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
1040 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
1041 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_DEBUG);
1042 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_HOST_ADDR_SPACE_SIZE);
1043 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_PERF_MSR);
1044 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_ACK_EXT_INT);
1045 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_PAT_MSR);
1046 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_PAT_MSR);
1047 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_GUEST_EFER_MSR);
1048 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_LOAD_HOST_EFER_MSR);
1049 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_CONTROLS_SAVE_VMX_PREEMPT_TIMER);
1050
1051 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
1052 {
1053 val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
1054 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", val));
1055 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1056 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1057 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1058 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1059 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1060 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1061 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1062 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1063 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1064 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1065 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1066 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1067 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1068 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1069 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1070 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1071 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1072 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1073 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1074 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1075 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1076 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1077 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1078 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1079 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1080 }
1081
1082 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
1083 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1084 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
1085 else
1086 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
1087 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
1088
1089 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
1090 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
1091 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
1092 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
1093
1094 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
1095 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
1096 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1097 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1098 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1099
1100 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1101
1102 /* Paranoia */
1103 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1104
1105 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1106 {
1107 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1108 LogRel(("HM: VCPU%3d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1109 }
1110
1111 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1112 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1113
1114 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1115 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1116
1117 /*
1118 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1119 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1120 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1121 */
1122 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1123 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1124 {
1125 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1126 LogRel(("HM: Disabled RDTSCP\n"));
1127 }
1128
1129 /* Unrestricted guest execution relies on EPT. */
1130 if ( pVM->hm.s.fNestedPaging
1131 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1132 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1133
1134 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1135 {
1136 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1137 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1138 if (RT_SUCCESS(rc))
1139 {
1140 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap.
1141 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1142 esp. Figure 20-5.*/
1143 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1144 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1145
1146 /* Bit set to 0 means software interrupts are redirected to the
1147 8086 program interrupt handler rather than switching to
1148 protected-mode handler. */
1149 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1150
1151 /* Allow all port IO, so that port IO instructions do not cause
1152 exceptions and would instead cause a VM-exit (based on VT-x's
1153 IO bitmap which we currently configure to always cause an exit). */
1154 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1155 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1156
1157 /*
1158 * Construct a 1024 element page directory with 4 MB pages for
1159 * the identity mapped page table used in real and protected mode
1160 * without paging with EPT.
1161 */
1162 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1163 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1164 {
1165 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1166 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1167 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1168 | X86_PDE4M_G;
1169 }
1170
1171 /* We convert it here every time as pci regions could be reconfigured. */
1172 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1173 AssertRCReturn(rc, rc);
1174 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1175
1176 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1177 AssertRCReturn(rc, rc);
1178 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1179 }
1180 else
1181 {
1182 /** @todo This cannot possibly work, there are other places which assumes
1183 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1184 * a failure case. */
1185 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1186 pVM->hm.s.vmx.pRealModeTSS = NULL;
1187 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1188 }
1189 }
1190
1191 /*
1192 * Call ring-0 to set up the VM.
1193 */
1194 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1195 if (rc != VINF_SUCCESS)
1196 {
1197 AssertMsgFailed(("%Rrc\n", rc));
1198 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1199 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1200 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1201 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1202 }
1203
1204 LogRel(("HM: VMX enabled!\n"));
1205 pVM->hm.s.vmx.fEnabled = true;
1206
1207 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1208
1209 /*
1210 * Change the CPU features.
1211 */
1212 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1213 if (pVM->hm.s.fAllow64BitGuests)
1214 {
1215 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1216 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1217 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1218 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1219 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1220#if 0 /** @todo r=bird: This ain't making any sense whatsoever. */
1221#if RT_ARCH_X86
1222 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1223 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1224 LogRel(("NX is only supported for 64-bit guests!\n"));
1225#endif
1226#endif
1227 }
1228 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1229 (we reuse the host EFER in the switcher). */
1230 /** @todo this needs to be fixed properly!! */
1231 else if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1232 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1233 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1234 else
1235 LogRel(("HM: NX not supported by the host\n"));
1236
1237 /*
1238 * Log configuration details.
1239 */
1240 LogRel((pVM->hm.s.fAllow64BitGuests
1241 ? "HM: Guest support: 32-bit and 64-bit.\n"
1242 : "HM: Guest support: 32-bit only.\n"));
1243 if (pVM->hm.s.fNestedPaging)
1244 {
1245 LogRel(("HM: Nested paging enabled!\n"));
1246 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1247 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1248 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1249 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1250 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1251 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1252 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1253 else
1254 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1255
1256 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1257 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1258
1259#if HC_ARCH_BITS == 64
1260 if (pVM->hm.s.fLargePages)
1261 {
1262 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1263 PGMSetLargePageUsage(pVM, true);
1264 LogRel(("HM: Large page support enabled!\n"));
1265 }
1266#endif
1267 }
1268 else
1269 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1270
1271 if (pVM->hm.s.vmx.fVpid)
1272 {
1273 LogRel(("HM: VPID enabled!\n"));
1274 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1275 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1276 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1277 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1278 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1279 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1280 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1281 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1282 else
1283 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1284 }
1285 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1286 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1287
1288 /*
1289 * TPR patching status logging.
1290 */
1291 if (pVM->hm.s.fTRPPatchingAllowed)
1292 {
1293 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1294 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1295 {
1296 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1297 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1298 }
1299 else
1300 {
1301 uint32_t u32Eax, u32Dummy;
1302
1303 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1304 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1305 if ( u32Eax < 0x80000001
1306 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1307 {
1308 pVM->hm.s.fTRPPatchingAllowed = false;
1309 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1310 }
1311 }
1312 }
1313 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1314
1315 /*
1316 * Check for preemption timer config override and log the state of it.
1317 */
1318 if (pVM->hm.s.vmx.fUsePreemptTimer)
1319 {
1320 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1321 rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1322 AssertLogRelRCReturn(rc, rc);
1323 }
1324 if (pVM->hm.s.vmx.fUsePreemptTimer)
1325 LogRel(("HM: Using the VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1326
1327 return VINF_SUCCESS;
1328}
1329
1330
1331/**
1332 * Finish AMD-V initialization (after ring-0 init).
1333 *
1334 * @returns VBox status code.
1335 * @param pVM The cross context VM structure.
1336 */
1337static int hmR3InitFinalizeR0Amd(PVM pVM)
1338{
1339 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1340
1341 /* Erratum 170 which requires a forced TLB flush for each world switch:
1342 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1343 *
1344 * All BH-G1/2 and DH-G1/2 models include a fix:
1345 * Athlon X2: 0x6b 1/2
1346 * 0x68 1/2
1347 * Athlon 64: 0x7f 1
1348 * 0x6f 2
1349 * Sempron: 0x7f 1/2
1350 * 0x6f 2
1351 * 0x6c 2
1352 * 0x7c 2
1353 * Turion 64: 0x68 2
1354 *
1355 */
1356 uint32_t u32Dummy;
1357 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1358 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1359 u32BaseFamily= (u32Version >> 8) & 0xf;
1360 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1361 u32Model = ((u32Version >> 4) & 0xf);
1362 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1363 u32Stepping = u32Version & 0xf;
1364 if ( u32Family == 0xf
1365 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1366 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1367 {
1368 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1369 }
1370
1371 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1372 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1373 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1374 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1375 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1376 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1377
1378 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1379 {
1380#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1381 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1382 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1383 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1384 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1385 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1386 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1387 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1388 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1389 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1390 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1391 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1392#undef FLAG_NAME
1393 };
1394 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1395 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1396 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1397 {
1398 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1399 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1400 }
1401 if (fSvmFeatures)
1402 for (unsigned iBit = 0; iBit < 32; iBit++)
1403 if (RT_BIT_32(iBit) & fSvmFeatures)
1404 LogRel(("HM: Reserved bit %u\n", iBit));
1405
1406 /*
1407 * Adjust feature(s).
1408 */
1409 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1410 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1411
1412 /*
1413 * Call ring-0 to set up the VM.
1414 */
1415 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1416 if (rc != VINF_SUCCESS)
1417 {
1418 AssertMsgFailed(("%Rrc\n", rc));
1419 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1420 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1421 }
1422
1423 LogRel(("HM: AMD-V enabled!\n"));
1424 pVM->hm.s.svm.fEnabled = true;
1425
1426 if (pVM->hm.s.fNestedPaging)
1427 {
1428 LogRel(("HM: Enabled nested paging!\n"));
1429
1430 /*
1431 * Enable large pages (2 MB) if applicable.
1432 */
1433#if HC_ARCH_BITS == 64
1434 if (pVM->hm.s.fLargePages)
1435 {
1436 PGMSetLargePageUsage(pVM, true);
1437 LogRel(("HM: Large page support enabled!\n"));
1438 }
1439#endif
1440 }
1441
1442 hmR3DisableRawMode(pVM);
1443
1444 /*
1445 * Change the CPU features.
1446 */
1447 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1448 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1449 if (pVM->hm.s.fAllow64BitGuests)
1450 {
1451 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1452 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1453 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1454 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1455 }
1456 /* Turn on NXE if PAE has been enabled. */
1457 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1458 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1459
1460
1461 LogRel((pVM->hm.s.fAllow64BitGuests
1462 ? "HM: 32-bit and 64-bit guest supported.\n"
1463 : "HM: 32-bit guest supported.\n"));
1464 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1465
1466 return VINF_SUCCESS;
1467}
1468
1469
1470/**
1471 * Applies relocations to data and code managed by this
1472 * component. This function will be called at init and
1473 * whenever the VMM need to relocate it self inside the GC.
1474 *
1475 * @param pVM The VM.
1476 */
1477VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1478{
1479 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1480
1481 /* Fetch the current paging mode during the relocate callback during state loading. */
1482 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1483 {
1484 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1485 {
1486 PVMCPU pVCpu = &pVM->aCpus[i];
1487
1488 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1489 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1490 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1491 }
1492 }
1493#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1494 if (HMIsEnabled(pVM))
1495 {
1496 int rc;
1497 switch (PGMGetHostMode(pVM))
1498 {
1499 case PGMMODE_32_BIT:
1500 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1501 break;
1502
1503 case PGMMODE_PAE:
1504 case PGMMODE_PAE_NX:
1505 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1506 break;
1507
1508 default:
1509 AssertFailed();
1510 break;
1511 }
1512 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "VMXGCStartVM64", &pVM->hm.s.pfnVMXGCStartVM64);
1513 AssertReleaseMsgRC(rc, ("VMXGCStartVM64 -> rc=%Rrc\n", rc));
1514
1515 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "SVMGCVMRun64", &pVM->hm.s.pfnSVMGCVMRun64);
1516 AssertReleaseMsgRC(rc, ("SVMGCVMRun64 -> rc=%Rrc\n", rc));
1517
1518 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestFPU64", &pVM->hm.s.pfnSaveGuestFPU64);
1519 AssertReleaseMsgRC(rc, ("HMSetupFPU64 -> rc=%Rrc\n", rc));
1520
1521 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMSaveGuestDebug64", &pVM->hm.s.pfnSaveGuestDebug64);
1522 AssertReleaseMsgRC(rc, ("HMSetupDebug64 -> rc=%Rrc\n", rc));
1523
1524# ifdef DEBUG
1525 rc = PDMR3LdrGetSymbolRC(pVM, NULL, "HMTestSwitcher64", &pVM->hm.s.pfnTest64);
1526 AssertReleaseMsgRC(rc, ("HMTestSwitcher64 -> rc=%Rrc\n", rc));
1527# endif
1528 }
1529#endif
1530 return;
1531}
1532
1533
1534/**
1535 * Notification callback which is called whenever there is a chance that a CR3
1536 * value might have changed.
1537 *
1538 * This is called by PGM.
1539 *
1540 * @param pVM Pointer to the VM.
1541 * @param pVCpu Pointer to the VMCPU.
1542 * @param enmShadowMode New shadow paging mode.
1543 * @param enmGuestMode New guest paging mode.
1544 */
1545VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1546{
1547 /* Ignore page mode changes during state loading. */
1548 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1549 return;
1550
1551 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1552
1553#ifdef VBOX_WITH_OLD_VTX_CODE
1554 if ( pVM->hm.s.vmx.fEnabled
1555 && HMIsEnabled(pVM))
1556 {
1557 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1558 && enmGuestMode >= PGMMODE_PROTECTED)
1559 {
1560 PCPUMCTX pCtx;
1561
1562 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1563
1564 /* After a real mode switch to protected mode we must force
1565 CPL to 0. Our real mode emulation had to set it to 3. */
1566 pCtx->ss.Attr.n.u2Dpl = 0;
1567 }
1568 }
1569#endif
1570
1571 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1572 {
1573 /* Keep track of paging mode changes. */
1574 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1575 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1576
1577 /* Did we miss a change, because all code was executed in the recompiler? */
1578 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1579 {
1580 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1581 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1582 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1583 }
1584 }
1585
1586 /** @todo r=ramshankar: Why do we need to do this? Most likely
1587 * VBOX_WITH_OLD_VTX_CODE only. */
1588 /* Reset the contents of the read cache. */
1589 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1590 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1591 pCache->Read.aFieldVal[j] = 0;
1592}
1593
1594
1595/**
1596 * Terminates the HM.
1597 *
1598 * Termination means cleaning up and freeing all resources,
1599 * the VM itself is, at this point, powered off or suspended.
1600 *
1601 * @returns VBox status code.
1602 * @param pVM Pointer to the VM.
1603 */
1604VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1605{
1606 if (pVM->hm.s.vmx.pRealModeTSS)
1607 {
1608 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1609 pVM->hm.s.vmx.pRealModeTSS = 0;
1610 }
1611 hmR3TermCPU(pVM);
1612 return 0;
1613}
1614
1615
1616/**
1617 * Terminates the per-VCPU HM.
1618 *
1619 * @returns VBox status code.
1620 * @param pVM Pointer to the VM.
1621 */
1622static int hmR3TermCPU(PVM pVM)
1623{
1624 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1625 {
1626 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1627
1628#ifdef VBOX_WITH_STATISTICS
1629 if (pVCpu->hm.s.paStatExitReason)
1630 {
1631 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1632 pVCpu->hm.s.paStatExitReason = NULL;
1633 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1634 }
1635 if (pVCpu->hm.s.paStatInjectedIrqs)
1636 {
1637 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1638 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1639 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1640 }
1641#endif
1642
1643#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1644 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1645 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1646 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1647#endif
1648 }
1649 return 0;
1650}
1651
1652
1653/**
1654 * Resets a virtual CPU.
1655 *
1656 * Used by HMR3Reset and CPU hot plugging.
1657 *
1658 * @param pVCpu The CPU to reset.
1659 */
1660VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1661{
1662 /* On first entry we'll sync everything. */
1663 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1664
1665 pVCpu->hm.s.vmx.cr0_mask = 0;
1666 pVCpu->hm.s.vmx.cr4_mask = 0;
1667
1668 pVCpu->hm.s.fActive = false;
1669 pVCpu->hm.s.Event.fPending = false;
1670
1671 /* Reset state information for real-mode emulation in VT-x. */
1672 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1673 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1674 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1675
1676 /* Reset the contents of the read cache. */
1677 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1678 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1679 pCache->Read.aFieldVal[j] = 0;
1680
1681#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1682 /* Magic marker for searching in crash dumps. */
1683 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1684 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1685#endif
1686}
1687
1688
1689/**
1690 * The VM is being reset.
1691 *
1692 * For the HM component this means that any GDT/LDT/TSS monitors
1693 * needs to be removed.
1694 *
1695 * @param pVM Pointer to the VM.
1696 */
1697VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1698{
1699 LogFlow(("HMR3Reset:\n"));
1700
1701 if (HMIsEnabled(pVM))
1702 hmR3DisableRawMode(pVM);
1703
1704 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1705 {
1706 PVMCPU pVCpu = &pVM->aCpus[i];
1707
1708 HMR3ResetCpu(pVCpu);
1709 }
1710
1711 /* Clear all patch information. */
1712 pVM->hm.s.pGuestPatchMem = 0;
1713 pVM->hm.s.pFreeGuestPatchMem = 0;
1714 pVM->hm.s.cbGuestPatchMem = 0;
1715 pVM->hm.s.cPatches = 0;
1716 pVM->hm.s.PatchTree = 0;
1717 pVM->hm.s.fTPRPatchingActive = false;
1718 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1719}
1720
1721
1722/**
1723 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1724 *
1725 * @returns VBox strict status code.
1726 * @param pVM Pointer to the VM.
1727 * @param pVCpu The VMCPU for the EMT we're being called on.
1728 * @param pvUser Unused.
1729 */
1730DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1731{
1732 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1733
1734 /* Only execute the handler on the VCPU the original patch request was issued. */
1735 if (pVCpu->idCpu != idCpu)
1736 return VINF_SUCCESS;
1737
1738 Log(("hmR3RemovePatches\n"));
1739 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1740 {
1741 uint8_t abInstr[15];
1742 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1743 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1744 int rc;
1745
1746#ifdef LOG_ENABLED
1747 char szOutput[256];
1748
1749 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1750 szOutput, sizeof(szOutput), NULL);
1751 if (RT_SUCCESS(rc))
1752 Log(("Patched instr: %s\n", szOutput));
1753#endif
1754
1755 /* Check if the instruction is still the same. */
1756 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1757 if (rc != VINF_SUCCESS)
1758 {
1759 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1760 continue; /* swapped out or otherwise removed; skip it. */
1761 }
1762
1763 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1764 {
1765 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1766 continue; /* skip it. */
1767 }
1768
1769 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1770 AssertRC(rc);
1771
1772#ifdef LOG_ENABLED
1773 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1774 szOutput, sizeof(szOutput), NULL);
1775 if (RT_SUCCESS(rc))
1776 Log(("Original instr: %s\n", szOutput));
1777#endif
1778 }
1779 pVM->hm.s.cPatches = 0;
1780 pVM->hm.s.PatchTree = 0;
1781 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1782 pVM->hm.s.fTPRPatchingActive = false;
1783 return VINF_SUCCESS;
1784}
1785
1786
1787/**
1788 * Worker for enabling patching in a VT-x/AMD-V guest.
1789 *
1790 * @returns VBox status code.
1791 * @param pVM Pointer to the VM.
1792 * @param idCpu VCPU to execute hmR3RemovePatches on.
1793 * @param pPatchMem Patch memory range.
1794 * @param cbPatchMem Size of the memory range.
1795 */
1796static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1797{
1798 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1799 AssertRC(rc);
1800
1801 pVM->hm.s.pGuestPatchMem = pPatchMem;
1802 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1803 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1804 return VINF_SUCCESS;
1805}
1806
1807
1808/**
1809 * Enable patching in a VT-x/AMD-V guest
1810 *
1811 * @returns VBox status code.
1812 * @param pVM Pointer to the VM.
1813 * @param pPatchMem Patch memory range.
1814 * @param cbPatchMem Size of the memory range.
1815 */
1816VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1817{
1818 VM_ASSERT_EMT(pVM);
1819 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1820 if (pVM->cCpus > 1)
1821 {
1822 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1823 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1824 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1825 AssertRC(rc);
1826 return rc;
1827 }
1828 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1829}
1830
1831
1832/**
1833 * Disable patching in a VT-x/AMD-V guest.
1834 *
1835 * @returns VBox status code.
1836 * @param pVM Pointer to the VM.
1837 * @param pPatchMem Patch memory range.
1838 * @param cbPatchMem Size of the memory range.
1839 */
1840VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1841{
1842 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1843
1844 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1845 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1846
1847 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1848 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1849 (void *)(uintptr_t)VMMGetCpuId(pVM));
1850 AssertRC(rc);
1851
1852 pVM->hm.s.pGuestPatchMem = 0;
1853 pVM->hm.s.pFreeGuestPatchMem = 0;
1854 pVM->hm.s.cbGuestPatchMem = 0;
1855 pVM->hm.s.fTPRPatchingActive = false;
1856 return VINF_SUCCESS;
1857}
1858
1859
1860/**
1861 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1862 *
1863 * @returns VBox strict status code.
1864 * @param pVM Pointer to the VM.
1865 * @param pVCpu The VMCPU for the EMT we're being called on.
1866 * @param pvUser User specified CPU context.
1867 *
1868 */
1869DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1870{
1871 /*
1872 * Only execute the handler on the VCPU the original patch request was
1873 * issued. (The other CPU(s) might not yet have switched to protected
1874 * mode, nor have the correct memory context.)
1875 */
1876 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1877 if (pVCpu->idCpu != idCpu)
1878 return VINF_SUCCESS;
1879
1880 /*
1881 * We're racing other VCPUs here, so don't try patch the instruction twice
1882 * and make sure there is still room for our patch record.
1883 */
1884 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1885 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1886 if (pPatch)
1887 {
1888 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1889 return VINF_SUCCESS;
1890 }
1891 uint32_t const idx = pVM->hm.s.cPatches;
1892 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1893 {
1894 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1895 return VINF_SUCCESS;
1896 }
1897 pPatch = &pVM->hm.s.aPatches[idx];
1898
1899 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1900
1901 /*
1902 * Disassembler the instruction and get cracking.
1903 */
1904 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1905 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1906 uint32_t cbOp;
1907 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1908 AssertRC(rc);
1909 if ( rc == VINF_SUCCESS
1910 && pDis->pCurInstr->uOpcode == OP_MOV
1911 && cbOp >= 3)
1912 {
1913 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1914
1915 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1916 AssertRC(rc);
1917
1918 pPatch->cbOp = cbOp;
1919
1920 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1921 {
1922 /* write. */
1923 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1924 {
1925 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1926 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1927 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1928 }
1929 else
1930 {
1931 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1932 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1933 pPatch->uSrcOperand = pDis->Param2.uValue;
1934 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1935 }
1936 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1937 AssertRC(rc);
1938
1939 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1940 pPatch->cbNewOp = sizeof(s_abVMMCall);
1941 }
1942 else
1943 {
1944 /*
1945 * TPR Read.
1946 *
1947 * Found:
1948 * mov eax, dword [fffe0080] (5 bytes)
1949 * Check if next instruction is:
1950 * shr eax, 4
1951 */
1952 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1953
1954 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1955 uint8_t const cbOpMmio = cbOp;
1956 uint64_t const uSavedRip = pCtx->rip;
1957
1958 pCtx->rip += cbOp;
1959 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1960 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1961 pCtx->rip = uSavedRip;
1962
1963 if ( rc == VINF_SUCCESS
1964 && pDis->pCurInstr->uOpcode == OP_SHR
1965 && pDis->Param1.fUse == DISUSE_REG_GEN32
1966 && pDis->Param1.Base.idxGenReg == idxMmioReg
1967 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1968 && pDis->Param2.uValue == 4
1969 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1970 {
1971 uint8_t abInstr[15];
1972
1973 /* Replacing two instructions now. */
1974 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1975 AssertRC(rc);
1976
1977 pPatch->cbOp = cbOpMmio + cbOp;
1978
1979 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1980 abInstr[0] = 0xF0;
1981 abInstr[1] = 0x0F;
1982 abInstr[2] = 0x20;
1983 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1984 for (unsigned i = 4; i < pPatch->cbOp; i++)
1985 abInstr[i] = 0x90; /* nop */
1986
1987 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1988 AssertRC(rc);
1989
1990 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1991 pPatch->cbNewOp = pPatch->cbOp;
1992
1993 Log(("Acceptable read/shr candidate!\n"));
1994 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1995 }
1996 else
1997 {
1998 pPatch->enmType = HMTPRINSTR_READ;
1999 pPatch->uDstOperand = idxMmioReg;
2000
2001 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2002 AssertRC(rc);
2003
2004 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2005 pPatch->cbNewOp = sizeof(s_abVMMCall);
2006 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2007 }
2008 }
2009
2010 pPatch->Core.Key = pCtx->eip;
2011 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2012 AssertRC(rc);
2013
2014 pVM->hm.s.cPatches++;
2015 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
2016 return VINF_SUCCESS;
2017 }
2018
2019 /*
2020 * Save invalid patch, so we will not try again.
2021 */
2022 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2023 pPatch->Core.Key = pCtx->eip;
2024 pPatch->enmType = HMTPRINSTR_INVALID;
2025 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2026 AssertRC(rc);
2027 pVM->hm.s.cPatches++;
2028 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2029 return VINF_SUCCESS;
2030}
2031
2032
2033/**
2034 * Callback to patch a TPR instruction (jump to generated code).
2035 *
2036 * @returns VBox strict status code.
2037 * @param pVM Pointer to the VM.
2038 * @param pVCpu The VMCPU for the EMT we're being called on.
2039 * @param pvUser User specified CPU context.
2040 *
2041 */
2042DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2043{
2044 /*
2045 * Only execute the handler on the VCPU the original patch request was
2046 * issued. (The other CPU(s) might not yet have switched to protected
2047 * mode, nor have the correct memory context.)
2048 */
2049 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2050 if (pVCpu->idCpu != idCpu)
2051 return VINF_SUCCESS;
2052
2053 /*
2054 * We're racing other VCPUs here, so don't try patch the instruction twice
2055 * and make sure there is still room for our patch record.
2056 */
2057 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2058 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2059 if (pPatch)
2060 {
2061 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2062 return VINF_SUCCESS;
2063 }
2064 uint32_t const idx = pVM->hm.s.cPatches;
2065 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2066 {
2067 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2068 return VINF_SUCCESS;
2069 }
2070 pPatch = &pVM->hm.s.aPatches[idx];
2071
2072 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2073 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2074
2075 /*
2076 * Disassemble the instruction and get cracking.
2077 */
2078 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2079 uint32_t cbOp;
2080 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2081 AssertRC(rc);
2082 if ( rc == VINF_SUCCESS
2083 && pDis->pCurInstr->uOpcode == OP_MOV
2084 && cbOp >= 5)
2085 {
2086 uint8_t aPatch[64];
2087 uint32_t off = 0;
2088
2089 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2090 AssertRC(rc);
2091
2092 pPatch->cbOp = cbOp;
2093 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2094
2095 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2096 {
2097 /*
2098 * TPR write:
2099 *
2100 * push ECX [51]
2101 * push EDX [52]
2102 * push EAX [50]
2103 * xor EDX,EDX [31 D2]
2104 * mov EAX,EAX [89 C0]
2105 * or
2106 * mov EAX,0000000CCh [B8 CC 00 00 00]
2107 * mov ECX,0C0000082h [B9 82 00 00 C0]
2108 * wrmsr [0F 30]
2109 * pop EAX [58]
2110 * pop EDX [5A]
2111 * pop ECX [59]
2112 * jmp return_address [E9 return_address]
2113 *
2114 */
2115 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2116
2117 aPatch[off++] = 0x51; /* push ecx */
2118 aPatch[off++] = 0x52; /* push edx */
2119 if (!fUsesEax)
2120 aPatch[off++] = 0x50; /* push eax */
2121 aPatch[off++] = 0x31; /* xor edx, edx */
2122 aPatch[off++] = 0xD2;
2123 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2124 {
2125 if (!fUsesEax)
2126 {
2127 aPatch[off++] = 0x89; /* mov eax, src_reg */
2128 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2129 }
2130 }
2131 else
2132 {
2133 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2134 aPatch[off++] = 0xB8; /* mov eax, immediate */
2135 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2136 off += sizeof(uint32_t);
2137 }
2138 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2139 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2140 off += sizeof(uint32_t);
2141
2142 aPatch[off++] = 0x0F; /* wrmsr */
2143 aPatch[off++] = 0x30;
2144 if (!fUsesEax)
2145 aPatch[off++] = 0x58; /* pop eax */
2146 aPatch[off++] = 0x5A; /* pop edx */
2147 aPatch[off++] = 0x59; /* pop ecx */
2148 }
2149 else
2150 {
2151 /*
2152 * TPR read:
2153 *
2154 * push ECX [51]
2155 * push EDX [52]
2156 * push EAX [50]
2157 * mov ECX,0C0000082h [B9 82 00 00 C0]
2158 * rdmsr [0F 32]
2159 * mov EAX,EAX [89 C0]
2160 * pop EAX [58]
2161 * pop EDX [5A]
2162 * pop ECX [59]
2163 * jmp return_address [E9 return_address]
2164 *
2165 */
2166 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2167
2168 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2169 aPatch[off++] = 0x51; /* push ecx */
2170 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2171 aPatch[off++] = 0x52; /* push edx */
2172 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2173 aPatch[off++] = 0x50; /* push eax */
2174
2175 aPatch[off++] = 0x31; /* xor edx, edx */
2176 aPatch[off++] = 0xD2;
2177
2178 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2179 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2180 off += sizeof(uint32_t);
2181
2182 aPatch[off++] = 0x0F; /* rdmsr */
2183 aPatch[off++] = 0x32;
2184
2185 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2186 {
2187 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2188 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2189 }
2190
2191 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2192 aPatch[off++] = 0x58; /* pop eax */
2193 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2194 aPatch[off++] = 0x5A; /* pop edx */
2195 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2196 aPatch[off++] = 0x59; /* pop ecx */
2197 }
2198 aPatch[off++] = 0xE9; /* jmp return_address */
2199 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2200 off += sizeof(RTRCUINTPTR);
2201
2202 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2203 {
2204 /* Write new code to the patch buffer. */
2205 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2206 AssertRC(rc);
2207
2208#ifdef LOG_ENABLED
2209 uint32_t cbCurInstr;
2210 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2211 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2212 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2213 {
2214 char szOutput[256];
2215 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2216 szOutput, sizeof(szOutput), &cbCurInstr);
2217 if (RT_SUCCESS(rc))
2218 Log(("Patch instr %s\n", szOutput));
2219 else
2220 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2221 }
2222#endif
2223
2224 pPatch->aNewOpcode[0] = 0xE9;
2225 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2226
2227 /* Overwrite the TPR instruction with a jump. */
2228 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2229 AssertRC(rc);
2230
2231 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2232
2233 pVM->hm.s.pFreeGuestPatchMem += off;
2234 pPatch->cbNewOp = 5;
2235
2236 pPatch->Core.Key = pCtx->eip;
2237 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2238 AssertRC(rc);
2239
2240 pVM->hm.s.cPatches++;
2241 pVM->hm.s.fTPRPatchingActive = true;
2242 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2243 return VINF_SUCCESS;
2244 }
2245
2246 Log(("Ran out of space in our patch buffer!\n"));
2247 }
2248 else
2249 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2250
2251
2252 /*
2253 * Save invalid patch, so we will not try again.
2254 */
2255 pPatch = &pVM->hm.s.aPatches[idx];
2256 pPatch->Core.Key = pCtx->eip;
2257 pPatch->enmType = HMTPRINSTR_INVALID;
2258 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2259 AssertRC(rc);
2260 pVM->hm.s.cPatches++;
2261 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2262 return VINF_SUCCESS;
2263}
2264
2265
2266/**
2267 * Attempt to patch TPR mmio instructions.
2268 *
2269 * @returns VBox status code.
2270 * @param pVM Pointer to the VM.
2271 * @param pVCpu Pointer to the VMCPU.
2272 * @param pCtx Pointer to the guest CPU context.
2273 */
2274VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2275{
2276 NOREF(pCtx);
2277 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2278 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2279 (void *)(uintptr_t)pVCpu->idCpu);
2280 AssertRC(rc);
2281 return rc;
2282}
2283
2284
2285/**
2286 * Force execution of the current IO code in the recompiler.
2287 *
2288 * @returns VBox status code.
2289 * @param pVM Pointer to the VM.
2290 * @param pCtx Partial VM execution context.
2291 */
2292VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2293{
2294 PVMCPU pVCpu = VMMGetCpu(pVM);
2295
2296 Assert(HMIsEnabled(pVM));
2297 Log(("HMR3EmulateIoBlock\n"));
2298
2299 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2300 if (HMCanEmulateIoBlockEx(pCtx))
2301 {
2302 Log(("HMR3EmulateIoBlock -> enabled\n"));
2303 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2304 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2305 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2306 return VINF_EM_RESCHEDULE_REM;
2307 }
2308 return VINF_SUCCESS;
2309}
2310
2311
2312/**
2313 * Checks if we can currently use hardware accelerated raw mode.
2314 *
2315 * @returns true if we can currently use hardware acceleration, otherwise false.
2316 * @param pVM Pointer to the VM.
2317 * @param pCtx Partial VM execution context.
2318 */
2319VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2320{
2321 PVMCPU pVCpu = VMMGetCpu(pVM);
2322
2323 Assert(HMIsEnabled(pVM));
2324
2325 /* If we're still executing the IO code, then return false. */
2326 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2327 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2328 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2329 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2330 return false;
2331
2332 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2333
2334 /* AMD-V supports real & protected mode with or without paging. */
2335 if (pVM->hm.s.svm.fEnabled)
2336 {
2337 pVCpu->hm.s.fActive = true;
2338 return true;
2339 }
2340
2341 pVCpu->hm.s.fActive = false;
2342
2343 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2344 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2345 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2346
2347 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2348 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2349 {
2350 /*
2351 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2352 * guest execution feature i missing (VT-x only).
2353 */
2354 if (fSupportsRealMode)
2355 {
2356 if (CPUMIsGuestInRealModeEx(pCtx))
2357 {
2358 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2359 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2360 * If this is not true, we cannot execute real mode as V86 and have to fall
2361 * back to emulation.
2362 */
2363 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2364 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2365 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2366 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2367 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2368 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4)
2369 || (pCtx->cs.u32Limit != 0xffff)
2370 || (pCtx->ds.u32Limit != 0xffff)
2371 || (pCtx->es.u32Limit != 0xffff)
2372 || (pCtx->ss.u32Limit != 0xffff)
2373 || (pCtx->fs.u32Limit != 0xffff)
2374 || (pCtx->gs.u32Limit != 0xffff))
2375 {
2376 return false;
2377 }
2378 }
2379 else
2380 {
2381 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2382 /* Verify the requirements for executing code in protected
2383 mode. VT-x can't handle the CPU state right after a switch
2384 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2385 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2386 && enmGuestMode >= PGMMODE_PROTECTED)
2387 {
2388 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2389 || (pCtx->ds.Sel & X86_SEL_RPL)
2390 || (pCtx->es.Sel & X86_SEL_RPL)
2391 || (pCtx->fs.Sel & X86_SEL_RPL)
2392 || (pCtx->gs.Sel & X86_SEL_RPL)
2393 || (pCtx->ss.Sel & X86_SEL_RPL))
2394 {
2395 return false;
2396 }
2397 }
2398 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2399 if ( pCtx->gdtr.cbGdt
2400 && ( pCtx->tr.Sel > pCtx->gdtr.cbGdt
2401 || pCtx->ldtr.Sel > pCtx->gdtr.cbGdt))
2402 {
2403 return false;
2404 }
2405 }
2406 }
2407 else
2408 {
2409 if ( !CPUMIsGuestInLongModeEx(pCtx)
2410 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2411 {
2412 /** @todo This should (probably) be set on every excursion to the REM,
2413 * however it's too risky right now. So, only apply it when we go
2414 * back to REM for real mode execution. (The XP hack below doesn't
2415 * work reliably without this.)
2416 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2417 for (uint32_t i = 0; i < pVM->cCpus; i++)
2418 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2419
2420 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2421 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2422 return false;
2423
2424 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2425 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2426 return false;
2427
2428 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2429 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2430 * hidden registers (possible recompiler bug; see load_seg_vm) */
2431 if (pCtx->cs.Attr.n.u1Present == 0)
2432 return false;
2433 if (pCtx->ss.Attr.n.u1Present == 0)
2434 return false;
2435
2436 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2437 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2438 /** @todo This check is actually wrong, it doesn't take the direction of the
2439 * stack segment into account. But, it does the job for now. */
2440 if (pCtx->rsp >= pCtx->ss.u32Limit)
2441 return false;
2442#if 0
2443 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2444 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2445 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2446 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2447 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2448 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2449 return false;
2450#endif
2451 }
2452 }
2453 }
2454
2455 if (pVM->hm.s.vmx.fEnabled)
2456 {
2457 uint32_t mask;
2458
2459 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2460 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2461 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2462 mask &= ~X86_CR0_NE;
2463
2464 if (fSupportsRealMode)
2465 {
2466 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2467 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2468 }
2469 else
2470 {
2471 /* We support protected mode without paging using identity mapping. */
2472 mask &= ~X86_CR0_PG;
2473 }
2474 if ((pCtx->cr0 & mask) != mask)
2475 return false;
2476
2477 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2478 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2479 if ((pCtx->cr0 & mask) != 0)
2480 return false;
2481
2482 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2483 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2484 mask &= ~X86_CR4_VMXE;
2485 if ((pCtx->cr4 & mask) != mask)
2486 return false;
2487
2488 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2489 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2490 if ((pCtx->cr4 & mask) != 0)
2491 return false;
2492
2493 pVCpu->hm.s.fActive = true;
2494 return true;
2495 }
2496
2497 return false;
2498}
2499
2500
2501/**
2502 * Checks if we need to reschedule due to VMM device heap changes.
2503 *
2504 * @returns true if a reschedule is required, otherwise false.
2505 * @param pVM Pointer to the VM.
2506 * @param pCtx VM execution context.
2507 */
2508VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2509{
2510 /*
2511 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2512 * when the unrestricted guest execution feature is missing (VT-x only).
2513 */
2514#ifdef VBOX_WITH_OLD_VTX_CODE
2515 if ( pVM->hm.s.vmx.fEnabled
2516 && !pVM->hm.s.vmx.fUnrestrictedGuest
2517 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2518 && !PDMVmmDevHeapIsEnabled(pVM)
2519 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2520 return true;
2521#else
2522 if ( pVM->hm.s.vmx.fEnabled
2523 && !pVM->hm.s.vmx.fUnrestrictedGuest
2524 && CPUMIsGuestInRealModeEx(pCtx)
2525 && !PDMVmmDevHeapIsEnabled(pVM))
2526 return true;
2527#endif
2528
2529 return false;
2530}
2531
2532
2533/**
2534 * Notification from EM about a rescheduling into hardware assisted execution
2535 * mode.
2536 *
2537 * @param pVCpu Pointer to the current VMCPU.
2538 */
2539VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2540{
2541 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2542}
2543
2544
2545/**
2546 * Notification from EM about returning from instruction emulation (REM / EM).
2547 *
2548 * @param pVCpu Pointer to the VMCPU.
2549 */
2550VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2551{
2552 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2553}
2554
2555
2556/**
2557 * Checks if we are currently using hardware accelerated raw mode.
2558 *
2559 * @returns true if hardware acceleration is being used, otherwise false.
2560 * @param pVCpu Pointer to the VMCPU.
2561 */
2562VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2563{
2564 return pVCpu->hm.s.fActive;
2565}
2566
2567
2568/**
2569 * External interface for querying whether hardware accelerated raw mode is
2570 * enabled.
2571 *
2572 * @returns true if nested paging is being used, otherwise false.
2573 * @param pUVM The user mode VM handle.
2574 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2575 */
2576VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2577{
2578 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2579 PVM pVM = pUVM->pVM;
2580 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2581 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2582}
2583
2584
2585/**
2586 * Checks if we are currently using nested paging.
2587 *
2588 * @returns true if nested paging is being used, otherwise false.
2589 * @param pUVM The user mode VM handle.
2590 */
2591VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2592{
2593 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2594 PVM pVM = pUVM->pVM;
2595 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2596 return pVM->hm.s.fNestedPaging;
2597}
2598
2599
2600/**
2601 * Checks if we are currently using VPID in VT-x mode.
2602 *
2603 * @returns true if VPID is being used, otherwise false.
2604 * @param pUVM The user mode VM handle.
2605 */
2606VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2607{
2608 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2609 PVM pVM = pUVM->pVM;
2610 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2611 return pVM->hm.s.vmx.fVpid;
2612}
2613
2614
2615/**
2616 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2617 *
2618 * @returns true if an internal event is pending, otherwise false.
2619 * @param pVM Pointer to the VM.
2620 */
2621VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2622{
2623 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2624}
2625
2626
2627/**
2628 * Checks if the VMX-preemption timer is being used.
2629 *
2630 * @returns true if the VMX-preemption timer is being used, otherwise false.
2631 * @param pVM Pointer to the VM.
2632 */
2633VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2634{
2635 return HMIsEnabled(pVM)
2636 && pVM->hm.s.vmx.fEnabled
2637 && pVM->hm.s.vmx.fUsePreemptTimer;
2638}
2639
2640
2641/**
2642 * Restart an I/O instruction that was refused in ring-0
2643 *
2644 * @returns Strict VBox status code. Informational status codes other than the one documented
2645 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2646 * @retval VINF_SUCCESS Success.
2647 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2648 * status code must be passed on to EM.
2649 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2650 *
2651 * @param pVM Pointer to the VM.
2652 * @param pVCpu Pointer to the VMCPU.
2653 * @param pCtx Pointer to the guest CPU context.
2654 */
2655VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2656{
2657 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2658
2659 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2660
2661 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2662 || enmType == HMPENDINGIO_INVALID)
2663 return VERR_NOT_FOUND;
2664
2665 VBOXSTRICTRC rcStrict;
2666 switch (enmType)
2667 {
2668 case HMPENDINGIO_PORT_READ:
2669 {
2670 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2671 uint32_t u32Val = 0;
2672
2673 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2674 &u32Val,
2675 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2676 if (IOM_SUCCESS(rcStrict))
2677 {
2678 /* Write back to the EAX register. */
2679 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2680 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2681 }
2682 break;
2683 }
2684
2685 case HMPENDINGIO_PORT_WRITE:
2686 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2687 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2688 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2689 if (IOM_SUCCESS(rcStrict))
2690 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2691 break;
2692
2693 default:
2694 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2695 }
2696
2697 return rcStrict;
2698}
2699
2700
2701/**
2702 * Check fatal VT-x/AMD-V error and produce some meaningful
2703 * log release message.
2704 *
2705 * @param pVM Pointer to the VM.
2706 * @param iStatusCode VBox status code.
2707 */
2708VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2709{
2710 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2711 {
2712 switch (iStatusCode)
2713 {
2714 case VERR_VMX_INVALID_VMCS_FIELD:
2715 break;
2716
2717 case VERR_VMX_INVALID_VMCS_PTR:
2718 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2719 LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2720 LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2721 LogRel(("HM: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2722 LogRel(("HM: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2723 break;
2724
2725 case VERR_VMX_UNABLE_TO_START_VM:
2726 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2727 LogRel(("HM: CPU%d instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2728 LogRel(("HM: CPU%d exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2729 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2730 {
2731 LogRel(("HM: Cpu%d PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2732 LogRel(("HM: Cpu%d ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2733 LogRel(("HM: Cpu%d ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2734 LogRel(("HM: Cpu%d EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2735 LogRel(("HM: Cpu%d ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2736 LogRel(("HM: Cpu%d MSRBitmapPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2737#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2738 LogRel(("HM: Cpu%d GuestMSRPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2739 LogRel(("HM: Cpu%d HostMsrPhys %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2740 LogRel(("HM: Cpu%d cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2741#endif
2742 }
2743 /** @todo Log VM-entry event injection control fields
2744 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2745 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2746 break;
2747
2748 case VERR_VMX_INVALID_VMXON_PTR:
2749 break;
2750 }
2751 }
2752
2753 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2754 {
2755 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2756 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2757 }
2758}
2759
2760
2761/**
2762 * Execute state save operation.
2763 *
2764 * @returns VBox status code.
2765 * @param pVM Pointer to the VM.
2766 * @param pSSM SSM operation handle.
2767 */
2768static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2769{
2770 int rc;
2771
2772 Log(("hmR3Save:\n"));
2773
2774 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2775 {
2776 /*
2777 * Save the basic bits - fortunately all the other things can be resynced on load.
2778 */
2779 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2780 AssertRCReturn(rc, rc);
2781 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2782 AssertRCReturn(rc, rc);
2783 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2784 AssertRCReturn(rc, rc);
2785
2786 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2787 AssertRCReturn(rc, rc);
2788 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2789 AssertRCReturn(rc, rc);
2790 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2791 AssertRCReturn(rc, rc);
2792 }
2793#ifdef VBOX_HM_WITH_GUEST_PATCHING
2794 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2795 AssertRCReturn(rc, rc);
2796 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2797 AssertRCReturn(rc, rc);
2798 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2799 AssertRCReturn(rc, rc);
2800
2801 /* Store all the guest patch records too. */
2802 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
2803 AssertRCReturn(rc, rc);
2804
2805 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2806 {
2807 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2808
2809 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
2810 AssertRCReturn(rc, rc);
2811
2812 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2813 AssertRCReturn(rc, rc);
2814
2815 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
2816 AssertRCReturn(rc, rc);
2817
2818 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2819 AssertRCReturn(rc, rc);
2820
2821 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
2822 AssertRCReturn(rc, rc);
2823
2824 AssertCompileSize(HMTPRINSTR, 4);
2825 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
2826 AssertRCReturn(rc, rc);
2827
2828 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
2829 AssertRCReturn(rc, rc);
2830
2831 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
2832 AssertRCReturn(rc, rc);
2833
2834 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
2835 AssertRCReturn(rc, rc);
2836
2837 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
2838 AssertRCReturn(rc, rc);
2839 }
2840#endif
2841 return VINF_SUCCESS;
2842}
2843
2844
2845/**
2846 * Execute state load operation.
2847 *
2848 * @returns VBox status code.
2849 * @param pVM Pointer to the VM.
2850 * @param pSSM SSM operation handle.
2851 * @param uVersion Data layout version.
2852 * @param uPass The data pass.
2853 */
2854static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
2855{
2856 int rc;
2857
2858 Log(("hmR3Load:\n"));
2859 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
2860
2861 /*
2862 * Validate version.
2863 */
2864 if ( uVersion != HM_SSM_VERSION
2865 && uVersion != HM_SSM_VERSION_NO_PATCHING
2866 && uVersion != HM_SSM_VERSION_2_0_X)
2867 {
2868 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
2869 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
2870 }
2871 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2872 {
2873 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
2874 AssertRCReturn(rc, rc);
2875 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
2876 AssertRCReturn(rc, rc);
2877 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2878 AssertRCReturn(rc, rc);
2879
2880 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
2881 {
2882 uint32_t val;
2883
2884 rc = SSMR3GetU32(pSSM, &val);
2885 AssertRCReturn(rc, rc);
2886 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
2887
2888 rc = SSMR3GetU32(pSSM, &val);
2889 AssertRCReturn(rc, rc);
2890 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
2891
2892 rc = SSMR3GetU32(pSSM, &val);
2893 AssertRCReturn(rc, rc);
2894 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
2895 }
2896 }
2897#ifdef VBOX_HM_WITH_GUEST_PATCHING
2898 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
2899 {
2900 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
2901 AssertRCReturn(rc, rc);
2902 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
2903 AssertRCReturn(rc, rc);
2904 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
2905 AssertRCReturn(rc, rc);
2906
2907 /* Fetch all TPR patch records. */
2908 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
2909 AssertRCReturn(rc, rc);
2910
2911 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2912 {
2913 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2914
2915 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
2916 AssertRCReturn(rc, rc);
2917
2918 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
2919 AssertRCReturn(rc, rc);
2920
2921 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
2922 AssertRCReturn(rc, rc);
2923
2924 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
2925 AssertRCReturn(rc, rc);
2926
2927 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
2928 AssertRCReturn(rc, rc);
2929
2930 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
2931 AssertRCReturn(rc, rc);
2932
2933 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
2934 pVM->hm.s.fTPRPatchingActive = true;
2935
2936 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
2937
2938 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
2939 AssertRCReturn(rc, rc);
2940
2941 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
2942 AssertRCReturn(rc, rc);
2943
2944 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
2945 AssertRCReturn(rc, rc);
2946
2947 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
2948 AssertRCReturn(rc, rc);
2949
2950 Log(("hmR3Load: patch %d\n", i));
2951 Log(("Key = %x\n", pPatch->Core.Key));
2952 Log(("cbOp = %d\n", pPatch->cbOp));
2953 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
2954 Log(("type = %d\n", pPatch->enmType));
2955 Log(("srcop = %d\n", pPatch->uSrcOperand));
2956 Log(("dstop = %d\n", pPatch->uDstOperand));
2957 Log(("cFaults = %d\n", pPatch->cFaults));
2958 Log(("target = %x\n", pPatch->pJumpTarget));
2959 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2960 AssertRC(rc);
2961 }
2962 }
2963#endif
2964
2965 /* Recheck all VCPUs if we can go straight into hm execution mode. */
2966 if (HMIsEnabled(pVM))
2967 {
2968 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2969 {
2970 PVMCPU pVCpu = &pVM->aCpus[i];
2971
2972 HMR3CanExecuteGuest(pVM, CPUMQueryGuestCtxPtr(pVCpu));
2973 }
2974 }
2975 return VINF_SUCCESS;
2976}
2977
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