VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 46118

Last change on this file since 46118 was 45971, checked in by vboxsync, 12 years ago

Main, VMM: Added an API seting to disable VT-x unrestricted execution.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 138.3 KB
Line 
1/* $Id: HM.cpp 45971 2013-05-09 19:46:52Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/ssm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/csam.h>
34#include <VBox/vmm/selm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/uvm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/asm-amd64-x86.h>
50#include <iprt/string.h>
51#include <iprt/env.h>
52#include <iprt/thread.h>
53
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58#ifdef VBOX_WITH_STATISTICS
59# define EXIT_REASON(def, val, str) #def " - " #val " - " str
60# define EXIT_REASON_NIL() NULL
61/** Exit reason descriptions for VT-x, used to describe statistics. */
62static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
63{
64 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
65 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
66 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
67 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
68 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
69 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
70 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
71 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
74 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest attempted to execute CPUID."),
75 EXIT_REASON_NIL(),
76 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest attempted to execute HLT."),
77 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest attempted to execute INVD."),
78 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest attempted to execute INVLPG."),
79 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest attempted to execute RDPMC."),
80 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest attempted to execute RDTSC."),
81 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest attempted to execute RSM in SMM."),
82 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest attempted to execute VMCALL."),
83 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest attempted to execute VMCLEAR."),
84 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest attempted to execute VMLAUNCH."),
85 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest attempted to execute VMPTRLD."),
86 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest attempted to execute VMPTRST."),
87 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest attempted to execute VMREAD."),
88 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest attempted to execute VMRESUME."),
89 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest attempted to execute VMWRITE."),
90 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest attempted to execute VMXOFF."),
91 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest attempted to execute VMXON."),
92 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
93 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
94 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
95 EXIT_REASON(VMX_EXIT_RDMSR , 31, "Guest attempted to execute RDMSR."),
96 EXIT_REASON(VMX_EXIT_WRMSR , 32, "Guest attempted to execute WRMSR."),
97 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
98 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest executed MWAIT."),
101 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest attempted to execute MONITOR."),
104 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest attempted to execute PAUSE."),
105 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest attempted to execute MOV to CR8."),
108 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest attempted to access memory at a physical address on the APIC-access page."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest attempted to execute LGDT, LIDT, SGDT, or SIDT."),
111 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest attempted to execute LLDT, LTR, SLDT, or STR."),
112 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
113 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
114 EXIT_REASON(VMX_EXIT_INVEPT , 50, "Guest attempted to execute INVEPT."),
115 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest attempted to execute RDTSCP."),
116 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
117 EXIT_REASON(VMX_EXIT_INVVPID , 53, "Guest attempted to execute INVVPID."),
118 EXIT_REASON(VMX_EXIT_WBINVD , 54, "Guest attempted to execute WBINVD."),
119 EXIT_REASON(VMX_EXIT_XSETBV , 55, "Guest attempted to execute XSETBV."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_RDRAND , 57, "Guest attempted to execute RDRAND."),
122 EXIT_REASON(VMX_EXIT_INVPCID , 58, "Guest attempted to execute INVPCID."),
123 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "Guest attempted to execute VMFUNC.")
124};
125/** Exit reason descriptions for AMD-V, used to describe statistics. */
126static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
231 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
232 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
252 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
270 EXIT_REASON_NIL()
271};
272# undef EXIT_REASON
273# undef EXIT_REASON_NIL
274#endif /* VBOX_WITH_STATISTICS */
275
276#define VMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
277 do { \
278 if ((allowed1) & (featflag)) \
279 LogRel(("HM: " #featflag "\n")); \
280 else \
281 LogRel(("HM: " #featflag " *must* be cleared\n")); \
282 if ((disallowed0) & (featflag)) \
283 LogRel(("HM: " #featflag " *must* be set\n")); \
284 } while (0)
285
286#define VMX_REPORT_CAPABILITY(msrcaps, cap) \
287 do { \
288 if ((msrcaps) & (cap)) \
289 LogRel(("HM: " #cap "\n")); \
290 } while (0)
291
292
293/*******************************************************************************
294* Internal Functions *
295*******************************************************************************/
296static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
297static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
298static int hmR3InitCPU(PVM pVM);
299static int hmR3InitFinalizeR0(PVM pVM);
300static int hmR3InitFinalizeR0Intel(PVM pVM);
301static int hmR3InitFinalizeR0Amd(PVM pVM);
302static int hmR3TermCPU(PVM pVM);
303
304
305
306/**
307 * Initializes the HM.
308 *
309 * This reads the config and check whether VT-x or AMD-V hardware is available
310 * if configured to use it. This is one of the very first components to be
311 * initialized after CFGM, so that we can fall back to raw-mode early in the
312 * initialization process.
313 *
314 * Note that a lot of the set up work is done in ring-0 and thus postponed till
315 * the ring-3 and ring-0 callback to HMR3InitCompleted.
316 *
317 * @returns VBox status code.
318 * @param pVM Pointer to the VM.
319 *
320 * @remarks Be careful with what we call here, since most of the VMM components
321 * are uninitialized.
322 */
323VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
324{
325 LogFlow(("HMR3Init\n"));
326
327 /*
328 * Assert alignment and sizes.
329 */
330 AssertCompileMemberAlignment(VM, hm.s, 32);
331 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
332
333 /* Some structure checks. */
334 AssertCompileMemberOffset(SVM_VMCB, ctrl.EventInject, 0xA8);
335 AssertCompileMemberOffset(SVM_VMCB, ctrl.ExitIntInfo, 0x88);
336 AssertCompileMemberOffset(SVM_VMCB, ctrl.TLBCtrl, 0x58);
337
338 AssertCompileMemberOffset(SVM_VMCB, guest, 0x400);
339 AssertCompileMemberOffset(SVM_VMCB, guest.TR, 0x490);
340 AssertCompileMemberOffset(SVM_VMCB, guest.u8CPL, 0x4CB);
341 AssertCompileMemberOffset(SVM_VMCB, guest.u64EFER, 0x4D0);
342 AssertCompileMemberOffset(SVM_VMCB, guest.u64CR4, 0x548);
343 AssertCompileMemberOffset(SVM_VMCB, guest.u64RIP, 0x578);
344 AssertCompileMemberOffset(SVM_VMCB, guest.u64RSP, 0x5D8);
345 AssertCompileMemberOffset(SVM_VMCB, guest.u64CR2, 0x640);
346 AssertCompileMemberOffset(SVM_VMCB, guest.u64GPAT, 0x668);
347 AssertCompileMemberOffset(SVM_VMCB, guest.u64LASTEXCPTO,0x690);
348 AssertCompileSize(SVM_VMCB, 0x1000);
349
350 /*
351 * Register the saved state data unit.
352 */
353 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
354 NULL, NULL, NULL,
355 NULL, hmR3Save, NULL,
356 NULL, hmR3Load, NULL);
357 if (RT_FAILURE(rc))
358 return rc;
359
360 /*
361 * Misc initialisation.
362 */
363 //pVM->hm.s.vmx.fSupported = false;
364 //pVM->hm.s.svm.fSupported = false;
365 //pVM->hm.s.vmx.fEnabled = false;
366 //pVM->hm.s.svm.fEnabled = false;
367 //pVM->hm.s.fNestedPaging = false;
368
369
370 /*
371 * Read configuration.
372 */
373 PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
374
375 /** @cfgm{/HM/HMForced, bool, false}
376 * Forces hardware virtualization, no falling back on raw-mode. HM must be
377 * enabled, i.e. /HMEnabled must be true. */
378 bool fHMForced;
379#ifdef VBOX_WITH_RAW_MODE
380 rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
381 AssertRCReturn(rc, rc);
382 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
383 VERR_INVALID_PARAMETER);
384# if defined(RT_OS_DARWIN)
385 if (pVM->fHMEnabled)
386 fHMForced = true;
387# endif
388 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
389 VERR_INVALID_PARAMETER);
390 if (pVM->cCpus > 1)
391 fHMForced = true;
392#else /* !VBOX_WITH_RAW_MODE */
393 AssertRelease(pVM->fHMEnabled);
394 fHMForced = true;
395#endif /* !VBOX_WITH_RAW_MODE */
396
397 /** @cfgm{/HM/EnableNestedPaging, bool, false}
398 * Enables nested paging (aka extended page tables). */
399 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
400 AssertRCReturn(rc, rc);
401
402 /** @cfgm{/HM/EnableUX, bool, true}
403 * Enables the VT-x unrestricted execution feature. */
404 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
405 AssertRCReturn(rc, rc);
406
407 /** @cfgm{/HM/EnableLargePages, bool, false}
408 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
409 * page table walking and maybe better TLB hit rate in some cases. */
410 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
411 AssertRCReturn(rc, rc);
412
413 /** @cfgm{/HM/EnableVPID, bool, false}
414 * Enables the VT-x VPID feature. */
415 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
416 AssertRCReturn(rc, rc);
417
418 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
419 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
420 rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
421 AssertRCReturn(rc, rc);
422
423 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
424 * Enables AMD64 cpu features.
425 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
426 * already have the support. */
427#ifdef VBOX_ENABLE_64_BITS_GUESTS
428 rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
429 AssertLogRelRCReturn(rc, rc);
430#else
431 pVM->hm.s.fAllow64BitGuests = false;
432#endif
433
434 /** @cfgm{/HM/Exclusive, bool}
435 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
436 * global init for each host CPU. If false, we do local init each time we wish
437 * to execute guest code.
438 *
439 * Default is false for Mac OS X and Windows due to the higher risk of conflicts
440 * with other hypervisors.
441 */
442 rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
443#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
444 false
445#else
446 true
447#endif
448 );
449 AssertLogRelRCReturn(rc, rc);
450
451 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
452 * The number of times to resume guest execution before we forcibly return to
453 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
454 * determins the default value. */
455 rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
456 AssertLogRelRCReturn(rc, rc);
457
458 /*
459 * Check if VT-x or AMD-v support according to the users wishes.
460 */
461 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
462 * VERR_SVM_IN_USE. */
463 if (pVM->fHMEnabled)
464 {
465 uint32_t fCaps;
466 rc = SUPR3QueryVTCaps(&fCaps);
467 if (RT_SUCCESS(rc))
468 {
469 if (fCaps & SUPVTCAPS_AMD_V)
470 LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
471 else if (fCaps & SUPVTCAPS_VT_X)
472 {
473 rc = SUPR3QueryVTxSupported();
474 if (RT_SUCCESS(rc))
475 LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
476 else
477 {
478#ifdef RT_OS_LINUX
479 const char *pszMinReq = " Linux 2.6.13 or newer required!";
480#else
481 const char *pszMinReq = "";
482#endif
483 if (fHMForced)
484 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
485
486 /* Fall back to raw-mode. */
487 LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
488 pVM->fHMEnabled = false;
489 }
490 }
491 else
492 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
493 VERR_INTERNAL_ERROR_5);
494
495 /*
496 * Do we require a little bit or raw-mode for 64-bit guest execution?
497 */
498 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
499 && pVM->fHMEnabled
500 && pVM->hm.s.fAllow64BitGuests;
501 }
502 else
503 {
504 const char *pszMsg;
505 switch (rc)
506 {
507 case VERR_UNSUPPORTED_CPU:
508 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
509 break;
510
511 case VERR_VMX_NO_VMX:
512 pszMsg = "VT-x is not available.";
513 break;
514
515 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
516 pszMsg = "VT-x is disabled in the BIOS (or by the host OS).";
517 break;
518
519 case VERR_SVM_NO_SVM:
520 pszMsg = "AMD-V is not available.";
521 break;
522
523 case VERR_SVM_DISABLED:
524 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
525 break;
526
527 default:
528 pszMsg = NULL;
529 break;
530 }
531 if (fHMForced && pszMsg)
532 return VM_SET_ERROR(pVM, rc, pszMsg);
533 if (!pszMsg)
534 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
535
536 /* Fall back to raw-mode. */
537 LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
538 pVM->fHMEnabled = false;
539 }
540 }
541
542 /* It's now OK to use the predicate function. */
543 pVM->fHMEnabledFixed = true;
544 return VINF_SUCCESS;
545}
546
547
548/**
549 * Initializes the per-VCPU HM.
550 *
551 * @returns VBox status code.
552 * @param pVM Pointer to the VM.
553 */
554static int hmR3InitCPU(PVM pVM)
555{
556 LogFlow(("HMR3InitCPU\n"));
557
558 if (!HMIsEnabled(pVM))
559 return VINF_SUCCESS;
560
561 for (VMCPUID i = 0; i < pVM->cCpus; i++)
562 {
563 PVMCPU pVCpu = &pVM->aCpus[i];
564 pVCpu->hm.s.fActive = false;
565 }
566
567#ifdef VBOX_WITH_STATISTICS
568 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
569 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
570 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
571 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
572
573 /*
574 * Statistics.
575 */
576 for (VMCPUID i = 0; i < pVM->cCpus; i++)
577 {
578 PVMCPU pVCpu = &pVM->aCpus[i];
579 int rc;
580
581 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
582 "Profiling of RTMpPokeCpu",
583 "/PROF/CPU%d/HM/Poke", i);
584 AssertRC(rc);
585 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
586 "Profiling of poke wait",
587 "/PROF/CPU%d/HM/PokeWait", i);
588 AssertRC(rc);
589 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
590 "Profiling of poke wait when RTMpPokeCpu fails",
591 "/PROF/CPU%d/HM/PokeWaitFailed", i);
592 AssertRC(rc);
593 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
594 "Profiling of VMXR0RunGuestCode entry",
595 "/PROF/CPU%d/HM/StatEntry", i);
596 AssertRC(rc);
597 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
598 "Profiling of VMXR0RunGuestCode exit part 1",
599 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
600 AssertRC(rc);
601 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
602 "Profiling of VMXR0RunGuestCode exit part 2",
603 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
604 AssertRC(rc);
605
606 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
607 "I/O",
608 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
609 AssertRC(rc);
610 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
611 "MOV CRx",
612 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
613 AssertRC(rc);
614 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
615 "Exceptions, NMIs",
616 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
617 AssertRC(rc);
618
619 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
620 "Profiling of VMXR0LoadGuestState",
621 "/PROF/CPU%d/HM/StatLoadGuestState", i);
622 AssertRC(rc);
623 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
624 "Profiling of VMLAUNCH/VMRESUME.",
625 "/PROF/CPU%d/HM/InGC", i);
626 AssertRC(rc);
627
628# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
629 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
630 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
631 "/PROF/CPU%d/HM/Switcher3264", i);
632 AssertRC(rc);
633# endif
634
635# ifdef HM_PROFILE_EXIT_DISPATCH
636 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
637 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
638 "/PROF/CPU%d/HM/ExitDispatch", i);
639 AssertRC(rc);
640# endif
641
642# define HM_REG_COUNTER(a, b, desc) \
643 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
644 AssertRC(rc);
645
646 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
647 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
648 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
649 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
650 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
651 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
652 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
653 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
654 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) execption.");
655 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
656 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
657 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
658 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
659 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
660 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
661 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
662 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
663 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
664 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
665 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
666 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
667 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
668 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
669 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
670 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
671 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
672 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
673 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
674 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
675 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
676 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
677 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
678 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
679 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
680 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
681 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
682 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
683 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
684 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
685 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
686 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
687 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
688 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
689 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
690 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
691 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
692 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
693 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
694 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
695 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
696 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
697 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
698
699 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
700 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
701 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
702 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
703
704 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject", "Injecting hardware interrupt into the guest.");
705 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject", "Re-injecting an event into the guest.");
706 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost", "Exiting to ring-3 due to preemption pending on the host.");
707
708 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
709 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
710 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
711 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
712 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
713 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
714 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
715 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
716 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
717 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
718 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
719 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
720 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
721
722 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
724 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
725
726 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
727 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
728 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
729
730 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading just RIP (+RSP, RFLAGs for old VT-x code).");
731 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading more of the state.");
732
733 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
734 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
735 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
736
737 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
738 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
739 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
740 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
741 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
742
743#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
744 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
745 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
746#endif
747
748 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
749 {
750 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
751 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
752 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
753 AssertRC(rc);
754 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
755 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
756 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
757 AssertRC(rc);
758 }
759
760#undef HM_REG_COUNTER
761
762 pVCpu->hm.s.paStatExitReason = NULL;
763
764 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
765 (void **)&pVCpu->hm.s.paStatExitReason);
766 AssertRC(rc);
767 if (RT_SUCCESS(rc))
768 {
769 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
770 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
771 {
772 if (papszDesc[j])
773 {
774 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
775 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
776 AssertRC(rc);
777 }
778 }
779 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
780 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
781 AssertRC(rc);
782 }
783 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
784# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
785 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
786# else
787 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
788# endif
789
790 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
791 AssertRCReturn(rc, rc);
792 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
793# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
794 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
795# else
796 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
797# endif
798 for (unsigned j = 0; j < 255; j++)
799 {
800 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
801 "Forwarded interrupts.",
802 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
803 }
804
805 }
806#endif /* VBOX_WITH_STATISTICS */
807
808#ifdef VBOX_WITH_CRASHDUMP_MAGIC
809 /*
810 * Magic marker for searching in crash dumps.
811 */
812 for (VMCPUID i = 0; i < pVM->cCpus; i++)
813 {
814 PVMCPU pVCpu = &pVM->aCpus[i];
815
816 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
817 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
818 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
819 }
820#endif
821
822 return VINF_SUCCESS;
823}
824
825
826/**
827 * Called when a init phase has completed.
828 *
829 * @returns VBox status code.
830 * @param pVM The VM.
831 * @param enmWhat The phase that completed.
832 */
833VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
834{
835 switch (enmWhat)
836 {
837 case VMINITCOMPLETED_RING3:
838 return hmR3InitCPU(pVM);
839 case VMINITCOMPLETED_RING0:
840 return hmR3InitFinalizeR0(pVM);
841 default:
842 return VINF_SUCCESS;
843 }
844}
845
846
847/**
848 * Turns off normal raw mode features.
849 *
850 * @param pVM Pointer to the VM.
851 */
852static void hmR3DisableRawMode(PVM pVM)
853{
854 /* Reinit the paging mode to force the new shadow mode. */
855 for (VMCPUID i = 0; i < pVM->cCpus; i++)
856 {
857 PVMCPU pVCpu = &pVM->aCpus[i];
858
859 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
860 }
861}
862
863
864/**
865 * Initialize VT-x or AMD-V.
866 *
867 * @returns VBox status code.
868 * @param pVM Pointer to the VM.
869 */
870static int hmR3InitFinalizeR0(PVM pVM)
871{
872 int rc;
873
874 if (!HMIsEnabled(pVM))
875 return VINF_SUCCESS;
876
877 /*
878 * Hack to allow users to work around broken BIOSes that incorrectly set
879 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
880 */
881 if ( !pVM->hm.s.vmx.fSupported
882 && !pVM->hm.s.svm.fSupported
883 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
884 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
885 {
886 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
887 pVM->hm.s.svm.fSupported = true;
888 pVM->hm.s.svm.fIgnoreInUseError = true;
889 pVM->hm.s.lLastError = VINF_SUCCESS;
890 }
891
892 /*
893 * Report ring-0 init errors.
894 */
895 if ( !pVM->hm.s.vmx.fSupported
896 && !pVM->hm.s.svm.fSupported)
897 {
898 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
899 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
900 switch (pVM->hm.s.lLastError)
901 {
902 case VERR_VMX_IN_VMX_ROOT_MODE:
903 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
904 case VERR_VMX_NO_VMX:
905 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
906 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
907 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS (or by the host OS).");
908
909 case VERR_SVM_IN_USE:
910 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
911 case VERR_SVM_NO_SVM:
912 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
913 case VERR_SVM_DISABLED:
914 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
915 }
916 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
917 }
918
919 /*
920 * Enable VT-x or AMD-V on all host CPUs.
921 */
922 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
923 if (RT_FAILURE(rc))
924 {
925 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
926 return rc;
927 }
928
929 /*
930 * No TPR patching is required when the IO-APIC is not enabled for this VM.
931 * (Main should have taken care of this already)
932 */
933 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
934 if (!pVM->hm.s.fHasIoApic)
935 {
936 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
937 pVM->hm.s.fTRPPatchingAllowed = false;
938 }
939
940 /*
941 * Do the vendor specific initalization .
942 * .
943 * Note! We disable release log buffering here since we're doing relatively .
944 * lot of logging and doesn't want to hit the disk with each LogRel .
945 * statement.
946 */
947 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
948 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
949 if (pVM->hm.s.vmx.fSupported)
950 rc = hmR3InitFinalizeR0Intel(pVM);
951 else
952 rc = hmR3InitFinalizeR0Amd(pVM);
953 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
954 RTLogRelSetBuffering(fOldBuffered);
955 pVM->hm.s.fInitialized = true;
956
957 return rc;
958}
959
960
961/**
962 * Finish VT-x initialization (after ring-0 init).
963 *
964 * @returns VBox status code.
965 * @param pVM The cross context VM structure.
966 */
967static int hmR3InitFinalizeR0Intel(PVM pVM)
968{
969 int rc;
970
971 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
972 AssertLogRelReturn(pVM->hm.s.vmx.msr.feature_ctrl != 0, VERR_HM_IPE_4);
973
974 uint64_t val;
975 uint64_t zap;
976 RTGCPHYS GCPhys = 0;
977
978#ifndef VBOX_WITH_OLD_VTX_CODE
979 LogRel(("HM: Using VT-x implementation 2.0!\n"));
980#endif
981 LogRel(("HM: Host CR4 = %08X\n", pVM->hm.s.vmx.hostCR4));
982 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
983 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
984 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
985 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
986 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
987 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
988 LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
989 LogRel(("HM: Max resume loops = %RX32\n", pVM->hm.s.cMaxResumeLoops));
990
991 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
992 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
993 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
994 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
995 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
996 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
997 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
998
999 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
1000 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
1001 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
1002 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1003 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1004 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1005 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1006 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1007 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1008 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1009 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1010 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1011 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1012 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1013 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1014 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1015 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1016 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1017 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1018 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1019 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1020 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1021 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1022 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1023 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1024 {
1025 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
1026 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
1027 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
1028 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1029 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1030 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1031 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1032 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1033 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1034 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1035 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1036 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1037 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1038 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1039 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1040 }
1041
1042 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
1043 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
1044 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
1045 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1046 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1047 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1048 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1049 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1050 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1051 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1052
1053 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
1054 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
1055 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
1056 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1057 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1058 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1059 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1060 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1061 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1062 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1063 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1064 VMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1065
1066 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
1067 {
1068 val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
1069 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", val));
1070 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1071 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1072 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1073 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1074 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1075 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1076 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1077 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1078 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1079 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1080 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1081 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1082 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1083 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1084 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1085 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1086 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1087 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1088 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1089 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1090 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1091 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1092 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1093 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1094 VMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1095 }
1096
1097 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
1098 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1099 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
1100 else
1101 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
1102 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
1103
1104 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
1105 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
1106 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
1107 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
1108
1109 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
1110 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
1111 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1112 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1113 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1114
1115 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1116
1117 /* Paranoia */
1118 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1119
1120 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1121 {
1122 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1123 LogRel(("HM: VCPU%3d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1124 }
1125
1126 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1127 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1128
1129 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1130 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1131
1132 /*
1133 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1134 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1135 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1136 */
1137 if (!(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1138 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1139 {
1140 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1141 LogRel(("HM: RDTSCP disabled.\n"));
1142 }
1143
1144 /* Unrestricted guest execution also requires EPT. */
1145 if ( pVM->hm.s.vmx.fAllowUnrestricted
1146 && pVM->hm.s.fNestedPaging
1147 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1148 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1149
1150 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1151 {
1152 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1153 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1154 if (RT_SUCCESS(rc))
1155 {
1156 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap.
1157 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1158 esp. Figure 20-5.*/
1159 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1160 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1161
1162 /* Bit set to 0 means software interrupts are redirected to the
1163 8086 program interrupt handler rather than switching to
1164 protected-mode handler. */
1165 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1166
1167 /* Allow all port IO, so that port IO instructions do not cause
1168 exceptions and would instead cause a VM-exit (based on VT-x's
1169 IO bitmap which we currently configure to always cause an exit). */
1170 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1171 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1172
1173 /*
1174 * Construct a 1024 element page directory with 4 MB pages for
1175 * the identity mapped page table used in real and protected mode
1176 * without paging with EPT.
1177 */
1178 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1179 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1180 {
1181 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1182 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1183 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1184 | X86_PDE4M_G;
1185 }
1186
1187 /* We convert it here every time as pci regions could be reconfigured. */
1188 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1189 AssertRCReturn(rc, rc);
1190 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1191
1192 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1193 AssertRCReturn(rc, rc);
1194 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1195 }
1196 else
1197 {
1198 /** @todo This cannot possibly work, there are other places which assumes
1199 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1200 * a failure case. */
1201 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1202 pVM->hm.s.vmx.pRealModeTSS = NULL;
1203 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1204 }
1205 }
1206
1207 /*
1208 * Call ring-0 to set up the VM.
1209 */
1210 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1211 if (rc != VINF_SUCCESS)
1212 {
1213 AssertMsgFailed(("%Rrc\n", rc));
1214 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1215 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1216 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1217 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1218 }
1219
1220 LogRel(("HM: VMX enabled!\n"));
1221 pVM->hm.s.vmx.fEnabled = true;
1222
1223 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1224
1225 /*
1226 * Change the CPU features.
1227 */
1228 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1229 if (pVM->hm.s.fAllow64BitGuests)
1230 {
1231 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1232 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1233 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1234 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1235 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1236#if 0 /** @todo r=bird: This ain't making any sense whatsoever. */
1237#if RT_ARCH_X86
1238 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1239 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1240 LogRel(("NX is only supported for 64-bit guests!\n"));
1241#endif
1242#endif
1243 }
1244 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1245 (we reuse the host EFER in the switcher). */
1246 /** @todo this needs to be fixed properly!! */
1247 else if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1248 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1249 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1250 else
1251 LogRel(("HM: NX not supported by the host.\n"));
1252
1253 /*
1254 * Log configuration details.
1255 */
1256 LogRel((pVM->hm.s.fAllow64BitGuests
1257 ? "HM: Guest support: 32-bit and 64-bit.\n"
1258 : "HM: Guest support: 32-bit only.\n"));
1259 if (pVM->hm.s.fNestedPaging)
1260 {
1261 LogRel(("HM: Nested paging enabled!\n"));
1262 LogRel(("HM: EPT root page = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1263 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1264 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1265 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1266 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1267 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1268 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1269 else
1270 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1271
1272 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1273 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1274
1275#if HC_ARCH_BITS == 64
1276 if (pVM->hm.s.fLargePages)
1277 {
1278 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1279 PGMSetLargePageUsage(pVM, true);
1280 LogRel(("HM: Large page support enabled!\n"));
1281 }
1282#endif
1283 }
1284 else
1285 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1286
1287 if (pVM->hm.s.vmx.fVpid)
1288 {
1289 LogRel(("HM: VPID enabled!\n"));
1290 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1291 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1292 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1293 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1294 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1295 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1296 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1297 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1298 else
1299 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1300 }
1301 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1302 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1303
1304 /*
1305 * TPR patching status logging.
1306 */
1307 if (pVM->hm.s.fTRPPatchingAllowed)
1308 {
1309 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1310 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1311 {
1312 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1313 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1314 }
1315 else
1316 {
1317 uint32_t u32Eax, u32Dummy;
1318
1319 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1320 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1321 if ( u32Eax < 0x80000001
1322 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1323 {
1324 pVM->hm.s.fTRPPatchingAllowed = false;
1325 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1326 }
1327 }
1328 }
1329 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1330
1331 /*
1332 * Check for preemption timer config override and log the state of it.
1333 */
1334 if (pVM->hm.s.vmx.fUsePreemptTimer)
1335 {
1336 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1337 rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1338 AssertLogRelRCReturn(rc, rc);
1339 }
1340 if (pVM->hm.s.vmx.fUsePreemptTimer)
1341 LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u).\n", pVM->hm.s.vmx.cPreemptTimerShift));
1342 else
1343 LogRel(("HM: VMX-preemption timer disabled.\n"));
1344
1345 return VINF_SUCCESS;
1346}
1347
1348
1349/**
1350 * Finish AMD-V initialization (after ring-0 init).
1351 *
1352 * @returns VBox status code.
1353 * @param pVM The cross context VM structure.
1354 */
1355static int hmR3InitFinalizeR0Amd(PVM pVM)
1356{
1357 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1358
1359 /* Erratum 170 which requires a forced TLB flush for each world switch:
1360 * See http://www.amd.com/us-en/assets/content_type/white_papers_and_tech_docs/33610.pdf
1361 *
1362 * All BH-G1/2 and DH-G1/2 models include a fix:
1363 * Athlon X2: 0x6b 1/2
1364 * 0x68 1/2
1365 * Athlon 64: 0x7f 1
1366 * 0x6f 2
1367 * Sempron: 0x7f 1/2
1368 * 0x6f 2
1369 * 0x6c 2
1370 * 0x7c 2
1371 * Turion 64: 0x68 2
1372 *
1373 */
1374 uint32_t u32Dummy;
1375 uint32_t u32Version, u32Family, u32Model, u32Stepping, u32BaseFamily;
1376 ASMCpuId(1, &u32Version, &u32Dummy, &u32Dummy, &u32Dummy);
1377 u32BaseFamily= (u32Version >> 8) & 0xf;
1378 u32Family = u32BaseFamily + (u32BaseFamily == 0xf ? ((u32Version >> 20) & 0x7f) : 0);
1379 u32Model = ((u32Version >> 4) & 0xf);
1380 u32Model = u32Model | ((u32BaseFamily == 0xf ? (u32Version >> 16) & 0x0f : 0) << 4);
1381 u32Stepping = u32Version & 0xf;
1382 if ( u32Family == 0xf
1383 && !((u32Model == 0x68 || u32Model == 0x6b || u32Model == 0x7f) && u32Stepping >= 1)
1384 && !((u32Model == 0x6f || u32Model == 0x6c || u32Model == 0x7c) && u32Stepping >= 2))
1385 {
1386 LogRel(("HM: AMD cpu with erratum 170 family %x model %x stepping %x\n", u32Family, u32Model, u32Stepping));
1387 }
1388
1389 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1390 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1391 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1392 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1393 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1394 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1395
1396 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1397 {
1398#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1399 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1400 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1401 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1402 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1403 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1404 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1405 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1406 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1407 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1408 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1409 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1410#undef FLAG_NAME
1411 };
1412 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1413 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1414 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1415 {
1416 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1417 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1418 }
1419 if (fSvmFeatures)
1420 for (unsigned iBit = 0; iBit < 32; iBit++)
1421 if (RT_BIT_32(iBit) & fSvmFeatures)
1422 LogRel(("HM: Reserved bit %u\n", iBit));
1423
1424 /*
1425 * Adjust feature(s).
1426 */
1427 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1428 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1429
1430 /*
1431 * Call ring-0 to set up the VM.
1432 */
1433 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1434 if (rc != VINF_SUCCESS)
1435 {
1436 AssertMsgFailed(("%Rrc\n", rc));
1437 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1438 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1439 }
1440
1441 LogRel(("HM: AMD-V enabled!\n"));
1442 pVM->hm.s.svm.fEnabled = true;
1443
1444 if (pVM->hm.s.fNestedPaging)
1445 {
1446 LogRel(("HM: Enabled nested paging!\n"));
1447
1448 /*
1449 * Enable large pages (2 MB) if applicable.
1450 */
1451#if HC_ARCH_BITS == 64
1452 if (pVM->hm.s.fLargePages)
1453 {
1454 PGMSetLargePageUsage(pVM, true);
1455 LogRel(("HM: Large page support enabled!\n"));
1456 }
1457#endif
1458 }
1459
1460 hmR3DisableRawMode(pVM);
1461
1462 /*
1463 * Change the CPU features.
1464 */
1465 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1466 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1467 if (pVM->hm.s.fAllow64BitGuests)
1468 {
1469 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1470 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1471 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1472 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1473 }
1474 /* Turn on NXE if PAE has been enabled. */
1475 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1476 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1477
1478
1479 LogRel((pVM->hm.s.fAllow64BitGuests
1480 ? "HM: 32-bit and 64-bit guest supported.\n"
1481 : "HM: 32-bit guest supported.\n"));
1482 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1483
1484 return VINF_SUCCESS;
1485}
1486
1487
1488/**
1489 * Applies relocations to data and code managed by this
1490 * component. This function will be called at init and
1491 * whenever the VMM need to relocate it self inside the GC.
1492 *
1493 * @param pVM The VM.
1494 */
1495VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1496{
1497 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1498
1499 /* Fetch the current paging mode during the relocate callback during state loading. */
1500 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1501 {
1502 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1503 {
1504 PVMCPU pVCpu = &pVM->aCpus[i];
1505
1506 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1507#ifdef VBOX_WITH_OLD_VTX_CODE
1508 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1509 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1510#endif
1511 }
1512 }
1513#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1514 if (HMIsEnabled(pVM))
1515 {
1516 switch (PGMGetHostMode(pVM))
1517 {
1518 case PGMMODE_32_BIT:
1519 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1520 break;
1521
1522 case PGMMODE_PAE:
1523 case PGMMODE_PAE_NX:
1524 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1525 break;
1526
1527 default:
1528 AssertFailed();
1529 break;
1530 }
1531 }
1532#endif
1533 return;
1534}
1535
1536
1537/**
1538 * Notification callback which is called whenever there is a chance that a CR3
1539 * value might have changed.
1540 *
1541 * This is called by PGM.
1542 *
1543 * @param pVM Pointer to the VM.
1544 * @param pVCpu Pointer to the VMCPU.
1545 * @param enmShadowMode New shadow paging mode.
1546 * @param enmGuestMode New guest paging mode.
1547 */
1548VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1549{
1550 /* Ignore page mode changes during state loading. */
1551 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1552 return;
1553
1554 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1555
1556#ifdef VBOX_WITH_OLD_VTX_CODE
1557 if ( pVM->hm.s.vmx.fEnabled
1558 && HMIsEnabled(pVM))
1559 {
1560 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1561 && enmGuestMode >= PGMMODE_PROTECTED)
1562 {
1563 PCPUMCTX pCtx;
1564
1565 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1566
1567 /* After a real mode switch to protected mode we must force
1568 CPL to 0. Our real mode emulation had to set it to 3. */
1569 pCtx->ss.Attr.n.u2Dpl = 0;
1570 }
1571 }
1572
1573 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1574 {
1575 /* Keep track of paging mode changes. */
1576 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1577 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1578
1579 /* Did we miss a change, because all code was executed in the recompiler? */
1580 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1581 {
1582 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1583 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1584 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1585 }
1586 }
1587#else
1588 /* If the guest left protected mode VMX execution, we'll have to be extra
1589 * careful if/when the guest switches back to protected mode.
1590 */
1591 if (enmGuestMode == PGMMODE_REAL)
1592 {
1593 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1594 pVCpu->hm.s.vmx.fWasInRealMode = true;
1595 }
1596#endif
1597
1598 /** @todo r=ramshankar: Why do we need to do this? Most likely
1599 * VBOX_WITH_OLD_VTX_CODE only. */
1600 /* Reset the contents of the read cache. */
1601 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1602 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1603 pCache->Read.aFieldVal[j] = 0;
1604}
1605
1606
1607/**
1608 * Terminates the HM.
1609 *
1610 * Termination means cleaning up and freeing all resources,
1611 * the VM itself is, at this point, powered off or suspended.
1612 *
1613 * @returns VBox status code.
1614 * @param pVM Pointer to the VM.
1615 */
1616VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1617{
1618 if (pVM->hm.s.vmx.pRealModeTSS)
1619 {
1620 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1621 pVM->hm.s.vmx.pRealModeTSS = 0;
1622 }
1623 hmR3TermCPU(pVM);
1624 return 0;
1625}
1626
1627
1628/**
1629 * Terminates the per-VCPU HM.
1630 *
1631 * @returns VBox status code.
1632 * @param pVM Pointer to the VM.
1633 */
1634static int hmR3TermCPU(PVM pVM)
1635{
1636 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1637 {
1638 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1639
1640#ifdef VBOX_WITH_STATISTICS
1641 if (pVCpu->hm.s.paStatExitReason)
1642 {
1643 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1644 pVCpu->hm.s.paStatExitReason = NULL;
1645 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1646 }
1647 if (pVCpu->hm.s.paStatInjectedIrqs)
1648 {
1649 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1650 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1651 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1652 }
1653#endif
1654
1655#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1656 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1657 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1658 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1659#endif
1660 }
1661 return 0;
1662}
1663
1664
1665/**
1666 * Resets a virtual CPU.
1667 *
1668 * Used by HMR3Reset and CPU hot plugging.
1669 *
1670 * @param pVCpu The CPU to reset.
1671 */
1672VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1673{
1674 /* On first entry we'll sync everything. */
1675 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1676
1677 pVCpu->hm.s.vmx.cr0_mask = 0;
1678 pVCpu->hm.s.vmx.cr4_mask = 0;
1679
1680 pVCpu->hm.s.fActive = false;
1681 pVCpu->hm.s.Event.fPending = false;
1682
1683#ifdef VBOX_WITH_OLD_VTX_CODE
1684 /* Reset state information for real-mode emulation in VT-x. */
1685 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1686 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1687 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1688#else
1689 pVCpu->hm.s.vmx.fWasInRealMode = true;
1690#endif
1691
1692 /* Reset the contents of the read cache. */
1693 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1694 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1695 pCache->Read.aFieldVal[j] = 0;
1696
1697#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1698 /* Magic marker for searching in crash dumps. */
1699 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1700 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1701#endif
1702}
1703
1704
1705/**
1706 * The VM is being reset.
1707 *
1708 * For the HM component this means that any GDT/LDT/TSS monitors
1709 * needs to be removed.
1710 *
1711 * @param pVM Pointer to the VM.
1712 */
1713VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1714{
1715 LogFlow(("HMR3Reset:\n"));
1716
1717 if (HMIsEnabled(pVM))
1718 hmR3DisableRawMode(pVM);
1719
1720 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1721 {
1722 PVMCPU pVCpu = &pVM->aCpus[i];
1723
1724 HMR3ResetCpu(pVCpu);
1725 }
1726
1727 /* Clear all patch information. */
1728 pVM->hm.s.pGuestPatchMem = 0;
1729 pVM->hm.s.pFreeGuestPatchMem = 0;
1730 pVM->hm.s.cbGuestPatchMem = 0;
1731 pVM->hm.s.cPatches = 0;
1732 pVM->hm.s.PatchTree = 0;
1733 pVM->hm.s.fTPRPatchingActive = false;
1734 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1735}
1736
1737
1738/**
1739 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1740 *
1741 * @returns VBox strict status code.
1742 * @param pVM Pointer to the VM.
1743 * @param pVCpu The VMCPU for the EMT we're being called on.
1744 * @param pvUser Unused.
1745 */
1746DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1747{
1748 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1749
1750 /* Only execute the handler on the VCPU the original patch request was issued. */
1751 if (pVCpu->idCpu != idCpu)
1752 return VINF_SUCCESS;
1753
1754 Log(("hmR3RemovePatches\n"));
1755 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1756 {
1757 uint8_t abInstr[15];
1758 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1759 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1760 int rc;
1761
1762#ifdef LOG_ENABLED
1763 char szOutput[256];
1764
1765 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1766 szOutput, sizeof(szOutput), NULL);
1767 if (RT_SUCCESS(rc))
1768 Log(("Patched instr: %s\n", szOutput));
1769#endif
1770
1771 /* Check if the instruction is still the same. */
1772 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1773 if (rc != VINF_SUCCESS)
1774 {
1775 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1776 continue; /* swapped out or otherwise removed; skip it. */
1777 }
1778
1779 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1780 {
1781 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1782 continue; /* skip it. */
1783 }
1784
1785 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1786 AssertRC(rc);
1787
1788#ifdef LOG_ENABLED
1789 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1790 szOutput, sizeof(szOutput), NULL);
1791 if (RT_SUCCESS(rc))
1792 Log(("Original instr: %s\n", szOutput));
1793#endif
1794 }
1795 pVM->hm.s.cPatches = 0;
1796 pVM->hm.s.PatchTree = 0;
1797 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1798 pVM->hm.s.fTPRPatchingActive = false;
1799 return VINF_SUCCESS;
1800}
1801
1802
1803/**
1804 * Worker for enabling patching in a VT-x/AMD-V guest.
1805 *
1806 * @returns VBox status code.
1807 * @param pVM Pointer to the VM.
1808 * @param idCpu VCPU to execute hmR3RemovePatches on.
1809 * @param pPatchMem Patch memory range.
1810 * @param cbPatchMem Size of the memory range.
1811 */
1812static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1813{
1814 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1815 AssertRC(rc);
1816
1817 pVM->hm.s.pGuestPatchMem = pPatchMem;
1818 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1819 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1820 return VINF_SUCCESS;
1821}
1822
1823
1824/**
1825 * Enable patching in a VT-x/AMD-V guest
1826 *
1827 * @returns VBox status code.
1828 * @param pVM Pointer to the VM.
1829 * @param pPatchMem Patch memory range.
1830 * @param cbPatchMem Size of the memory range.
1831 */
1832VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1833{
1834 VM_ASSERT_EMT(pVM);
1835 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1836 if (pVM->cCpus > 1)
1837 {
1838 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1839 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1840 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1841 AssertRC(rc);
1842 return rc;
1843 }
1844 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1845}
1846
1847
1848/**
1849 * Disable patching in a VT-x/AMD-V guest.
1850 *
1851 * @returns VBox status code.
1852 * @param pVM Pointer to the VM.
1853 * @param pPatchMem Patch memory range.
1854 * @param cbPatchMem Size of the memory range.
1855 */
1856VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1857{
1858 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1859
1860 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1861 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1862
1863 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1864 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1865 (void *)(uintptr_t)VMMGetCpuId(pVM));
1866 AssertRC(rc);
1867
1868 pVM->hm.s.pGuestPatchMem = 0;
1869 pVM->hm.s.pFreeGuestPatchMem = 0;
1870 pVM->hm.s.cbGuestPatchMem = 0;
1871 pVM->hm.s.fTPRPatchingActive = false;
1872 return VINF_SUCCESS;
1873}
1874
1875
1876/**
1877 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1878 *
1879 * @returns VBox strict status code.
1880 * @param pVM Pointer to the VM.
1881 * @param pVCpu The VMCPU for the EMT we're being called on.
1882 * @param pvUser User specified CPU context.
1883 *
1884 */
1885DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1886{
1887 /*
1888 * Only execute the handler on the VCPU the original patch request was
1889 * issued. (The other CPU(s) might not yet have switched to protected
1890 * mode, nor have the correct memory context.)
1891 */
1892 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1893 if (pVCpu->idCpu != idCpu)
1894 return VINF_SUCCESS;
1895
1896 /*
1897 * We're racing other VCPUs here, so don't try patch the instruction twice
1898 * and make sure there is still room for our patch record.
1899 */
1900 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1901 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1902 if (pPatch)
1903 {
1904 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1905 return VINF_SUCCESS;
1906 }
1907 uint32_t const idx = pVM->hm.s.cPatches;
1908 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1909 {
1910 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1911 return VINF_SUCCESS;
1912 }
1913 pPatch = &pVM->hm.s.aPatches[idx];
1914
1915 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1916
1917 /*
1918 * Disassembler the instruction and get cracking.
1919 */
1920 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1921 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1922 uint32_t cbOp;
1923 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1924 AssertRC(rc);
1925 if ( rc == VINF_SUCCESS
1926 && pDis->pCurInstr->uOpcode == OP_MOV
1927 && cbOp >= 3)
1928 {
1929 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1930
1931 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1932 AssertRC(rc);
1933
1934 pPatch->cbOp = cbOp;
1935
1936 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1937 {
1938 /* write. */
1939 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1940 {
1941 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1942 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1943 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1944 }
1945 else
1946 {
1947 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1948 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1949 pPatch->uSrcOperand = pDis->Param2.uValue;
1950 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1951 }
1952 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1953 AssertRC(rc);
1954
1955 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1956 pPatch->cbNewOp = sizeof(s_abVMMCall);
1957 }
1958 else
1959 {
1960 /*
1961 * TPR Read.
1962 *
1963 * Found:
1964 * mov eax, dword [fffe0080] (5 bytes)
1965 * Check if next instruction is:
1966 * shr eax, 4
1967 */
1968 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1969
1970 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1971 uint8_t const cbOpMmio = cbOp;
1972 uint64_t const uSavedRip = pCtx->rip;
1973
1974 pCtx->rip += cbOp;
1975 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1976 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1977 pCtx->rip = uSavedRip;
1978
1979 if ( rc == VINF_SUCCESS
1980 && pDis->pCurInstr->uOpcode == OP_SHR
1981 && pDis->Param1.fUse == DISUSE_REG_GEN32
1982 && pDis->Param1.Base.idxGenReg == idxMmioReg
1983 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1984 && pDis->Param2.uValue == 4
1985 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1986 {
1987 uint8_t abInstr[15];
1988
1989 /* Replacing two instructions now. */
1990 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1991 AssertRC(rc);
1992
1993 pPatch->cbOp = cbOpMmio + cbOp;
1994
1995 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1996 abInstr[0] = 0xF0;
1997 abInstr[1] = 0x0F;
1998 abInstr[2] = 0x20;
1999 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2000 for (unsigned i = 4; i < pPatch->cbOp; i++)
2001 abInstr[i] = 0x90; /* nop */
2002
2003 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2004 AssertRC(rc);
2005
2006 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2007 pPatch->cbNewOp = pPatch->cbOp;
2008
2009 Log(("Acceptable read/shr candidate!\n"));
2010 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2011 }
2012 else
2013 {
2014 pPatch->enmType = HMTPRINSTR_READ;
2015 pPatch->uDstOperand = idxMmioReg;
2016
2017 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2018 AssertRC(rc);
2019
2020 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2021 pPatch->cbNewOp = sizeof(s_abVMMCall);
2022 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2023 }
2024 }
2025
2026 pPatch->Core.Key = pCtx->eip;
2027 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2028 AssertRC(rc);
2029
2030 pVM->hm.s.cPatches++;
2031 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
2032 return VINF_SUCCESS;
2033 }
2034
2035 /*
2036 * Save invalid patch, so we will not try again.
2037 */
2038 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2039 pPatch->Core.Key = pCtx->eip;
2040 pPatch->enmType = HMTPRINSTR_INVALID;
2041 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2042 AssertRC(rc);
2043 pVM->hm.s.cPatches++;
2044 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2045 return VINF_SUCCESS;
2046}
2047
2048
2049/**
2050 * Callback to patch a TPR instruction (jump to generated code).
2051 *
2052 * @returns VBox strict status code.
2053 * @param pVM Pointer to the VM.
2054 * @param pVCpu The VMCPU for the EMT we're being called on.
2055 * @param pvUser User specified CPU context.
2056 *
2057 */
2058DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2059{
2060 /*
2061 * Only execute the handler on the VCPU the original patch request was
2062 * issued. (The other CPU(s) might not yet have switched to protected
2063 * mode, nor have the correct memory context.)
2064 */
2065 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2066 if (pVCpu->idCpu != idCpu)
2067 return VINF_SUCCESS;
2068
2069 /*
2070 * We're racing other VCPUs here, so don't try patch the instruction twice
2071 * and make sure there is still room for our patch record.
2072 */
2073 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2074 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2075 if (pPatch)
2076 {
2077 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2078 return VINF_SUCCESS;
2079 }
2080 uint32_t const idx = pVM->hm.s.cPatches;
2081 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2082 {
2083 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2084 return VINF_SUCCESS;
2085 }
2086 pPatch = &pVM->hm.s.aPatches[idx];
2087
2088 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2089 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2090
2091 /*
2092 * Disassemble the instruction and get cracking.
2093 */
2094 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2095 uint32_t cbOp;
2096 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2097 AssertRC(rc);
2098 if ( rc == VINF_SUCCESS
2099 && pDis->pCurInstr->uOpcode == OP_MOV
2100 && cbOp >= 5)
2101 {
2102 uint8_t aPatch[64];
2103 uint32_t off = 0;
2104
2105 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2106 AssertRC(rc);
2107
2108 pPatch->cbOp = cbOp;
2109 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2110
2111 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2112 {
2113 /*
2114 * TPR write:
2115 *
2116 * push ECX [51]
2117 * push EDX [52]
2118 * push EAX [50]
2119 * xor EDX,EDX [31 D2]
2120 * mov EAX,EAX [89 C0]
2121 * or
2122 * mov EAX,0000000CCh [B8 CC 00 00 00]
2123 * mov ECX,0C0000082h [B9 82 00 00 C0]
2124 * wrmsr [0F 30]
2125 * pop EAX [58]
2126 * pop EDX [5A]
2127 * pop ECX [59]
2128 * jmp return_address [E9 return_address]
2129 *
2130 */
2131 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2132
2133 aPatch[off++] = 0x51; /* push ecx */
2134 aPatch[off++] = 0x52; /* push edx */
2135 if (!fUsesEax)
2136 aPatch[off++] = 0x50; /* push eax */
2137 aPatch[off++] = 0x31; /* xor edx, edx */
2138 aPatch[off++] = 0xD2;
2139 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2140 {
2141 if (!fUsesEax)
2142 {
2143 aPatch[off++] = 0x89; /* mov eax, src_reg */
2144 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2145 }
2146 }
2147 else
2148 {
2149 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2150 aPatch[off++] = 0xB8; /* mov eax, immediate */
2151 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2152 off += sizeof(uint32_t);
2153 }
2154 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2155 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2156 off += sizeof(uint32_t);
2157
2158 aPatch[off++] = 0x0F; /* wrmsr */
2159 aPatch[off++] = 0x30;
2160 if (!fUsesEax)
2161 aPatch[off++] = 0x58; /* pop eax */
2162 aPatch[off++] = 0x5A; /* pop edx */
2163 aPatch[off++] = 0x59; /* pop ecx */
2164 }
2165 else
2166 {
2167 /*
2168 * TPR read:
2169 *
2170 * push ECX [51]
2171 * push EDX [52]
2172 * push EAX [50]
2173 * mov ECX,0C0000082h [B9 82 00 00 C0]
2174 * rdmsr [0F 32]
2175 * mov EAX,EAX [89 C0]
2176 * pop EAX [58]
2177 * pop EDX [5A]
2178 * pop ECX [59]
2179 * jmp return_address [E9 return_address]
2180 *
2181 */
2182 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2183
2184 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2185 aPatch[off++] = 0x51; /* push ecx */
2186 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2187 aPatch[off++] = 0x52; /* push edx */
2188 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2189 aPatch[off++] = 0x50; /* push eax */
2190
2191 aPatch[off++] = 0x31; /* xor edx, edx */
2192 aPatch[off++] = 0xD2;
2193
2194 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2195 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2196 off += sizeof(uint32_t);
2197
2198 aPatch[off++] = 0x0F; /* rdmsr */
2199 aPatch[off++] = 0x32;
2200
2201 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2202 {
2203 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2204 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2205 }
2206
2207 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2208 aPatch[off++] = 0x58; /* pop eax */
2209 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2210 aPatch[off++] = 0x5A; /* pop edx */
2211 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2212 aPatch[off++] = 0x59; /* pop ecx */
2213 }
2214 aPatch[off++] = 0xE9; /* jmp return_address */
2215 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2216 off += sizeof(RTRCUINTPTR);
2217
2218 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2219 {
2220 /* Write new code to the patch buffer. */
2221 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2222 AssertRC(rc);
2223
2224#ifdef LOG_ENABLED
2225 uint32_t cbCurInstr;
2226 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2227 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2228 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2229 {
2230 char szOutput[256];
2231 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2232 szOutput, sizeof(szOutput), &cbCurInstr);
2233 if (RT_SUCCESS(rc))
2234 Log(("Patch instr %s\n", szOutput));
2235 else
2236 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2237 }
2238#endif
2239
2240 pPatch->aNewOpcode[0] = 0xE9;
2241 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2242
2243 /* Overwrite the TPR instruction with a jump. */
2244 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2245 AssertRC(rc);
2246
2247 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2248
2249 pVM->hm.s.pFreeGuestPatchMem += off;
2250 pPatch->cbNewOp = 5;
2251
2252 pPatch->Core.Key = pCtx->eip;
2253 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2254 AssertRC(rc);
2255
2256 pVM->hm.s.cPatches++;
2257 pVM->hm.s.fTPRPatchingActive = true;
2258 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2259 return VINF_SUCCESS;
2260 }
2261
2262 Log(("Ran out of space in our patch buffer!\n"));
2263 }
2264 else
2265 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2266
2267
2268 /*
2269 * Save invalid patch, so we will not try again.
2270 */
2271 pPatch = &pVM->hm.s.aPatches[idx];
2272 pPatch->Core.Key = pCtx->eip;
2273 pPatch->enmType = HMTPRINSTR_INVALID;
2274 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2275 AssertRC(rc);
2276 pVM->hm.s.cPatches++;
2277 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2278 return VINF_SUCCESS;
2279}
2280
2281
2282/**
2283 * Attempt to patch TPR mmio instructions.
2284 *
2285 * @returns VBox status code.
2286 * @param pVM Pointer to the VM.
2287 * @param pVCpu Pointer to the VMCPU.
2288 * @param pCtx Pointer to the guest CPU context.
2289 */
2290VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2291{
2292 NOREF(pCtx);
2293 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2294 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2295 (void *)(uintptr_t)pVCpu->idCpu);
2296 AssertRC(rc);
2297 return rc;
2298}
2299
2300
2301/**
2302 * Checks if a code selector (CS) is suitable for execution
2303 * within VMX when unrestricted execution isn't available.
2304 *
2305 * @returns true if selector is suitable for VMX, otherwise
2306 * false.
2307 * @param pSel Pointer to the selector to check (CS).
2308 * uStackDpl The DPL of the stack segment.
2309 */
2310static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2311{
2312 bool rc = false;
2313
2314 do
2315 {
2316 /* Segment must be accessed. */
2317 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2318 break;
2319 /* Segment must be a code segment. */
2320 if (!(pSel->Attr.u & X86_SEL_TYPE_CODE))
2321 break;
2322 /* The S bit must be set. */
2323 if (!pSel->Attr.n.u1DescType)
2324 break;
2325 if (pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF)
2326 {
2327 /* For conforming segments, CS.DPL must be <= SS.DPL. */
2328 if (pSel->Attr.n.u2Dpl > uStackDpl)
2329 break;
2330 }
2331 else
2332 {
2333 /* For non-conforming segments, CS.DPL must equal SS.DPL. */
2334 if (pSel->Attr.n.u2Dpl != uStackDpl)
2335 break;
2336 }
2337 /* Segment must be present. */
2338 if (!pSel->Attr.n.u1Present)
2339 break;
2340 /* G bit must be set if any high limit bits are set. */
2341 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2342 break;
2343 /* G bit must be clear if any low limit bits are clear. */
2344 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2345 break;
2346
2347 rc = true;
2348 } while (0);
2349 return rc;
2350}
2351
2352
2353/**
2354 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2355 * execution within VMX when unrestricted execution isn't
2356 * available.
2357 *
2358 * @returns true if selector is suitable for VMX, otherwise
2359 * false.
2360 * @param pSel Pointer to the selector to check
2361 * (DS/ES/FS/GS).
2362 */
2363static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2364{
2365 bool rc = false;
2366
2367 /* If attributes are all zero, consider the segment unusable and therefore OK.
2368 * This logic must be in sync with HMVMXR0.cpp!
2369 */
2370 if (!pSel->Attr.u)
2371 return true;
2372
2373 do
2374 {
2375 /* Segment must be accessed. */
2376 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2377 break;
2378 /* Code segments must also be readable. */
2379 if (pSel->Attr.u & X86_SEL_TYPE_CODE && !(pSel->Attr.u & X86_SEL_TYPE_READ))
2380 break;
2381 /* The S bit must be set. */
2382 if (!pSel->Attr.n.u1DescType)
2383 break;
2384 /* Except for conforming segments, DPL >= RPL. */
2385 if (pSel->Attr.n.u4Type <= X86_SEL_TYPE_ER_ACC && pSel->Attr.n.u2Dpl < (pSel->Sel & X86_SEL_RPL))
2386 break;
2387 /* Segment must be present. */
2388 if (!pSel->Attr.n.u1Present)
2389 break;
2390 /* G bit must be set if any high limit bits are set. */
2391 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2392 break;
2393 /* G bit must be clear if any low limit bits are clear. */
2394 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2395 break;
2396
2397 rc = true;
2398 } while (0);
2399 return rc;
2400}
2401
2402
2403/**
2404 * Checks if the stack selector (SS) is suitable for execution
2405 * within VMX when unrestricted execution isn't available.
2406 *
2407 * @returns true if selector is suitable for VMX, otherwise
2408 * false.
2409 * @param pSel Pointer to the selector to check (SS).
2410 */
2411static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2412{
2413 bool rc = false;
2414
2415 /* If attributes are all zero, consider the segment unusable and therefore OK.
2416 * This logic must be in sync with HMVMXR0.cpp!
2417 */
2418 if (!pSel->Attr.u)
2419 return true;
2420
2421 do
2422 {
2423 /* Segment must be accessed. */
2424 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2425 break;
2426 /* Segment must be writable. */
2427 if (!(pSel->Attr.u & X86_SEL_TYPE_WRITE))
2428 break;
2429 /* Segment must not be a code segment. */
2430 if (pSel->Attr.u & X86_SEL_TYPE_CODE)
2431 break;
2432 /* The S bit must be set. */
2433 if (!pSel->Attr.n.u1DescType)
2434 break;
2435 /* DPL must equal RPL. */
2436 if (pSel->Attr.n.u2Dpl != (pSel->Sel & X86_SEL_RPL))
2437 break;
2438 /* Segment must be present. */
2439 if (!pSel->Attr.n.u1Present)
2440 break;
2441 /* G bit must be set if any high limit bits are set. */
2442 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2443 break;
2444 /* G bit must be clear if any low limit bits are clear. */
2445 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2446 break;
2447
2448 rc = true;
2449 } while (0);
2450 return rc;
2451}
2452
2453
2454/**
2455 * Force execution of the current IO code in the recompiler.
2456 *
2457 * @returns VBox status code.
2458 * @param pVM Pointer to the VM.
2459 * @param pCtx Partial VM execution context.
2460 */
2461VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2462{
2463 PVMCPU pVCpu = VMMGetCpu(pVM);
2464
2465 Assert(HMIsEnabled(pVM));
2466 Log(("HMR3EmulateIoBlock\n"));
2467
2468 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2469 if (HMCanEmulateIoBlockEx(pCtx))
2470 {
2471 Log(("HMR3EmulateIoBlock -> enabled\n"));
2472 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2473 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2474 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2475 return VINF_EM_RESCHEDULE_REM;
2476 }
2477 return VINF_SUCCESS;
2478}
2479
2480
2481/**
2482 * Checks if we can currently use hardware accelerated raw mode.
2483 *
2484 * @returns true if we can currently use hardware acceleration, otherwise false.
2485 * @param pVM Pointer to the VM.
2486 * @param pCtx Partial VM execution context.
2487 */
2488VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2489{
2490 PVMCPU pVCpu = VMMGetCpu(pVM);
2491
2492 Assert(HMIsEnabled(pVM));
2493
2494 /* If we're still executing the IO code, then return false. */
2495 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2496 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2497 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2498 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2499 return false;
2500
2501 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2502
2503 /* AMD-V supports real & protected mode with or without paging. */
2504 if (pVM->hm.s.svm.fEnabled)
2505 {
2506 pVCpu->hm.s.fActive = true;
2507 return true;
2508 }
2509
2510 pVCpu->hm.s.fActive = false;
2511
2512 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2513 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2514 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2515
2516 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2517 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2518 {
2519 /*
2520 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2521 * guest execution feature i missing (VT-x only).
2522 */
2523 if (fSupportsRealMode)
2524 {
2525 if (CPUMIsGuestInRealModeEx(pCtx))
2526 {
2527 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2528 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2529 * If this is not true, we cannot execute real mode as V86 and have to fall
2530 * back to emulation.
2531 */
2532 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2533 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2534 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2535 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2536 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2537 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2538 {
2539 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2540 return false;
2541 }
2542 if ( (pCtx->cs.u32Limit != 0xffff)
2543 || (pCtx->ds.u32Limit != 0xffff)
2544 || (pCtx->es.u32Limit != 0xffff)
2545 || (pCtx->ss.u32Limit != 0xffff)
2546 || (pCtx->fs.u32Limit != 0xffff)
2547 || (pCtx->gs.u32Limit != 0xffff))
2548 {
2549 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2550 return false;
2551 }
2552 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2553 }
2554 else
2555 {
2556 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2557 /* Verify the requirements for executing code in protected
2558 mode. VT-x can't handle the CPU state right after a switch
2559 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2560#if VBOX_WITH_OLD_VTX_CODE
2561 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2562 && enmGuestMode >= PGMMODE_PROTECTED)
2563#else
2564 if (pVCpu->hm.s.vmx.fWasInRealMode)
2565#endif
2566 {
2567 //@todo: If guest is in V86 mode, these checks should be different!
2568#if VBOX_WITH_OLD_VTX_CODE
2569 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2570 || (pCtx->ds.Sel & X86_SEL_RPL)
2571 || (pCtx->es.Sel & X86_SEL_RPL)
2572 || (pCtx->fs.Sel & X86_SEL_RPL)
2573 || (pCtx->gs.Sel & X86_SEL_RPL)
2574 || (pCtx->ss.Sel & X86_SEL_RPL))
2575 {
2576 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2577 return false;
2578 }
2579#else
2580 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2581 {
2582 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2583 return false;
2584 }
2585 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2586 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2587 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2588 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2589 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2590 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2591 {
2592 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2593 return false;
2594 }
2595#endif
2596 }
2597 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2598 if (pCtx->gdtr.cbGdt)
2599 {
2600 if (pCtx->tr.Sel > pCtx->gdtr.cbGdt)
2601 {
2602 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2603 return false;
2604 }
2605 else if (pCtx->ldtr.Sel > pCtx->gdtr.cbGdt)
2606 {
2607 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2608 return false;
2609 }
2610 }
2611 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2612 }
2613 }
2614 else
2615 {
2616 if ( !CPUMIsGuestInLongModeEx(pCtx)
2617 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2618 {
2619 /** @todo This should (probably) be set on every excursion to the REM,
2620 * however it's too risky right now. So, only apply it when we go
2621 * back to REM for real mode execution. (The XP hack below doesn't
2622 * work reliably without this.)
2623 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2624 for (uint32_t i = 0; i < pVM->cCpus; i++)
2625 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2626
2627 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2628 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2629 return false;
2630
2631 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2632 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2633 return false;
2634
2635 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2636 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2637 * hidden registers (possible recompiler bug; see load_seg_vm) */
2638 if (pCtx->cs.Attr.n.u1Present == 0)
2639 return false;
2640 if (pCtx->ss.Attr.n.u1Present == 0)
2641 return false;
2642
2643 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2644 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2645 /** @todo This check is actually wrong, it doesn't take the direction of the
2646 * stack segment into account. But, it does the job for now. */
2647 if (pCtx->rsp >= pCtx->ss.u32Limit)
2648 return false;
2649#if 0
2650 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2651 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2652 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2653 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2654 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2655 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2656 return false;
2657#endif
2658 }
2659 }
2660 }
2661
2662 if (pVM->hm.s.vmx.fEnabled)
2663 {
2664 uint32_t mask;
2665
2666 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2667 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2668 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2669 mask &= ~X86_CR0_NE;
2670
2671 if (fSupportsRealMode)
2672 {
2673 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2674 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2675 }
2676 else
2677 {
2678 /* We support protected mode without paging using identity mapping. */
2679 mask &= ~X86_CR0_PG;
2680 }
2681 if ((pCtx->cr0 & mask) != mask)
2682 return false;
2683
2684 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2685 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2686 if ((pCtx->cr0 & mask) != 0)
2687 return false;
2688
2689 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2690 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2691 mask &= ~X86_CR4_VMXE;
2692 if ((pCtx->cr4 & mask) != mask)
2693 return false;
2694
2695 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2696 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2697 if ((pCtx->cr4 & mask) != 0)
2698 return false;
2699
2700 pVCpu->hm.s.fActive = true;
2701 return true;
2702 }
2703
2704 return false;
2705}
2706
2707
2708/**
2709 * Checks if we need to reschedule due to VMM device heap changes.
2710 *
2711 * @returns true if a reschedule is required, otherwise false.
2712 * @param pVM Pointer to the VM.
2713 * @param pCtx VM execution context.
2714 */
2715VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2716{
2717 /*
2718 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2719 * when the unrestricted guest execution feature is missing (VT-x only).
2720 */
2721#ifdef VBOX_WITH_OLD_VTX_CODE
2722 if ( pVM->hm.s.vmx.fEnabled
2723 && !pVM->hm.s.vmx.fUnrestrictedGuest
2724 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2725 && !PDMVmmDevHeapIsEnabled(pVM)
2726 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2727 return true;
2728#else
2729 if ( pVM->hm.s.vmx.fEnabled
2730 && !pVM->hm.s.vmx.fUnrestrictedGuest
2731 && CPUMIsGuestInRealModeEx(pCtx)
2732 && !PDMVmmDevHeapIsEnabled(pVM))
2733 return true;
2734#endif
2735
2736 return false;
2737}
2738
2739
2740/**
2741 * Notification from EM about a rescheduling into hardware assisted execution
2742 * mode.
2743 *
2744 * @param pVCpu Pointer to the current VMCPU.
2745 */
2746VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2747{
2748 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2749}
2750
2751
2752/**
2753 * Notification from EM about returning from instruction emulation (REM / EM).
2754 *
2755 * @param pVCpu Pointer to the VMCPU.
2756 */
2757VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2758{
2759 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2760}
2761
2762
2763/**
2764 * Checks if we are currently using hardware accelerated raw mode.
2765 *
2766 * @returns true if hardware acceleration is being used, otherwise false.
2767 * @param pVCpu Pointer to the VMCPU.
2768 */
2769VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2770{
2771 return pVCpu->hm.s.fActive;
2772}
2773
2774
2775/**
2776 * External interface for querying whether hardware accelerated raw mode is
2777 * enabled.
2778 *
2779 * @returns true if nested paging is being used, otherwise false.
2780 * @param pUVM The user mode VM handle.
2781 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2782 */
2783VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2784{
2785 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2786 PVM pVM = pUVM->pVM;
2787 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2788 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2789}
2790
2791
2792/**
2793 * Checks if we are currently using nested paging.
2794 *
2795 * @returns true if nested paging is being used, otherwise false.
2796 * @param pUVM The user mode VM handle.
2797 */
2798VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2799{
2800 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2801 PVM pVM = pUVM->pVM;
2802 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2803 return pVM->hm.s.fNestedPaging;
2804}
2805
2806
2807/**
2808 * Checks if we are currently using VPID in VT-x mode.
2809 *
2810 * @returns true if VPID is being used, otherwise false.
2811 * @param pUVM The user mode VM handle.
2812 */
2813VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2814{
2815 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2816 PVM pVM = pUVM->pVM;
2817 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2818 return pVM->hm.s.vmx.fVpid;
2819}
2820
2821
2822/**
2823 * Checks if we are currently using VT-x unrestricted execution,
2824 * aka UX.
2825 *
2826 * @returns true if UX is being used, otherwise false.
2827 * @param pUVM The user mode VM handle.
2828 */
2829VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2830{
2831 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2832 PVM pVM = pUVM->pVM;
2833 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2834 return pVM->hm.s.vmx.fUnrestrictedGuest;
2835}
2836
2837
2838/**
2839 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2840 *
2841 * @returns true if an internal event is pending, otherwise false.
2842 * @param pVM Pointer to the VM.
2843 */
2844VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2845{
2846 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2847}
2848
2849
2850/**
2851 * Checks if the VMX-preemption timer is being used.
2852 *
2853 * @returns true if the VMX-preemption timer is being used, otherwise false.
2854 * @param pVM Pointer to the VM.
2855 */
2856VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2857{
2858 return HMIsEnabled(pVM)
2859 && pVM->hm.s.vmx.fEnabled
2860 && pVM->hm.s.vmx.fUsePreemptTimer;
2861}
2862
2863
2864/**
2865 * Restart an I/O instruction that was refused in ring-0
2866 *
2867 * @returns Strict VBox status code. Informational status codes other than the one documented
2868 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2869 * @retval VINF_SUCCESS Success.
2870 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2871 * status code must be passed on to EM.
2872 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2873 *
2874 * @param pVM Pointer to the VM.
2875 * @param pVCpu Pointer to the VMCPU.
2876 * @param pCtx Pointer to the guest CPU context.
2877 */
2878VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2879{
2880 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2881
2882 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2883
2884 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2885 || enmType == HMPENDINGIO_INVALID)
2886 return VERR_NOT_FOUND;
2887
2888 VBOXSTRICTRC rcStrict;
2889 switch (enmType)
2890 {
2891 case HMPENDINGIO_PORT_READ:
2892 {
2893 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2894 uint32_t u32Val = 0;
2895
2896 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2897 &u32Val,
2898 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2899 if (IOM_SUCCESS(rcStrict))
2900 {
2901 /* Write back to the EAX register. */
2902 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2903 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2904 }
2905 break;
2906 }
2907
2908 case HMPENDINGIO_PORT_WRITE:
2909 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2910 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2911 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2912 if (IOM_SUCCESS(rcStrict))
2913 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2914 break;
2915
2916 default:
2917 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2918 }
2919
2920 return rcStrict;
2921}
2922
2923
2924/**
2925 * Check fatal VT-x/AMD-V error and produce some meaningful
2926 * log release message.
2927 *
2928 * @param pVM Pointer to the VM.
2929 * @param iStatusCode VBox status code.
2930 */
2931VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2932{
2933 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2934 {
2935 switch (iStatusCode)
2936 {
2937 case VERR_VMX_INVALID_VMCS_FIELD:
2938 break;
2939
2940 case VERR_VMX_INVALID_VMCS_PTR:
2941 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2942 LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2943 LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2944 LogRel(("HM: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2945 LogRel(("HM: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2946 break;
2947
2948 case VERR_VMX_UNABLE_TO_START_VM:
2949 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2950 LogRel(("HM: CPU%d instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2951 LogRel(("HM: CPU%d exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2952 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2953 {
2954 LogRel(("HM: Cpu%d PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2955 LogRel(("HM: Cpu%d ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2956 LogRel(("HM: Cpu%d ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2957 LogRel(("HM: Cpu%d EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2958 LogRel(("HM: Cpu%d ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2959 LogRel(("HM: Cpu%d MSRBitmapPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2960#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2961 LogRel(("HM: Cpu%d GuestMSRPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2962 LogRel(("HM: Cpu%d HostMsrPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2963 LogRel(("HM: Cpu%d cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2964#endif
2965 }
2966 /** @todo Log VM-entry event injection control fields
2967 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2968 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2969 break;
2970
2971 case VERR_VMX_INVALID_VMXON_PTR:
2972 break;
2973 }
2974 }
2975
2976 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2977 {
2978 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2979 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2980 }
2981}
2982
2983
2984/**
2985 * Execute state save operation.
2986 *
2987 * @returns VBox status code.
2988 * @param pVM Pointer to the VM.
2989 * @param pSSM SSM operation handle.
2990 */
2991static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2992{
2993 int rc;
2994
2995 Log(("hmR3Save:\n"));
2996
2997 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2998 {
2999 /*
3000 * Save the basic bits - fortunately all the other things can be resynced on load.
3001 */
3002 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3003 AssertRCReturn(rc, rc);
3004 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3005 AssertRCReturn(rc, rc);
3006 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
3007 AssertRCReturn(rc, rc);
3008
3009#ifdef VBOX_WITH_OLD_VTX_CODE
3010 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
3011 AssertRCReturn(rc, rc);
3012 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
3013 AssertRCReturn(rc, rc);
3014 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
3015 AssertRCReturn(rc, rc);
3016#else
3017 //@todo: We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3018 // perhaps not even that (the initial value of 'true' is safe).
3019 uint32_t u32Dummy = PGMMODE_REAL;
3020 rc = SSMR3PutU32(pSSM, u32Dummy);
3021 AssertRCReturn(rc, rc);
3022 rc = SSMR3PutU32(pSSM, u32Dummy);
3023 AssertRCReturn(rc, rc);
3024 rc = SSMR3PutU32(pSSM, u32Dummy);
3025 AssertRCReturn(rc, rc);
3026#endif
3027 }
3028#ifdef VBOX_HM_WITH_GUEST_PATCHING
3029 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3030 AssertRCReturn(rc, rc);
3031 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3032 AssertRCReturn(rc, rc);
3033 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3034 AssertRCReturn(rc, rc);
3035
3036 /* Store all the guest patch records too. */
3037 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3038 AssertRCReturn(rc, rc);
3039
3040 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3041 {
3042 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3043
3044 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3045 AssertRCReturn(rc, rc);
3046
3047 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3048 AssertRCReturn(rc, rc);
3049
3050 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3051 AssertRCReturn(rc, rc);
3052
3053 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3054 AssertRCReturn(rc, rc);
3055
3056 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3057 AssertRCReturn(rc, rc);
3058
3059 AssertCompileSize(HMTPRINSTR, 4);
3060 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3061 AssertRCReturn(rc, rc);
3062
3063 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3064 AssertRCReturn(rc, rc);
3065
3066 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3067 AssertRCReturn(rc, rc);
3068
3069 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3070 AssertRCReturn(rc, rc);
3071
3072 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3073 AssertRCReturn(rc, rc);
3074 }
3075#endif
3076 return VINF_SUCCESS;
3077}
3078
3079
3080/**
3081 * Execute state load operation.
3082 *
3083 * @returns VBox status code.
3084 * @param pVM Pointer to the VM.
3085 * @param pSSM SSM operation handle.
3086 * @param uVersion Data layout version.
3087 * @param uPass The data pass.
3088 */
3089static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3090{
3091 int rc;
3092
3093 Log(("hmR3Load:\n"));
3094 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3095
3096 /*
3097 * Validate version.
3098 */
3099 if ( uVersion != HM_SSM_VERSION
3100 && uVersion != HM_SSM_VERSION_NO_PATCHING
3101 && uVersion != HM_SSM_VERSION_2_0_X)
3102 {
3103 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3104 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3105 }
3106 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3107 {
3108 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3109 AssertRCReturn(rc, rc);
3110 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3111 AssertRCReturn(rc, rc);
3112 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
3113 AssertRCReturn(rc, rc);
3114
3115 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
3116 {
3117 uint32_t val;
3118
3119#ifdef VBOX_WITH_OLD_VTX_CODE
3120 rc = SSMR3GetU32(pSSM, &val);
3121 AssertRCReturn(rc, rc);
3122 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
3123
3124 rc = SSMR3GetU32(pSSM, &val);
3125 AssertRCReturn(rc, rc);
3126 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
3127
3128 rc = SSMR3GetU32(pSSM, &val);
3129 AssertRCReturn(rc, rc);
3130 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
3131#else
3132 //@todo: See note above re saving enmLastSeenGuestMode
3133 rc = SSMR3GetU32(pSSM, &val);
3134 AssertRCReturn(rc, rc);
3135 rc = SSMR3GetU32(pSSM, &val);
3136 AssertRCReturn(rc, rc);
3137 rc = SSMR3GetU32(pSSM, &val);
3138 AssertRCReturn(rc, rc);
3139#endif
3140 }
3141 }
3142#ifdef VBOX_HM_WITH_GUEST_PATCHING
3143 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
3144 {
3145 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3146 AssertRCReturn(rc, rc);
3147 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3148 AssertRCReturn(rc, rc);
3149 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3150 AssertRCReturn(rc, rc);
3151
3152 /* Fetch all TPR patch records. */
3153 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3154 AssertRCReturn(rc, rc);
3155
3156 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3157 {
3158 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3159
3160 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3161 AssertRCReturn(rc, rc);
3162
3163 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3164 AssertRCReturn(rc, rc);
3165
3166 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3167 AssertRCReturn(rc, rc);
3168
3169 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3170 AssertRCReturn(rc, rc);
3171
3172 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3173 AssertRCReturn(rc, rc);
3174
3175 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3176 AssertRCReturn(rc, rc);
3177
3178 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3179 pVM->hm.s.fTPRPatchingActive = true;
3180
3181 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3182
3183 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3184 AssertRCReturn(rc, rc);
3185
3186 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3187 AssertRCReturn(rc, rc);
3188
3189 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3190 AssertRCReturn(rc, rc);
3191
3192 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3193 AssertRCReturn(rc, rc);
3194
3195 Log(("hmR3Load: patch %d\n", i));
3196 Log(("Key = %x\n", pPatch->Core.Key));
3197 Log(("cbOp = %d\n", pPatch->cbOp));
3198 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3199 Log(("type = %d\n", pPatch->enmType));
3200 Log(("srcop = %d\n", pPatch->uSrcOperand));
3201 Log(("dstop = %d\n", pPatch->uDstOperand));
3202 Log(("cFaults = %d\n", pPatch->cFaults));
3203 Log(("target = %x\n", pPatch->pJumpTarget));
3204 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3205 AssertRC(rc);
3206 }
3207 }
3208#endif
3209
3210 return VINF_SUCCESS;
3211}
3212
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette