VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 46378

Last change on this file since 46378 was 46378, checked in by vboxsync, 12 years ago

VMM/HM: Recognize more VT-x misc. MSR features as per the spec.
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File size: 137.1 KB
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1/* $Id: HM.cpp 46378 2013-06-04 12:11:23Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/ssm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/csam.h>
34#include <VBox/vmm/selm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/uvm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/asm-amd64-x86.h>
50#include <iprt/string.h>
51#include <iprt/env.h>
52#include <iprt/thread.h>
53
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58#ifdef VBOX_WITH_STATISTICS
59# define EXIT_REASON(def, val, str) #def " - " #val " - " str
60# define EXIT_REASON_NIL() NULL
61/** Exit reason descriptions for VT-x, used to describe statistics. */
62static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
63{
64 EXIT_REASON(VMX_EXIT_XCPT_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
65 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
66 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
67 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
68 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
69 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
70 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
71 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
74 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest attempted to execute CPUID."),
75 EXIT_REASON_NIL(),
76 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest attempted to execute HLT."),
77 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest attempted to execute INVD."),
78 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest attempted to execute INVLPG."),
79 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest attempted to execute RDPMC."),
80 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest attempted to execute RDTSC."),
81 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest attempted to execute RSM in SMM."),
82 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest attempted to execute VMCALL."),
83 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest attempted to execute VMCLEAR."),
84 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest attempted to execute VMLAUNCH."),
85 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest attempted to execute VMPTRLD."),
86 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest attempted to execute VMPTRST."),
87 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest attempted to execute VMREAD."),
88 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest attempted to execute VMRESUME."),
89 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest attempted to execute VMWRITE."),
90 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest attempted to execute VMXOFF."),
91 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest attempted to execute VMXON."),
92 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
93 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
94 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
95 EXIT_REASON(VMX_EXIT_RDMSR , 31, "Guest attempted to execute RDMSR."),
96 EXIT_REASON(VMX_EXIT_WRMSR , 32, "Guest attempted to execute WRMSR."),
97 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
98 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest executed MWAIT."),
101 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest attempted to execute MONITOR."),
104 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest attempted to execute PAUSE."),
105 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest attempted to execute MOV to CR8."),
108 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest attempted to access memory at a physical address on the APIC-access page."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest attempted to execute LGDT, LIDT, SGDT, or SIDT."),
111 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest attempted to execute LLDT, LTR, SLDT, or STR."),
112 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
113 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
114 EXIT_REASON(VMX_EXIT_INVEPT , 50, "Guest attempted to execute INVEPT."),
115 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest attempted to execute RDTSCP."),
116 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
117 EXIT_REASON(VMX_EXIT_INVVPID , 53, "Guest attempted to execute INVVPID."),
118 EXIT_REASON(VMX_EXIT_WBINVD , 54, "Guest attempted to execute WBINVD."),
119 EXIT_REASON(VMX_EXIT_XSETBV , 55, "Guest attempted to execute XSETBV."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_RDRAND , 57, "Guest attempted to execute RDRAND."),
122 EXIT_REASON(VMX_EXIT_INVPCID , 58, "Guest attempted to execute INVPCID."),
123 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "Guest attempted to execute VMFUNC.")
124};
125/** Exit reason descriptions for AMD-V, used to describe statistics. */
126static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (0x0)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (0x1)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (0x2)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (0x3)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (0x4)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (0x5)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (0x6)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (0x7)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (0x8)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (0x9)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (0xA)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (0xB)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (0xC)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (0xD)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (0xE)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0xF)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (0x10)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (0x11)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (0x12)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (0x13)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal."),
228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
231 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
232 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port (EXITINFO1 field provides more information)."),
252 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "FP legacy handling enabled, and processor is frozen in an x87/mmx instruction waiting for an interrupt"),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT_UNCOND ,139, "MWAIT instruction unconditional."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging: host-level page fault occurred (EXITINFO1 contains fault errorcode; EXITINFO2 contains the guest physical address causing the fault)."),
270 EXIT_REASON_NIL()
271};
272# undef EXIT_REASON
273# undef EXIT_REASON_NIL
274#endif /* VBOX_WITH_STATISTICS */
275
276#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
277 do { \
278 if ((allowed1) & (featflag)) \
279 LogRel(("HM: " #featflag "\n")); \
280 else \
281 LogRel(("HM: " #featflag " *must* be cleared\n")); \
282 if ((disallowed0) & (featflag)) \
283 LogRel(("HM: " #featflag " *must* be set\n")); \
284 } while (0)
285
286#define HMVMX_REPORT_CAPABILITY(msrcaps, cap) \
287 do { \
288 if ((msrcaps) & (cap)) \
289 LogRel(("HM: " #cap "\n")); \
290 } while (0)
291
292
293/*******************************************************************************
294* Internal Functions *
295*******************************************************************************/
296static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
297static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
298static int hmR3InitCPU(PVM pVM);
299static int hmR3InitFinalizeR0(PVM pVM);
300static int hmR3InitFinalizeR0Intel(PVM pVM);
301static int hmR3InitFinalizeR0Amd(PVM pVM);
302static int hmR3TermCPU(PVM pVM);
303
304
305
306/**
307 * Initializes the HM.
308 *
309 * This reads the config and check whether VT-x or AMD-V hardware is available
310 * if configured to use it. This is one of the very first components to be
311 * initialized after CFGM, so that we can fall back to raw-mode early in the
312 * initialization process.
313 *
314 * Note that a lot of the set up work is done in ring-0 and thus postponed till
315 * the ring-3 and ring-0 callback to HMR3InitCompleted.
316 *
317 * @returns VBox status code.
318 * @param pVM Pointer to the VM.
319 *
320 * @remarks Be careful with what we call here, since most of the VMM components
321 * are uninitialized.
322 */
323VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
324{
325 LogFlow(("HMR3Init\n"));
326
327 /*
328 * Assert alignment and sizes.
329 */
330 AssertCompileMemberAlignment(VM, hm.s, 32);
331 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
332
333 /*
334 * Register the saved state data unit.
335 */
336 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
337 NULL, NULL, NULL,
338 NULL, hmR3Save, NULL,
339 NULL, hmR3Load, NULL);
340 if (RT_FAILURE(rc))
341 return rc;
342
343 /*
344 * Misc initialisation.
345 */
346 //pVM->hm.s.vmx.fSupported = false;
347 //pVM->hm.s.svm.fSupported = false;
348 //pVM->hm.s.vmx.fEnabled = false;
349 //pVM->hm.s.svm.fEnabled = false;
350 //pVM->hm.s.fNestedPaging = false;
351
352
353 /*
354 * Read configuration.
355 */
356 PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
357
358 /** @cfgm{/HM/HMForced, bool, false}
359 * Forces hardware virtualization, no falling back on raw-mode. HM must be
360 * enabled, i.e. /HMEnabled must be true. */
361 bool fHMForced;
362#ifdef VBOX_WITH_RAW_MODE
363 rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
364 AssertRCReturn(rc, rc);
365 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
366 VERR_INVALID_PARAMETER);
367# if defined(RT_OS_DARWIN)
368 if (pVM->fHMEnabled)
369 fHMForced = true;
370# endif
371 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
372 VERR_INVALID_PARAMETER);
373 if (pVM->cCpus > 1)
374 fHMForced = true;
375#else /* !VBOX_WITH_RAW_MODE */
376 AssertRelease(pVM->fHMEnabled);
377 fHMForced = true;
378#endif /* !VBOX_WITH_RAW_MODE */
379
380 /** @cfgm{/HM/EnableNestedPaging, bool, false}
381 * Enables nested paging (aka extended page tables). */
382 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
383 AssertRCReturn(rc, rc);
384
385 /** @cfgm{/HM/EnableUX, bool, true}
386 * Enables the VT-x unrestricted execution feature. */
387 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
388 AssertRCReturn(rc, rc);
389
390 /** @cfgm{/HM/EnableLargePages, bool, false}
391 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
392 * page table walking and maybe better TLB hit rate in some cases. */
393 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
394 AssertRCReturn(rc, rc);
395
396 /** @cfgm{/HM/EnableVPID, bool, false}
397 * Enables the VT-x VPID feature. */
398 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
399 AssertRCReturn(rc, rc);
400
401 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
402 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
403 rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
404 AssertRCReturn(rc, rc);
405
406 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
407 * Enables AMD64 cpu features.
408 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
409 * already have the support. */
410#ifdef VBOX_ENABLE_64_BITS_GUESTS
411 rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
412 AssertLogRelRCReturn(rc, rc);
413#else
414 pVM->hm.s.fAllow64BitGuests = false;
415#endif
416
417 /** @cfgm{/HM/Exclusive, bool}
418 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
419 * global init for each host CPU. If false, we do local init each time we wish
420 * to execute guest code.
421 *
422 * Default is false for Mac OS X and Windows due to the higher risk of conflicts
423 * with other hypervisors.
424 */
425 rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
426#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
427 false
428#else
429 true
430#endif
431 );
432 AssertLogRelRCReturn(rc, rc);
433
434 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
435 * The number of times to resume guest execution before we forcibly return to
436 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
437 * determins the default value. */
438 rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
439 AssertLogRelRCReturn(rc, rc);
440
441 /*
442 * Check if VT-x or AMD-v support according to the users wishes.
443 */
444 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
445 * VERR_SVM_IN_USE. */
446 if (pVM->fHMEnabled)
447 {
448 uint32_t fCaps;
449 rc = SUPR3QueryVTCaps(&fCaps);
450 if (RT_SUCCESS(rc))
451 {
452 if (fCaps & SUPVTCAPS_AMD_V)
453 LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
454 else if (fCaps & SUPVTCAPS_VT_X)
455 {
456 rc = SUPR3QueryVTxSupported();
457 if (RT_SUCCESS(rc))
458 LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
459 else
460 {
461#ifdef RT_OS_LINUX
462 const char *pszMinReq = " Linux 2.6.13 or newer required!";
463#else
464 const char *pszMinReq = "";
465#endif
466 if (fHMForced)
467 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
468
469 /* Fall back to raw-mode. */
470 LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
471 pVM->fHMEnabled = false;
472 }
473 }
474 else
475 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
476 VERR_INTERNAL_ERROR_5);
477
478 /*
479 * Do we require a little bit or raw-mode for 64-bit guest execution?
480 */
481 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
482 && pVM->fHMEnabled
483 && pVM->hm.s.fAllow64BitGuests;
484 }
485 else
486 {
487 const char *pszMsg;
488 switch (rc)
489 {
490 case VERR_UNSUPPORTED_CPU:
491 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
492 break;
493
494 case VERR_VMX_NO_VMX:
495 pszMsg = "VT-x is not available.";
496 break;
497
498 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
499 pszMsg = "VT-x is disabled in the BIOS (or by the host OS).";
500 break;
501
502 case VERR_SVM_NO_SVM:
503 pszMsg = "AMD-V is not available.";
504 break;
505
506 case VERR_SVM_DISABLED:
507 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
508 break;
509
510 default:
511 pszMsg = NULL;
512 break;
513 }
514 if (fHMForced && pszMsg)
515 return VM_SET_ERROR(pVM, rc, pszMsg);
516 if (!pszMsg)
517 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
518
519 /* Fall back to raw-mode. */
520 LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
521 pVM->fHMEnabled = false;
522 }
523 }
524
525 /* It's now OK to use the predicate function. */
526 pVM->fHMEnabledFixed = true;
527 return VINF_SUCCESS;
528}
529
530
531/**
532 * Initializes the per-VCPU HM.
533 *
534 * @returns VBox status code.
535 * @param pVM Pointer to the VM.
536 */
537static int hmR3InitCPU(PVM pVM)
538{
539 LogFlow(("HMR3InitCPU\n"));
540
541 if (!HMIsEnabled(pVM))
542 return VINF_SUCCESS;
543
544 for (VMCPUID i = 0; i < pVM->cCpus; i++)
545 {
546 PVMCPU pVCpu = &pVM->aCpus[i];
547 pVCpu->hm.s.fActive = false;
548 }
549
550#ifdef VBOX_WITH_STATISTICS
551 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
552 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
553 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
554 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
555
556 /*
557 * Statistics.
558 */
559 for (VMCPUID i = 0; i < pVM->cCpus; i++)
560 {
561 PVMCPU pVCpu = &pVM->aCpus[i];
562 int rc;
563
564 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
565 "Profiling of RTMpPokeCpu",
566 "/PROF/CPU%d/HM/Poke", i);
567 AssertRC(rc);
568 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
569 "Profiling of poke wait",
570 "/PROF/CPU%d/HM/PokeWait", i);
571 AssertRC(rc);
572 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
573 "Profiling of poke wait when RTMpPokeCpu fails",
574 "/PROF/CPU%d/HM/PokeWaitFailed", i);
575 AssertRC(rc);
576 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
577 "Profiling of VMXR0RunGuestCode entry",
578 "/PROF/CPU%d/HM/StatEntry", i);
579 AssertRC(rc);
580 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
581 "Profiling of VMXR0RunGuestCode exit part 1",
582 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
583 AssertRC(rc);
584 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
585 "Profiling of VMXR0RunGuestCode exit part 2",
586 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
587 AssertRC(rc);
588
589 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
590 "I/O",
591 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
592 AssertRC(rc);
593 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
594 "MOV CRx",
595 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
596 AssertRC(rc);
597 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
598 "Exceptions, NMIs",
599 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
600 AssertRC(rc);
601
602 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
603 "Profiling of VMXR0LoadGuestState",
604 "/PROF/CPU%d/HM/StatLoadGuestState", i);
605 AssertRC(rc);
606 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
607 "Profiling of VMLAUNCH/VMRESUME.",
608 "/PROF/CPU%d/HM/InGC", i);
609 AssertRC(rc);
610
611# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
612 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
613 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
614 "/PROF/CPU%d/HM/Switcher3264", i);
615 AssertRC(rc);
616# endif
617
618# ifdef HM_PROFILE_EXIT_DISPATCH
619 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
620 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
621 "/PROF/CPU%d/HM/ExitDispatch", i);
622 AssertRC(rc);
623# endif
624
625# define HM_REG_COUNTER(a, b, desc) \
626 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
627 AssertRC(rc);
628
629 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
630 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
631 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
632 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
633 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
634 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
635 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
636 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
637 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) execption.");
638 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
639 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
640 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
641 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
642 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
643 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
644 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
645 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
646 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
647 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
648 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
649 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
650 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
651 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
652 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
653 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
654 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
655 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
656 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
657 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
658 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
659 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
660 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
661 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
662 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
663 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
664 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
665 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
666 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
667 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
668 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
669 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
670 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
671 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
672 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
673 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
674 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
675 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
676 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
677 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
678 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
679 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
680 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
681
682 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
683 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
684 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
685 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
686
687 HM_REG_COUNTER(&pVCpu->hm.s.StatIntInject, "/HM/CPU%d/Irq/Inject", "Injecting hardware interrupt into the guest.");
688 HM_REG_COUNTER(&pVCpu->hm.s.StatIntReinject, "/HM/CPU%d/Irq/Reinject", "Re-injecting an event into the guest.");
689 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Irq/PendingOnHost", "Exiting to ring-3 due to preemption pending on the host.");
690
691 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
692 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
693 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
694 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
695 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
696 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
697 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
698 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
699 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
700 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
701 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
702 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
703 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
704
705 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
706 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
707 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
708
709 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
710 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
711 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
712
713 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading just RIP (+RSP, RFLAGs for old VT-x code).");
714 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading more of the state.");
715
716 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
717 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
718 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
719
720 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
721 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
722 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
724 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
725
726#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
727 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
728 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
729#endif
730
731 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
732 {
733 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
734 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
735 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
736 AssertRC(rc);
737 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
738 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
739 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
740 AssertRC(rc);
741 }
742
743#undef HM_REG_COUNTER
744
745 pVCpu->hm.s.paStatExitReason = NULL;
746
747 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
748 (void **)&pVCpu->hm.s.paStatExitReason);
749 AssertRC(rc);
750 if (RT_SUCCESS(rc))
751 {
752 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
753 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
754 {
755 if (papszDesc[j])
756 {
757 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
758 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
759 AssertRC(rc);
760 }
761 }
762 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
763 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
764 AssertRC(rc);
765 }
766 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
767# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
768 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
769# else
770 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
771# endif
772
773 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
774 AssertRCReturn(rc, rc);
775 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
776# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
777 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
778# else
779 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
780# endif
781 for (unsigned j = 0; j < 255; j++)
782 {
783 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
784 "Forwarded interrupts.",
785 (j < 0x20) ? "/HM/CPU%d/Interrupt/Trap/%02X" : "/HM/CPU%d/Interrupt/IRQ/%02X", i, j);
786 }
787
788 }
789#endif /* VBOX_WITH_STATISTICS */
790
791#ifdef VBOX_WITH_CRASHDUMP_MAGIC
792 /*
793 * Magic marker for searching in crash dumps.
794 */
795 for (VMCPUID i = 0; i < pVM->cCpus; i++)
796 {
797 PVMCPU pVCpu = &pVM->aCpus[i];
798
799 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
800 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
801 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
802 }
803#endif
804
805 return VINF_SUCCESS;
806}
807
808
809/**
810 * Called when a init phase has completed.
811 *
812 * @returns VBox status code.
813 * @param pVM The VM.
814 * @param enmWhat The phase that completed.
815 */
816VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
817{
818 switch (enmWhat)
819 {
820 case VMINITCOMPLETED_RING3:
821 return hmR3InitCPU(pVM);
822 case VMINITCOMPLETED_RING0:
823 return hmR3InitFinalizeR0(pVM);
824 default:
825 return VINF_SUCCESS;
826 }
827}
828
829
830/**
831 * Turns off normal raw mode features.
832 *
833 * @param pVM Pointer to the VM.
834 */
835static void hmR3DisableRawMode(PVM pVM)
836{
837 /* Reinit the paging mode to force the new shadow mode. */
838 for (VMCPUID i = 0; i < pVM->cCpus; i++)
839 {
840 PVMCPU pVCpu = &pVM->aCpus[i];
841
842 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
843 }
844}
845
846
847/**
848 * Initialize VT-x or AMD-V.
849 *
850 * @returns VBox status code.
851 * @param pVM Pointer to the VM.
852 */
853static int hmR3InitFinalizeR0(PVM pVM)
854{
855 int rc;
856
857 if (!HMIsEnabled(pVM))
858 return VINF_SUCCESS;
859
860 /*
861 * Hack to allow users to work around broken BIOSes that incorrectly set
862 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
863 */
864 if ( !pVM->hm.s.vmx.fSupported
865 && !pVM->hm.s.svm.fSupported
866 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
867 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
868 {
869 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
870 pVM->hm.s.svm.fSupported = true;
871 pVM->hm.s.svm.fIgnoreInUseError = true;
872 pVM->hm.s.lLastError = VINF_SUCCESS;
873 }
874
875 /*
876 * Report ring-0 init errors.
877 */
878 if ( !pVM->hm.s.vmx.fSupported
879 && !pVM->hm.s.svm.fSupported)
880 {
881 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
882 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
883 switch (pVM->hm.s.lLastError)
884 {
885 case VERR_VMX_IN_VMX_ROOT_MODE:
886 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
887 case VERR_VMX_NO_VMX:
888 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
889 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
890 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS (or by the host OS).");
891
892 case VERR_SVM_IN_USE:
893 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
894 case VERR_SVM_NO_SVM:
895 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
896 case VERR_SVM_DISABLED:
897 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
898 }
899 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
900 }
901
902 /*
903 * Enable VT-x or AMD-V on all host CPUs.
904 */
905 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
906 if (RT_FAILURE(rc))
907 {
908 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
909 return rc;
910 }
911
912 /*
913 * No TPR patching is required when the IO-APIC is not enabled for this VM.
914 * (Main should have taken care of this already)
915 */
916 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
917 if (!pVM->hm.s.fHasIoApic)
918 {
919 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
920 pVM->hm.s.fTRPPatchingAllowed = false;
921 }
922
923 /*
924 * Do the vendor specific initalization .
925 * .
926 * Note! We disable release log buffering here since we're doing relatively .
927 * lot of logging and doesn't want to hit the disk with each LogRel .
928 * statement.
929 */
930 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
931 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
932 if (pVM->hm.s.vmx.fSupported)
933 rc = hmR3InitFinalizeR0Intel(pVM);
934 else
935 rc = hmR3InitFinalizeR0Amd(pVM);
936 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
937 RTLogRelSetBuffering(fOldBuffered);
938 pVM->hm.s.fInitialized = true;
939
940 return rc;
941}
942
943
944/**
945 * Finish VT-x initialization (after ring-0 init).
946 *
947 * @returns VBox status code.
948 * @param pVM The cross context VM structure.
949 */
950static int hmR3InitFinalizeR0Intel(PVM pVM)
951{
952 int rc;
953
954 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
955 AssertLogRelReturn(pVM->hm.s.vmx.msr.feature_ctrl != 0, VERR_HM_IPE_4);
956
957 uint64_t val;
958 uint64_t zap;
959 RTGCPHYS GCPhys = 0;
960
961#ifndef VBOX_WITH_OLD_VTX_CODE
962 LogRel(("HM: Using VT-x implementation 2.0!\n"));
963#endif
964 LogRel(("HM: Host CR4 = %08X\n", pVM->hm.s.vmx.hostCR4));
965 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %RX64\n", pVM->hm.s.vmx.msr.feature_ctrl));
966 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %RX64\n", pVM->hm.s.vmx.msr.vmx_basic_info));
967 LogRel(("HM: VMCS id = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.vmx_basic_info)));
968 LogRel(("HM: VMCS size = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.vmx_basic_info)));
969 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.vmx_basic_info) ? "< 4 GB" : "None"));
970 LogRel(("HM: VMCS memory type = %x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.vmx_basic_info)));
971 LogRel(("HM: Dual-monitor treatment = %d\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.vmx_basic_info)));
972 LogRel(("HM: Max resume loops = %RX32\n", pVM->hm.s.cMaxResumeLoops));
973
974 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_pin_ctls.u));
975 val = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.allowed1;
976 zap = pVM->hm.s.vmx.msr.vmx_pin_ctls.n.disallowed0;
977 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
978 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
979 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
980 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
981
982 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls.u));
983 val = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1;
984 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls.n.disallowed0;
985 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
986 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
987 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
988 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
989 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
990 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
991 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
992 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
993 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
994 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
995 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
996 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
997 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
998 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
999 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1000 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1001 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1002 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1003 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1004 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1005 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1006 if (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1007 {
1008 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %RX64\n", pVM->hm.s.vmx.msr.vmx_proc_ctls2.u));
1009 val = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1;
1010 zap = pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.disallowed0;
1011 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1012 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1013 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1014 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1015 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1016 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1017 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1018 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1019 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1020 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1021 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1022 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1023 }
1024
1025 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_entry.u));
1026 val = pVM->hm.s.vmx.msr.vmx_entry.n.allowed1;
1027 zap = pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0;
1028 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1029 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1030 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1031 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1032 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1033 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1034 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1035
1036 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %RX64\n", pVM->hm.s.vmx.msr.vmx_exit.u));
1037 val = pVM->hm.s.vmx.msr.vmx_exit.n.allowed1;
1038 zap = pVM->hm.s.vmx.msr.vmx_exit.n.disallowed0;
1039 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1040 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1041 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1042 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1043 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1044 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1045 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1046 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1047 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1048
1049 if (pVM->hm.s.vmx.msr.vmx_ept_vpid_caps)
1050 {
1051 val = pVM->hm.s.vmx.msr.vmx_ept_vpid_caps;
1052 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %RX64\n", val));
1053 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1054 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1055 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1056 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1057 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1058 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1059 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1060 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1061 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1062 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1063 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1064 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1065 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1066 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1067 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1068 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1069 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1070 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1071 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1072 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1073 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1074 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1075 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1076 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1077 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1078 }
1079
1080 LogRel(("HM: MSR_IA32_VMX_MISC = %RX64\n", pVM->hm.s.vmx.msr.vmx_misc));
1081 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1082 {
1083 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x\n",
1084 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc)));
1085 }
1086 else
1087 {
1088 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %x - erratum detected, using %x instead\n",
1089 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.vmx_misc), pVM->hm.s.vmx.cPreemptTimerShift));
1090 }
1091
1092 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %x\n", MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(pVM->hm.s.vmx.msr.vmx_misc)));
1093 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(pVM->hm.s.vmx.msr.vmx_misc)));
1094 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %x\n", MSR_IA32_VMX_MISC_CR3_TARGET(pVM->hm.s.vmx.msr.vmx_misc)));
1095 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %x\n", MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc)));
1096 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %x\n", MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(pVM->hm.s.vmx.msr.vmx_misc)));
1097 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %x\n", MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(pVM->hm.s.vmx.msr.vmx_misc)));
1098 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %x\n", MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(pVM->hm.s.vmx.msr.vmx_misc)));
1099 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %x\n", MSR_IA32_VMX_MISC_MSEG_ID(pVM->hm.s.vmx.msr.vmx_misc)));
1100
1101 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed0));
1102 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr0_fixed1));
1103 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed0));
1104 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %RX64\n", pVM->hm.s.vmx.msr.vmx_cr4_fixed1));
1105 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %RX64\n", pVM->hm.s.vmx.msr.vmx_vmcs_enum));
1106
1107 LogRel(("HM: APIC-access page physaddr = %RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1108
1109 /* Paranoia */
1110 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.vmx_misc) >= 512);
1111
1112 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1113 {
1114 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1115 LogRel(("HM: VCPU%3d: VMCS physaddr = %RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1116 }
1117
1118 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1119 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1120
1121 if (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1122 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1123
1124 /*
1125 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1126 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1127 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1128 */
1129 if ( !(pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1130 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1131 {
1132 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1133 LogRel(("HM: RDTSCP disabled.\n"));
1134 }
1135
1136 /* Unrestricted guest execution also requires EPT. */
1137 if ( pVM->hm.s.vmx.fAllowUnrestricted
1138 && pVM->hm.s.fNestedPaging
1139 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1140 {
1141 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1142 }
1143
1144 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1145 {
1146 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1147 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1148 if (RT_SUCCESS(rc))
1149 {
1150 /* The I/O bitmap starts right after the virtual interrupt redirection bitmap.
1151 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1152 esp. Figure 20-5.*/
1153 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1154 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1155
1156 /* Bit set to 0 means software interrupts are redirected to the
1157 8086 program interrupt handler rather than switching to
1158 protected-mode handler. */
1159 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1160
1161 /* Allow all port IO, so that port IO instructions do not cause
1162 exceptions and would instead cause a VM-exit (based on VT-x's
1163 IO bitmap which we currently configure to always cause an exit). */
1164 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1165 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1166
1167 /*
1168 * Construct a 1024 element page directory with 4 MB pages for
1169 * the identity mapped page table used in real and protected mode
1170 * without paging with EPT.
1171 */
1172 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1173 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1174 {
1175 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1176 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1177 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1178 | X86_PDE4M_G;
1179 }
1180
1181 /* We convert it here every time as pci regions could be reconfigured. */
1182 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1183 AssertRCReturn(rc, rc);
1184 LogRel(("HM: Real Mode TSS guest physaddr = %RGp\n", GCPhys));
1185
1186 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1187 AssertRCReturn(rc, rc);
1188 LogRel(("HM: Non-Paging Mode EPT CR3 = %RGp\n", GCPhys));
1189 }
1190 else
1191 {
1192 /** @todo This cannot possibly work, there are other places which assumes
1193 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1194 * a failure case. */
1195 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1196 pVM->hm.s.vmx.pRealModeTSS = NULL;
1197 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1198 }
1199 }
1200
1201 /*
1202 * Call ring-0 to set up the VM.
1203 */
1204 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1205 if (rc != VINF_SUCCESS)
1206 {
1207 AssertMsgFailed(("%Rrc\n", rc));
1208 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1209 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1210 LogRel(("HM: CPU[%ld] Last instruction error %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
1211 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1212 }
1213
1214 LogRel(("HM: VMX enabled!\n"));
1215 pVM->hm.s.vmx.fEnabled = true;
1216
1217 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1218
1219 /*
1220 * Change the CPU features.
1221 */
1222 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1223 if (pVM->hm.s.fAllow64BitGuests)
1224 {
1225 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1226 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1227 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1228 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1229 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1230#if 0 /** @todo r=bird: This ain't making any sense whatsoever. */
1231#if RT_ARCH_X86
1232 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1233 || !(pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1234 LogRel(("NX is only supported for 64-bit guests!\n"));
1235#endif
1236#endif
1237 }
1238 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1239 (we reuse the host EFER in the switcher). */
1240 /** @todo this needs to be fixed properly!! */
1241 else if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1242 && (pVM->hm.s.vmx.hostEFER & MSR_K6_EFER_NXE))
1243 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1244 else
1245 LogRel(("HM: NX not supported by the host.\n"));
1246
1247 /*
1248 * Log configuration details.
1249 */
1250 LogRel((pVM->hm.s.fAllow64BitGuests
1251 ? "HM: Guest support: 32-bit and 64-bit.\n"
1252 : "HM: Guest support: 32-bit only.\n"));
1253 if (pVM->hm.s.fNestedPaging)
1254 {
1255 LogRel(("HM: Nested paging enabled!\n"));
1256 LogRel(("HM: EPT root page physaddr = %RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1257 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1258 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1259 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1260 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1261 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1262 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1263 else
1264 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1265
1266 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1267 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1268
1269#if HC_ARCH_BITS == 64
1270 if (pVM->hm.s.fLargePages)
1271 {
1272 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1273 PGMSetLargePageUsage(pVM, true);
1274 LogRel(("HM: Large page support enabled!\n"));
1275 }
1276#endif
1277 }
1278 else
1279 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1280
1281 if (pVM->hm.s.vmx.fVpid)
1282 {
1283 LogRel(("HM: VPID enabled!\n"));
1284 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1285 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1286 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1287 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1288 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1289 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1290 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1291 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1292 else
1293 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1294 }
1295 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1296 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1297
1298 /*
1299 * TPR patching status logging.
1300 */
1301 if (pVM->hm.s.fTRPPatchingAllowed)
1302 {
1303 if ( (pVM->hm.s.vmx.msr.vmx_proc_ctls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1304 && (pVM->hm.s.vmx.msr.vmx_proc_ctls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC))
1305 {
1306 pVM->hm.s.fTRPPatchingAllowed = false; /* not necessary as we have a hardware solution. */
1307 LogRel(("HM: TPR Patching not required (VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC).\n"));
1308 }
1309 else
1310 {
1311 uint32_t u32Eax, u32Dummy;
1312
1313 /* TPR patching needs access to the MSR_K8_LSTAR msr. */
1314 ASMCpuId(0x80000000, &u32Eax, &u32Dummy, &u32Dummy, &u32Dummy);
1315 if ( u32Eax < 0x80000001
1316 || !(ASMCpuId_EDX(0x80000001) & X86_CPUID_EXT_FEATURE_EDX_LONG_MODE))
1317 {
1318 pVM->hm.s.fTRPPatchingAllowed = false;
1319 LogRel(("HM: TPR patching disabled (long mode not supported).\n"));
1320 }
1321 }
1322 }
1323 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1324
1325 /*
1326 * Check for preemption timer config override and log the state of it.
1327 */
1328 if (pVM->hm.s.vmx.fUsePreemptTimer)
1329 {
1330 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1331 rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1332 AssertLogRelRCReturn(rc, rc);
1333 }
1334 if (pVM->hm.s.vmx.fUsePreemptTimer)
1335 LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u).\n", pVM->hm.s.vmx.cPreemptTimerShift));
1336 else
1337 LogRel(("HM: VMX-preemption timer disabled.\n"));
1338
1339 return VINF_SUCCESS;
1340}
1341
1342
1343/**
1344 * Finish AMD-V initialization (after ring-0 init).
1345 *
1346 * @returns VBox status code.
1347 * @param pVM The cross context VM structure.
1348 */
1349static int hmR3InitFinalizeR0Amd(PVM pVM)
1350{
1351 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1352
1353 uint32_t u32Family;
1354 uint32_t u32Model;
1355 uint32_t u32Stepping;
1356 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1357 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1358 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureECX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1359 LogRel(("HM: cpuid 0x80000001.u32AMDFeatureEDX = %RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1360 LogRel(("HM: AMD HWCR MSR = %RX64\n", pVM->hm.s.svm.msrHwcr));
1361 LogRel(("HM: AMD-V revision = %X\n", pVM->hm.s.svm.u32Rev));
1362 LogRel(("HM: AMD-V max ASID = %d\n", pVM->hm.s.uMaxAsid));
1363 LogRel(("HM: AMD-V features = %X\n", pVM->hm.s.svm.u32Features));
1364
1365 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1366 {
1367#define FLAG_NAME(a_Define) { a_Define, #a_Define }
1368 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1369 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1370 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1371 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1372 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1373 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1374 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1375 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1376 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_SSE_3_5_DISABLE),
1377 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1378 FLAG_NAME(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1379#undef FLAG_NAME
1380 };
1381 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1382 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1383 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1384 {
1385 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1386 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1387 }
1388 if (fSvmFeatures)
1389 for (unsigned iBit = 0; iBit < 32; iBit++)
1390 if (RT_BIT_32(iBit) & fSvmFeatures)
1391 LogRel(("HM: Reserved bit %u\n", iBit));
1392
1393 /*
1394 * Adjust feature(s).
1395 */
1396 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1397 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1398
1399 /*
1400 * Call ring-0 to set up the VM.
1401 */
1402 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1403 if (rc != VINF_SUCCESS)
1404 {
1405 AssertMsgFailed(("%Rrc\n", rc));
1406 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1407 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1408 }
1409
1410 LogRel(("HM: AMD-V enabled!\n"));
1411 pVM->hm.s.svm.fEnabled = true;
1412
1413 if (pVM->hm.s.fNestedPaging)
1414 {
1415 LogRel(("HM: Enabled nested paging!\n"));
1416
1417 /*
1418 * Enable large pages (2 MB) if applicable.
1419 */
1420#if HC_ARCH_BITS == 64
1421 if (pVM->hm.s.fLargePages)
1422 {
1423 PGMSetLargePageUsage(pVM, true);
1424 LogRel(("HM: Large page support enabled!\n"));
1425 }
1426#endif
1427 }
1428
1429 hmR3DisableRawMode(pVM);
1430
1431 /*
1432 * Change the CPU features.
1433 */
1434 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1435 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1436 if (pVM->hm.s.fAllow64BitGuests)
1437 {
1438 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1439 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1440 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1441 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1442 }
1443 /* Turn on NXE if PAE has been enabled. */
1444 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1445 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1446
1447
1448 LogRel((pVM->hm.s.fAllow64BitGuests
1449 ? "HM: 32-bit and 64-bit guest supported.\n"
1450 : "HM: 32-bit guest supported.\n"));
1451 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1452
1453 return VINF_SUCCESS;
1454}
1455
1456
1457/**
1458 * Applies relocations to data and code managed by this
1459 * component. This function will be called at init and
1460 * whenever the VMM need to relocate it self inside the GC.
1461 *
1462 * @param pVM The VM.
1463 */
1464VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1465{
1466 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1467
1468 /* Fetch the current paging mode during the relocate callback during state loading. */
1469 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1470 {
1471 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1472 {
1473 PVMCPU pVCpu = &pVM->aCpus[i];
1474
1475 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1476#ifdef VBOX_WITH_OLD_VTX_CODE
1477 Assert(pVCpu->hm.s.vmx.enmCurrGuestMode == PGMGetGuestMode(pVCpu));
1478 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMGetGuestMode(pVCpu);
1479#endif
1480 }
1481 }
1482#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1483 if (HMIsEnabled(pVM))
1484 {
1485 switch (PGMGetHostMode(pVM))
1486 {
1487 case PGMMODE_32_BIT:
1488 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1489 break;
1490
1491 case PGMMODE_PAE:
1492 case PGMMODE_PAE_NX:
1493 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1494 break;
1495
1496 default:
1497 AssertFailed();
1498 break;
1499 }
1500 }
1501#endif
1502 return;
1503}
1504
1505
1506/**
1507 * Notification callback which is called whenever there is a chance that a CR3
1508 * value might have changed.
1509 *
1510 * This is called by PGM.
1511 *
1512 * @param pVM Pointer to the VM.
1513 * @param pVCpu Pointer to the VMCPU.
1514 * @param enmShadowMode New shadow paging mode.
1515 * @param enmGuestMode New guest paging mode.
1516 */
1517VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1518{
1519 /* Ignore page mode changes during state loading. */
1520 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1521 return;
1522
1523 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1524
1525#ifdef VBOX_WITH_OLD_VTX_CODE
1526 if ( pVM->hm.s.vmx.fEnabled
1527 && HMIsEnabled(pVM))
1528 {
1529 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
1530 && enmGuestMode >= PGMMODE_PROTECTED)
1531 {
1532 PCPUMCTX pCtx;
1533
1534 pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1535
1536 /* After a real mode switch to protected mode we must force
1537 CPL to 0. Our real mode emulation had to set it to 3. */
1538 pCtx->ss.Attr.n.u2Dpl = 0;
1539 }
1540 }
1541
1542 if (pVCpu->hm.s.vmx.enmCurrGuestMode != enmGuestMode)
1543 {
1544 /* Keep track of paging mode changes. */
1545 pVCpu->hm.s.vmx.enmPrevGuestMode = pVCpu->hm.s.vmx.enmCurrGuestMode;
1546 pVCpu->hm.s.vmx.enmCurrGuestMode = enmGuestMode;
1547
1548 /* Did we miss a change, because all code was executed in the recompiler? */
1549 if (pVCpu->hm.s.vmx.enmLastSeenGuestMode == enmGuestMode)
1550 {
1551 Log(("HMR3PagingModeChanged missed %s->%s transition (prev %s)\n", PGMGetModeName(pVCpu->hm.s.vmx.enmPrevGuestMode),
1552 PGMGetModeName(pVCpu->hm.s.vmx.enmCurrGuestMode), PGMGetModeName(pVCpu->hm.s.vmx.enmLastSeenGuestMode)));
1553 pVCpu->hm.s.vmx.enmLastSeenGuestMode = pVCpu->hm.s.vmx.enmPrevGuestMode;
1554 }
1555 }
1556#else
1557 /* If the guest left protected mode VMX execution, we'll have to be extra
1558 * careful if/when the guest switches back to protected mode.
1559 */
1560 if (enmGuestMode == PGMMODE_REAL)
1561 {
1562 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1563 pVCpu->hm.s.vmx.fWasInRealMode = true;
1564 }
1565#endif
1566
1567 /** @todo r=ramshankar: Why do we need to do this? */
1568#ifdef VMX_USE_CACHED_VMCS_ACCESSES
1569 /* Reset the contents of the read cache. */
1570 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1571 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1572 pCache->Read.aFieldVal[j] = 0;
1573#endif
1574}
1575
1576
1577/**
1578 * Terminates the HM.
1579 *
1580 * Termination means cleaning up and freeing all resources,
1581 * the VM itself is, at this point, powered off or suspended.
1582 *
1583 * @returns VBox status code.
1584 * @param pVM Pointer to the VM.
1585 */
1586VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1587{
1588 if (pVM->hm.s.vmx.pRealModeTSS)
1589 {
1590 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1591 pVM->hm.s.vmx.pRealModeTSS = 0;
1592 }
1593 hmR3TermCPU(pVM);
1594 return 0;
1595}
1596
1597
1598/**
1599 * Terminates the per-VCPU HM.
1600 *
1601 * @returns VBox status code.
1602 * @param pVM Pointer to the VM.
1603 */
1604static int hmR3TermCPU(PVM pVM)
1605{
1606 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1607 {
1608 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1609
1610#ifdef VBOX_WITH_STATISTICS
1611 if (pVCpu->hm.s.paStatExitReason)
1612 {
1613 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1614 pVCpu->hm.s.paStatExitReason = NULL;
1615 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1616 }
1617 if (pVCpu->hm.s.paStatInjectedIrqs)
1618 {
1619 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1620 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1621 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1622 }
1623#endif
1624
1625#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1626 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1627 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1628 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1629#endif
1630 }
1631 return 0;
1632}
1633
1634
1635/**
1636 * Resets a virtual CPU.
1637 *
1638 * Used by HMR3Reset and CPU hot plugging.
1639 *
1640 * @param pVCpu The CPU to reset.
1641 */
1642VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1643{
1644 /* On first entry we'll sync everything. */
1645 pVCpu->hm.s.fContextUseFlags = HM_CHANGED_ALL;
1646
1647 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1648 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1649
1650 pVCpu->hm.s.fActive = false;
1651 pVCpu->hm.s.Event.fPending = false;
1652
1653#ifdef VBOX_WITH_OLD_VTX_CODE
1654 /* Reset state information for real-mode emulation in VT-x. */
1655 pVCpu->hm.s.vmx.enmLastSeenGuestMode = PGMMODE_REAL;
1656 pVCpu->hm.s.vmx.enmPrevGuestMode = PGMMODE_REAL;
1657 pVCpu->hm.s.vmx.enmCurrGuestMode = PGMMODE_REAL;
1658#else
1659 pVCpu->hm.s.vmx.fWasInRealMode = true;
1660#endif
1661
1662 /* Reset the contents of the read cache. */
1663 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1664 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1665 pCache->Read.aFieldVal[j] = 0;
1666
1667#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1668 /* Magic marker for searching in crash dumps. */
1669 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1670 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1671#endif
1672}
1673
1674
1675/**
1676 * The VM is being reset.
1677 *
1678 * For the HM component this means that any GDT/LDT/TSS monitors
1679 * needs to be removed.
1680 *
1681 * @param pVM Pointer to the VM.
1682 */
1683VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1684{
1685 LogFlow(("HMR3Reset:\n"));
1686
1687 if (HMIsEnabled(pVM))
1688 hmR3DisableRawMode(pVM);
1689
1690 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1691 {
1692 PVMCPU pVCpu = &pVM->aCpus[i];
1693
1694 HMR3ResetCpu(pVCpu);
1695 }
1696
1697 /* Clear all patch information. */
1698 pVM->hm.s.pGuestPatchMem = 0;
1699 pVM->hm.s.pFreeGuestPatchMem = 0;
1700 pVM->hm.s.cbGuestPatchMem = 0;
1701 pVM->hm.s.cPatches = 0;
1702 pVM->hm.s.PatchTree = 0;
1703 pVM->hm.s.fTPRPatchingActive = false;
1704 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1705}
1706
1707
1708/**
1709 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1710 *
1711 * @returns VBox strict status code.
1712 * @param pVM Pointer to the VM.
1713 * @param pVCpu The VMCPU for the EMT we're being called on.
1714 * @param pvUser Unused.
1715 */
1716DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1717{
1718 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1719
1720 /* Only execute the handler on the VCPU the original patch request was issued. */
1721 if (pVCpu->idCpu != idCpu)
1722 return VINF_SUCCESS;
1723
1724 Log(("hmR3RemovePatches\n"));
1725 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1726 {
1727 uint8_t abInstr[15];
1728 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1729 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1730 int rc;
1731
1732#ifdef LOG_ENABLED
1733 char szOutput[256];
1734
1735 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1736 szOutput, sizeof(szOutput), NULL);
1737 if (RT_SUCCESS(rc))
1738 Log(("Patched instr: %s\n", szOutput));
1739#endif
1740
1741 /* Check if the instruction is still the same. */
1742 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1743 if (rc != VINF_SUCCESS)
1744 {
1745 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1746 continue; /* swapped out or otherwise removed; skip it. */
1747 }
1748
1749 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1750 {
1751 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1752 continue; /* skip it. */
1753 }
1754
1755 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1756 AssertRC(rc);
1757
1758#ifdef LOG_ENABLED
1759 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1760 szOutput, sizeof(szOutput), NULL);
1761 if (RT_SUCCESS(rc))
1762 Log(("Original instr: %s\n", szOutput));
1763#endif
1764 }
1765 pVM->hm.s.cPatches = 0;
1766 pVM->hm.s.PatchTree = 0;
1767 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1768 pVM->hm.s.fTPRPatchingActive = false;
1769 return VINF_SUCCESS;
1770}
1771
1772
1773/**
1774 * Worker for enabling patching in a VT-x/AMD-V guest.
1775 *
1776 * @returns VBox status code.
1777 * @param pVM Pointer to the VM.
1778 * @param idCpu VCPU to execute hmR3RemovePatches on.
1779 * @param pPatchMem Patch memory range.
1780 * @param cbPatchMem Size of the memory range.
1781 */
1782static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1783{
1784 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1785 AssertRC(rc);
1786
1787 pVM->hm.s.pGuestPatchMem = pPatchMem;
1788 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1789 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1790 return VINF_SUCCESS;
1791}
1792
1793
1794/**
1795 * Enable patching in a VT-x/AMD-V guest
1796 *
1797 * @returns VBox status code.
1798 * @param pVM Pointer to the VM.
1799 * @param pPatchMem Patch memory range.
1800 * @param cbPatchMem Size of the memory range.
1801 */
1802VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1803{
1804 VM_ASSERT_EMT(pVM);
1805 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1806 if (pVM->cCpus > 1)
1807 {
1808 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1809 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1810 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1811 AssertRC(rc);
1812 return rc;
1813 }
1814 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1815}
1816
1817
1818/**
1819 * Disable patching in a VT-x/AMD-V guest.
1820 *
1821 * @returns VBox status code.
1822 * @param pVM Pointer to the VM.
1823 * @param pPatchMem Patch memory range.
1824 * @param cbPatchMem Size of the memory range.
1825 */
1826VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1827{
1828 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1829
1830 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1831 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1832
1833 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1834 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1835 (void *)(uintptr_t)VMMGetCpuId(pVM));
1836 AssertRC(rc);
1837
1838 pVM->hm.s.pGuestPatchMem = 0;
1839 pVM->hm.s.pFreeGuestPatchMem = 0;
1840 pVM->hm.s.cbGuestPatchMem = 0;
1841 pVM->hm.s.fTPRPatchingActive = false;
1842 return VINF_SUCCESS;
1843}
1844
1845
1846/**
1847 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1848 *
1849 * @returns VBox strict status code.
1850 * @param pVM Pointer to the VM.
1851 * @param pVCpu The VMCPU for the EMT we're being called on.
1852 * @param pvUser User specified CPU context.
1853 *
1854 */
1855DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1856{
1857 /*
1858 * Only execute the handler on the VCPU the original patch request was
1859 * issued. (The other CPU(s) might not yet have switched to protected
1860 * mode, nor have the correct memory context.)
1861 */
1862 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1863 if (pVCpu->idCpu != idCpu)
1864 return VINF_SUCCESS;
1865
1866 /*
1867 * We're racing other VCPUs here, so don't try patch the instruction twice
1868 * and make sure there is still room for our patch record.
1869 */
1870 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1871 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1872 if (pPatch)
1873 {
1874 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1875 return VINF_SUCCESS;
1876 }
1877 uint32_t const idx = pVM->hm.s.cPatches;
1878 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1879 {
1880 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1881 return VINF_SUCCESS;
1882 }
1883 pPatch = &pVM->hm.s.aPatches[idx];
1884
1885 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1886
1887 /*
1888 * Disassembler the instruction and get cracking.
1889 */
1890 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1891 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1892 uint32_t cbOp;
1893 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1894 AssertRC(rc);
1895 if ( rc == VINF_SUCCESS
1896 && pDis->pCurInstr->uOpcode == OP_MOV
1897 && cbOp >= 3)
1898 {
1899 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1900
1901 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1902 AssertRC(rc);
1903
1904 pPatch->cbOp = cbOp;
1905
1906 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1907 {
1908 /* write. */
1909 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1910 {
1911 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1912 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1913 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1914 }
1915 else
1916 {
1917 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1918 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1919 pPatch->uSrcOperand = pDis->Param2.uValue;
1920 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1921 }
1922 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1923 AssertRC(rc);
1924
1925 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1926 pPatch->cbNewOp = sizeof(s_abVMMCall);
1927 }
1928 else
1929 {
1930 /*
1931 * TPR Read.
1932 *
1933 * Found:
1934 * mov eax, dword [fffe0080] (5 bytes)
1935 * Check if next instruction is:
1936 * shr eax, 4
1937 */
1938 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1939
1940 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1941 uint8_t const cbOpMmio = cbOp;
1942 uint64_t const uSavedRip = pCtx->rip;
1943
1944 pCtx->rip += cbOp;
1945 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1946 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1947 pCtx->rip = uSavedRip;
1948
1949 if ( rc == VINF_SUCCESS
1950 && pDis->pCurInstr->uOpcode == OP_SHR
1951 && pDis->Param1.fUse == DISUSE_REG_GEN32
1952 && pDis->Param1.Base.idxGenReg == idxMmioReg
1953 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1954 && pDis->Param2.uValue == 4
1955 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1956 {
1957 uint8_t abInstr[15];
1958
1959 /* Replacing two instructions now. */
1960 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1961 AssertRC(rc);
1962
1963 pPatch->cbOp = cbOpMmio + cbOp;
1964
1965 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1966 abInstr[0] = 0xF0;
1967 abInstr[1] = 0x0F;
1968 abInstr[2] = 0x20;
1969 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1970 for (unsigned i = 4; i < pPatch->cbOp; i++)
1971 abInstr[i] = 0x90; /* nop */
1972
1973 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1974 AssertRC(rc);
1975
1976 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1977 pPatch->cbNewOp = pPatch->cbOp;
1978
1979 Log(("Acceptable read/shr candidate!\n"));
1980 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1981 }
1982 else
1983 {
1984 pPatch->enmType = HMTPRINSTR_READ;
1985 pPatch->uDstOperand = idxMmioReg;
1986
1987 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1988 AssertRC(rc);
1989
1990 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1991 pPatch->cbNewOp = sizeof(s_abVMMCall);
1992 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1993 }
1994 }
1995
1996 pPatch->Core.Key = pCtx->eip;
1997 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1998 AssertRC(rc);
1999
2000 pVM->hm.s.cPatches++;
2001 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
2002 return VINF_SUCCESS;
2003 }
2004
2005 /*
2006 * Save invalid patch, so we will not try again.
2007 */
2008 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2009 pPatch->Core.Key = pCtx->eip;
2010 pPatch->enmType = HMTPRINSTR_INVALID;
2011 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2012 AssertRC(rc);
2013 pVM->hm.s.cPatches++;
2014 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2015 return VINF_SUCCESS;
2016}
2017
2018
2019/**
2020 * Callback to patch a TPR instruction (jump to generated code).
2021 *
2022 * @returns VBox strict status code.
2023 * @param pVM Pointer to the VM.
2024 * @param pVCpu The VMCPU for the EMT we're being called on.
2025 * @param pvUser User specified CPU context.
2026 *
2027 */
2028DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2029{
2030 /*
2031 * Only execute the handler on the VCPU the original patch request was
2032 * issued. (The other CPU(s) might not yet have switched to protected
2033 * mode, nor have the correct memory context.)
2034 */
2035 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2036 if (pVCpu->idCpu != idCpu)
2037 return VINF_SUCCESS;
2038
2039 /*
2040 * We're racing other VCPUs here, so don't try patch the instruction twice
2041 * and make sure there is still room for our patch record.
2042 */
2043 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2044 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2045 if (pPatch)
2046 {
2047 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2048 return VINF_SUCCESS;
2049 }
2050 uint32_t const idx = pVM->hm.s.cPatches;
2051 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2052 {
2053 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2054 return VINF_SUCCESS;
2055 }
2056 pPatch = &pVM->hm.s.aPatches[idx];
2057
2058 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2059 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2060
2061 /*
2062 * Disassemble the instruction and get cracking.
2063 */
2064 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2065 uint32_t cbOp;
2066 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2067 AssertRC(rc);
2068 if ( rc == VINF_SUCCESS
2069 && pDis->pCurInstr->uOpcode == OP_MOV
2070 && cbOp >= 5)
2071 {
2072 uint8_t aPatch[64];
2073 uint32_t off = 0;
2074
2075 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2076 AssertRC(rc);
2077
2078 pPatch->cbOp = cbOp;
2079 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2080
2081 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2082 {
2083 /*
2084 * TPR write:
2085 *
2086 * push ECX [51]
2087 * push EDX [52]
2088 * push EAX [50]
2089 * xor EDX,EDX [31 D2]
2090 * mov EAX,EAX [89 C0]
2091 * or
2092 * mov EAX,0000000CCh [B8 CC 00 00 00]
2093 * mov ECX,0C0000082h [B9 82 00 00 C0]
2094 * wrmsr [0F 30]
2095 * pop EAX [58]
2096 * pop EDX [5A]
2097 * pop ECX [59]
2098 * jmp return_address [E9 return_address]
2099 *
2100 */
2101 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2102
2103 aPatch[off++] = 0x51; /* push ecx */
2104 aPatch[off++] = 0x52; /* push edx */
2105 if (!fUsesEax)
2106 aPatch[off++] = 0x50; /* push eax */
2107 aPatch[off++] = 0x31; /* xor edx, edx */
2108 aPatch[off++] = 0xD2;
2109 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2110 {
2111 if (!fUsesEax)
2112 {
2113 aPatch[off++] = 0x89; /* mov eax, src_reg */
2114 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2115 }
2116 }
2117 else
2118 {
2119 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2120 aPatch[off++] = 0xB8; /* mov eax, immediate */
2121 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2122 off += sizeof(uint32_t);
2123 }
2124 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2125 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2126 off += sizeof(uint32_t);
2127
2128 aPatch[off++] = 0x0F; /* wrmsr */
2129 aPatch[off++] = 0x30;
2130 if (!fUsesEax)
2131 aPatch[off++] = 0x58; /* pop eax */
2132 aPatch[off++] = 0x5A; /* pop edx */
2133 aPatch[off++] = 0x59; /* pop ecx */
2134 }
2135 else
2136 {
2137 /*
2138 * TPR read:
2139 *
2140 * push ECX [51]
2141 * push EDX [52]
2142 * push EAX [50]
2143 * mov ECX,0C0000082h [B9 82 00 00 C0]
2144 * rdmsr [0F 32]
2145 * mov EAX,EAX [89 C0]
2146 * pop EAX [58]
2147 * pop EDX [5A]
2148 * pop ECX [59]
2149 * jmp return_address [E9 return_address]
2150 *
2151 */
2152 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2153
2154 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2155 aPatch[off++] = 0x51; /* push ecx */
2156 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2157 aPatch[off++] = 0x52; /* push edx */
2158 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2159 aPatch[off++] = 0x50; /* push eax */
2160
2161 aPatch[off++] = 0x31; /* xor edx, edx */
2162 aPatch[off++] = 0xD2;
2163
2164 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2165 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2166 off += sizeof(uint32_t);
2167
2168 aPatch[off++] = 0x0F; /* rdmsr */
2169 aPatch[off++] = 0x32;
2170
2171 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2172 {
2173 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2174 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2175 }
2176
2177 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2178 aPatch[off++] = 0x58; /* pop eax */
2179 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2180 aPatch[off++] = 0x5A; /* pop edx */
2181 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2182 aPatch[off++] = 0x59; /* pop ecx */
2183 }
2184 aPatch[off++] = 0xE9; /* jmp return_address */
2185 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2186 off += sizeof(RTRCUINTPTR);
2187
2188 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2189 {
2190 /* Write new code to the patch buffer. */
2191 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2192 AssertRC(rc);
2193
2194#ifdef LOG_ENABLED
2195 uint32_t cbCurInstr;
2196 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2197 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2198 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2199 {
2200 char szOutput[256];
2201 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2202 szOutput, sizeof(szOutput), &cbCurInstr);
2203 if (RT_SUCCESS(rc))
2204 Log(("Patch instr %s\n", szOutput));
2205 else
2206 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2207 }
2208#endif
2209
2210 pPatch->aNewOpcode[0] = 0xE9;
2211 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2212
2213 /* Overwrite the TPR instruction with a jump. */
2214 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2215 AssertRC(rc);
2216
2217 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2218
2219 pVM->hm.s.pFreeGuestPatchMem += off;
2220 pPatch->cbNewOp = 5;
2221
2222 pPatch->Core.Key = pCtx->eip;
2223 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2224 AssertRC(rc);
2225
2226 pVM->hm.s.cPatches++;
2227 pVM->hm.s.fTPRPatchingActive = true;
2228 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2229 return VINF_SUCCESS;
2230 }
2231
2232 Log(("Ran out of space in our patch buffer!\n"));
2233 }
2234 else
2235 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2236
2237
2238 /*
2239 * Save invalid patch, so we will not try again.
2240 */
2241 pPatch = &pVM->hm.s.aPatches[idx];
2242 pPatch->Core.Key = pCtx->eip;
2243 pPatch->enmType = HMTPRINSTR_INVALID;
2244 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2245 AssertRC(rc);
2246 pVM->hm.s.cPatches++;
2247 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2248 return VINF_SUCCESS;
2249}
2250
2251
2252/**
2253 * Attempt to patch TPR mmio instructions.
2254 *
2255 * @returns VBox status code.
2256 * @param pVM Pointer to the VM.
2257 * @param pVCpu Pointer to the VMCPU.
2258 * @param pCtx Pointer to the guest CPU context.
2259 */
2260VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2261{
2262 NOREF(pCtx);
2263 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2264 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2265 (void *)(uintptr_t)pVCpu->idCpu);
2266 AssertRC(rc);
2267 return rc;
2268}
2269
2270
2271/**
2272 * Checks if a code selector (CS) is suitable for execution
2273 * within VMX when unrestricted execution isn't available.
2274 *
2275 * @returns true if selector is suitable for VMX, otherwise
2276 * false.
2277 * @param pSel Pointer to the selector to check (CS).
2278 * uStackDpl The DPL of the stack segment.
2279 */
2280static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2281{
2282 bool rc = false;
2283
2284 do
2285 {
2286 /* Segment must be accessed. */
2287 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2288 break;
2289 /* Segment must be a code segment. */
2290 if (!(pSel->Attr.u & X86_SEL_TYPE_CODE))
2291 break;
2292 /* The S bit must be set. */
2293 if (!pSel->Attr.n.u1DescType)
2294 break;
2295 if (pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF)
2296 {
2297 /* For conforming segments, CS.DPL must be <= SS.DPL. */
2298 if (pSel->Attr.n.u2Dpl > uStackDpl)
2299 break;
2300 }
2301 else
2302 {
2303 /* For non-conforming segments, CS.DPL must equal SS.DPL. */
2304 if (pSel->Attr.n.u2Dpl != uStackDpl)
2305 break;
2306 }
2307 /* Segment must be present. */
2308 if (!pSel->Attr.n.u1Present)
2309 break;
2310 /* G bit must be set if any high limit bits are set. */
2311 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2312 break;
2313 /* G bit must be clear if any low limit bits are clear. */
2314 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2315 break;
2316
2317 rc = true;
2318 } while (0);
2319 return rc;
2320}
2321
2322
2323/**
2324 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2325 * execution within VMX when unrestricted execution isn't
2326 * available.
2327 *
2328 * @returns true if selector is suitable for VMX, otherwise
2329 * false.
2330 * @param pSel Pointer to the selector to check
2331 * (DS/ES/FS/GS).
2332 */
2333static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2334{
2335 bool rc = false;
2336
2337 /* If attributes are all zero, consider the segment unusable and therefore OK.
2338 * This logic must be in sync with HMVMXR0.cpp!
2339 */
2340 if (!pSel->Attr.u)
2341 return true;
2342
2343 do
2344 {
2345 /* Segment must be accessed. */
2346 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2347 break;
2348 /* Code segments must also be readable. */
2349 if (pSel->Attr.u & X86_SEL_TYPE_CODE && !(pSel->Attr.u & X86_SEL_TYPE_READ))
2350 break;
2351 /* The S bit must be set. */
2352 if (!pSel->Attr.n.u1DescType)
2353 break;
2354 /* Except for conforming segments, DPL >= RPL. */
2355 if (pSel->Attr.n.u4Type <= X86_SEL_TYPE_ER_ACC && pSel->Attr.n.u2Dpl < (pSel->Sel & X86_SEL_RPL))
2356 break;
2357 /* Segment must be present. */
2358 if (!pSel->Attr.n.u1Present)
2359 break;
2360 /* G bit must be set if any high limit bits are set. */
2361 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2362 break;
2363 /* G bit must be clear if any low limit bits are clear. */
2364 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2365 break;
2366
2367 rc = true;
2368 } while (0);
2369 return rc;
2370}
2371
2372
2373/**
2374 * Checks if the stack selector (SS) is suitable for execution
2375 * within VMX when unrestricted execution isn't available.
2376 *
2377 * @returns true if selector is suitable for VMX, otherwise
2378 * false.
2379 * @param pSel Pointer to the selector to check (SS).
2380 */
2381static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2382{
2383 bool rc = false;
2384
2385 /* If attributes are all zero, consider the segment unusable and therefore OK.
2386 * This logic must be in sync with HMVMXR0.cpp!
2387 */
2388 if (!pSel->Attr.u)
2389 return true;
2390
2391 do
2392 {
2393 /* Segment must be accessed. */
2394 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2395 break;
2396 /* Segment must be writable. */
2397 if (!(pSel->Attr.u & X86_SEL_TYPE_WRITE))
2398 break;
2399 /* Segment must not be a code segment. */
2400 if (pSel->Attr.u & X86_SEL_TYPE_CODE)
2401 break;
2402 /* The S bit must be set. */
2403 if (!pSel->Attr.n.u1DescType)
2404 break;
2405 /* DPL must equal RPL. */
2406 if (pSel->Attr.n.u2Dpl != (pSel->Sel & X86_SEL_RPL))
2407 break;
2408 /* Segment must be present. */
2409 if (!pSel->Attr.n.u1Present)
2410 break;
2411 /* G bit must be set if any high limit bits are set. */
2412 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2413 break;
2414 /* G bit must be clear if any low limit bits are clear. */
2415 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2416 break;
2417
2418 rc = true;
2419 } while (0);
2420 return rc;
2421}
2422
2423
2424/**
2425 * Force execution of the current IO code in the recompiler.
2426 *
2427 * @returns VBox status code.
2428 * @param pVM Pointer to the VM.
2429 * @param pCtx Partial VM execution context.
2430 */
2431VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2432{
2433 PVMCPU pVCpu = VMMGetCpu(pVM);
2434
2435 Assert(HMIsEnabled(pVM));
2436 Log(("HMR3EmulateIoBlock\n"));
2437
2438 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2439 if (HMCanEmulateIoBlockEx(pCtx))
2440 {
2441 Log(("HMR3EmulateIoBlock -> enabled\n"));
2442 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2443 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2444 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2445 return VINF_EM_RESCHEDULE_REM;
2446 }
2447 return VINF_SUCCESS;
2448}
2449
2450
2451/**
2452 * Checks if we can currently use hardware accelerated raw mode.
2453 *
2454 * @returns true if we can currently use hardware acceleration, otherwise false.
2455 * @param pVM Pointer to the VM.
2456 * @param pCtx Partial VM execution context.
2457 */
2458VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2459{
2460 PVMCPU pVCpu = VMMGetCpu(pVM);
2461
2462 Assert(HMIsEnabled(pVM));
2463
2464 /* If we're still executing the IO code, then return false. */
2465 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2466 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2467 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2468 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2469 return false;
2470
2471 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2472
2473 /* AMD-V supports real & protected mode with or without paging. */
2474 if (pVM->hm.s.svm.fEnabled)
2475 {
2476 pVCpu->hm.s.fActive = true;
2477 return true;
2478 }
2479
2480 pVCpu->hm.s.fActive = false;
2481
2482 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2483 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2484 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2485
2486 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2487 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2488 {
2489 /*
2490 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2491 * guest execution feature i missing (VT-x only).
2492 */
2493 if (fSupportsRealMode)
2494 {
2495 if (CPUMIsGuestInRealModeEx(pCtx))
2496 {
2497 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2498 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2499 * If this is not true, we cannot execute real mode as V86 and have to fall
2500 * back to emulation.
2501 */
2502 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2503 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2504 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2505 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2506 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2507 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2508 {
2509 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2510 return false;
2511 }
2512 if ( (pCtx->cs.u32Limit != 0xffff)
2513 || (pCtx->ds.u32Limit != 0xffff)
2514 || (pCtx->es.u32Limit != 0xffff)
2515 || (pCtx->ss.u32Limit != 0xffff)
2516 || (pCtx->fs.u32Limit != 0xffff)
2517 || (pCtx->gs.u32Limit != 0xffff))
2518 {
2519 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2520 return false;
2521 }
2522 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2523 }
2524 else
2525 {
2526 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2527 /* Verify the requirements for executing code in protected
2528 mode. VT-x can't handle the CPU state right after a switch
2529 from real to protected mode. (all sorts of RPL & DPL assumptions) */
2530#if VBOX_WITH_OLD_VTX_CODE
2531 if ( pVCpu->hm.s.vmx.enmLastSeenGuestMode == PGMMODE_REAL
2532 && enmGuestMode >= PGMMODE_PROTECTED)
2533#else
2534 if (pVCpu->hm.s.vmx.fWasInRealMode)
2535#endif
2536 {
2537 //@todo: If guest is in V86 mode, these checks should be different!
2538#if VBOX_WITH_OLD_VTX_CODE
2539 if ( (pCtx->cs.Sel & X86_SEL_RPL)
2540 || (pCtx->ds.Sel & X86_SEL_RPL)
2541 || (pCtx->es.Sel & X86_SEL_RPL)
2542 || (pCtx->fs.Sel & X86_SEL_RPL)
2543 || (pCtx->gs.Sel & X86_SEL_RPL)
2544 || (pCtx->ss.Sel & X86_SEL_RPL))
2545 {
2546 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2547 return false;
2548 }
2549#else
2550 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2551 {
2552 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2553 return false;
2554 }
2555 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2556 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2557 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2558 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2559 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2560 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2561 {
2562 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2563 return false;
2564 }
2565#endif
2566 }
2567 /* VT-x also chokes on invalid tr or ldtr selectors (minix) */
2568 if (pCtx->gdtr.cbGdt)
2569 {
2570 if (pCtx->tr.Sel > pCtx->gdtr.cbGdt)
2571 {
2572 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2573 return false;
2574 }
2575 else if (pCtx->ldtr.Sel > pCtx->gdtr.cbGdt)
2576 {
2577 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2578 return false;
2579 }
2580 }
2581 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2582 }
2583 }
2584 else
2585 {
2586 if ( !CPUMIsGuestInLongModeEx(pCtx)
2587 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2588 {
2589 /** @todo This should (probably) be set on every excursion to the REM,
2590 * however it's too risky right now. So, only apply it when we go
2591 * back to REM for real mode execution. (The XP hack below doesn't
2592 * work reliably without this.)
2593 * Update: Implemented in EM.cpp, see #ifdef EM_NOTIFY_HM. */
2594 for (uint32_t i = 0; i < pVM->cCpus; i++)
2595 pVM->aCpus[i].hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2596
2597 if ( !pVM->hm.s.fNestedPaging /* requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2598 || CPUMIsGuestInRealModeEx(pCtx)) /* requires a fake TSS for real mode - stored in the VMM device heap */
2599 return false;
2600
2601 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2602 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2603 return false;
2604
2605 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2606 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2607 * hidden registers (possible recompiler bug; see load_seg_vm) */
2608 if (pCtx->cs.Attr.n.u1Present == 0)
2609 return false;
2610 if (pCtx->ss.Attr.n.u1Present == 0)
2611 return false;
2612
2613 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2614 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2615 /** @todo This check is actually wrong, it doesn't take the direction of the
2616 * stack segment into account. But, it does the job for now. */
2617 if (pCtx->rsp >= pCtx->ss.u32Limit)
2618 return false;
2619#if 0
2620 if ( pCtx->cs.Sel >= pCtx->gdtr.cbGdt
2621 || pCtx->ss.Sel >= pCtx->gdtr.cbGdt
2622 || pCtx->ds.Sel >= pCtx->gdtr.cbGdt
2623 || pCtx->es.Sel >= pCtx->gdtr.cbGdt
2624 || pCtx->fs.Sel >= pCtx->gdtr.cbGdt
2625 || pCtx->gs.Sel >= pCtx->gdtr.cbGdt)
2626 return false;
2627#endif
2628 }
2629 }
2630 }
2631
2632 if (pVM->hm.s.vmx.fEnabled)
2633 {
2634 uint32_t mask;
2635
2636 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2637 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr0_fixed0;
2638 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2639 mask &= ~X86_CR0_NE;
2640
2641 if (fSupportsRealMode)
2642 {
2643 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2644 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2645 }
2646 else
2647 {
2648 /* We support protected mode without paging using identity mapping. */
2649 mask &= ~X86_CR0_PG;
2650 }
2651 if ((pCtx->cr0 & mask) != mask)
2652 return false;
2653
2654 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2655 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr0_fixed1;
2656 if ((pCtx->cr0 & mask) != 0)
2657 return false;
2658
2659 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2660 mask = (uint32_t)pVM->hm.s.vmx.msr.vmx_cr4_fixed0;
2661 mask &= ~X86_CR4_VMXE;
2662 if ((pCtx->cr4 & mask) != mask)
2663 return false;
2664
2665 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2666 mask = (uint32_t)~pVM->hm.s.vmx.msr.vmx_cr4_fixed1;
2667 if ((pCtx->cr4 & mask) != 0)
2668 return false;
2669
2670 pVCpu->hm.s.fActive = true;
2671 return true;
2672 }
2673
2674 return false;
2675}
2676
2677
2678/**
2679 * Checks if we need to reschedule due to VMM device heap changes.
2680 *
2681 * @returns true if a reschedule is required, otherwise false.
2682 * @param pVM Pointer to the VM.
2683 * @param pCtx VM execution context.
2684 */
2685VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2686{
2687 /*
2688 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2689 * when the unrestricted guest execution feature is missing (VT-x only).
2690 */
2691#ifdef VBOX_WITH_OLD_VTX_CODE
2692 if ( pVM->hm.s.vmx.fEnabled
2693 && !pVM->hm.s.vmx.fUnrestrictedGuest
2694 && !CPUMIsGuestInPagedProtectedModeEx(pCtx)
2695 && !PDMVmmDevHeapIsEnabled(pVM)
2696 && (pVM->hm.s.fNestedPaging || CPUMIsGuestInRealModeEx(pCtx)))
2697 return true;
2698#else
2699 if ( pVM->hm.s.vmx.fEnabled
2700 && !pVM->hm.s.vmx.fUnrestrictedGuest
2701 && CPUMIsGuestInRealModeEx(pCtx)
2702 && !PDMVmmDevHeapIsEnabled(pVM))
2703 return true;
2704#endif
2705
2706 return false;
2707}
2708
2709
2710/**
2711 * Notification from EM about a rescheduling into hardware assisted execution
2712 * mode.
2713 *
2714 * @param pVCpu Pointer to the current VMCPU.
2715 */
2716VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2717{
2718 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2719}
2720
2721
2722/**
2723 * Notification from EM about returning from instruction emulation (REM / EM).
2724 *
2725 * @param pVCpu Pointer to the VMCPU.
2726 */
2727VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2728{
2729 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2730}
2731
2732
2733/**
2734 * Checks if we are currently using hardware accelerated raw mode.
2735 *
2736 * @returns true if hardware acceleration is being used, otherwise false.
2737 * @param pVCpu Pointer to the VMCPU.
2738 */
2739VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2740{
2741 return pVCpu->hm.s.fActive;
2742}
2743
2744
2745/**
2746 * External interface for querying whether hardware accelerated raw mode is
2747 * enabled.
2748 *
2749 * @returns true if nested paging is being used, otherwise false.
2750 * @param pUVM The user mode VM handle.
2751 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2752 */
2753VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2754{
2755 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2756 PVM pVM = pUVM->pVM;
2757 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2758 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2759}
2760
2761
2762/**
2763 * Checks if we are currently using nested paging.
2764 *
2765 * @returns true if nested paging is being used, otherwise false.
2766 * @param pUVM The user mode VM handle.
2767 */
2768VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2769{
2770 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2771 PVM pVM = pUVM->pVM;
2772 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2773 return pVM->hm.s.fNestedPaging;
2774}
2775
2776
2777/**
2778 * Checks if we are currently using VPID in VT-x mode.
2779 *
2780 * @returns true if VPID is being used, otherwise false.
2781 * @param pUVM The user mode VM handle.
2782 */
2783VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2784{
2785 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2786 PVM pVM = pUVM->pVM;
2787 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2788 return pVM->hm.s.vmx.fVpid;
2789}
2790
2791
2792/**
2793 * Checks if we are currently using VT-x unrestricted execution,
2794 * aka UX.
2795 *
2796 * @returns true if UX is being used, otherwise false.
2797 * @param pUVM The user mode VM handle.
2798 */
2799VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2800{
2801 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2802 PVM pVM = pUVM->pVM;
2803 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2804 return pVM->hm.s.vmx.fUnrestrictedGuest;
2805}
2806
2807
2808/**
2809 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2810 *
2811 * @returns true if an internal event is pending, otherwise false.
2812 * @param pVM Pointer to the VM.
2813 */
2814VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2815{
2816 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2817}
2818
2819
2820/**
2821 * Checks if the VMX-preemption timer is being used.
2822 *
2823 * @returns true if the VMX-preemption timer is being used, otherwise false.
2824 * @param pVM Pointer to the VM.
2825 */
2826VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2827{
2828 return HMIsEnabled(pVM)
2829 && pVM->hm.s.vmx.fEnabled
2830 && pVM->hm.s.vmx.fUsePreemptTimer;
2831}
2832
2833
2834/**
2835 * Restart an I/O instruction that was refused in ring-0
2836 *
2837 * @returns Strict VBox status code. Informational status codes other than the one documented
2838 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2839 * @retval VINF_SUCCESS Success.
2840 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2841 * status code must be passed on to EM.
2842 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2843 *
2844 * @param pVM Pointer to the VM.
2845 * @param pVCpu Pointer to the VMCPU.
2846 * @param pCtx Pointer to the guest CPU context.
2847 */
2848VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2849{
2850 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2851
2852 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2853
2854 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2855 || enmType == HMPENDINGIO_INVALID)
2856 return VERR_NOT_FOUND;
2857
2858 VBOXSTRICTRC rcStrict;
2859 switch (enmType)
2860 {
2861 case HMPENDINGIO_PORT_READ:
2862 {
2863 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2864 uint32_t u32Val = 0;
2865
2866 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2867 &u32Val,
2868 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2869 if (IOM_SUCCESS(rcStrict))
2870 {
2871 /* Write back to the EAX register. */
2872 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2873 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2874 }
2875 break;
2876 }
2877
2878 case HMPENDINGIO_PORT_WRITE:
2879 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2880 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2881 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2882 if (IOM_SUCCESS(rcStrict))
2883 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2884 break;
2885
2886 default:
2887 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2888 }
2889
2890 return rcStrict;
2891}
2892
2893
2894/**
2895 * Check fatal VT-x/AMD-V error and produce some meaningful
2896 * log release message.
2897 *
2898 * @param pVM Pointer to the VM.
2899 * @param iStatusCode VBox status code.
2900 */
2901VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2902{
2903 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2904 {
2905 switch (iStatusCode)
2906 {
2907 case VERR_VMX_INVALID_VMCS_FIELD:
2908 break;
2909
2910 case VERR_VMX_INVALID_VMCS_PTR:
2911 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2912 LogRel(("HM: CPU%d Current pointer %RGp vs %RGp\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u64VMCSPhys, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
2913 LogRel(("HM: CPU%d Current VMCS version %x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32VMCSRevision));
2914 LogRel(("HM: CPU%d Entered Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idEnteredCpu));
2915 LogRel(("HM: CPU%d Current Cpu %d\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.idCurrentCpu));
2916 break;
2917
2918 case VERR_VMX_UNABLE_TO_START_VM:
2919 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2920 LogRel(("HM: CPU%d instruction error %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError));
2921 LogRel(("HM: CPU%d exit reason %#x\n", i, pVM->aCpus[i].hm.s.vmx.lasterror.u32ExitReason));
2922 if (pVM->aCpus[i].hm.s.vmx.lasterror.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2923 {
2924 LogRel(("HM: Cpu%d PinCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32PinCtls));
2925 LogRel(("HM: Cpu%d ProcCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls));
2926 LogRel(("HM: Cpu%d ProcCtls2 %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ProcCtls2));
2927 LogRel(("HM: Cpu%d EntryCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32EntryCtls));
2928 LogRel(("HM: Cpu%d ExitCtls %#RX32\n", i, pVM->aCpus[i].hm.s.vmx.u32ExitCtls));
2929 LogRel(("HM: Cpu%d MSRBitmapPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
2930#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2931 LogRel(("HM: Cpu%d GuestMSRPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysGuestMsr));
2932 LogRel(("HM: Cpu%d HostMsrPhys %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysHostMsr));
2933 LogRel(("HM: Cpu%d cGuestMSRs %u\n", i, pVM->aCpus[i].hm.s.vmx.cGuestMsrs));
2934#endif
2935 }
2936 /** @todo Log VM-entry event injection control fields
2937 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2938 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2939 break;
2940
2941 case VERR_VMX_INVALID_VMXON_PTR:
2942 break;
2943 }
2944 }
2945
2946 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2947 {
2948 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.allowed1));
2949 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %x\n", pVM->hm.s.vmx.msr.vmx_entry.n.disallowed0));
2950 }
2951}
2952
2953
2954/**
2955 * Execute state save operation.
2956 *
2957 * @returns VBox status code.
2958 * @param pVM Pointer to the VM.
2959 * @param pSSM SSM operation handle.
2960 */
2961static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2962{
2963 int rc;
2964
2965 Log(("hmR3Save:\n"));
2966
2967 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2968 {
2969 /*
2970 * Save the basic bits - fortunately all the other things can be resynced on load.
2971 */
2972 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2973 AssertRCReturn(rc, rc);
2974 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2975 AssertRCReturn(rc, rc);
2976 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2977 AssertRCReturn(rc, rc);
2978
2979#ifdef VBOX_WITH_OLD_VTX_CODE
2980 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode);
2981 AssertRCReturn(rc, rc);
2982 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode);
2983 AssertRCReturn(rc, rc);
2984 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode);
2985 AssertRCReturn(rc, rc);
2986#else
2987 //@todo: We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
2988 // perhaps not even that (the initial value of 'true' is safe).
2989 uint32_t u32Dummy = PGMMODE_REAL;
2990 rc = SSMR3PutU32(pSSM, u32Dummy);
2991 AssertRCReturn(rc, rc);
2992 rc = SSMR3PutU32(pSSM, u32Dummy);
2993 AssertRCReturn(rc, rc);
2994 rc = SSMR3PutU32(pSSM, u32Dummy);
2995 AssertRCReturn(rc, rc);
2996#endif
2997 }
2998#ifdef VBOX_HM_WITH_GUEST_PATCHING
2999 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3000 AssertRCReturn(rc, rc);
3001 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3002 AssertRCReturn(rc, rc);
3003 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3004 AssertRCReturn(rc, rc);
3005
3006 /* Store all the guest patch records too. */
3007 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3008 AssertRCReturn(rc, rc);
3009
3010 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3011 {
3012 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3013
3014 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3015 AssertRCReturn(rc, rc);
3016
3017 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3018 AssertRCReturn(rc, rc);
3019
3020 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3021 AssertRCReturn(rc, rc);
3022
3023 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3024 AssertRCReturn(rc, rc);
3025
3026 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3027 AssertRCReturn(rc, rc);
3028
3029 AssertCompileSize(HMTPRINSTR, 4);
3030 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3031 AssertRCReturn(rc, rc);
3032
3033 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3034 AssertRCReturn(rc, rc);
3035
3036 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3037 AssertRCReturn(rc, rc);
3038
3039 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3040 AssertRCReturn(rc, rc);
3041
3042 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3043 AssertRCReturn(rc, rc);
3044 }
3045#endif
3046 return VINF_SUCCESS;
3047}
3048
3049
3050/**
3051 * Execute state load operation.
3052 *
3053 * @returns VBox status code.
3054 * @param pVM Pointer to the VM.
3055 * @param pSSM SSM operation handle.
3056 * @param uVersion Data layout version.
3057 * @param uPass The data pass.
3058 */
3059static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3060{
3061 int rc;
3062
3063 Log(("hmR3Load:\n"));
3064 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3065
3066 /*
3067 * Validate version.
3068 */
3069 if ( uVersion != HM_SSM_VERSION
3070 && uVersion != HM_SSM_VERSION_NO_PATCHING
3071 && uVersion != HM_SSM_VERSION_2_0_X)
3072 {
3073 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3074 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3075 }
3076 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3077 {
3078 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3079 AssertRCReturn(rc, rc);
3080 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3081 AssertRCReturn(rc, rc);
3082 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
3083 AssertRCReturn(rc, rc);
3084
3085 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
3086 {
3087 uint32_t val;
3088
3089#ifdef VBOX_WITH_OLD_VTX_CODE
3090 rc = SSMR3GetU32(pSSM, &val);
3091 AssertRCReturn(rc, rc);
3092 pVM->aCpus[i].hm.s.vmx.enmLastSeenGuestMode = (PGMMODE)val;
3093
3094 rc = SSMR3GetU32(pSSM, &val);
3095 AssertRCReturn(rc, rc);
3096 pVM->aCpus[i].hm.s.vmx.enmCurrGuestMode = (PGMMODE)val;
3097
3098 rc = SSMR3GetU32(pSSM, &val);
3099 AssertRCReturn(rc, rc);
3100 pVM->aCpus[i].hm.s.vmx.enmPrevGuestMode = (PGMMODE)val;
3101#else
3102 //@todo: See note above re saving enmLastSeenGuestMode
3103 rc = SSMR3GetU32(pSSM, &val);
3104 AssertRCReturn(rc, rc);
3105 rc = SSMR3GetU32(pSSM, &val);
3106 AssertRCReturn(rc, rc);
3107 rc = SSMR3GetU32(pSSM, &val);
3108 AssertRCReturn(rc, rc);
3109#endif
3110 }
3111 }
3112#ifdef VBOX_HM_WITH_GUEST_PATCHING
3113 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
3114 {
3115 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3116 AssertRCReturn(rc, rc);
3117 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3118 AssertRCReturn(rc, rc);
3119 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3120 AssertRCReturn(rc, rc);
3121
3122 /* Fetch all TPR patch records. */
3123 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3124 AssertRCReturn(rc, rc);
3125
3126 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3127 {
3128 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3129
3130 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3131 AssertRCReturn(rc, rc);
3132
3133 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3134 AssertRCReturn(rc, rc);
3135
3136 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3137 AssertRCReturn(rc, rc);
3138
3139 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3140 AssertRCReturn(rc, rc);
3141
3142 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3143 AssertRCReturn(rc, rc);
3144
3145 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3146 AssertRCReturn(rc, rc);
3147
3148 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3149 pVM->hm.s.fTPRPatchingActive = true;
3150
3151 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3152
3153 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3154 AssertRCReturn(rc, rc);
3155
3156 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3157 AssertRCReturn(rc, rc);
3158
3159 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3160 AssertRCReturn(rc, rc);
3161
3162 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3163 AssertRCReturn(rc, rc);
3164
3165 Log(("hmR3Load: patch %d\n", i));
3166 Log(("Key = %x\n", pPatch->Core.Key));
3167 Log(("cbOp = %d\n", pPatch->cbOp));
3168 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3169 Log(("type = %d\n", pPatch->enmType));
3170 Log(("srcop = %d\n", pPatch->uSrcOperand));
3171 Log(("dstop = %d\n", pPatch->uDstOperand));
3172 Log(("cFaults = %d\n", pPatch->cFaults));
3173 Log(("target = %x\n", pPatch->pJumpTarget));
3174 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3175 AssertRC(rc);
3176 }
3177 }
3178#endif
3179
3180 return VINF_SUCCESS;
3181}
3182
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