VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 48212

Last change on this file since 48212 was 48212, checked in by vboxsync, 12 years ago

VMM/HM: Naming fixes.
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1/* $Id: HM.cpp 48212 2013-08-30 23:02:22Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/ssm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/csam.h>
34#include <VBox/vmm/selm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/uvm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/asm-amd64-x86.h>
50#include <iprt/string.h>
51#include <iprt/env.h>
52#include <iprt/thread.h>
53
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58#ifdef VBOX_WITH_STATISTICS
59# define EXIT_REASON(def, val, str) #def " - " #val " - " str
60# define EXIT_REASON_NIL() NULL
61/** Exit reason descriptions for VT-x, used to describe statistics. */
62static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
63{
64 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
65 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
66 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
67 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
68 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
69 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
70 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
71 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
74 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest attempted to execute CPUID."),
75 EXIT_REASON_NIL(),
76 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest attempted to execute HLT."),
77 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest attempted to execute INVD."),
78 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest attempted to execute INVLPG."),
79 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest attempted to execute RDPMC."),
80 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest attempted to execute RDTSC."),
81 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest attempted to execute RSM in SMM."),
82 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest attempted to execute VMCALL."),
83 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest attempted to execute VMCLEAR."),
84 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest attempted to execute VMLAUNCH."),
85 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest attempted to execute VMPTRLD."),
86 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest attempted to execute VMPTRST."),
87 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest attempted to execute VMREAD."),
88 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest attempted to execute VMRESUME."),
89 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest attempted to execute VMWRITE."),
90 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest attempted to execute VMXOFF."),
91 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest attempted to execute VMXON."),
92 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
93 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
94 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
95 EXIT_REASON(VMX_EXIT_RDMSR , 31, "Guest attempted to execute RDMSR."),
96 EXIT_REASON(VMX_EXIT_WRMSR , 32, "Guest attempted to execute WRMSR."),
97 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
98 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest executed MWAIT."),
101 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest attempted to execute MONITOR."),
104 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest attempted to execute PAUSE."),
105 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest attempted to execute MOV to CR8."),
108 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest attempted to access memory at a physical address on the APIC-access page."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest attempted to execute LGDT, LIDT, SGDT, or SIDT."),
111 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest attempted to execute LLDT, LTR, SLDT, or STR."),
112 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
113 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
114 EXIT_REASON(VMX_EXIT_INVEPT , 50, "Guest attempted to execute INVEPT."),
115 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest attempted to execute RDTSCP."),
116 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
117 EXIT_REASON(VMX_EXIT_INVVPID , 53, "Guest attempted to execute INVVPID."),
118 EXIT_REASON(VMX_EXIT_WBINVD , 54, "Guest attempted to execute WBINVD."),
119 EXIT_REASON(VMX_EXIT_XSETBV , 55, "Guest attempted to execute XSETBV."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_RDRAND , 57, "Guest attempted to execute RDRAND."),
122 EXIT_REASON(VMX_EXIT_INVPCID , 58, "Guest attempted to execute INVPCID."),
123 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "Guest attempted to execute VMFUNC.")
124};
125/** Exit reason descriptions for AMD-V, used to describe statistics. */
126static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
231 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
232 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
252 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
270 EXIT_REASON_NIL()
271};
272# undef EXIT_REASON
273# undef EXIT_REASON_NIL
274#endif /* VBOX_WITH_STATISTICS */
275
276#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
277 do { \
278 if ((allowed1) & (featflag)) \
279 LogRel(("HM: " #featflag "\n")); \
280 else \
281 LogRel(("HM: " #featflag " *must* be cleared\n")); \
282 if ((disallowed0) & (featflag)) \
283 LogRel(("HM: " #featflag " *must* be set\n")); \
284 } while (0)
285
286#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, featflag) \
287 do { \
288 if ((allowed1) & (featflag)) \
289 LogRel(("HM: " #featflag "\n")); \
290 else \
291 LogRel(("HM: " #featflag " not supported\n")); \
292 } while (0)
293
294#define HMVMX_REPORT_CAPABILITY(msrcaps, cap) \
295 do { \
296 if ((msrcaps) & (cap)) \
297 LogRel(("HM: " #cap "\n")); \
298 } while (0)
299
300
301/*******************************************************************************
302* Internal Functions *
303*******************************************************************************/
304static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
305static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
306static int hmR3InitCPU(PVM pVM);
307static int hmR3InitFinalizeR0(PVM pVM);
308static int hmR3InitFinalizeR0Intel(PVM pVM);
309static int hmR3InitFinalizeR0Amd(PVM pVM);
310static int hmR3TermCPU(PVM pVM);
311
312
313
314/**
315 * Initializes the HM.
316 *
317 * This reads the config and check whether VT-x or AMD-V hardware is available
318 * if configured to use it. This is one of the very first components to be
319 * initialized after CFGM, so that we can fall back to raw-mode early in the
320 * initialization process.
321 *
322 * Note that a lot of the set up work is done in ring-0 and thus postponed till
323 * the ring-3 and ring-0 callback to HMR3InitCompleted.
324 *
325 * @returns VBox status code.
326 * @param pVM Pointer to the VM.
327 *
328 * @remarks Be careful with what we call here, since most of the VMM components
329 * are uninitialized.
330 */
331VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
332{
333 LogFlow(("HMR3Init\n"));
334
335 /*
336 * Assert alignment and sizes.
337 */
338 AssertCompileMemberAlignment(VM, hm.s, 32);
339 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
340
341 /*
342 * Register the saved state data unit.
343 */
344 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
345 NULL, NULL, NULL,
346 NULL, hmR3Save, NULL,
347 NULL, hmR3Load, NULL);
348 if (RT_FAILURE(rc))
349 return rc;
350
351 /*
352 * Misc initialisation.
353 */
354 //pVM->hm.s.vmx.fSupported = false;
355 //pVM->hm.s.svm.fSupported = false;
356 //pVM->hm.s.vmx.fEnabled = false;
357 //pVM->hm.s.svm.fEnabled = false;
358 //pVM->hm.s.fNestedPaging = false;
359
360
361 /*
362 * Read configuration.
363 */
364 PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
365
366 /** @cfgm{/HM/HMForced, bool, false}
367 * Forces hardware virtualization, no falling back on raw-mode. HM must be
368 * enabled, i.e. /HMEnabled must be true. */
369 bool fHMForced;
370#ifdef VBOX_WITH_RAW_MODE
371 rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
372 AssertRCReturn(rc, rc);
373 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
374 VERR_INVALID_PARAMETER);
375# if defined(RT_OS_DARWIN)
376 if (pVM->fHMEnabled)
377 fHMForced = true;
378# endif
379 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
380 VERR_INVALID_PARAMETER);
381 if (pVM->cCpus > 1)
382 fHMForced = true;
383#else /* !VBOX_WITH_RAW_MODE */
384 AssertRelease(pVM->fHMEnabled);
385 fHMForced = true;
386#endif /* !VBOX_WITH_RAW_MODE */
387
388 /** @cfgm{/HM/EnableNestedPaging, bool, false}
389 * Enables nested paging (aka extended page tables). */
390 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
391 AssertRCReturn(rc, rc);
392
393 /** @cfgm{/HM/EnableUX, bool, true}
394 * Enables the VT-x unrestricted execution feature. */
395 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
396 AssertRCReturn(rc, rc);
397
398 /** @cfgm{/HM/EnableLargePages, bool, false}
399 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
400 * page table walking and maybe better TLB hit rate in some cases. */
401 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
402 AssertRCReturn(rc, rc);
403
404 /** @cfgm{/HM/EnableVPID, bool, false}
405 * Enables the VT-x VPID feature. */
406 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
407 AssertRCReturn(rc, rc);
408
409 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
410 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
411 rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
412 AssertRCReturn(rc, rc);
413
414 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
415 * Enables AMD64 cpu features.
416 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
417 * already have the support. */
418#ifdef VBOX_ENABLE_64_BITS_GUESTS
419 rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
420 AssertLogRelRCReturn(rc, rc);
421#else
422 pVM->hm.s.fAllow64BitGuests = false;
423#endif
424
425 /** @cfgm{/HM/Exclusive, bool}
426 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
427 * global init for each host CPU. If false, we do local init each time we wish
428 * to execute guest code.
429 *
430 * Default is false for Mac OS X and Windows due to the higher risk of conflicts
431 * with other hypervisors.
432 */
433 rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
434#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
435 false
436#else
437 true
438#endif
439 );
440 AssertLogRelRCReturn(rc, rc);
441
442 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
443 * The number of times to resume guest execution before we forcibly return to
444 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445 * determines the default value. */
446 rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
447 AssertLogRelRCReturn(rc, rc);
448
449 /*
450 * Check if VT-x or AMD-v support according to the users wishes.
451 */
452 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
453 * VERR_SVM_IN_USE. */
454 if (pVM->fHMEnabled)
455 {
456 uint32_t fCaps;
457 rc = SUPR3QueryVTCaps(&fCaps);
458 if (RT_SUCCESS(rc))
459 {
460 if (fCaps & SUPVTCAPS_AMD_V)
461 LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
462 else if (fCaps & SUPVTCAPS_VT_X)
463 {
464 rc = SUPR3QueryVTxSupported();
465 if (RT_SUCCESS(rc))
466 LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
467 else
468 {
469#ifdef RT_OS_LINUX
470 const char *pszMinReq = " Linux 2.6.13 or newer required!";
471#else
472 const char *pszMinReq = "";
473#endif
474 if (fHMForced)
475 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
476
477 /* Fall back to raw-mode. */
478 LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
479 pVM->fHMEnabled = false;
480 }
481 }
482 else
483 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
484 VERR_INTERNAL_ERROR_5);
485
486 /*
487 * Do we require a little bit or raw-mode for 64-bit guest execution?
488 */
489 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
490 && pVM->fHMEnabled
491 && pVM->hm.s.fAllow64BitGuests;
492 }
493 else
494 {
495 const char *pszMsg;
496 switch (rc)
497 {
498 case VERR_UNSUPPORTED_CPU:
499 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
500 break;
501
502 case VERR_VMX_NO_VMX:
503 pszMsg = "VT-x is not available.";
504 break;
505
506 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
507 pszMsg = "VT-x is disabled in the BIOS (or by the host OS).";
508 break;
509
510 case VERR_SVM_NO_SVM:
511 pszMsg = "AMD-V is not available.";
512 break;
513
514 case VERR_SVM_DISABLED:
515 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
516 break;
517
518 default:
519 pszMsg = NULL;
520 break;
521 }
522 if (fHMForced && pszMsg)
523 return VM_SET_ERROR(pVM, rc, pszMsg);
524 if (!pszMsg)
525 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
526
527 /* Fall back to raw-mode. */
528 LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
529 pVM->fHMEnabled = false;
530 }
531 }
532
533 /* It's now OK to use the predicate function. */
534 pVM->fHMEnabledFixed = true;
535 return VINF_SUCCESS;
536}
537
538
539/**
540 * Initializes the per-VCPU HM.
541 *
542 * @returns VBox status code.
543 * @param pVM Pointer to the VM.
544 */
545static int hmR3InitCPU(PVM pVM)
546{
547 LogFlow(("HMR3InitCPU\n"));
548
549 if (!HMIsEnabled(pVM))
550 return VINF_SUCCESS;
551
552 for (VMCPUID i = 0; i < pVM->cCpus; i++)
553 {
554 PVMCPU pVCpu = &pVM->aCpus[i];
555 pVCpu->hm.s.fActive = false;
556 }
557
558#ifdef VBOX_WITH_STATISTICS
559 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
560 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
561 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
562 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
563#endif
564
565 /*
566 * Statistics.
567 */
568 for (VMCPUID i = 0; i < pVM->cCpus; i++)
569 {
570 PVMCPU pVCpu = &pVM->aCpus[i];
571 int rc;
572
573#ifdef VBOX_WITH_STATISTICS
574 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
575 "Profiling of RTMpPokeCpu",
576 "/PROF/CPU%d/HM/Poke", i);
577 AssertRC(rc);
578 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
579 "Profiling of poke wait",
580 "/PROF/CPU%d/HM/PokeWait", i);
581 AssertRC(rc);
582 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
583 "Profiling of poke wait when RTMpPokeCpu fails",
584 "/PROF/CPU%d/HM/PokeWaitFailed", i);
585 AssertRC(rc);
586 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
587 "Profiling of VMXR0RunGuestCode entry",
588 "/PROF/CPU%d/HM/StatEntry", i);
589 AssertRC(rc);
590 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
591 "Profiling of VMXR0RunGuestCode exit part 1",
592 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
593 AssertRC(rc);
594 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
595 "Profiling of VMXR0RunGuestCode exit part 2",
596 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
597 AssertRC(rc);
598
599 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
600 "I/O",
601 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
602 AssertRC(rc);
603 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
604 "MOV CRx",
605 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
606 AssertRC(rc);
607 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
608 "Exceptions, NMIs",
609 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
610 AssertRC(rc);
611
612 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
613 "Profiling of VMXR0LoadGuestState",
614 "/PROF/CPU%d/HM/StatLoadGuestState", i);
615 AssertRC(rc);
616 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
617 "Profiling of VMLAUNCH/VMRESUME.",
618 "/PROF/CPU%d/HM/InGC", i);
619 AssertRC(rc);
620
621# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
622 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
623 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
624 "/PROF/CPU%d/HM/Switcher3264", i);
625 AssertRC(rc);
626# endif
627
628# ifdef HM_PROFILE_EXIT_DISPATCH
629 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
630 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
631 "/PROF/CPU%d/HM/ExitDispatch", i);
632 AssertRC(rc);
633# endif
634
635#endif
636# define HM_REG_COUNTER(a, b, desc) \
637 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
638 AssertRC(rc);
639
640#ifdef VBOX_WITH_STATISTICS
641 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
642 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
643 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
644 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
645 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
646 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
647 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
648 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
649 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) execption.");
650 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
651 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
652 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
653 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
654 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
655 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
656 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
657 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
658 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
659 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
660 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
661 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
662 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
663 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
664 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
665 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
666 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
667 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
668 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
669 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
670 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
671 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
672 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
673 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
674 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
675 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
676 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
677 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
678 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
679 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
680 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
681 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
682 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
683 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
684 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
685 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
686 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
687 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
688#endif
689 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmi, "/HM/CPU%d/Exit/HostNmi", "Host NMI received.");
690#ifdef VBOX_WITH_STATISTICS
691 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
692 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
693 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
694 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
695 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
696
697 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
698 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
699 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
700 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
701 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
702
703 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
704 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
705 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
706
707 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
708 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
709 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
710 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
711 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
712 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
713 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
714 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
715 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
716 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
717 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
718 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
719 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
720 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
721
722 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
724 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
725
726 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
727 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
728 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
729
730 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
731 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
732
733 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
734 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
735 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
736 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
737 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
738 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
739 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
740 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
741
742#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
743 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
744 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
745#endif
746
747 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
748 {
749 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
750 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
751 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
752 AssertRC(rc);
753 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
754 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
755 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
756 AssertRC(rc);
757 }
758
759#undef HM_REG_COUNTER
760
761 pVCpu->hm.s.paStatExitReason = NULL;
762
763 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
764 (void **)&pVCpu->hm.s.paStatExitReason);
765 AssertRC(rc);
766 if (RT_SUCCESS(rc))
767 {
768 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
769 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
770 {
771 if (papszDesc[j])
772 {
773 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
774 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
775 AssertRC(rc);
776 }
777 }
778 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
779 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
780 AssertRC(rc);
781 }
782 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
783# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
784 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
785# else
786 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
787# endif
788
789 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
790 AssertRCReturn(rc, rc);
791 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
792# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
793 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
794# else
795 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
796# endif
797 for (unsigned j = 0; j < 255; j++)
798 {
799 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
800 "Injected event.",
801 (j < 0x20) ? "/HM/CPU%d/EventInject/Event/Trap/%02X" : "/HM/CPU%d/EventInject/Event/IRQ/%02X", i, j);
802 }
803
804#endif /* VBOX_WITH_STATISTICS */
805 }
806
807#ifdef VBOX_WITH_CRASHDUMP_MAGIC
808 /*
809 * Magic marker for searching in crash dumps.
810 */
811 for (VMCPUID i = 0; i < pVM->cCpus; i++)
812 {
813 PVMCPU pVCpu = &pVM->aCpus[i];
814
815 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
816 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
817 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
818 }
819#endif
820
821 return VINF_SUCCESS;
822}
823
824
825/**
826 * Called when a init phase has completed.
827 *
828 * @returns VBox status code.
829 * @param pVM The VM.
830 * @param enmWhat The phase that completed.
831 */
832VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
833{
834 switch (enmWhat)
835 {
836 case VMINITCOMPLETED_RING3:
837 return hmR3InitCPU(pVM);
838 case VMINITCOMPLETED_RING0:
839 return hmR3InitFinalizeR0(pVM);
840 default:
841 return VINF_SUCCESS;
842 }
843}
844
845
846/**
847 * Turns off normal raw mode features.
848 *
849 * @param pVM Pointer to the VM.
850 */
851static void hmR3DisableRawMode(PVM pVM)
852{
853 /* Reinit the paging mode to force the new shadow mode. */
854 for (VMCPUID i = 0; i < pVM->cCpus; i++)
855 {
856 PVMCPU pVCpu = &pVM->aCpus[i];
857
858 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
859 }
860}
861
862
863/**
864 * Initialize VT-x or AMD-V.
865 *
866 * @returns VBox status code.
867 * @param pVM Pointer to the VM.
868 */
869static int hmR3InitFinalizeR0(PVM pVM)
870{
871 int rc;
872
873 if (!HMIsEnabled(pVM))
874 return VINF_SUCCESS;
875
876 /*
877 * Hack to allow users to work around broken BIOSes that incorrectly set
878 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
879 */
880 if ( !pVM->hm.s.vmx.fSupported
881 && !pVM->hm.s.svm.fSupported
882 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
883 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
884 {
885 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
886 pVM->hm.s.svm.fSupported = true;
887 pVM->hm.s.svm.fIgnoreInUseError = true;
888 pVM->hm.s.lLastError = VINF_SUCCESS;
889 }
890
891 /*
892 * Report ring-0 init errors.
893 */
894 if ( !pVM->hm.s.vmx.fSupported
895 && !pVM->hm.s.svm.fSupported)
896 {
897 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
898 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl));
899 switch (pVM->hm.s.lLastError)
900 {
901 case VERR_VMX_IN_VMX_ROOT_MODE:
902 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
903 case VERR_VMX_NO_VMX:
904 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
905 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
906 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS (or by the host OS).");
907
908 case VERR_SVM_IN_USE:
909 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
910 case VERR_SVM_NO_SVM:
911 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
912 case VERR_SVM_DISABLED:
913 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
914 }
915 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
916 }
917
918 /*
919 * Enable VT-x or AMD-V on all host CPUs.
920 */
921 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
922 if (RT_FAILURE(rc))
923 {
924 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
925 return rc;
926 }
927
928 /*
929 * No TPR patching is required when the IO-APIC is not enabled for this VM.
930 * (Main should have taken care of this already)
931 */
932 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
933 if (!pVM->hm.s.fHasIoApic)
934 {
935 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
936 pVM->hm.s.fTRPPatchingAllowed = false;
937 }
938
939 /*
940 * Do the vendor specific initalization .
941 * .
942 * Note! We disable release log buffering here since we're doing relatively .
943 * lot of logging and doesn't want to hit the disk with each LogRel .
944 * statement.
945 */
946 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
947 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
948 if (pVM->hm.s.vmx.fSupported)
949 rc = hmR3InitFinalizeR0Intel(pVM);
950 else
951 rc = hmR3InitFinalizeR0Amd(pVM);
952 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
953 RTLogRelSetBuffering(fOldBuffered);
954 pVM->hm.s.fInitialized = true;
955
956 return rc;
957}
958
959
960/**
961 * Finish VT-x initialization (after ring-0 init).
962 *
963 * @returns VBox status code.
964 * @param pVM The cross context VM structure.
965 */
966static int hmR3InitFinalizeR0Intel(PVM pVM)
967{
968 int rc;
969
970 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
971 AssertLogRelReturn(pVM->hm.s.vmx.msr.u64FeatureCtrl != 0, VERR_HM_IPE_4);
972
973 uint64_t val;
974 uint64_t zap;
975 RTGCPHYS GCPhys = 0;
976
977 LogRel(("HM: Using VT-x implementation 2.0!\n"));
978 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
979 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.msr.u64FeatureCtrl));
980 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.msr.u64BasicInfo));
981 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.msr.u64BasicInfo)));
982 LogRel(("HM: VMCS size = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.msr.u64BasicInfo)));
983 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.msr.u64BasicInfo) ? "< 4 GB" : "None"));
984 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.msr.u64BasicInfo)));
985 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.msr.u64BasicInfo)));
986 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.msr.u64BasicInfo)));
987 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
988
989 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.VmxPinCtls.u));
990 val = pVM->hm.s.vmx.msr.VmxPinCtls.n.allowed1;
991 zap = pVM->hm.s.vmx.msr.VmxPinCtls.n.disallowed0;
992 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
993 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
994 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
995 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
996
997 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls.u));
998 val = pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1;
999 zap = pVM->hm.s.vmx.msr.VmxProcCtls.n.disallowed0;
1000 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1001 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1002 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1003 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1004 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1005 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1006 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1007 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1008 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1009 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1010 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1011 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1012 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1013 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1014 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1015 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1016 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1017 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1018 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1019 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1020 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1021 if (pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1022 {
1023 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.msr.VmxProcCtls2.u));
1024 val = pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1;
1025 zap = pVM->hm.s.vmx.msr.VmxProcCtls2.n.disallowed0;
1026 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1027 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1028 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1029 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1030 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1031 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1032 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1033 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1034 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1035 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1036 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1037 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1038 }
1039
1040 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.VmxEntry.u));
1041 val = pVM->hm.s.vmx.msr.VmxEntry.n.allowed1;
1042 zap = pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0;
1043 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1044 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1045 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1046 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1047 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1048 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1049 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1050
1051 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.msr.VmxExit.u));
1052 val = pVM->hm.s.vmx.msr.VmxExit.n.allowed1;
1053 zap = pVM->hm.s.vmx.msr.VmxExit.n.disallowed0;
1054 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1055 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1056 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1057 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1058 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1059 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1060 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1061 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1062 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1063
1064 if (pVM->hm.s.vmx.msr.u64EptVpidCaps)
1065 {
1066 val = pVM->hm.s.vmx.msr.u64EptVpidCaps;
1067 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1068 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1069 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1070 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1071 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1072 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1073 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1074 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1075 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1076 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1077 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1078 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1079 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1080 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1081 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1082 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1083 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1084 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1085 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1086 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1087 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1088 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1089 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1090 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1091 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1092 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1093 }
1094
1095 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", pVM->hm.s.vmx.msr.u64Misc));
1096 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc) == pVM->hm.s.vmx.cPreemptTimerShift)
1097 {
1098 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n",
1099 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc)));
1100 }
1101 else
1102 {
1103 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1104 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(pVM->hm.s.vmx.msr.u64Misc), pVM->hm.s.vmx.cPreemptTimerShift));
1105 }
1106
1107 val = pVM->hm.s.vmx.msr.u64Misc;
1108 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val)));
1109 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1110 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1111 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1112 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val)));
1113 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val)));
1114 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val)));
1115 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1116
1117 /* Paranoia */
1118 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.msr.u64Misc) >= 512);
1119
1120 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr0Fixed0));
1121 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr0Fixed1));
1122 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr4Fixed0));
1123 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.msr.u64Cr4Fixed1));
1124
1125 val = pVM->hm.s.vmx.msr.u64VmcsEnum;
1126 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1127 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1128
1129 val = pVM->hm.s.vmx.msr.u64Vmfunc;
1130 if (val)
1131 {
1132 LogRel(("HM: MSR_A32_VMX_VMFUNC = %#RX64\n", val));
1133 HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1134 }
1135
1136 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1137
1138 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1139 {
1140 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1141 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1142 }
1143
1144 if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1145 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1146
1147 if (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1148 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1149
1150 /*
1151 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1152 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1153 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1154 */
1155 if ( !(pVM->hm.s.vmx.msr.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1156 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1157 {
1158 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1159 LogRel(("HM: RDTSCP disabled.\n"));
1160 }
1161
1162 /* Unrestricted guest execution also requires EPT. */
1163 if ( pVM->hm.s.vmx.fAllowUnrestricted
1164 && pVM->hm.s.fNestedPaging
1165 && (pVM->hm.s.vmx.msr.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1166 {
1167 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1168 }
1169
1170 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1171 {
1172 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1173 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1174 if (RT_SUCCESS(rc))
1175 {
1176 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1177 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1178 esp. Figure 20-5.*/
1179 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1180 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1181
1182 /* Bit set to 0 means software interrupts are redirected to the
1183 8086 program interrupt handler rather than switching to
1184 protected-mode handler. */
1185 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1186
1187 /* Allow all port IO, so that port IO instructions do not cause
1188 exceptions and would instead cause a VM-exit (based on VT-x's
1189 IO bitmap which we currently configure to always cause an exit). */
1190 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1191 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1192
1193 /*
1194 * Construct a 1024 element page directory with 4 MB pages for
1195 * the identity mapped page table used in real and protected mode
1196 * without paging with EPT.
1197 */
1198 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1199 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1200 {
1201 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1202 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1203 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1204 | X86_PDE4M_G;
1205 }
1206
1207 /* We convert it here every time as pci regions could be reconfigured. */
1208 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1209 AssertRCReturn(rc, rc);
1210 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1211
1212 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1213 AssertRCReturn(rc, rc);
1214 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1215 }
1216 else
1217 {
1218 /** @todo This cannot possibly work, there are other places which assumes
1219 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1220 * a failure case. */
1221 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1222 pVM->hm.s.vmx.pRealModeTSS = NULL;
1223 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1224 }
1225 }
1226
1227 /*
1228 * Call ring-0 to set up the VM.
1229 */
1230 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1231 if (rc != VINF_SUCCESS)
1232 {
1233 AssertMsgFailed(("%Rrc\n", rc));
1234 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1235 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1236 {
1237 PVMCPU pVCpu = &pVM->aCpus[i];
1238 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1239 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1240 }
1241 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1242 }
1243
1244 LogRel(("HM: VMX enabled!\n"));
1245 pVM->hm.s.vmx.fEnabled = true;
1246
1247 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1248
1249 /*
1250 * Change the CPU features.
1251 */
1252 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1253 if (pVM->hm.s.fAllow64BitGuests)
1254 {
1255 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1256 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1257 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1258 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1259 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1260#if 0 /** @todo r=bird: This ain't making any sense whatsoever. */
1261#if RT_ARCH_X86
1262 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1263 || !(pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE))
1264 LogRel(("NX is only supported for 64-bit guests!\n"));
1265#endif
1266#endif
1267 }
1268 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1269 (we reuse the host EFER in the switcher). */
1270 /** @todo this needs to be fixed properly!! */
1271 else if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1272 && (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE))
1273 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1274 else
1275 LogRel(("HM: NX not supported by the host.\n"));
1276
1277 /*
1278 * Log configuration details.
1279 */
1280 LogRel((pVM->hm.s.fAllow64BitGuests
1281 ? "HM: Guest support: 32-bit and 64-bit.\n"
1282 : "HM: Guest support: 32-bit only.\n"));
1283 if (pVM->hm.s.fNestedPaging)
1284 {
1285 LogRel(("HM: Nested paging enabled!\n"));
1286 LogRel(("HM: EPT root page physaddr = %#RHp\n", PGMGetHyperCR3(VMMGetCpu(pVM))));
1287 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1288 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1289 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1290 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1291 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1292 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1293 else
1294 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1295
1296 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1297 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1298
1299#if HC_ARCH_BITS == 64
1300 if (pVM->hm.s.fLargePages)
1301 {
1302 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1303 PGMSetLargePageUsage(pVM, true);
1304 LogRel(("HM: Large page support enabled!\n"));
1305 }
1306#endif
1307 }
1308 else
1309 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1310
1311 if (pVM->hm.s.vmx.fVpid)
1312 {
1313 LogRel(("HM: VPID enabled!\n"));
1314 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1315 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1316 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1317 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1318 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1319 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1320 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1321 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1322 else
1323 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1324 }
1325 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1326 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1327
1328 /*
1329 * Check for preemption timer config override and log the state of it.
1330 */
1331 if (pVM->hm.s.vmx.fUsePreemptTimer)
1332 {
1333 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1334 rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1335 AssertLogRelRCReturn(rc, rc);
1336 }
1337 if (pVM->hm.s.vmx.fUsePreemptTimer)
1338 LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u).\n", pVM->hm.s.vmx.cPreemptTimerShift));
1339 else
1340 LogRel(("HM: VMX-preemption timer disabled.\n"));
1341
1342 return VINF_SUCCESS;
1343}
1344
1345
1346/**
1347 * Finish AMD-V initialization (after ring-0 init).
1348 *
1349 * @returns VBox status code.
1350 * @param pVM The cross context VM structure.
1351 */
1352static int hmR3InitFinalizeR0Amd(PVM pVM)
1353{
1354 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1355
1356 LogRel(("HM: Using AMD-V implementation 2.0!\n"));
1357
1358 uint32_t u32Family;
1359 uint32_t u32Model;
1360 uint32_t u32Stepping;
1361 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1362 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1363 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1364 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1365 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.msrHwcr));
1366 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1367 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1368 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1369
1370 /*
1371 * Enumerate AMD-V features.
1372 */
1373 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1374 {
1375#define HMSVM_REPORT_FEATURE(a_Define) { a_Define, #a_Define }
1376 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1377 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1378 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1379 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1380 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1381 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1382 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1383 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1384 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1385 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1386 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1387#undef HMSVM_REPORT_FEATURE
1388 };
1389
1390 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1391 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1392 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1393 {
1394 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1395 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1396 }
1397 if (fSvmFeatures)
1398 for (unsigned iBit = 0; iBit < 32; iBit++)
1399 if (RT_BIT_32(iBit) & fSvmFeatures)
1400 LogRel(("HM: Reserved bit %u\n", iBit));
1401
1402 /*
1403 * Adjust feature(s).
1404 */
1405 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1406 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1407
1408 /*
1409 * Call ring-0 to set up the VM.
1410 */
1411 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1412 if (rc != VINF_SUCCESS)
1413 {
1414 AssertMsgFailed(("%Rrc\n", rc));
1415 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1416 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1417 }
1418
1419 LogRel(("HM: AMD-V enabled!\n"));
1420 pVM->hm.s.svm.fEnabled = true;
1421
1422 if (pVM->hm.s.fNestedPaging)
1423 {
1424 LogRel(("HM: Nested paging enabled!\n"));
1425
1426 /*
1427 * Enable large pages (2 MB) if applicable.
1428 */
1429#if HC_ARCH_BITS == 64
1430 if (pVM->hm.s.fLargePages)
1431 {
1432 PGMSetLargePageUsage(pVM, true);
1433 LogRel(("HM: Large page support enabled!\n"));
1434 }
1435#endif
1436 }
1437
1438 hmR3DisableRawMode(pVM);
1439
1440 /*
1441 * Change the CPU features.
1442 */
1443 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1444 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1445 if (pVM->hm.s.fAllow64BitGuests)
1446 {
1447 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1448 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1449 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1450 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1451 }
1452 /* Turn on NXE if PAE has been enabled. */
1453 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1454 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1455
1456 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1457
1458 LogRel((pVM->hm.s.fAllow64BitGuests
1459 ? "HM: Guest support: 32-bit and 64-bit.\n"
1460 : "HM: Guest support: 32-bit only.\n"));
1461
1462 return VINF_SUCCESS;
1463}
1464
1465
1466/**
1467 * Applies relocations to data and code managed by this
1468 * component. This function will be called at init and
1469 * whenever the VMM need to relocate it self inside the GC.
1470 *
1471 * @param pVM The VM.
1472 */
1473VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1474{
1475 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1476
1477 /* Fetch the current paging mode during the relocate callback during state loading. */
1478 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1479 {
1480 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1481 {
1482 PVMCPU pVCpu = &pVM->aCpus[i];
1483 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1484 }
1485 }
1486#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1487 if (HMIsEnabled(pVM))
1488 {
1489 switch (PGMGetHostMode(pVM))
1490 {
1491 case PGMMODE_32_BIT:
1492 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1493 break;
1494
1495 case PGMMODE_PAE:
1496 case PGMMODE_PAE_NX:
1497 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1498 break;
1499
1500 default:
1501 AssertFailed();
1502 break;
1503 }
1504 }
1505#endif
1506 return;
1507}
1508
1509
1510/**
1511 * Notification callback which is called whenever there is a chance that a CR3
1512 * value might have changed.
1513 *
1514 * This is called by PGM.
1515 *
1516 * @param pVM Pointer to the VM.
1517 * @param pVCpu Pointer to the VMCPU.
1518 * @param enmShadowMode New shadow paging mode.
1519 * @param enmGuestMode New guest paging mode.
1520 */
1521VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1522{
1523 /* Ignore page mode changes during state loading. */
1524 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1525 return;
1526
1527 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1528
1529 /*
1530 * If the guest left protected mode VMX execution, we'll have to be
1531 * extra careful if/when the guest switches back to protected mode.
1532 */
1533 if (enmGuestMode == PGMMODE_REAL)
1534 {
1535 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1536 pVCpu->hm.s.vmx.fWasInRealMode = true;
1537 }
1538
1539 /** @todo r=ramshankar: Disabling for now. If nothing breaks remove it
1540 * eventually. (Test platforms that use the cache ofc). */
1541#if 0
1542#ifdef VMX_USE_CACHED_VMCS_ACCESSES
1543 /* Reset the contents of the read cache. */
1544 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1545 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1546 pCache->Read.aFieldVal[j] = 0;
1547#endif
1548#endif
1549}
1550
1551
1552/**
1553 * Terminates the HM.
1554 *
1555 * Termination means cleaning up and freeing all resources,
1556 * the VM itself is, at this point, powered off or suspended.
1557 *
1558 * @returns VBox status code.
1559 * @param pVM Pointer to the VM.
1560 */
1561VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1562{
1563 if (pVM->hm.s.vmx.pRealModeTSS)
1564 {
1565 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1566 pVM->hm.s.vmx.pRealModeTSS = 0;
1567 }
1568 hmR3TermCPU(pVM);
1569 return 0;
1570}
1571
1572
1573/**
1574 * Terminates the per-VCPU HM.
1575 *
1576 * @returns VBox status code.
1577 * @param pVM Pointer to the VM.
1578 */
1579static int hmR3TermCPU(PVM pVM)
1580{
1581 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1582 {
1583 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1584
1585#ifdef VBOX_WITH_STATISTICS
1586 if (pVCpu->hm.s.paStatExitReason)
1587 {
1588 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1589 pVCpu->hm.s.paStatExitReason = NULL;
1590 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1591 }
1592 if (pVCpu->hm.s.paStatInjectedIrqs)
1593 {
1594 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1595 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1596 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1597 }
1598#endif
1599
1600#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1601 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1602 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1603 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1604#endif
1605 }
1606 return 0;
1607}
1608
1609
1610/**
1611 * Resets a virtual CPU.
1612 *
1613 * Used by HMR3Reset and CPU hot plugging.
1614 *
1615 * @param pVCpu The CPU to reset.
1616 */
1617VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1618{
1619 /* On first entry we'll sync everything. */
1620 pVCpu->hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1621
1622 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1623 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1624 pVCpu->hm.s.fActive = false;
1625 pVCpu->hm.s.Event.fPending = false;
1626 pVCpu->hm.s.vmx.fWasInRealMode = true;
1627
1628 /* Reset the contents of the read cache. */
1629 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1630 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1631 pCache->Read.aFieldVal[j] = 0;
1632
1633#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1634 /* Magic marker for searching in crash dumps. */
1635 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1636 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1637#endif
1638}
1639
1640
1641/**
1642 * The VM is being reset.
1643 *
1644 * For the HM component this means that any GDT/LDT/TSS monitors
1645 * needs to be removed.
1646 *
1647 * @param pVM Pointer to the VM.
1648 */
1649VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1650{
1651 LogFlow(("HMR3Reset:\n"));
1652
1653 if (HMIsEnabled(pVM))
1654 hmR3DisableRawMode(pVM);
1655
1656 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1657 {
1658 PVMCPU pVCpu = &pVM->aCpus[i];
1659
1660 HMR3ResetCpu(pVCpu);
1661 }
1662
1663 /* Clear all patch information. */
1664 pVM->hm.s.pGuestPatchMem = 0;
1665 pVM->hm.s.pFreeGuestPatchMem = 0;
1666 pVM->hm.s.cbGuestPatchMem = 0;
1667 pVM->hm.s.cPatches = 0;
1668 pVM->hm.s.PatchTree = 0;
1669 pVM->hm.s.fTPRPatchingActive = false;
1670 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1671}
1672
1673
1674/**
1675 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1676 *
1677 * @returns VBox strict status code.
1678 * @param pVM Pointer to the VM.
1679 * @param pVCpu The VMCPU for the EMT we're being called on.
1680 * @param pvUser Unused.
1681 */
1682DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1683{
1684 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1685
1686 /* Only execute the handler on the VCPU the original patch request was issued. */
1687 if (pVCpu->idCpu != idCpu)
1688 return VINF_SUCCESS;
1689
1690 Log(("hmR3RemovePatches\n"));
1691 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1692 {
1693 uint8_t abInstr[15];
1694 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1695 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1696 int rc;
1697
1698#ifdef LOG_ENABLED
1699 char szOutput[256];
1700
1701 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1702 szOutput, sizeof(szOutput), NULL);
1703 if (RT_SUCCESS(rc))
1704 Log(("Patched instr: %s\n", szOutput));
1705#endif
1706
1707 /* Check if the instruction is still the same. */
1708 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1709 if (rc != VINF_SUCCESS)
1710 {
1711 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1712 continue; /* swapped out or otherwise removed; skip it. */
1713 }
1714
1715 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1716 {
1717 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1718 continue; /* skip it. */
1719 }
1720
1721 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1722 AssertRC(rc);
1723
1724#ifdef LOG_ENABLED
1725 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1726 szOutput, sizeof(szOutput), NULL);
1727 if (RT_SUCCESS(rc))
1728 Log(("Original instr: %s\n", szOutput));
1729#endif
1730 }
1731 pVM->hm.s.cPatches = 0;
1732 pVM->hm.s.PatchTree = 0;
1733 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1734 pVM->hm.s.fTPRPatchingActive = false;
1735 return VINF_SUCCESS;
1736}
1737
1738
1739/**
1740 * Worker for enabling patching in a VT-x/AMD-V guest.
1741 *
1742 * @returns VBox status code.
1743 * @param pVM Pointer to the VM.
1744 * @param idCpu VCPU to execute hmR3RemovePatches on.
1745 * @param pPatchMem Patch memory range.
1746 * @param cbPatchMem Size of the memory range.
1747 */
1748static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1749{
1750 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1751 AssertRC(rc);
1752
1753 pVM->hm.s.pGuestPatchMem = pPatchMem;
1754 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1755 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1756 return VINF_SUCCESS;
1757}
1758
1759
1760/**
1761 * Enable patching in a VT-x/AMD-V guest
1762 *
1763 * @returns VBox status code.
1764 * @param pVM Pointer to the VM.
1765 * @param pPatchMem Patch memory range.
1766 * @param cbPatchMem Size of the memory range.
1767 */
1768VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1769{
1770 VM_ASSERT_EMT(pVM);
1771 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1772 if (pVM->cCpus > 1)
1773 {
1774 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1775 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1776 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1777 AssertRC(rc);
1778 return rc;
1779 }
1780 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1781}
1782
1783
1784/**
1785 * Disable patching in a VT-x/AMD-V guest.
1786 *
1787 * @returns VBox status code.
1788 * @param pVM Pointer to the VM.
1789 * @param pPatchMem Patch memory range.
1790 * @param cbPatchMem Size of the memory range.
1791 */
1792VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1793{
1794 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1795
1796 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1797 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1798
1799 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1800 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1801 (void *)(uintptr_t)VMMGetCpuId(pVM));
1802 AssertRC(rc);
1803
1804 pVM->hm.s.pGuestPatchMem = 0;
1805 pVM->hm.s.pFreeGuestPatchMem = 0;
1806 pVM->hm.s.cbGuestPatchMem = 0;
1807 pVM->hm.s.fTPRPatchingActive = false;
1808 return VINF_SUCCESS;
1809}
1810
1811
1812/**
1813 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1814 *
1815 * @returns VBox strict status code.
1816 * @param pVM Pointer to the VM.
1817 * @param pVCpu The VMCPU for the EMT we're being called on.
1818 * @param pvUser User specified CPU context.
1819 *
1820 */
1821DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1822{
1823 /*
1824 * Only execute the handler on the VCPU the original patch request was
1825 * issued. (The other CPU(s) might not yet have switched to protected
1826 * mode, nor have the correct memory context.)
1827 */
1828 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1829 if (pVCpu->idCpu != idCpu)
1830 return VINF_SUCCESS;
1831
1832 /*
1833 * We're racing other VCPUs here, so don't try patch the instruction twice
1834 * and make sure there is still room for our patch record.
1835 */
1836 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1837 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1838 if (pPatch)
1839 {
1840 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1841 return VINF_SUCCESS;
1842 }
1843 uint32_t const idx = pVM->hm.s.cPatches;
1844 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1845 {
1846 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1847 return VINF_SUCCESS;
1848 }
1849 pPatch = &pVM->hm.s.aPatches[idx];
1850
1851 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1852
1853 /*
1854 * Disassembler the instruction and get cracking.
1855 */
1856 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1857 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1858 uint32_t cbOp;
1859 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1860 AssertRC(rc);
1861 if ( rc == VINF_SUCCESS
1862 && pDis->pCurInstr->uOpcode == OP_MOV
1863 && cbOp >= 3)
1864 {
1865 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1866
1867 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1868 AssertRC(rc);
1869
1870 pPatch->cbOp = cbOp;
1871
1872 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1873 {
1874 /* write. */
1875 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1876 {
1877 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1878 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1879 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1880 }
1881 else
1882 {
1883 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1884 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1885 pPatch->uSrcOperand = pDis->Param2.uValue;
1886 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1887 }
1888 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1889 AssertRC(rc);
1890
1891 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1892 pPatch->cbNewOp = sizeof(s_abVMMCall);
1893 }
1894 else
1895 {
1896 /*
1897 * TPR Read.
1898 *
1899 * Found:
1900 * mov eax, dword [fffe0080] (5 bytes)
1901 * Check if next instruction is:
1902 * shr eax, 4
1903 */
1904 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1905
1906 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1907 uint8_t const cbOpMmio = cbOp;
1908 uint64_t const uSavedRip = pCtx->rip;
1909
1910 pCtx->rip += cbOp;
1911 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1912 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1913 pCtx->rip = uSavedRip;
1914
1915 if ( rc == VINF_SUCCESS
1916 && pDis->pCurInstr->uOpcode == OP_SHR
1917 && pDis->Param1.fUse == DISUSE_REG_GEN32
1918 && pDis->Param1.Base.idxGenReg == idxMmioReg
1919 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1920 && pDis->Param2.uValue == 4
1921 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1922 {
1923 uint8_t abInstr[15];
1924
1925 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
1926 access CR8 in 32-bit mode and not cause a #VMEXIT. */
1927 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1928 AssertRC(rc);
1929
1930 pPatch->cbOp = cbOpMmio + cbOp;
1931
1932 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1933 abInstr[0] = 0xF0;
1934 abInstr[1] = 0x0F;
1935 abInstr[2] = 0x20;
1936 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1937 for (unsigned i = 4; i < pPatch->cbOp; i++)
1938 abInstr[i] = 0x90; /* nop */
1939
1940 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1941 AssertRC(rc);
1942
1943 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1944 pPatch->cbNewOp = pPatch->cbOp;
1945
1946 Log(("Acceptable read/shr candidate!\n"));
1947 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1948 }
1949 else
1950 {
1951 pPatch->enmType = HMTPRINSTR_READ;
1952 pPatch->uDstOperand = idxMmioReg;
1953
1954 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1955 AssertRC(rc);
1956
1957 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1958 pPatch->cbNewOp = sizeof(s_abVMMCall);
1959 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1960 }
1961 }
1962
1963 pPatch->Core.Key = pCtx->eip;
1964 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1965 AssertRC(rc);
1966
1967 pVM->hm.s.cPatches++;
1968 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1969 return VINF_SUCCESS;
1970 }
1971
1972 /*
1973 * Save invalid patch, so we will not try again.
1974 */
1975 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1976 pPatch->Core.Key = pCtx->eip;
1977 pPatch->enmType = HMTPRINSTR_INVALID;
1978 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1979 AssertRC(rc);
1980 pVM->hm.s.cPatches++;
1981 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1982 return VINF_SUCCESS;
1983}
1984
1985
1986/**
1987 * Callback to patch a TPR instruction (jump to generated code).
1988 *
1989 * @returns VBox strict status code.
1990 * @param pVM Pointer to the VM.
1991 * @param pVCpu The VMCPU for the EMT we're being called on.
1992 * @param pvUser User specified CPU context.
1993 *
1994 */
1995DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1996{
1997 /*
1998 * Only execute the handler on the VCPU the original patch request was
1999 * issued. (The other CPU(s) might not yet have switched to protected
2000 * mode, nor have the correct memory context.)
2001 */
2002 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2003 if (pVCpu->idCpu != idCpu)
2004 return VINF_SUCCESS;
2005
2006 /*
2007 * We're racing other VCPUs here, so don't try patch the instruction twice
2008 * and make sure there is still room for our patch record.
2009 */
2010 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2011 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2012 if (pPatch)
2013 {
2014 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2015 return VINF_SUCCESS;
2016 }
2017 uint32_t const idx = pVM->hm.s.cPatches;
2018 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2019 {
2020 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2021 return VINF_SUCCESS;
2022 }
2023 pPatch = &pVM->hm.s.aPatches[idx];
2024
2025 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2026 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2027
2028 /*
2029 * Disassemble the instruction and get cracking.
2030 */
2031 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2032 uint32_t cbOp;
2033 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2034 AssertRC(rc);
2035 if ( rc == VINF_SUCCESS
2036 && pDis->pCurInstr->uOpcode == OP_MOV
2037 && cbOp >= 5)
2038 {
2039 uint8_t aPatch[64];
2040 uint32_t off = 0;
2041
2042 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2043 AssertRC(rc);
2044
2045 pPatch->cbOp = cbOp;
2046 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2047
2048 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2049 {
2050 /*
2051 * TPR write:
2052 *
2053 * push ECX [51]
2054 * push EDX [52]
2055 * push EAX [50]
2056 * xor EDX,EDX [31 D2]
2057 * mov EAX,EAX [89 C0]
2058 * or
2059 * mov EAX,0000000CCh [B8 CC 00 00 00]
2060 * mov ECX,0C0000082h [B9 82 00 00 C0]
2061 * wrmsr [0F 30]
2062 * pop EAX [58]
2063 * pop EDX [5A]
2064 * pop ECX [59]
2065 * jmp return_address [E9 return_address]
2066 *
2067 */
2068 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2069
2070 aPatch[off++] = 0x51; /* push ecx */
2071 aPatch[off++] = 0x52; /* push edx */
2072 if (!fUsesEax)
2073 aPatch[off++] = 0x50; /* push eax */
2074 aPatch[off++] = 0x31; /* xor edx, edx */
2075 aPatch[off++] = 0xD2;
2076 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2077 {
2078 if (!fUsesEax)
2079 {
2080 aPatch[off++] = 0x89; /* mov eax, src_reg */
2081 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2082 }
2083 }
2084 else
2085 {
2086 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2087 aPatch[off++] = 0xB8; /* mov eax, immediate */
2088 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2089 off += sizeof(uint32_t);
2090 }
2091 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2092 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2093 off += sizeof(uint32_t);
2094
2095 aPatch[off++] = 0x0F; /* wrmsr */
2096 aPatch[off++] = 0x30;
2097 if (!fUsesEax)
2098 aPatch[off++] = 0x58; /* pop eax */
2099 aPatch[off++] = 0x5A; /* pop edx */
2100 aPatch[off++] = 0x59; /* pop ecx */
2101 }
2102 else
2103 {
2104 /*
2105 * TPR read:
2106 *
2107 * push ECX [51]
2108 * push EDX [52]
2109 * push EAX [50]
2110 * mov ECX,0C0000082h [B9 82 00 00 C0]
2111 * rdmsr [0F 32]
2112 * mov EAX,EAX [89 C0]
2113 * pop EAX [58]
2114 * pop EDX [5A]
2115 * pop ECX [59]
2116 * jmp return_address [E9 return_address]
2117 *
2118 */
2119 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2120
2121 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2122 aPatch[off++] = 0x51; /* push ecx */
2123 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2124 aPatch[off++] = 0x52; /* push edx */
2125 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2126 aPatch[off++] = 0x50; /* push eax */
2127
2128 aPatch[off++] = 0x31; /* xor edx, edx */
2129 aPatch[off++] = 0xD2;
2130
2131 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2132 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2133 off += sizeof(uint32_t);
2134
2135 aPatch[off++] = 0x0F; /* rdmsr */
2136 aPatch[off++] = 0x32;
2137
2138 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2139 {
2140 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2141 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2142 }
2143
2144 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2145 aPatch[off++] = 0x58; /* pop eax */
2146 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2147 aPatch[off++] = 0x5A; /* pop edx */
2148 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2149 aPatch[off++] = 0x59; /* pop ecx */
2150 }
2151 aPatch[off++] = 0xE9; /* jmp return_address */
2152 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2153 off += sizeof(RTRCUINTPTR);
2154
2155 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2156 {
2157 /* Write new code to the patch buffer. */
2158 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2159 AssertRC(rc);
2160
2161#ifdef LOG_ENABLED
2162 uint32_t cbCurInstr;
2163 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2164 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2165 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2166 {
2167 char szOutput[256];
2168 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2169 szOutput, sizeof(szOutput), &cbCurInstr);
2170 if (RT_SUCCESS(rc))
2171 Log(("Patch instr %s\n", szOutput));
2172 else
2173 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2174 }
2175#endif
2176
2177 pPatch->aNewOpcode[0] = 0xE9;
2178 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2179
2180 /* Overwrite the TPR instruction with a jump. */
2181 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2182 AssertRC(rc);
2183
2184 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2185
2186 pVM->hm.s.pFreeGuestPatchMem += off;
2187 pPatch->cbNewOp = 5;
2188
2189 pPatch->Core.Key = pCtx->eip;
2190 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2191 AssertRC(rc);
2192
2193 pVM->hm.s.cPatches++;
2194 pVM->hm.s.fTPRPatchingActive = true;
2195 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2196 return VINF_SUCCESS;
2197 }
2198
2199 Log(("Ran out of space in our patch buffer!\n"));
2200 }
2201 else
2202 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2203
2204
2205 /*
2206 * Save invalid patch, so we will not try again.
2207 */
2208 pPatch = &pVM->hm.s.aPatches[idx];
2209 pPatch->Core.Key = pCtx->eip;
2210 pPatch->enmType = HMTPRINSTR_INVALID;
2211 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2212 AssertRC(rc);
2213 pVM->hm.s.cPatches++;
2214 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2215 return VINF_SUCCESS;
2216}
2217
2218
2219/**
2220 * Attempt to patch TPR mmio instructions.
2221 *
2222 * @returns VBox status code.
2223 * @param pVM Pointer to the VM.
2224 * @param pVCpu Pointer to the VMCPU.
2225 * @param pCtx Pointer to the guest CPU context.
2226 */
2227VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2228{
2229 NOREF(pCtx);
2230 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2231 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2232 (void *)(uintptr_t)pVCpu->idCpu);
2233 AssertRC(rc);
2234 return rc;
2235}
2236
2237
2238/**
2239 * Checks if a code selector (CS) is suitable for execution
2240 * within VMX when unrestricted execution isn't available.
2241 *
2242 * @returns true if selector is suitable for VMX, otherwise
2243 * false.
2244 * @param pSel Pointer to the selector to check (CS).
2245 * uStackDpl The DPL of the stack segment.
2246 */
2247static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2248{
2249 bool rc = false;
2250
2251 do
2252 {
2253 /* Segment must be accessed. */
2254 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2255 break;
2256 /* Segment must be a code segment. */
2257 if (!(pSel->Attr.u & X86_SEL_TYPE_CODE))
2258 break;
2259 /* The S bit must be set. */
2260 if (!pSel->Attr.n.u1DescType)
2261 break;
2262 if (pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF)
2263 {
2264 /* For conforming segments, CS.DPL must be <= SS.DPL. */
2265 if (pSel->Attr.n.u2Dpl > uStackDpl)
2266 break;
2267 }
2268 else
2269 {
2270 /* For non-conforming segments, CS.DPL must equal SS.DPL. */
2271 if (pSel->Attr.n.u2Dpl != uStackDpl)
2272 break;
2273 }
2274 /* Segment must be present. */
2275 if (!pSel->Attr.n.u1Present)
2276 break;
2277 /* G bit must be set if any high limit bits are set. */
2278 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2279 break;
2280 /* G bit must be clear if any low limit bits are clear. */
2281 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2282 break;
2283
2284 rc = true;
2285 } while (0);
2286 return rc;
2287}
2288
2289
2290/**
2291 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2292 * execution within VMX when unrestricted execution isn't
2293 * available.
2294 *
2295 * @returns true if selector is suitable for VMX, otherwise
2296 * false.
2297 * @param pSel Pointer to the selector to check
2298 * (DS/ES/FS/GS).
2299 */
2300static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2301{
2302 bool rc = false;
2303
2304 /* If attributes are all zero, consider the segment unusable and therefore OK.
2305 * This logic must be in sync with HMVMXR0.cpp!
2306 */
2307 if (!pSel->Attr.u)
2308 return true;
2309
2310 do
2311 {
2312 /* Segment must be accessed. */
2313 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2314 break;
2315 /* Code segments must also be readable. */
2316 if (pSel->Attr.u & X86_SEL_TYPE_CODE && !(pSel->Attr.u & X86_SEL_TYPE_READ))
2317 break;
2318 /* The S bit must be set. */
2319 if (!pSel->Attr.n.u1DescType)
2320 break;
2321 /* Except for conforming segments, DPL >= RPL. */
2322 if (pSel->Attr.n.u4Type <= X86_SEL_TYPE_ER_ACC && pSel->Attr.n.u2Dpl < (pSel->Sel & X86_SEL_RPL))
2323 break;
2324 /* Segment must be present. */
2325 if (!pSel->Attr.n.u1Present)
2326 break;
2327 /* G bit must be set if any high limit bits are set. */
2328 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2329 break;
2330 /* G bit must be clear if any low limit bits are clear. */
2331 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2332 break;
2333
2334 rc = true;
2335 } while (0);
2336 return rc;
2337}
2338
2339
2340/**
2341 * Checks if the stack selector (SS) is suitable for execution
2342 * within VMX when unrestricted execution isn't available.
2343 *
2344 * @returns true if selector is suitable for VMX, otherwise
2345 * false.
2346 * @param pSel Pointer to the selector to check (SS).
2347 */
2348static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2349{
2350 bool rc = false;
2351
2352 /* If attributes are all zero, consider the segment unusable and therefore OK.
2353 * This logic must be in sync with HMVMXR0.cpp!
2354 */
2355 if (!pSel->Attr.u)
2356 return true;
2357
2358 do
2359 {
2360 /* Segment must be accessed. */
2361 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2362 break;
2363 /* Segment must be writable. */
2364 if (!(pSel->Attr.u & X86_SEL_TYPE_WRITE))
2365 break;
2366 /* Segment must not be a code segment. */
2367 if (pSel->Attr.u & X86_SEL_TYPE_CODE)
2368 break;
2369 /* The S bit must be set. */
2370 if (!pSel->Attr.n.u1DescType)
2371 break;
2372 /* DPL must equal RPL. */
2373 if (pSel->Attr.n.u2Dpl != (pSel->Sel & X86_SEL_RPL))
2374 break;
2375 /* Segment must be present. */
2376 if (!pSel->Attr.n.u1Present)
2377 break;
2378 /* G bit must be set if any high limit bits are set. */
2379 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2380 break;
2381 /* G bit must be clear if any low limit bits are clear. */
2382 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2383 break;
2384
2385 rc = true;
2386 } while (0);
2387 return rc;
2388}
2389
2390
2391/**
2392 * Force execution of the current IO code in the recompiler.
2393 *
2394 * @returns VBox status code.
2395 * @param pVM Pointer to the VM.
2396 * @param pCtx Partial VM execution context.
2397 */
2398VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2399{
2400 PVMCPU pVCpu = VMMGetCpu(pVM);
2401
2402 Assert(HMIsEnabled(pVM));
2403 Log(("HMR3EmulateIoBlock\n"));
2404
2405 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2406 if (HMCanEmulateIoBlockEx(pCtx))
2407 {
2408 Log(("HMR3EmulateIoBlock -> enabled\n"));
2409 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2410 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2411 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2412 return VINF_EM_RESCHEDULE_REM;
2413 }
2414 return VINF_SUCCESS;
2415}
2416
2417
2418/**
2419 * Checks if we can currently use hardware accelerated raw mode.
2420 *
2421 * @returns true if we can currently use hardware acceleration, otherwise false.
2422 * @param pVM Pointer to the VM.
2423 * @param pCtx Partial VM execution context.
2424 */
2425VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2426{
2427 PVMCPU pVCpu = VMMGetCpu(pVM);
2428
2429 Assert(HMIsEnabled(pVM));
2430
2431 /* If we're still executing the IO code, then return false. */
2432 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2433 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2434 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2435 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2436 return false;
2437
2438 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2439
2440 /* AMD-V supports real & protected mode with or without paging. */
2441 if (pVM->hm.s.svm.fEnabled)
2442 {
2443 pVCpu->hm.s.fActive = true;
2444 return true;
2445 }
2446
2447 pVCpu->hm.s.fActive = false;
2448
2449 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2450 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2451 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2452
2453 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2454 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2455 {
2456 /*
2457 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2458 * guest execution feature i missing (VT-x only).
2459 */
2460 if (fSupportsRealMode)
2461 {
2462 if (CPUMIsGuestInRealModeEx(pCtx))
2463 {
2464 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2465 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2466 * If this is not true, we cannot execute real mode as V86 and have to fall
2467 * back to emulation.
2468 */
2469 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2470 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2471 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2472 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2473 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2474 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2475 {
2476 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2477 return false;
2478 }
2479 if ( (pCtx->cs.u32Limit != 0xffff)
2480 || (pCtx->ds.u32Limit != 0xffff)
2481 || (pCtx->es.u32Limit != 0xffff)
2482 || (pCtx->ss.u32Limit != 0xffff)
2483 || (pCtx->fs.u32Limit != 0xffff)
2484 || (pCtx->gs.u32Limit != 0xffff))
2485 {
2486 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2487 return false;
2488 }
2489 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2490 }
2491 else
2492 {
2493 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2494 /* Verify the requirements for executing code in protected
2495 mode. VT-x can't handle the CPU state right after a switch
2496 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2497 if (pVCpu->hm.s.vmx.fWasInRealMode)
2498 {
2499 /** @todo If guest is in V86 mode, these checks should be different! */
2500 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2501 {
2502 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2503 return false;
2504 }
2505 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2506 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2507 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2508 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2509 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2510 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2511 {
2512 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2513 return false;
2514 }
2515 }
2516 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2517 if (pCtx->gdtr.cbGdt)
2518 {
2519 if (pCtx->tr.Sel > pCtx->gdtr.cbGdt)
2520 {
2521 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2522 return false;
2523 }
2524 else if (pCtx->ldtr.Sel > pCtx->gdtr.cbGdt)
2525 {
2526 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2527 return false;
2528 }
2529 }
2530 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2531 }
2532 }
2533 else
2534 {
2535 if ( !CPUMIsGuestInLongModeEx(pCtx)
2536 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2537 {
2538 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2539 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2540 return false;
2541
2542 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2543 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2544 return false;
2545
2546 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2547 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2548 * hidden registers (possible recompiler bug; see load_seg_vm) */
2549 if (pCtx->cs.Attr.n.u1Present == 0)
2550 return false;
2551 if (pCtx->ss.Attr.n.u1Present == 0)
2552 return false;
2553
2554 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2555 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2556 /** @todo This check is actually wrong, it doesn't take the direction of the
2557 * stack segment into account. But, it does the job for now. */
2558 if (pCtx->rsp >= pCtx->ss.u32Limit)
2559 return false;
2560 }
2561 }
2562 }
2563
2564 if (pVM->hm.s.vmx.fEnabled)
2565 {
2566 uint32_t mask;
2567
2568 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2569 mask = (uint32_t)pVM->hm.s.vmx.msr.u64Cr0Fixed0;
2570 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2571 mask &= ~X86_CR0_NE;
2572
2573 if (fSupportsRealMode)
2574 {
2575 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2576 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2577 }
2578 else
2579 {
2580 /* We support protected mode without paging using identity mapping. */
2581 mask &= ~X86_CR0_PG;
2582 }
2583 if ((pCtx->cr0 & mask) != mask)
2584 return false;
2585
2586 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2587 mask = (uint32_t)~pVM->hm.s.vmx.msr.u64Cr0Fixed1;
2588 if ((pCtx->cr0 & mask) != 0)
2589 return false;
2590
2591 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2592 mask = (uint32_t)pVM->hm.s.vmx.msr.u64Cr4Fixed0;
2593 mask &= ~X86_CR4_VMXE;
2594 if ((pCtx->cr4 & mask) != mask)
2595 return false;
2596
2597 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2598 mask = (uint32_t)~pVM->hm.s.vmx.msr.u64Cr4Fixed1;
2599 if ((pCtx->cr4 & mask) != 0)
2600 return false;
2601
2602 pVCpu->hm.s.fActive = true;
2603 return true;
2604 }
2605
2606 return false;
2607}
2608
2609
2610/**
2611 * Checks if we need to reschedule due to VMM device heap changes.
2612 *
2613 * @returns true if a reschedule is required, otherwise false.
2614 * @param pVM Pointer to the VM.
2615 * @param pCtx VM execution context.
2616 */
2617VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2618{
2619 /*
2620 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2621 * when the unrestricted guest execution feature is missing (VT-x only).
2622 */
2623 if ( pVM->hm.s.vmx.fEnabled
2624 && !pVM->hm.s.vmx.fUnrestrictedGuest
2625 && CPUMIsGuestInRealModeEx(pCtx)
2626 && !PDMVmmDevHeapIsEnabled(pVM))
2627 {
2628 return true;
2629 }
2630
2631 return false;
2632}
2633
2634
2635/**
2636 * Notification from EM about a rescheduling into hardware assisted execution
2637 * mode.
2638 *
2639 * @param pVCpu Pointer to the current VMCPU.
2640 */
2641VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2642{
2643 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2644}
2645
2646
2647/**
2648 * Notification from EM about returning from instruction emulation (REM / EM).
2649 *
2650 * @param pVCpu Pointer to the VMCPU.
2651 */
2652VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2653{
2654 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2655}
2656
2657
2658/**
2659 * Checks if we are currently using hardware accelerated raw mode.
2660 *
2661 * @returns true if hardware acceleration is being used, otherwise false.
2662 * @param pVCpu Pointer to the VMCPU.
2663 */
2664VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2665{
2666 return pVCpu->hm.s.fActive;
2667}
2668
2669
2670/**
2671 * External interface for querying whether hardware accelerated raw mode is
2672 * enabled.
2673 *
2674 * @returns true if VT-x or AMD-V is being used, otherwise false.
2675 * @param pUVM The user mode VM handle.
2676 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2677 */
2678VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2679{
2680 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2681 PVM pVM = pUVM->pVM;
2682 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2683 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2684}
2685
2686
2687/**
2688 * External interface for querying whether VT-x is being used.
2689 *
2690 * @returns true if VT-x is being used, otherwise false.
2691 * @param pUVM The user mode VM handle.
2692 * @sa HMR3IsSvmEnabled, HMIsEnabled
2693 */
2694VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2695{
2696 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2697 PVM pVM = pUVM->pVM;
2698 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2699 return pVM->hm.s.vmx.fEnabled
2700 && pVM->hm.s.vmx.fSupported
2701 && pVM->fHMEnabled;
2702}
2703
2704
2705/**
2706 * External interface for querying whether AMD-V is being used.
2707 *
2708 * @returns true if VT-x is being used, otherwise false.
2709 * @param pUVM The user mode VM handle.
2710 * @sa HMR3IsVmxEnabled, HMIsEnabled
2711 */
2712VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2713{
2714 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2715 PVM pVM = pUVM->pVM;
2716 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2717 return pVM->hm.s.svm.fEnabled
2718 && pVM->hm.s.svm.fSupported
2719 && pVM->fHMEnabled;
2720}
2721
2722
2723/**
2724 * Checks if we are currently using nested paging.
2725 *
2726 * @returns true if nested paging is being used, otherwise false.
2727 * @param pUVM The user mode VM handle.
2728 */
2729VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2730{
2731 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2732 PVM pVM = pUVM->pVM;
2733 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2734 return pVM->hm.s.fNestedPaging;
2735}
2736
2737
2738/**
2739 * Checks if we are currently using VPID in VT-x mode.
2740 *
2741 * @returns true if VPID is being used, otherwise false.
2742 * @param pUVM The user mode VM handle.
2743 */
2744VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2745{
2746 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2747 PVM pVM = pUVM->pVM;
2748 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2749 return pVM->hm.s.vmx.fVpid;
2750}
2751
2752
2753/**
2754 * Checks if we are currently using VT-x unrestricted execution,
2755 * aka UX.
2756 *
2757 * @returns true if UX is being used, otherwise false.
2758 * @param pUVM The user mode VM handle.
2759 */
2760VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2761{
2762 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2763 PVM pVM = pUVM->pVM;
2764 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2765 return pVM->hm.s.vmx.fUnrestrictedGuest;
2766}
2767
2768
2769/**
2770 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2771 *
2772 * @returns true if an internal event is pending, otherwise false.
2773 * @param pVM Pointer to the VM.
2774 */
2775VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2776{
2777 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2778}
2779
2780
2781/**
2782 * Checks if the VMX-preemption timer is being used.
2783 *
2784 * @returns true if the VMX-preemption timer is being used, otherwise false.
2785 * @param pVM Pointer to the VM.
2786 */
2787VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2788{
2789 return HMIsEnabled(pVM)
2790 && pVM->hm.s.vmx.fEnabled
2791 && pVM->hm.s.vmx.fUsePreemptTimer;
2792}
2793
2794
2795/**
2796 * Restart an I/O instruction that was refused in ring-0
2797 *
2798 * @returns Strict VBox status code. Informational status codes other than the one documented
2799 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2800 * @retval VINF_SUCCESS Success.
2801 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2802 * status code must be passed on to EM.
2803 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2804 *
2805 * @param pVM Pointer to the VM.
2806 * @param pVCpu Pointer to the VMCPU.
2807 * @param pCtx Pointer to the guest CPU context.
2808 */
2809VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2810{
2811 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2812
2813 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2814
2815 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2816 || enmType == HMPENDINGIO_INVALID)
2817 return VERR_NOT_FOUND;
2818
2819 VBOXSTRICTRC rcStrict;
2820 switch (enmType)
2821 {
2822 case HMPENDINGIO_PORT_READ:
2823 {
2824 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2825 uint32_t u32Val = 0;
2826
2827 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2828 &u32Val,
2829 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2830 if (IOM_SUCCESS(rcStrict))
2831 {
2832 /* Write back to the EAX register. */
2833 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2834 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2835 }
2836 break;
2837 }
2838
2839 case HMPENDINGIO_PORT_WRITE:
2840 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2841 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2842 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2843 if (IOM_SUCCESS(rcStrict))
2844 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2845 break;
2846
2847 default:
2848 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2849 }
2850
2851 if (IOM_SUCCESS(rcStrict))
2852 {
2853 /*
2854 * Check for I/O breakpoints.
2855 */
2856 uint32_t const uDr7 = pCtx->dr[7];
2857 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
2858 && X86_DR7_ANY_RW_IO(uDr7)
2859 && (pCtx->cr4 & X86_CR4_DE))
2860 || DBGFBpIsHwIoArmed(pVM))
2861 {
2862 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
2863 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2864 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
2865 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
2866 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
2867 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
2868 rcStrict = rcStrict2;
2869 }
2870 }
2871 return rcStrict;
2872}
2873
2874
2875/**
2876 * Check fatal VT-x/AMD-V error and produce some meaningful
2877 * log release message.
2878 *
2879 * @param pVM Pointer to the VM.
2880 * @param iStatusCode VBox status code.
2881 */
2882VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2883{
2884 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2885 {
2886 PVMCPU pVCpu = &pVM->aCpus[i];
2887 switch (iStatusCode)
2888 {
2889 case VERR_VMX_INVALID_VMCS_FIELD:
2890 break;
2891
2892 case VERR_VMX_INVALID_VMCS_PTR:
2893 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2894 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
2895 pVCpu->hm.s.vmx.HCPhysVmcs));
2896 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
2897 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2898 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2899 break;
2900
2901 case VERR_VMX_UNABLE_TO_START_VM:
2902 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2903 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
2904 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2905
2906 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
2907 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
2908 {
2909 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2910 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2911 }
2912 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2913 {
2914 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
2915 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
2916 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
2917 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
2918 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
2919 LogRel(("HM: CPU[%u] MSRBitmapPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
2920#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2921 LogRel(("HM: CPU[%u] GuestMSRPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
2922 LogRel(("HM: CPU[%u] HostMsrPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
2923 LogRel(("HM: CPU[%u] cGuestMSRs %u\n", i, pVCpu->hm.s.vmx.cGuestMsrs));
2924#endif
2925 }
2926 /** @todo Log VM-entry event injection control fields
2927 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2928 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2929 break;
2930
2931 case VERR_VMX_INVALID_VMXON_PTR:
2932 break;
2933
2934 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
2935 case VERR_VMX_INVALID_GUEST_STATE:
2936 case VERR_VMX_UNEXPECTED_EXIT_CODE:
2937 case VERR_SVM_UNKNOWN_EXIT:
2938 case VERR_SVM_UNEXPECTED_EXIT:
2939 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
2940 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
2941 {
2942 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
2943 break;
2944 }
2945 }
2946 }
2947
2948 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2949 {
2950 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.msr.VmxEntry.n.allowed1));
2951 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.msr.VmxEntry.n.disallowed0));
2952 }
2953}
2954
2955
2956/**
2957 * Execute state save operation.
2958 *
2959 * @returns VBox status code.
2960 * @param pVM Pointer to the VM.
2961 * @param pSSM SSM operation handle.
2962 */
2963static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2964{
2965 int rc;
2966
2967 Log(("hmR3Save:\n"));
2968
2969 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2970 {
2971 /*
2972 * Save the basic bits - fortunately all the other things can be resynced on load.
2973 */
2974 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2975 AssertRCReturn(rc, rc);
2976 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2977 AssertRCReturn(rc, rc);
2978 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2979 AssertRCReturn(rc, rc);
2980
2981 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
2982 * perhaps not even that (the initial value of @c true is safe. */
2983 uint32_t u32Dummy = PGMMODE_REAL;
2984 rc = SSMR3PutU32(pSSM, u32Dummy);
2985 AssertRCReturn(rc, rc);
2986 rc = SSMR3PutU32(pSSM, u32Dummy);
2987 AssertRCReturn(rc, rc);
2988 rc = SSMR3PutU32(pSSM, u32Dummy);
2989 AssertRCReturn(rc, rc);
2990 }
2991
2992#ifdef VBOX_HM_WITH_GUEST_PATCHING
2993 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2994 AssertRCReturn(rc, rc);
2995 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2996 AssertRCReturn(rc, rc);
2997 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2998 AssertRCReturn(rc, rc);
2999
3000 /* Store all the guest patch records too. */
3001 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3002 AssertRCReturn(rc, rc);
3003
3004 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3005 {
3006 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3007
3008 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3009 AssertRCReturn(rc, rc);
3010
3011 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3012 AssertRCReturn(rc, rc);
3013
3014 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3015 AssertRCReturn(rc, rc);
3016
3017 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3018 AssertRCReturn(rc, rc);
3019
3020 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3021 AssertRCReturn(rc, rc);
3022
3023 AssertCompileSize(HMTPRINSTR, 4);
3024 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3025 AssertRCReturn(rc, rc);
3026
3027 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3028 AssertRCReturn(rc, rc);
3029
3030 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3031 AssertRCReturn(rc, rc);
3032
3033 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3034 AssertRCReturn(rc, rc);
3035
3036 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3037 AssertRCReturn(rc, rc);
3038 }
3039#endif
3040 return VINF_SUCCESS;
3041}
3042
3043
3044/**
3045 * Execute state load operation.
3046 *
3047 * @returns VBox status code.
3048 * @param pVM Pointer to the VM.
3049 * @param pSSM SSM operation handle.
3050 * @param uVersion Data layout version.
3051 * @param uPass The data pass.
3052 */
3053static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3054{
3055 int rc;
3056
3057 Log(("hmR3Load:\n"));
3058 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3059
3060 /*
3061 * Validate version.
3062 */
3063 if ( uVersion != HM_SSM_VERSION
3064 && uVersion != HM_SSM_VERSION_NO_PATCHING
3065 && uVersion != HM_SSM_VERSION_2_0_X)
3066 {
3067 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3068 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3069 }
3070 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3071 {
3072 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3073 AssertRCReturn(rc, rc);
3074 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3075 AssertRCReturn(rc, rc);
3076 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
3077 AssertRCReturn(rc, rc);
3078
3079 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
3080 {
3081 uint32_t val;
3082 /** @todo See note in hmR3Save(). */
3083 rc = SSMR3GetU32(pSSM, &val);
3084 AssertRCReturn(rc, rc);
3085 rc = SSMR3GetU32(pSSM, &val);
3086 AssertRCReturn(rc, rc);
3087 rc = SSMR3GetU32(pSSM, &val);
3088 AssertRCReturn(rc, rc);
3089 }
3090 }
3091#ifdef VBOX_HM_WITH_GUEST_PATCHING
3092 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
3093 {
3094 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3095 AssertRCReturn(rc, rc);
3096 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3097 AssertRCReturn(rc, rc);
3098 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3099 AssertRCReturn(rc, rc);
3100
3101 /* Fetch all TPR patch records. */
3102 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3103 AssertRCReturn(rc, rc);
3104
3105 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3106 {
3107 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3108
3109 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3110 AssertRCReturn(rc, rc);
3111
3112 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3113 AssertRCReturn(rc, rc);
3114
3115 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3116 AssertRCReturn(rc, rc);
3117
3118 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3119 AssertRCReturn(rc, rc);
3120
3121 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3122 AssertRCReturn(rc, rc);
3123
3124 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3125 AssertRCReturn(rc, rc);
3126
3127 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3128 pVM->hm.s.fTPRPatchingActive = true;
3129
3130 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3131
3132 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3133 AssertRCReturn(rc, rc);
3134
3135 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3136 AssertRCReturn(rc, rc);
3137
3138 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3139 AssertRCReturn(rc, rc);
3140
3141 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3142 AssertRCReturn(rc, rc);
3143
3144 Log(("hmR3Load: patch %d\n", i));
3145 Log(("Key = %x\n", pPatch->Core.Key));
3146 Log(("cbOp = %d\n", pPatch->cbOp));
3147 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3148 Log(("type = %d\n", pPatch->enmType));
3149 Log(("srcop = %d\n", pPatch->uSrcOperand));
3150 Log(("dstop = %d\n", pPatch->uDstOperand));
3151 Log(("cFaults = %d\n", pPatch->cFaults));
3152 Log(("target = %x\n", pPatch->pJumpTarget));
3153 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3154 AssertRC(rc);
3155 }
3156 }
3157#endif
3158
3159 return VINF_SUCCESS;
3160}
3161
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