VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 48262

Last change on this file since 48262 was 48262, checked in by vboxsync, 11 years ago

VMM/HM: Preempt stats and minor optimizations to VT-x when thread-context hooks are used.
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File size: 136.3 KB
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1/* $Id: HM.cpp 48262 2013-09-04 12:01:35Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/ssm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/csam.h>
34#include <VBox/vmm/selm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/uvm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/asm-amd64-x86.h>
50#include <iprt/string.h>
51#include <iprt/env.h>
52#include <iprt/thread.h>
53
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58#ifdef VBOX_WITH_STATISTICS
59# define EXIT_REASON(def, val, str) #def " - " #val " - " str
60# define EXIT_REASON_NIL() NULL
61/** Exit reason descriptions for VT-x, used to describe statistics. */
62static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
63{
64 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
65 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
66 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
67 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
68 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
69 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
70 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
71 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
74 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest attempted to execute CPUID."),
75 EXIT_REASON_NIL(),
76 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest attempted to execute HLT."),
77 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest attempted to execute INVD."),
78 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest attempted to execute INVLPG."),
79 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest attempted to execute RDPMC."),
80 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest attempted to execute RDTSC."),
81 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest attempted to execute RSM in SMM."),
82 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest attempted to execute VMCALL."),
83 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest attempted to execute VMCLEAR."),
84 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest attempted to execute VMLAUNCH."),
85 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest attempted to execute VMPTRLD."),
86 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest attempted to execute VMPTRST."),
87 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest attempted to execute VMREAD."),
88 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest attempted to execute VMRESUME."),
89 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest attempted to execute VMWRITE."),
90 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest attempted to execute VMXOFF."),
91 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest attempted to execute VMXON."),
92 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
93 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
94 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
95 EXIT_REASON(VMX_EXIT_RDMSR , 31, "Guest attempted to execute RDMSR."),
96 EXIT_REASON(VMX_EXIT_WRMSR , 32, "Guest attempted to execute WRMSR."),
97 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
98 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest executed MWAIT."),
101 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest attempted to execute MONITOR."),
104 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest attempted to execute PAUSE."),
105 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest attempted to execute MOV to CR8."),
108 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest attempted to access memory at a physical address on the APIC-access page."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest attempted to execute LGDT, LIDT, SGDT, or SIDT."),
111 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest attempted to execute LLDT, LTR, SLDT, or STR."),
112 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
113 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
114 EXIT_REASON(VMX_EXIT_INVEPT , 50, "Guest attempted to execute INVEPT."),
115 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest attempted to execute RDTSCP."),
116 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
117 EXIT_REASON(VMX_EXIT_INVVPID , 53, "Guest attempted to execute INVVPID."),
118 EXIT_REASON(VMX_EXIT_WBINVD , 54, "Guest attempted to execute WBINVD."),
119 EXIT_REASON(VMX_EXIT_XSETBV , 55, "Guest attempted to execute XSETBV."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_RDRAND , 57, "Guest attempted to execute RDRAND."),
122 EXIT_REASON(VMX_EXIT_INVPCID , 58, "Guest attempted to execute INVPCID."),
123 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "Guest attempted to execute VMFUNC.")
124};
125/** Exit reason descriptions for AMD-V, used to describe statistics. */
126static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
231 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
232 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
252 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
270 EXIT_REASON_NIL()
271};
272# undef EXIT_REASON
273# undef EXIT_REASON_NIL
274#endif /* VBOX_WITH_STATISTICS */
275
276#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
277 do { \
278 if ((allowed1) & (featflag)) \
279 LogRel(("HM: " #featflag "\n")); \
280 else \
281 LogRel(("HM: " #featflag " *must* be cleared\n")); \
282 if ((disallowed0) & (featflag)) \
283 LogRel(("HM: " #featflag " *must* be set\n")); \
284 } while (0)
285
286#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, featflag) \
287 do { \
288 if ((allowed1) & (featflag)) \
289 LogRel(("HM: " #featflag "\n")); \
290 else \
291 LogRel(("HM: " #featflag " not supported\n")); \
292 } while (0)
293
294#define HMVMX_REPORT_CAPABILITY(msrcaps, cap) \
295 do { \
296 if ((msrcaps) & (cap)) \
297 LogRel(("HM: " #cap "\n")); \
298 } while (0)
299
300
301/*******************************************************************************
302* Internal Functions *
303*******************************************************************************/
304static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
305static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
306static int hmR3InitCPU(PVM pVM);
307static int hmR3InitFinalizeR0(PVM pVM);
308static int hmR3InitFinalizeR0Intel(PVM pVM);
309static int hmR3InitFinalizeR0Amd(PVM pVM);
310static int hmR3TermCPU(PVM pVM);
311
312
313
314/**
315 * Initializes the HM.
316 *
317 * This reads the config and check whether VT-x or AMD-V hardware is available
318 * if configured to use it. This is one of the very first components to be
319 * initialized after CFGM, so that we can fall back to raw-mode early in the
320 * initialization process.
321 *
322 * Note that a lot of the set up work is done in ring-0 and thus postponed till
323 * the ring-3 and ring-0 callback to HMR3InitCompleted.
324 *
325 * @returns VBox status code.
326 * @param pVM Pointer to the VM.
327 *
328 * @remarks Be careful with what we call here, since most of the VMM components
329 * are uninitialized.
330 */
331VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
332{
333 LogFlow(("HMR3Init\n"));
334
335 /*
336 * Assert alignment and sizes.
337 */
338 AssertCompileMemberAlignment(VM, hm.s, 32);
339 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
340
341 /*
342 * Register the saved state data unit.
343 */
344 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
345 NULL, NULL, NULL,
346 NULL, hmR3Save, NULL,
347 NULL, hmR3Load, NULL);
348 if (RT_FAILURE(rc))
349 return rc;
350
351 /*
352 * Misc initialisation.
353 */
354 //pVM->hm.s.vmx.fSupported = false;
355 //pVM->hm.s.svm.fSupported = false;
356 //pVM->hm.s.vmx.fEnabled = false;
357 //pVM->hm.s.svm.fEnabled = false;
358 //pVM->hm.s.fNestedPaging = false;
359
360
361 /*
362 * Read configuration.
363 */
364 PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
365
366 /** @cfgm{/HM/HMForced, bool, false}
367 * Forces hardware virtualization, no falling back on raw-mode. HM must be
368 * enabled, i.e. /HMEnabled must be true. */
369 bool fHMForced;
370#ifdef VBOX_WITH_RAW_MODE
371 rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
372 AssertRCReturn(rc, rc);
373 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
374 VERR_INVALID_PARAMETER);
375# if defined(RT_OS_DARWIN)
376 if (pVM->fHMEnabled)
377 fHMForced = true;
378# endif
379 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
380 VERR_INVALID_PARAMETER);
381 if (pVM->cCpus > 1)
382 fHMForced = true;
383#else /* !VBOX_WITH_RAW_MODE */
384 AssertRelease(pVM->fHMEnabled);
385 fHMForced = true;
386#endif /* !VBOX_WITH_RAW_MODE */
387
388 /** @cfgm{/HM/EnableNestedPaging, bool, false}
389 * Enables nested paging (aka extended page tables). */
390 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
391 AssertRCReturn(rc, rc);
392
393 /** @cfgm{/HM/EnableUX, bool, true}
394 * Enables the VT-x unrestricted execution feature. */
395 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
396 AssertRCReturn(rc, rc);
397
398 /** @cfgm{/HM/EnableLargePages, bool, false}
399 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
400 * page table walking and maybe better TLB hit rate in some cases. */
401 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
402 AssertRCReturn(rc, rc);
403
404 /** @cfgm{/HM/EnableVPID, bool, false}
405 * Enables the VT-x VPID feature. */
406 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
407 AssertRCReturn(rc, rc);
408
409 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
410 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
411 rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
412 AssertRCReturn(rc, rc);
413
414 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
415 * Enables AMD64 cpu features.
416 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
417 * already have the support. */
418#ifdef VBOX_ENABLE_64_BITS_GUESTS
419 rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
420 AssertLogRelRCReturn(rc, rc);
421#else
422 pVM->hm.s.fAllow64BitGuests = false;
423#endif
424
425 /** @cfgm{/HM/Exclusive, bool}
426 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
427 * global init for each host CPU. If false, we do local init each time we wish
428 * to execute guest code.
429 *
430 * Default is false for Mac OS X and Windows due to the higher risk of conflicts
431 * with other hypervisors.
432 */
433 rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
434#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
435 false
436#else
437 true
438#endif
439 );
440 AssertLogRelRCReturn(rc, rc);
441
442 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
443 * The number of times to resume guest execution before we forcibly return to
444 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445 * determines the default value. */
446 rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
447 AssertLogRelRCReturn(rc, rc);
448
449 /*
450 * Check if VT-x or AMD-v support according to the users wishes.
451 */
452 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
453 * VERR_SVM_IN_USE. */
454 if (pVM->fHMEnabled)
455 {
456 uint32_t fCaps;
457 rc = SUPR3QueryVTCaps(&fCaps);
458 if (RT_SUCCESS(rc))
459 {
460 if (fCaps & SUPVTCAPS_AMD_V)
461 LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
462 else if (fCaps & SUPVTCAPS_VT_X)
463 {
464 rc = SUPR3QueryVTxSupported();
465 if (RT_SUCCESS(rc))
466 LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
467 else
468 {
469#ifdef RT_OS_LINUX
470 const char *pszMinReq = " Linux 2.6.13 or newer required!";
471#else
472 const char *pszMinReq = "";
473#endif
474 if (fHMForced)
475 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
476
477 /* Fall back to raw-mode. */
478 LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
479 pVM->fHMEnabled = false;
480 }
481 }
482 else
483 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
484 VERR_INTERNAL_ERROR_5);
485
486 /*
487 * Do we require a little bit or raw-mode for 64-bit guest execution?
488 */
489 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
490 && pVM->fHMEnabled
491 && pVM->hm.s.fAllow64BitGuests;
492 }
493 else
494 {
495 const char *pszMsg;
496 switch (rc)
497 {
498 case VERR_UNSUPPORTED_CPU:
499 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
500 break;
501
502 case VERR_VMX_NO_VMX:
503 pszMsg = "VT-x is not available.";
504 break;
505
506 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
507 pszMsg = "VT-x is disabled in the BIOS (or by the host OS).";
508 break;
509
510 case VERR_SVM_NO_SVM:
511 pszMsg = "AMD-V is not available.";
512 break;
513
514 case VERR_SVM_DISABLED:
515 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
516 break;
517
518 default:
519 pszMsg = NULL;
520 break;
521 }
522 if (fHMForced && pszMsg)
523 return VM_SET_ERROR(pVM, rc, pszMsg);
524 if (!pszMsg)
525 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
526
527 /* Fall back to raw-mode. */
528 LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
529 pVM->fHMEnabled = false;
530 }
531 }
532
533 /* It's now OK to use the predicate function. */
534 pVM->fHMEnabledFixed = true;
535 return VINF_SUCCESS;
536}
537
538
539/**
540 * Initializes the per-VCPU HM.
541 *
542 * @returns VBox status code.
543 * @param pVM Pointer to the VM.
544 */
545static int hmR3InitCPU(PVM pVM)
546{
547 LogFlow(("HMR3InitCPU\n"));
548
549 if (!HMIsEnabled(pVM))
550 return VINF_SUCCESS;
551
552 for (VMCPUID i = 0; i < pVM->cCpus; i++)
553 {
554 PVMCPU pVCpu = &pVM->aCpus[i];
555 pVCpu->hm.s.fActive = false;
556 }
557
558#ifdef VBOX_WITH_STATISTICS
559 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
560 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
561 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
562 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
563#endif
564
565 /*
566 * Statistics.
567 */
568 for (VMCPUID i = 0; i < pVM->cCpus; i++)
569 {
570 PVMCPU pVCpu = &pVM->aCpus[i];
571 int rc;
572
573#ifdef VBOX_WITH_STATISTICS
574 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
575 "Profiling of RTMpPokeCpu",
576 "/PROF/CPU%d/HM/Poke", i);
577 AssertRC(rc);
578 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
579 "Profiling of poke wait",
580 "/PROF/CPU%d/HM/PokeWait", i);
581 AssertRC(rc);
582 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
583 "Profiling of poke wait when RTMpPokeCpu fails",
584 "/PROF/CPU%d/HM/PokeWaitFailed", i);
585 AssertRC(rc);
586 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
587 "Profiling of VMXR0RunGuestCode entry",
588 "/PROF/CPU%d/HM/StatEntry", i);
589 AssertRC(rc);
590 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
591 "Profiling of VMXR0RunGuestCode exit part 1",
592 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
593 AssertRC(rc);
594 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
595 "Profiling of VMXR0RunGuestCode exit part 2",
596 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
597 AssertRC(rc);
598
599 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
600 "I/O",
601 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
602 AssertRC(rc);
603 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
604 "MOV CRx",
605 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
606 AssertRC(rc);
607 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
608 "Exceptions, NMIs",
609 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
610 AssertRC(rc);
611
612 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
613 "Profiling of VMXR0LoadGuestState",
614 "/PROF/CPU%d/HM/StatLoadGuestState", i);
615 AssertRC(rc);
616 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
617 "Profiling of VMLAUNCH/VMRESUME.",
618 "/PROF/CPU%d/HM/InGC", i);
619 AssertRC(rc);
620
621# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
622 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
623 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
624 "/PROF/CPU%d/HM/Switcher3264", i);
625 AssertRC(rc);
626# endif
627
628# ifdef HM_PROFILE_EXIT_DISPATCH
629 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
630 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
631 "/PROF/CPU%d/HM/ExitDispatch", i);
632 AssertRC(rc);
633# endif
634
635#endif
636# define HM_REG_COUNTER(a, b, desc) \
637 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
638 AssertRC(rc);
639
640#ifdef VBOX_WITH_STATISTICS
641 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
642 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
643 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
644 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
645 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
646 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
647 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
648 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
649 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) execption.");
650 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
651 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
652 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
653 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
654 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
655 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
656 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
657 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
658 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
659 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
660 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
661 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
662 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
663 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
664 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
665 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
666 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
667 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
668 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
669 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
670 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
671 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
672 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
673 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
674 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
675 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
676 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
677 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
678 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
679 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
680 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
681 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
682 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
683 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
684 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
685 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
686 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
687 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
688#endif
689 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
690#ifdef VBOX_WITH_STATISTICS
691 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
692 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
693 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
694 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
695 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
696
697 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
698 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
699 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
700 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
701 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
702
703 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
704 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
705 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
706
707 HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptPreempting, "/HM/CPU%d/Preempt/Preempting", "EMT has been preempted while in HM context.");
708 HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptSaveHostState, "/HM/CPU%d/Preempt/SaveHostState", "Preemption caused us to resave host state.");
709
710 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
711 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
712 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
713 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
714 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
715 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
716 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
717 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
718 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
719 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
720 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
721 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
722 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
724
725 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
726 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
727 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
728
729 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
730 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
731 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
732
733 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
734 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
735
736 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
737 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
738 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
739 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
740 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
741 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
742 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
743 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
744
745#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
746 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
747 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
748#endif
749
750 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
751 {
752 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
753 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
754 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
755 AssertRC(rc);
756 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
757 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
758 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
759 AssertRC(rc);
760 }
761
762#undef HM_REG_COUNTER
763
764 pVCpu->hm.s.paStatExitReason = NULL;
765
766 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
767 (void **)&pVCpu->hm.s.paStatExitReason);
768 AssertRC(rc);
769 if (RT_SUCCESS(rc))
770 {
771 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
772 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
773 {
774 if (papszDesc[j])
775 {
776 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
777 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
778 AssertRC(rc);
779 }
780 }
781 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
782 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
783 AssertRC(rc);
784 }
785 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
786# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
787 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
788# else
789 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
790# endif
791
792 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
793 AssertRCReturn(rc, rc);
794 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
795# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
796 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
797# else
798 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
799# endif
800 for (unsigned j = 0; j < 255; j++)
801 {
802 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
803 "Injected event.",
804 (j < 0x20) ? "/HM/CPU%d/EventInject/Event/Trap/%02X" : "/HM/CPU%d/EventInject/Event/IRQ/%02X", i, j);
805 }
806
807#endif /* VBOX_WITH_STATISTICS */
808 }
809
810#ifdef VBOX_WITH_CRASHDUMP_MAGIC
811 /*
812 * Magic marker for searching in crash dumps.
813 */
814 for (VMCPUID i = 0; i < pVM->cCpus; i++)
815 {
816 PVMCPU pVCpu = &pVM->aCpus[i];
817
818 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
819 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
820 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
821 }
822#endif
823
824 return VINF_SUCCESS;
825}
826
827
828/**
829 * Called when a init phase has completed.
830 *
831 * @returns VBox status code.
832 * @param pVM The VM.
833 * @param enmWhat The phase that completed.
834 */
835VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
836{
837 switch (enmWhat)
838 {
839 case VMINITCOMPLETED_RING3:
840 return hmR3InitCPU(pVM);
841 case VMINITCOMPLETED_RING0:
842 return hmR3InitFinalizeR0(pVM);
843 default:
844 return VINF_SUCCESS;
845 }
846}
847
848
849/**
850 * Turns off normal raw mode features.
851 *
852 * @param pVM Pointer to the VM.
853 */
854static void hmR3DisableRawMode(PVM pVM)
855{
856 /* Reinit the paging mode to force the new shadow mode. */
857 for (VMCPUID i = 0; i < pVM->cCpus; i++)
858 {
859 PVMCPU pVCpu = &pVM->aCpus[i];
860
861 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
862 }
863}
864
865
866/**
867 * Initialize VT-x or AMD-V.
868 *
869 * @returns VBox status code.
870 * @param pVM Pointer to the VM.
871 */
872static int hmR3InitFinalizeR0(PVM pVM)
873{
874 int rc;
875
876 if (!HMIsEnabled(pVM))
877 return VINF_SUCCESS;
878
879 /*
880 * Hack to allow users to work around broken BIOSes that incorrectly set
881 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
882 */
883 if ( !pVM->hm.s.vmx.fSupported
884 && !pVM->hm.s.svm.fSupported
885 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
886 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
887 {
888 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
889 pVM->hm.s.svm.fSupported = true;
890 pVM->hm.s.svm.fIgnoreInUseError = true;
891 pVM->hm.s.lLastError = VINF_SUCCESS;
892 }
893
894 /*
895 * Report ring-0 init errors.
896 */
897 if ( !pVM->hm.s.vmx.fSupported
898 && !pVM->hm.s.svm.fSupported)
899 {
900 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
901 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
902 switch (pVM->hm.s.lLastError)
903 {
904 case VERR_VMX_IN_VMX_ROOT_MODE:
905 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
906 case VERR_VMX_NO_VMX:
907 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
908 case VERR_VMX_MSR_LOCKED_OR_DISABLED:
909 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS (or by the host OS).");
910
911 case VERR_SVM_IN_USE:
912 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
913 case VERR_SVM_NO_SVM:
914 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
915 case VERR_SVM_DISABLED:
916 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
917 }
918 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
919 }
920
921 /*
922 * Enable VT-x or AMD-V on all host CPUs.
923 */
924 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
925 if (RT_FAILURE(rc))
926 {
927 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
928 return rc;
929 }
930
931 /*
932 * No TPR patching is required when the IO-APIC is not enabled for this VM.
933 * (Main should have taken care of this already)
934 */
935 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
936 if (!pVM->hm.s.fHasIoApic)
937 {
938 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
939 pVM->hm.s.fTRPPatchingAllowed = false;
940 }
941
942 /*
943 * Do the vendor specific initalization .
944 * .
945 * Note! We disable release log buffering here since we're doing relatively .
946 * lot of logging and doesn't want to hit the disk with each LogRel .
947 * statement.
948 */
949 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
950 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
951 if (pVM->hm.s.vmx.fSupported)
952 rc = hmR3InitFinalizeR0Intel(pVM);
953 else
954 rc = hmR3InitFinalizeR0Amd(pVM);
955 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
956 RTLogRelSetBuffering(fOldBuffered);
957 pVM->hm.s.fInitialized = true;
958
959 return rc;
960}
961
962
963/**
964 * Finish VT-x initialization (after ring-0 init).
965 *
966 * @returns VBox status code.
967 * @param pVM The cross context VM structure.
968 */
969static int hmR3InitFinalizeR0Intel(PVM pVM)
970{
971 int rc;
972
973 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
974 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
975
976 uint64_t val;
977 uint64_t zap;
978 RTGCPHYS GCPhys = 0;
979
980 LogRel(("HM: Using VT-x implementation 2.0!\n"));
981 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
982 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
983 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
984 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
985 LogRel(("HM: VMCS size = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
986 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
987 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
988 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
989 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", !!MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
990 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
991
992 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
993 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
994 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
995 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
996 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
997 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
998 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
999
1000 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1001 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1002 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1003 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1004 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1005 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1006 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1007 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1008 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1009 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1010 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1011 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1012 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1013 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1014 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1015 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1016 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1017 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1018 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1019 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1020 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1021 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1022 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1023 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1024 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1025 {
1026 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1027 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1028 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1029 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1030 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1031 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1032 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1033 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1034 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1035 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1036 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1037 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1038 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1039 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1040 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1041 }
1042
1043 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1044 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1045 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1046 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1047 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1048 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1049 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1050 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1051 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1052 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1053
1054 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1055 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1056 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1057 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1058 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1059 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1060 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1061 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1062 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1063 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1064 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1065 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1066
1067 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1068 {
1069 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1070 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1071 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1072 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1073 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1074 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1075 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1076 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1077 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1078 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1079 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1080 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1081 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1082 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1083 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1084 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1085 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1086 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1087 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1088 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1089 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1090 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1091 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1092 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1093 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1094 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1095 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1096 }
1097
1098 val = pVM->hm.s.vmx.Msrs.u64Misc;
1099 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1100 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1101 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1102 else
1103 {
1104 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1105 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1106 }
1107
1108 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", !!MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val)));
1109 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1110 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1111 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1112 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", !!MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val)));
1113 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", !!MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val)));
1114 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", !!MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val)));
1115 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1116
1117 /* Paranoia */
1118 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1119
1120 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1121 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1122 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1123 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1124
1125 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1126 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1127 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1128
1129 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1130 if (val)
1131 {
1132 LogRel(("HM: MSR_A32_VMX_VMFUNC = %#RX64\n", val));
1133 HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1134 }
1135
1136 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1137
1138 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1139 {
1140 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1141 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1142 }
1143
1144 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1145 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1146
1147 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1148 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1149
1150 /*
1151 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1152 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1153 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1154 */
1155 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1156 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1157 {
1158 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1159 LogRel(("HM: RDTSCP disabled.\n"));
1160 }
1161
1162 /* Unrestricted guest execution also requires EPT. */
1163 if ( pVM->hm.s.vmx.fAllowUnrestricted
1164 && pVM->hm.s.fNestedPaging
1165 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1166 {
1167 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1168 }
1169
1170 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1171 {
1172 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1173 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1174 if (RT_SUCCESS(rc))
1175 {
1176 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1177 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1178 esp. Figure 20-5.*/
1179 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1180 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1181
1182 /* Bit set to 0 means software interrupts are redirected to the
1183 8086 program interrupt handler rather than switching to
1184 protected-mode handler. */
1185 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1186
1187 /* Allow all port IO, so that port IO instructions do not cause
1188 exceptions and would instead cause a VM-exit (based on VT-x's
1189 IO bitmap which we currently configure to always cause an exit). */
1190 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1191 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1192
1193 /*
1194 * Construct a 1024 element page directory with 4 MB pages for
1195 * the identity mapped page table used in real and protected mode
1196 * without paging with EPT.
1197 */
1198 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1199 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1200 {
1201 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1202 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1203 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1204 | X86_PDE4M_G;
1205 }
1206
1207 /* We convert it here every time as pci regions could be reconfigured. */
1208 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1209 AssertRCReturn(rc, rc);
1210 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1211
1212 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1213 AssertRCReturn(rc, rc);
1214 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1215 }
1216 else
1217 {
1218 /** @todo This cannot possibly work, there are other places which assumes
1219 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1220 * a failure case. */
1221 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1222 pVM->hm.s.vmx.pRealModeTSS = NULL;
1223 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1224 }
1225 }
1226
1227 /*
1228 * Call ring-0 to set up the VM.
1229 */
1230 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1231 if (rc != VINF_SUCCESS)
1232 {
1233 AssertMsgFailed(("%Rrc\n", rc));
1234 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1235 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1236 {
1237 PVMCPU pVCpu = &pVM->aCpus[i];
1238 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1239 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1240 }
1241 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1242 }
1243
1244 LogRel(("HM: VMX enabled!\n"));
1245 pVM->hm.s.vmx.fEnabled = true;
1246
1247 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1248
1249 /*
1250 * Change the CPU features.
1251 */
1252 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1253 if (pVM->hm.s.fAllow64BitGuests)
1254 {
1255 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1256 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1257 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1258 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1259 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1260#if 0 /** @todo r=bird: This ain't making any sense whatsoever. */
1261#if RT_ARCH_X86
1262 if ( !CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1263 || !(pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE))
1264 LogRel(("NX is only supported for 64-bit guests!\n"));
1265#endif
1266#endif
1267 }
1268 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1269 (we reuse the host EFER in the switcher). */
1270 /** @todo this needs to be fixed properly!! */
1271 else if ( CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE)
1272 && (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE))
1273 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1274 else
1275 LogRel(("HM: NX not supported by the host.\n"));
1276
1277 /*
1278 * Log configuration details.
1279 */
1280 LogRel((pVM->hm.s.fAllow64BitGuests
1281 ? "HM: Guest support: 32-bit and 64-bit.\n"
1282 : "HM: Guest support: 32-bit only.\n"));
1283 if (pVM->hm.s.fNestedPaging)
1284 {
1285 LogRel(("HM: Nested paging enabled!\n"));
1286 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1287 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1288 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1289 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1290 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1291 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1292 else
1293 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1294
1295 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1296 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1297
1298#if HC_ARCH_BITS == 64
1299 if (pVM->hm.s.fLargePages)
1300 {
1301 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1302 PGMSetLargePageUsage(pVM, true);
1303 LogRel(("HM: Large page support enabled!\n"));
1304 }
1305#endif
1306 }
1307 else
1308 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1309
1310 if (pVM->hm.s.vmx.fVpid)
1311 {
1312 LogRel(("HM: VPID enabled!\n"));
1313 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1314 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1315 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1316 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1317 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1318 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1319 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1320 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1321 else
1322 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1323 }
1324 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1325 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1326
1327 /*
1328 * Check for preemption timer config override and log the state of it.
1329 */
1330 if (pVM->hm.s.vmx.fUsePreemptTimer)
1331 {
1332 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1333 rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1334 AssertLogRelRCReturn(rc, rc);
1335 }
1336 if (pVM->hm.s.vmx.fUsePreemptTimer)
1337 LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u).\n", pVM->hm.s.vmx.cPreemptTimerShift));
1338 else
1339 LogRel(("HM: VMX-preemption timer disabled.\n"));
1340
1341 return VINF_SUCCESS;
1342}
1343
1344
1345/**
1346 * Finish AMD-V initialization (after ring-0 init).
1347 *
1348 * @returns VBox status code.
1349 * @param pVM The cross context VM structure.
1350 */
1351static int hmR3InitFinalizeR0Amd(PVM pVM)
1352{
1353 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1354
1355 LogRel(("HM: Using AMD-V implementation 2.0!\n"));
1356
1357 uint32_t u32Family;
1358 uint32_t u32Model;
1359 uint32_t u32Stepping;
1360 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1361 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1362 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1363 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1364 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1365 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1366 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1367 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1368
1369 /*
1370 * Enumerate AMD-V features.
1371 */
1372 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1373 {
1374#define HMSVM_REPORT_FEATURE(a_Define) { a_Define, #a_Define }
1375 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1376 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1377 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1378 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1379 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1380 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1381 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1382 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1383 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1384 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1385 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1386#undef HMSVM_REPORT_FEATURE
1387 };
1388
1389 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1390 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1391 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1392 {
1393 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1394 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1395 }
1396 if (fSvmFeatures)
1397 for (unsigned iBit = 0; iBit < 32; iBit++)
1398 if (RT_BIT_32(iBit) & fSvmFeatures)
1399 LogRel(("HM: Reserved bit %u\n", iBit));
1400
1401 /*
1402 * Adjust feature(s).
1403 */
1404 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1405 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1406
1407 /*
1408 * Call ring-0 to set up the VM.
1409 */
1410 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1411 if (rc != VINF_SUCCESS)
1412 {
1413 AssertMsgFailed(("%Rrc\n", rc));
1414 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1415 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1416 }
1417
1418 LogRel(("HM: AMD-V enabled!\n"));
1419 pVM->hm.s.svm.fEnabled = true;
1420
1421 if (pVM->hm.s.fNestedPaging)
1422 {
1423 LogRel(("HM: Nested paging enabled!\n"));
1424
1425 /*
1426 * Enable large pages (2 MB) if applicable.
1427 */
1428#if HC_ARCH_BITS == 64
1429 if (pVM->hm.s.fLargePages)
1430 {
1431 PGMSetLargePageUsage(pVM, true);
1432 LogRel(("HM: Large page support enabled!\n"));
1433 }
1434#endif
1435 }
1436
1437 hmR3DisableRawMode(pVM);
1438
1439 /*
1440 * Change the CPU features.
1441 */
1442 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1443 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1444 if (pVM->hm.s.fAllow64BitGuests)
1445 {
1446 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1447 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1448 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1449 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1450 }
1451 /* Turn on NXE if PAE has been enabled. */
1452 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1453 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1454
1455 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1456
1457 LogRel((pVM->hm.s.fAllow64BitGuests
1458 ? "HM: Guest support: 32-bit and 64-bit.\n"
1459 : "HM: Guest support: 32-bit only.\n"));
1460
1461 return VINF_SUCCESS;
1462}
1463
1464
1465/**
1466 * Applies relocations to data and code managed by this
1467 * component. This function will be called at init and
1468 * whenever the VMM need to relocate it self inside the GC.
1469 *
1470 * @param pVM The VM.
1471 */
1472VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1473{
1474 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1475
1476 /* Fetch the current paging mode during the relocate callback during state loading. */
1477 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1478 {
1479 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1480 {
1481 PVMCPU pVCpu = &pVM->aCpus[i];
1482 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1483 }
1484 }
1485#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1486 if (HMIsEnabled(pVM))
1487 {
1488 switch (PGMGetHostMode(pVM))
1489 {
1490 case PGMMODE_32_BIT:
1491 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1492 break;
1493
1494 case PGMMODE_PAE:
1495 case PGMMODE_PAE_NX:
1496 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1497 break;
1498
1499 default:
1500 AssertFailed();
1501 break;
1502 }
1503 }
1504#endif
1505 return;
1506}
1507
1508
1509/**
1510 * Notification callback which is called whenever there is a chance that a CR3
1511 * value might have changed.
1512 *
1513 * This is called by PGM.
1514 *
1515 * @param pVM Pointer to the VM.
1516 * @param pVCpu Pointer to the VMCPU.
1517 * @param enmShadowMode New shadow paging mode.
1518 * @param enmGuestMode New guest paging mode.
1519 */
1520VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1521{
1522 /* Ignore page mode changes during state loading. */
1523 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1524 return;
1525
1526 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1527
1528 /*
1529 * If the guest left protected mode VMX execution, we'll have to be
1530 * extra careful if/when the guest switches back to protected mode.
1531 */
1532 if (enmGuestMode == PGMMODE_REAL)
1533 {
1534 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1535 pVCpu->hm.s.vmx.fWasInRealMode = true;
1536 }
1537
1538 /** @todo r=ramshankar: Disabling for now. If nothing breaks remove it
1539 * eventually. (Test platforms that use the cache ofc). */
1540#if 0
1541#ifdef VMX_USE_CACHED_VMCS_ACCESSES
1542 /* Reset the contents of the read cache. */
1543 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1544 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1545 pCache->Read.aFieldVal[j] = 0;
1546#endif
1547#endif
1548}
1549
1550
1551/**
1552 * Terminates the HM.
1553 *
1554 * Termination means cleaning up and freeing all resources,
1555 * the VM itself is, at this point, powered off or suspended.
1556 *
1557 * @returns VBox status code.
1558 * @param pVM Pointer to the VM.
1559 */
1560VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1561{
1562 if (pVM->hm.s.vmx.pRealModeTSS)
1563 {
1564 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1565 pVM->hm.s.vmx.pRealModeTSS = 0;
1566 }
1567 hmR3TermCPU(pVM);
1568 return 0;
1569}
1570
1571
1572/**
1573 * Terminates the per-VCPU HM.
1574 *
1575 * @returns VBox status code.
1576 * @param pVM Pointer to the VM.
1577 */
1578static int hmR3TermCPU(PVM pVM)
1579{
1580 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1581 {
1582 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1583
1584#ifdef VBOX_WITH_STATISTICS
1585 if (pVCpu->hm.s.paStatExitReason)
1586 {
1587 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1588 pVCpu->hm.s.paStatExitReason = NULL;
1589 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1590 }
1591 if (pVCpu->hm.s.paStatInjectedIrqs)
1592 {
1593 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1594 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1595 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1596 }
1597#endif
1598
1599#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1600 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1601 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1602 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1603#endif
1604 }
1605 return 0;
1606}
1607
1608
1609/**
1610 * Resets a virtual CPU.
1611 *
1612 * Used by HMR3Reset and CPU hot plugging.
1613 *
1614 * @param pVCpu The CPU to reset.
1615 */
1616VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1617{
1618 /* On first entry we'll sync everything. */
1619 pVCpu->hm.s.fContextUseFlags = (HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1620
1621 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1622 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1623 pVCpu->hm.s.fActive = false;
1624 pVCpu->hm.s.Event.fPending = false;
1625 pVCpu->hm.s.vmx.fWasInRealMode = true;
1626
1627 /* Reset the contents of the read cache. */
1628 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1629 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1630 pCache->Read.aFieldVal[j] = 0;
1631
1632#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1633 /* Magic marker for searching in crash dumps. */
1634 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1635 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1636#endif
1637}
1638
1639
1640/**
1641 * The VM is being reset.
1642 *
1643 * For the HM component this means that any GDT/LDT/TSS monitors
1644 * needs to be removed.
1645 *
1646 * @param pVM Pointer to the VM.
1647 */
1648VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1649{
1650 LogFlow(("HMR3Reset:\n"));
1651
1652 if (HMIsEnabled(pVM))
1653 hmR3DisableRawMode(pVM);
1654
1655 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1656 {
1657 PVMCPU pVCpu = &pVM->aCpus[i];
1658
1659 HMR3ResetCpu(pVCpu);
1660 }
1661
1662 /* Clear all patch information. */
1663 pVM->hm.s.pGuestPatchMem = 0;
1664 pVM->hm.s.pFreeGuestPatchMem = 0;
1665 pVM->hm.s.cbGuestPatchMem = 0;
1666 pVM->hm.s.cPatches = 0;
1667 pVM->hm.s.PatchTree = 0;
1668 pVM->hm.s.fTPRPatchingActive = false;
1669 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1670}
1671
1672
1673/**
1674 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1675 *
1676 * @returns VBox strict status code.
1677 * @param pVM Pointer to the VM.
1678 * @param pVCpu The VMCPU for the EMT we're being called on.
1679 * @param pvUser Unused.
1680 */
1681DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1682{
1683 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1684
1685 /* Only execute the handler on the VCPU the original patch request was issued. */
1686 if (pVCpu->idCpu != idCpu)
1687 return VINF_SUCCESS;
1688
1689 Log(("hmR3RemovePatches\n"));
1690 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1691 {
1692 uint8_t abInstr[15];
1693 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1694 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1695 int rc;
1696
1697#ifdef LOG_ENABLED
1698 char szOutput[256];
1699
1700 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1701 szOutput, sizeof(szOutput), NULL);
1702 if (RT_SUCCESS(rc))
1703 Log(("Patched instr: %s\n", szOutput));
1704#endif
1705
1706 /* Check if the instruction is still the same. */
1707 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1708 if (rc != VINF_SUCCESS)
1709 {
1710 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1711 continue; /* swapped out or otherwise removed; skip it. */
1712 }
1713
1714 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1715 {
1716 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1717 continue; /* skip it. */
1718 }
1719
1720 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1721 AssertRC(rc);
1722
1723#ifdef LOG_ENABLED
1724 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1725 szOutput, sizeof(szOutput), NULL);
1726 if (RT_SUCCESS(rc))
1727 Log(("Original instr: %s\n", szOutput));
1728#endif
1729 }
1730 pVM->hm.s.cPatches = 0;
1731 pVM->hm.s.PatchTree = 0;
1732 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1733 pVM->hm.s.fTPRPatchingActive = false;
1734 return VINF_SUCCESS;
1735}
1736
1737
1738/**
1739 * Worker for enabling patching in a VT-x/AMD-V guest.
1740 *
1741 * @returns VBox status code.
1742 * @param pVM Pointer to the VM.
1743 * @param idCpu VCPU to execute hmR3RemovePatches on.
1744 * @param pPatchMem Patch memory range.
1745 * @param cbPatchMem Size of the memory range.
1746 */
1747static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1748{
1749 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1750 AssertRC(rc);
1751
1752 pVM->hm.s.pGuestPatchMem = pPatchMem;
1753 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1754 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1755 return VINF_SUCCESS;
1756}
1757
1758
1759/**
1760 * Enable patching in a VT-x/AMD-V guest
1761 *
1762 * @returns VBox status code.
1763 * @param pVM Pointer to the VM.
1764 * @param pPatchMem Patch memory range.
1765 * @param cbPatchMem Size of the memory range.
1766 */
1767VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1768{
1769 VM_ASSERT_EMT(pVM);
1770 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1771 if (pVM->cCpus > 1)
1772 {
1773 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1774 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1775 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1776 AssertRC(rc);
1777 return rc;
1778 }
1779 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1780}
1781
1782
1783/**
1784 * Disable patching in a VT-x/AMD-V guest.
1785 *
1786 * @returns VBox status code.
1787 * @param pVM Pointer to the VM.
1788 * @param pPatchMem Patch memory range.
1789 * @param cbPatchMem Size of the memory range.
1790 */
1791VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1792{
1793 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1794
1795 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1796 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1797
1798 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1799 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1800 (void *)(uintptr_t)VMMGetCpuId(pVM));
1801 AssertRC(rc);
1802
1803 pVM->hm.s.pGuestPatchMem = 0;
1804 pVM->hm.s.pFreeGuestPatchMem = 0;
1805 pVM->hm.s.cbGuestPatchMem = 0;
1806 pVM->hm.s.fTPRPatchingActive = false;
1807 return VINF_SUCCESS;
1808}
1809
1810
1811/**
1812 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1813 *
1814 * @returns VBox strict status code.
1815 * @param pVM Pointer to the VM.
1816 * @param pVCpu The VMCPU for the EMT we're being called on.
1817 * @param pvUser User specified CPU context.
1818 *
1819 */
1820DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1821{
1822 /*
1823 * Only execute the handler on the VCPU the original patch request was
1824 * issued. (The other CPU(s) might not yet have switched to protected
1825 * mode, nor have the correct memory context.)
1826 */
1827 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1828 if (pVCpu->idCpu != idCpu)
1829 return VINF_SUCCESS;
1830
1831 /*
1832 * We're racing other VCPUs here, so don't try patch the instruction twice
1833 * and make sure there is still room for our patch record.
1834 */
1835 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1836 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1837 if (pPatch)
1838 {
1839 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1840 return VINF_SUCCESS;
1841 }
1842 uint32_t const idx = pVM->hm.s.cPatches;
1843 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1844 {
1845 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1846 return VINF_SUCCESS;
1847 }
1848 pPatch = &pVM->hm.s.aPatches[idx];
1849
1850 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1851
1852 /*
1853 * Disassembler the instruction and get cracking.
1854 */
1855 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1856 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1857 uint32_t cbOp;
1858 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1859 AssertRC(rc);
1860 if ( rc == VINF_SUCCESS
1861 && pDis->pCurInstr->uOpcode == OP_MOV
1862 && cbOp >= 3)
1863 {
1864 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1865
1866 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1867 AssertRC(rc);
1868
1869 pPatch->cbOp = cbOp;
1870
1871 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1872 {
1873 /* write. */
1874 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1875 {
1876 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1877 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1878 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1879 }
1880 else
1881 {
1882 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1883 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1884 pPatch->uSrcOperand = pDis->Param2.uValue;
1885 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1886 }
1887 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1888 AssertRC(rc);
1889
1890 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1891 pPatch->cbNewOp = sizeof(s_abVMMCall);
1892 }
1893 else
1894 {
1895 /*
1896 * TPR Read.
1897 *
1898 * Found:
1899 * mov eax, dword [fffe0080] (5 bytes)
1900 * Check if next instruction is:
1901 * shr eax, 4
1902 */
1903 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1904
1905 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1906 uint8_t const cbOpMmio = cbOp;
1907 uint64_t const uSavedRip = pCtx->rip;
1908
1909 pCtx->rip += cbOp;
1910 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1911 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1912 pCtx->rip = uSavedRip;
1913
1914 if ( rc == VINF_SUCCESS
1915 && pDis->pCurInstr->uOpcode == OP_SHR
1916 && pDis->Param1.fUse == DISUSE_REG_GEN32
1917 && pDis->Param1.Base.idxGenReg == idxMmioReg
1918 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1919 && pDis->Param2.uValue == 4
1920 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1921 {
1922 uint8_t abInstr[15];
1923
1924 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
1925 access CR8 in 32-bit mode and not cause a #VMEXIT. */
1926 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1927 AssertRC(rc);
1928
1929 pPatch->cbOp = cbOpMmio + cbOp;
1930
1931 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1932 abInstr[0] = 0xF0;
1933 abInstr[1] = 0x0F;
1934 abInstr[2] = 0x20;
1935 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1936 for (unsigned i = 4; i < pPatch->cbOp; i++)
1937 abInstr[i] = 0x90; /* nop */
1938
1939 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1940 AssertRC(rc);
1941
1942 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1943 pPatch->cbNewOp = pPatch->cbOp;
1944
1945 Log(("Acceptable read/shr candidate!\n"));
1946 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1947 }
1948 else
1949 {
1950 pPatch->enmType = HMTPRINSTR_READ;
1951 pPatch->uDstOperand = idxMmioReg;
1952
1953 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1954 AssertRC(rc);
1955
1956 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1957 pPatch->cbNewOp = sizeof(s_abVMMCall);
1958 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1959 }
1960 }
1961
1962 pPatch->Core.Key = pCtx->eip;
1963 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1964 AssertRC(rc);
1965
1966 pVM->hm.s.cPatches++;
1967 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1968 return VINF_SUCCESS;
1969 }
1970
1971 /*
1972 * Save invalid patch, so we will not try again.
1973 */
1974 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1975 pPatch->Core.Key = pCtx->eip;
1976 pPatch->enmType = HMTPRINSTR_INVALID;
1977 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1978 AssertRC(rc);
1979 pVM->hm.s.cPatches++;
1980 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1981 return VINF_SUCCESS;
1982}
1983
1984
1985/**
1986 * Callback to patch a TPR instruction (jump to generated code).
1987 *
1988 * @returns VBox strict status code.
1989 * @param pVM Pointer to the VM.
1990 * @param pVCpu The VMCPU for the EMT we're being called on.
1991 * @param pvUser User specified CPU context.
1992 *
1993 */
1994DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1995{
1996 /*
1997 * Only execute the handler on the VCPU the original patch request was
1998 * issued. (The other CPU(s) might not yet have switched to protected
1999 * mode, nor have the correct memory context.)
2000 */
2001 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2002 if (pVCpu->idCpu != idCpu)
2003 return VINF_SUCCESS;
2004
2005 /*
2006 * We're racing other VCPUs here, so don't try patch the instruction twice
2007 * and make sure there is still room for our patch record.
2008 */
2009 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2010 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2011 if (pPatch)
2012 {
2013 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2014 return VINF_SUCCESS;
2015 }
2016 uint32_t const idx = pVM->hm.s.cPatches;
2017 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2018 {
2019 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2020 return VINF_SUCCESS;
2021 }
2022 pPatch = &pVM->hm.s.aPatches[idx];
2023
2024 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2025 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2026
2027 /*
2028 * Disassemble the instruction and get cracking.
2029 */
2030 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2031 uint32_t cbOp;
2032 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2033 AssertRC(rc);
2034 if ( rc == VINF_SUCCESS
2035 && pDis->pCurInstr->uOpcode == OP_MOV
2036 && cbOp >= 5)
2037 {
2038 uint8_t aPatch[64];
2039 uint32_t off = 0;
2040
2041 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2042 AssertRC(rc);
2043
2044 pPatch->cbOp = cbOp;
2045 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2046
2047 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2048 {
2049 /*
2050 * TPR write:
2051 *
2052 * push ECX [51]
2053 * push EDX [52]
2054 * push EAX [50]
2055 * xor EDX,EDX [31 D2]
2056 * mov EAX,EAX [89 C0]
2057 * or
2058 * mov EAX,0000000CCh [B8 CC 00 00 00]
2059 * mov ECX,0C0000082h [B9 82 00 00 C0]
2060 * wrmsr [0F 30]
2061 * pop EAX [58]
2062 * pop EDX [5A]
2063 * pop ECX [59]
2064 * jmp return_address [E9 return_address]
2065 *
2066 */
2067 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2068
2069 aPatch[off++] = 0x51; /* push ecx */
2070 aPatch[off++] = 0x52; /* push edx */
2071 if (!fUsesEax)
2072 aPatch[off++] = 0x50; /* push eax */
2073 aPatch[off++] = 0x31; /* xor edx, edx */
2074 aPatch[off++] = 0xD2;
2075 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2076 {
2077 if (!fUsesEax)
2078 {
2079 aPatch[off++] = 0x89; /* mov eax, src_reg */
2080 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2081 }
2082 }
2083 else
2084 {
2085 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2086 aPatch[off++] = 0xB8; /* mov eax, immediate */
2087 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2088 off += sizeof(uint32_t);
2089 }
2090 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2091 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2092 off += sizeof(uint32_t);
2093
2094 aPatch[off++] = 0x0F; /* wrmsr */
2095 aPatch[off++] = 0x30;
2096 if (!fUsesEax)
2097 aPatch[off++] = 0x58; /* pop eax */
2098 aPatch[off++] = 0x5A; /* pop edx */
2099 aPatch[off++] = 0x59; /* pop ecx */
2100 }
2101 else
2102 {
2103 /*
2104 * TPR read:
2105 *
2106 * push ECX [51]
2107 * push EDX [52]
2108 * push EAX [50]
2109 * mov ECX,0C0000082h [B9 82 00 00 C0]
2110 * rdmsr [0F 32]
2111 * mov EAX,EAX [89 C0]
2112 * pop EAX [58]
2113 * pop EDX [5A]
2114 * pop ECX [59]
2115 * jmp return_address [E9 return_address]
2116 *
2117 */
2118 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2119
2120 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2121 aPatch[off++] = 0x51; /* push ecx */
2122 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2123 aPatch[off++] = 0x52; /* push edx */
2124 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2125 aPatch[off++] = 0x50; /* push eax */
2126
2127 aPatch[off++] = 0x31; /* xor edx, edx */
2128 aPatch[off++] = 0xD2;
2129
2130 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2131 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2132 off += sizeof(uint32_t);
2133
2134 aPatch[off++] = 0x0F; /* rdmsr */
2135 aPatch[off++] = 0x32;
2136
2137 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2138 {
2139 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2140 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2141 }
2142
2143 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2144 aPatch[off++] = 0x58; /* pop eax */
2145 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2146 aPatch[off++] = 0x5A; /* pop edx */
2147 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2148 aPatch[off++] = 0x59; /* pop ecx */
2149 }
2150 aPatch[off++] = 0xE9; /* jmp return_address */
2151 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2152 off += sizeof(RTRCUINTPTR);
2153
2154 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2155 {
2156 /* Write new code to the patch buffer. */
2157 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2158 AssertRC(rc);
2159
2160#ifdef LOG_ENABLED
2161 uint32_t cbCurInstr;
2162 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2163 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2164 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2165 {
2166 char szOutput[256];
2167 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2168 szOutput, sizeof(szOutput), &cbCurInstr);
2169 if (RT_SUCCESS(rc))
2170 Log(("Patch instr %s\n", szOutput));
2171 else
2172 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2173 }
2174#endif
2175
2176 pPatch->aNewOpcode[0] = 0xE9;
2177 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2178
2179 /* Overwrite the TPR instruction with a jump. */
2180 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2181 AssertRC(rc);
2182
2183 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2184
2185 pVM->hm.s.pFreeGuestPatchMem += off;
2186 pPatch->cbNewOp = 5;
2187
2188 pPatch->Core.Key = pCtx->eip;
2189 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2190 AssertRC(rc);
2191
2192 pVM->hm.s.cPatches++;
2193 pVM->hm.s.fTPRPatchingActive = true;
2194 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2195 return VINF_SUCCESS;
2196 }
2197
2198 Log(("Ran out of space in our patch buffer!\n"));
2199 }
2200 else
2201 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2202
2203
2204 /*
2205 * Save invalid patch, so we will not try again.
2206 */
2207 pPatch = &pVM->hm.s.aPatches[idx];
2208 pPatch->Core.Key = pCtx->eip;
2209 pPatch->enmType = HMTPRINSTR_INVALID;
2210 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2211 AssertRC(rc);
2212 pVM->hm.s.cPatches++;
2213 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2214 return VINF_SUCCESS;
2215}
2216
2217
2218/**
2219 * Attempt to patch TPR mmio instructions.
2220 *
2221 * @returns VBox status code.
2222 * @param pVM Pointer to the VM.
2223 * @param pVCpu Pointer to the VMCPU.
2224 * @param pCtx Pointer to the guest CPU context.
2225 */
2226VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2227{
2228 NOREF(pCtx);
2229 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2230 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2231 (void *)(uintptr_t)pVCpu->idCpu);
2232 AssertRC(rc);
2233 return rc;
2234}
2235
2236
2237/**
2238 * Checks if a code selector (CS) is suitable for execution
2239 * within VMX when unrestricted execution isn't available.
2240 *
2241 * @returns true if selector is suitable for VMX, otherwise
2242 * false.
2243 * @param pSel Pointer to the selector to check (CS).
2244 * uStackDpl The DPL of the stack segment.
2245 */
2246static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2247{
2248 bool rc = false;
2249
2250 do
2251 {
2252 /* Segment must be accessed. */
2253 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2254 break;
2255 /* Segment must be a code segment. */
2256 if (!(pSel->Attr.u & X86_SEL_TYPE_CODE))
2257 break;
2258 /* The S bit must be set. */
2259 if (!pSel->Attr.n.u1DescType)
2260 break;
2261 if (pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF)
2262 {
2263 /* For conforming segments, CS.DPL must be <= SS.DPL. */
2264 if (pSel->Attr.n.u2Dpl > uStackDpl)
2265 break;
2266 }
2267 else
2268 {
2269 /* For non-conforming segments, CS.DPL must equal SS.DPL. */
2270 if (pSel->Attr.n.u2Dpl != uStackDpl)
2271 break;
2272 }
2273 /* Segment must be present. */
2274 if (!pSel->Attr.n.u1Present)
2275 break;
2276 /* G bit must be set if any high limit bits are set. */
2277 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2278 break;
2279 /* G bit must be clear if any low limit bits are clear. */
2280 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2281 break;
2282
2283 rc = true;
2284 } while (0);
2285 return rc;
2286}
2287
2288
2289/**
2290 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2291 * execution within VMX when unrestricted execution isn't
2292 * available.
2293 *
2294 * @returns true if selector is suitable for VMX, otherwise
2295 * false.
2296 * @param pSel Pointer to the selector to check
2297 * (DS/ES/FS/GS).
2298 */
2299static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2300{
2301 bool rc = false;
2302
2303 /* If attributes are all zero, consider the segment unusable and therefore OK.
2304 * This logic must be in sync with HMVMXR0.cpp!
2305 */
2306 if (!pSel->Attr.u)
2307 return true;
2308
2309 do
2310 {
2311 /* Segment must be accessed. */
2312 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2313 break;
2314 /* Code segments must also be readable. */
2315 if (pSel->Attr.u & X86_SEL_TYPE_CODE && !(pSel->Attr.u & X86_SEL_TYPE_READ))
2316 break;
2317 /* The S bit must be set. */
2318 if (!pSel->Attr.n.u1DescType)
2319 break;
2320 /* Except for conforming segments, DPL >= RPL. */
2321 if (pSel->Attr.n.u4Type <= X86_SEL_TYPE_ER_ACC && pSel->Attr.n.u2Dpl < (pSel->Sel & X86_SEL_RPL))
2322 break;
2323 /* Segment must be present. */
2324 if (!pSel->Attr.n.u1Present)
2325 break;
2326 /* G bit must be set if any high limit bits are set. */
2327 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2328 break;
2329 /* G bit must be clear if any low limit bits are clear. */
2330 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2331 break;
2332
2333 rc = true;
2334 } while (0);
2335 return rc;
2336}
2337
2338
2339/**
2340 * Checks if the stack selector (SS) is suitable for execution
2341 * within VMX when unrestricted execution isn't available.
2342 *
2343 * @returns true if selector is suitable for VMX, otherwise
2344 * false.
2345 * @param pSel Pointer to the selector to check (SS).
2346 */
2347static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2348{
2349 bool rc = false;
2350
2351 /* If attributes are all zero, consider the segment unusable and therefore OK.
2352 * This logic must be in sync with HMVMXR0.cpp!
2353 */
2354 if (!pSel->Attr.u)
2355 return true;
2356
2357 do
2358 {
2359 /* Segment must be accessed. */
2360 if (!(pSel->Attr.u & X86_SEL_TYPE_ACCESSED))
2361 break;
2362 /* Segment must be writable. */
2363 if (!(pSel->Attr.u & X86_SEL_TYPE_WRITE))
2364 break;
2365 /* Segment must not be a code segment. */
2366 if (pSel->Attr.u & X86_SEL_TYPE_CODE)
2367 break;
2368 /* The S bit must be set. */
2369 if (!pSel->Attr.n.u1DescType)
2370 break;
2371 /* DPL must equal RPL. */
2372 if (pSel->Attr.n.u2Dpl != (pSel->Sel & X86_SEL_RPL))
2373 break;
2374 /* Segment must be present. */
2375 if (!pSel->Attr.n.u1Present)
2376 break;
2377 /* G bit must be set if any high limit bits are set. */
2378 if ((pSel->u32Limit & 0xfff00000) && !pSel->Attr.n.u1Granularity)
2379 break;
2380 /* G bit must be clear if any low limit bits are clear. */
2381 if ((pSel->u32Limit & 0x0fff) != 0x0fff && pSel->Attr.n.u1Granularity)
2382 break;
2383
2384 rc = true;
2385 } while (0);
2386 return rc;
2387}
2388
2389
2390/**
2391 * Force execution of the current IO code in the recompiler.
2392 *
2393 * @returns VBox status code.
2394 * @param pVM Pointer to the VM.
2395 * @param pCtx Partial VM execution context.
2396 */
2397VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2398{
2399 PVMCPU pVCpu = VMMGetCpu(pVM);
2400
2401 Assert(HMIsEnabled(pVM));
2402 Log(("HMR3EmulateIoBlock\n"));
2403
2404 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2405 if (HMCanEmulateIoBlockEx(pCtx))
2406 {
2407 Log(("HMR3EmulateIoBlock -> enabled\n"));
2408 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2409 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2410 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2411 return VINF_EM_RESCHEDULE_REM;
2412 }
2413 return VINF_SUCCESS;
2414}
2415
2416
2417/**
2418 * Checks if we can currently use hardware accelerated raw mode.
2419 *
2420 * @returns true if we can currently use hardware acceleration, otherwise false.
2421 * @param pVM Pointer to the VM.
2422 * @param pCtx Partial VM execution context.
2423 */
2424VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2425{
2426 PVMCPU pVCpu = VMMGetCpu(pVM);
2427
2428 Assert(HMIsEnabled(pVM));
2429
2430 /* If we're still executing the IO code, then return false. */
2431 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2432 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2433 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2434 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2435 return false;
2436
2437 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2438
2439 /* AMD-V supports real & protected mode with or without paging. */
2440 if (pVM->hm.s.svm.fEnabled)
2441 {
2442 pVCpu->hm.s.fActive = true;
2443 return true;
2444 }
2445
2446 pVCpu->hm.s.fActive = false;
2447
2448 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2449 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2450 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2451
2452 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2453 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2454 {
2455 /*
2456 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2457 * guest execution feature i missing (VT-x only).
2458 */
2459 if (fSupportsRealMode)
2460 {
2461 if (CPUMIsGuestInRealModeEx(pCtx))
2462 {
2463 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2464 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2465 * If this is not true, we cannot execute real mode as V86 and have to fall
2466 * back to emulation.
2467 */
2468 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2469 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2470 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2471 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2472 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2473 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2474 {
2475 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2476 return false;
2477 }
2478 if ( (pCtx->cs.u32Limit != 0xffff)
2479 || (pCtx->ds.u32Limit != 0xffff)
2480 || (pCtx->es.u32Limit != 0xffff)
2481 || (pCtx->ss.u32Limit != 0xffff)
2482 || (pCtx->fs.u32Limit != 0xffff)
2483 || (pCtx->gs.u32Limit != 0xffff))
2484 {
2485 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2486 return false;
2487 }
2488 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2489 }
2490 else
2491 {
2492 PGMMODE enmGuestMode = PGMGetGuestMode(pVCpu);
2493 /* Verify the requirements for executing code in protected
2494 mode. VT-x can't handle the CPU state right after a switch
2495 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2496 if (pVCpu->hm.s.vmx.fWasInRealMode)
2497 {
2498 /** @todo If guest is in V86 mode, these checks should be different! */
2499 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2500 {
2501 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2502 return false;
2503 }
2504 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2505 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2506 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2507 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2508 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2509 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2510 {
2511 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2512 return false;
2513 }
2514 }
2515 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2516 if (pCtx->gdtr.cbGdt)
2517 {
2518 if (pCtx->tr.Sel > pCtx->gdtr.cbGdt)
2519 {
2520 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2521 return false;
2522 }
2523 else if (pCtx->ldtr.Sel > pCtx->gdtr.cbGdt)
2524 {
2525 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2526 return false;
2527 }
2528 }
2529 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2530 }
2531 }
2532 else
2533 {
2534 if ( !CPUMIsGuestInLongModeEx(pCtx)
2535 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2536 {
2537 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2538 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2539 return false;
2540
2541 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2542 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2543 return false;
2544
2545 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2546 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2547 * hidden registers (possible recompiler bug; see load_seg_vm) */
2548 if (pCtx->cs.Attr.n.u1Present == 0)
2549 return false;
2550 if (pCtx->ss.Attr.n.u1Present == 0)
2551 return false;
2552
2553 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2554 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2555 /** @todo This check is actually wrong, it doesn't take the direction of the
2556 * stack segment into account. But, it does the job for now. */
2557 if (pCtx->rsp >= pCtx->ss.u32Limit)
2558 return false;
2559 }
2560 }
2561 }
2562
2563 if (pVM->hm.s.vmx.fEnabled)
2564 {
2565 uint32_t mask;
2566
2567 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2568 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2569 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2570 mask &= ~X86_CR0_NE;
2571
2572 if (fSupportsRealMode)
2573 {
2574 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2575 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2576 }
2577 else
2578 {
2579 /* We support protected mode without paging using identity mapping. */
2580 mask &= ~X86_CR0_PG;
2581 }
2582 if ((pCtx->cr0 & mask) != mask)
2583 return false;
2584
2585 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2586 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2587 if ((pCtx->cr0 & mask) != 0)
2588 return false;
2589
2590 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2591 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2592 mask &= ~X86_CR4_VMXE;
2593 if ((pCtx->cr4 & mask) != mask)
2594 return false;
2595
2596 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2597 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2598 if ((pCtx->cr4 & mask) != 0)
2599 return false;
2600
2601 pVCpu->hm.s.fActive = true;
2602 return true;
2603 }
2604
2605 return false;
2606}
2607
2608
2609/**
2610 * Checks if we need to reschedule due to VMM device heap changes.
2611 *
2612 * @returns true if a reschedule is required, otherwise false.
2613 * @param pVM Pointer to the VM.
2614 * @param pCtx VM execution context.
2615 */
2616VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2617{
2618 /*
2619 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2620 * when the unrestricted guest execution feature is missing (VT-x only).
2621 */
2622 if ( pVM->hm.s.vmx.fEnabled
2623 && !pVM->hm.s.vmx.fUnrestrictedGuest
2624 && CPUMIsGuestInRealModeEx(pCtx)
2625 && !PDMVmmDevHeapIsEnabled(pVM))
2626 {
2627 return true;
2628 }
2629
2630 return false;
2631}
2632
2633
2634/**
2635 * Notification from EM about a rescheduling into hardware assisted execution
2636 * mode.
2637 *
2638 * @param pVCpu Pointer to the current VMCPU.
2639 */
2640VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2641{
2642 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2643}
2644
2645
2646/**
2647 * Notification from EM about returning from instruction emulation (REM / EM).
2648 *
2649 * @param pVCpu Pointer to the VMCPU.
2650 */
2651VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2652{
2653 pVCpu->hm.s.fContextUseFlags |= HM_CHANGED_ALL_GUEST;
2654}
2655
2656
2657/**
2658 * Checks if we are currently using hardware accelerated raw mode.
2659 *
2660 * @returns true if hardware acceleration is being used, otherwise false.
2661 * @param pVCpu Pointer to the VMCPU.
2662 */
2663VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2664{
2665 return pVCpu->hm.s.fActive;
2666}
2667
2668
2669/**
2670 * External interface for querying whether hardware accelerated raw mode is
2671 * enabled.
2672 *
2673 * @returns true if VT-x or AMD-V is being used, otherwise false.
2674 * @param pUVM The user mode VM handle.
2675 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2676 */
2677VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2678{
2679 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2680 PVM pVM = pUVM->pVM;
2681 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2682 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2683}
2684
2685
2686/**
2687 * External interface for querying whether VT-x is being used.
2688 *
2689 * @returns true if VT-x is being used, otherwise false.
2690 * @param pUVM The user mode VM handle.
2691 * @sa HMR3IsSvmEnabled, HMIsEnabled
2692 */
2693VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2694{
2695 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2696 PVM pVM = pUVM->pVM;
2697 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2698 return pVM->hm.s.vmx.fEnabled
2699 && pVM->hm.s.vmx.fSupported
2700 && pVM->fHMEnabled;
2701}
2702
2703
2704/**
2705 * External interface for querying whether AMD-V is being used.
2706 *
2707 * @returns true if VT-x is being used, otherwise false.
2708 * @param pUVM The user mode VM handle.
2709 * @sa HMR3IsVmxEnabled, HMIsEnabled
2710 */
2711VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2712{
2713 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2714 PVM pVM = pUVM->pVM;
2715 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2716 return pVM->hm.s.svm.fEnabled
2717 && pVM->hm.s.svm.fSupported
2718 && pVM->fHMEnabled;
2719}
2720
2721
2722/**
2723 * Checks if we are currently using nested paging.
2724 *
2725 * @returns true if nested paging is being used, otherwise false.
2726 * @param pUVM The user mode VM handle.
2727 */
2728VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2729{
2730 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2731 PVM pVM = pUVM->pVM;
2732 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2733 return pVM->hm.s.fNestedPaging;
2734}
2735
2736
2737/**
2738 * Checks if we are currently using VPID in VT-x mode.
2739 *
2740 * @returns true if VPID is being used, otherwise false.
2741 * @param pUVM The user mode VM handle.
2742 */
2743VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2744{
2745 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2746 PVM pVM = pUVM->pVM;
2747 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2748 return pVM->hm.s.vmx.fVpid;
2749}
2750
2751
2752/**
2753 * Checks if we are currently using VT-x unrestricted execution,
2754 * aka UX.
2755 *
2756 * @returns true if UX is being used, otherwise false.
2757 * @param pUVM The user mode VM handle.
2758 */
2759VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2760{
2761 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2762 PVM pVM = pUVM->pVM;
2763 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2764 return pVM->hm.s.vmx.fUnrestrictedGuest;
2765}
2766
2767
2768/**
2769 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2770 *
2771 * @returns true if an internal event is pending, otherwise false.
2772 * @param pVM Pointer to the VM.
2773 */
2774VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2775{
2776 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2777}
2778
2779
2780/**
2781 * Checks if the VMX-preemption timer is being used.
2782 *
2783 * @returns true if the VMX-preemption timer is being used, otherwise false.
2784 * @param pVM Pointer to the VM.
2785 */
2786VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2787{
2788 return HMIsEnabled(pVM)
2789 && pVM->hm.s.vmx.fEnabled
2790 && pVM->hm.s.vmx.fUsePreemptTimer;
2791}
2792
2793
2794/**
2795 * Restart an I/O instruction that was refused in ring-0
2796 *
2797 * @returns Strict VBox status code. Informational status codes other than the one documented
2798 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2799 * @retval VINF_SUCCESS Success.
2800 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2801 * status code must be passed on to EM.
2802 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2803 *
2804 * @param pVM Pointer to the VM.
2805 * @param pVCpu Pointer to the VMCPU.
2806 * @param pCtx Pointer to the guest CPU context.
2807 */
2808VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2809{
2810 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2811
2812 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2813
2814 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2815 || enmType == HMPENDINGIO_INVALID)
2816 return VERR_NOT_FOUND;
2817
2818 VBOXSTRICTRC rcStrict;
2819 switch (enmType)
2820 {
2821 case HMPENDINGIO_PORT_READ:
2822 {
2823 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2824 uint32_t u32Val = 0;
2825
2826 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2827 &u32Val,
2828 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2829 if (IOM_SUCCESS(rcStrict))
2830 {
2831 /* Write back to the EAX register. */
2832 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2833 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2834 }
2835 break;
2836 }
2837
2838 case HMPENDINGIO_PORT_WRITE:
2839 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2840 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2841 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2842 if (IOM_SUCCESS(rcStrict))
2843 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2844 break;
2845
2846 default:
2847 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2848 }
2849
2850 if (IOM_SUCCESS(rcStrict))
2851 {
2852 /*
2853 * Check for I/O breakpoints.
2854 */
2855 uint32_t const uDr7 = pCtx->dr[7];
2856 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
2857 && X86_DR7_ANY_RW_IO(uDr7)
2858 && (pCtx->cr4 & X86_CR4_DE))
2859 || DBGFBpIsHwIoArmed(pVM))
2860 {
2861 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
2862 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2863 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
2864 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
2865 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
2866 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
2867 rcStrict = rcStrict2;
2868 }
2869 }
2870 return rcStrict;
2871}
2872
2873
2874/**
2875 * Check fatal VT-x/AMD-V error and produce some meaningful
2876 * log release message.
2877 *
2878 * @param pVM Pointer to the VM.
2879 * @param iStatusCode VBox status code.
2880 */
2881VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2882{
2883 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2884 {
2885 PVMCPU pVCpu = &pVM->aCpus[i];
2886 switch (iStatusCode)
2887 {
2888 case VERR_VMX_INVALID_VMCS_FIELD:
2889 break;
2890
2891 case VERR_VMX_INVALID_VMCS_PTR:
2892 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2893 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
2894 pVCpu->hm.s.vmx.HCPhysVmcs));
2895 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
2896 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2897 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2898 break;
2899
2900 case VERR_VMX_UNABLE_TO_START_VM:
2901 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2902 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
2903 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2904
2905 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
2906 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
2907 {
2908 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2909 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2910 }
2911 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2912 {
2913 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
2914 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
2915 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
2916 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
2917 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
2918 LogRel(("HM: CPU[%u] MSRBitmapPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
2919#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2920 LogRel(("HM: CPU[%u] GuestMSRPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
2921 LogRel(("HM: CPU[%u] HostMsrPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
2922 LogRel(("HM: CPU[%u] cGuestMSRs %u\n", i, pVCpu->hm.s.vmx.cGuestMsrs));
2923#endif
2924 }
2925 /** @todo Log VM-entry event injection control fields
2926 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2927 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2928 break;
2929
2930 case VERR_VMX_INVALID_VMXON_PTR:
2931 break;
2932
2933 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
2934 case VERR_VMX_INVALID_GUEST_STATE:
2935 case VERR_VMX_UNEXPECTED_EXIT_CODE:
2936 case VERR_SVM_UNKNOWN_EXIT:
2937 case VERR_SVM_UNEXPECTED_EXIT:
2938 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
2939 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
2940 {
2941 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
2942 break;
2943 }
2944 }
2945 }
2946
2947 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2948 {
2949 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
2950 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
2951 }
2952}
2953
2954
2955/**
2956 * Execute state save operation.
2957 *
2958 * @returns VBox status code.
2959 * @param pVM Pointer to the VM.
2960 * @param pSSM SSM operation handle.
2961 */
2962static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2963{
2964 int rc;
2965
2966 Log(("hmR3Save:\n"));
2967
2968 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2969 {
2970 /*
2971 * Save the basic bits - fortunately all the other things can be resynced on load.
2972 */
2973 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2974 AssertRCReturn(rc, rc);
2975 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2976 AssertRCReturn(rc, rc);
2977 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2978 AssertRCReturn(rc, rc);
2979
2980 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
2981 * perhaps not even that (the initial value of @c true is safe. */
2982 uint32_t u32Dummy = PGMMODE_REAL;
2983 rc = SSMR3PutU32(pSSM, u32Dummy);
2984 AssertRCReturn(rc, rc);
2985 rc = SSMR3PutU32(pSSM, u32Dummy);
2986 AssertRCReturn(rc, rc);
2987 rc = SSMR3PutU32(pSSM, u32Dummy);
2988 AssertRCReturn(rc, rc);
2989 }
2990
2991#ifdef VBOX_HM_WITH_GUEST_PATCHING
2992 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2993 AssertRCReturn(rc, rc);
2994 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
2995 AssertRCReturn(rc, rc);
2996 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
2997 AssertRCReturn(rc, rc);
2998
2999 /* Store all the guest patch records too. */
3000 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3001 AssertRCReturn(rc, rc);
3002
3003 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3004 {
3005 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3006
3007 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3008 AssertRCReturn(rc, rc);
3009
3010 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3011 AssertRCReturn(rc, rc);
3012
3013 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3014 AssertRCReturn(rc, rc);
3015
3016 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3017 AssertRCReturn(rc, rc);
3018
3019 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3020 AssertRCReturn(rc, rc);
3021
3022 AssertCompileSize(HMTPRINSTR, 4);
3023 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3024 AssertRCReturn(rc, rc);
3025
3026 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3027 AssertRCReturn(rc, rc);
3028
3029 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3030 AssertRCReturn(rc, rc);
3031
3032 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3033 AssertRCReturn(rc, rc);
3034
3035 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3036 AssertRCReturn(rc, rc);
3037 }
3038#endif
3039 return VINF_SUCCESS;
3040}
3041
3042
3043/**
3044 * Execute state load operation.
3045 *
3046 * @returns VBox status code.
3047 * @param pVM Pointer to the VM.
3048 * @param pSSM SSM operation handle.
3049 * @param uVersion Data layout version.
3050 * @param uPass The data pass.
3051 */
3052static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3053{
3054 int rc;
3055
3056 Log(("hmR3Load:\n"));
3057 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3058
3059 /*
3060 * Validate version.
3061 */
3062 if ( uVersion != HM_SSM_VERSION
3063 && uVersion != HM_SSM_VERSION_NO_PATCHING
3064 && uVersion != HM_SSM_VERSION_2_0_X)
3065 {
3066 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3067 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3068 }
3069 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3070 {
3071 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3072 AssertRCReturn(rc, rc);
3073 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3074 AssertRCReturn(rc, rc);
3075 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
3076 AssertRCReturn(rc, rc);
3077
3078 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
3079 {
3080 uint32_t val;
3081 /** @todo See note in hmR3Save(). */
3082 rc = SSMR3GetU32(pSSM, &val);
3083 AssertRCReturn(rc, rc);
3084 rc = SSMR3GetU32(pSSM, &val);
3085 AssertRCReturn(rc, rc);
3086 rc = SSMR3GetU32(pSSM, &val);
3087 AssertRCReturn(rc, rc);
3088 }
3089 }
3090#ifdef VBOX_HM_WITH_GUEST_PATCHING
3091 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
3092 {
3093 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3094 AssertRCReturn(rc, rc);
3095 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3096 AssertRCReturn(rc, rc);
3097 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3098 AssertRCReturn(rc, rc);
3099
3100 /* Fetch all TPR patch records. */
3101 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3102 AssertRCReturn(rc, rc);
3103
3104 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3105 {
3106 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3107
3108 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3109 AssertRCReturn(rc, rc);
3110
3111 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3112 AssertRCReturn(rc, rc);
3113
3114 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3115 AssertRCReturn(rc, rc);
3116
3117 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3118 AssertRCReturn(rc, rc);
3119
3120 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3121 AssertRCReturn(rc, rc);
3122
3123 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3124 AssertRCReturn(rc, rc);
3125
3126 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3127 pVM->hm.s.fTPRPatchingActive = true;
3128
3129 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3130
3131 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3132 AssertRCReturn(rc, rc);
3133
3134 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3135 AssertRCReturn(rc, rc);
3136
3137 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3138 AssertRCReturn(rc, rc);
3139
3140 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3141 AssertRCReturn(rc, rc);
3142
3143 Log(("hmR3Load: patch %d\n", i));
3144 Log(("Key = %x\n", pPatch->Core.Key));
3145 Log(("cbOp = %d\n", pPatch->cbOp));
3146 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3147 Log(("type = %d\n", pPatch->enmType));
3148 Log(("srcop = %d\n", pPatch->uSrcOperand));
3149 Log(("dstop = %d\n", pPatch->uDstOperand));
3150 Log(("cFaults = %d\n", pPatch->cFaults));
3151 Log(("target = %x\n", pPatch->pJumpTarget));
3152 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3153 AssertRC(rc);
3154 }
3155 }
3156#endif
3157
3158 return VINF_SUCCESS;
3159}
3160
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