VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 48601

Last change on this file since 48601 was 48601, checked in by vboxsync, 11 years ago

VMM/HM: Log correction.
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1/* $Id: HM.cpp 48601 2013-09-20 14:37:39Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/ssm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/csam.h>
34#include <VBox/vmm/selm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/uvm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/asm-amd64-x86.h>
50#include <iprt/string.h>
51#include <iprt/env.h>
52#include <iprt/thread.h>
53
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58#ifdef VBOX_WITH_STATISTICS
59# define EXIT_REASON(def, val, str) #def " - " #val " - " str
60# define EXIT_REASON_NIL() NULL
61/** Exit reason descriptions for VT-x, used to describe statistics. */
62static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
63{
64 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
65 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
66 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
67 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
68 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
69 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
70 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
71 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
72 EXIT_REASON_NIL(),
73 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
74 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest attempted to execute CPUID."),
75 EXIT_REASON_NIL(),
76 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest attempted to execute HLT."),
77 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest attempted to execute INVD."),
78 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest attempted to execute INVLPG."),
79 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest attempted to execute RDPMC."),
80 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest attempted to execute RDTSC."),
81 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest attempted to execute RSM in SMM."),
82 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest attempted to execute VMCALL."),
83 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest attempted to execute VMCLEAR."),
84 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest attempted to execute VMLAUNCH."),
85 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest attempted to execute VMPTRLD."),
86 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest attempted to execute VMPTRST."),
87 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest attempted to execute VMREAD."),
88 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest attempted to execute VMRESUME."),
89 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest attempted to execute VMWRITE."),
90 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest attempted to execute VMXOFF."),
91 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest attempted to execute VMXON."),
92 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
93 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
94 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
95 EXIT_REASON(VMX_EXIT_RDMSR , 31, "Guest attempted to execute RDMSR."),
96 EXIT_REASON(VMX_EXIT_WRMSR , 32, "Guest attempted to execute WRMSR."),
97 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
98 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest executed MWAIT."),
101 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest attempted to execute MONITOR."),
104 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest attempted to execute PAUSE."),
105 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest attempted to execute MOV to CR8."),
108 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest attempted to access memory at a physical address on the APIC-access page."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest attempted to execute LGDT, LIDT, SGDT, or SIDT."),
111 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest attempted to execute LLDT, LTR, SLDT, or STR."),
112 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
113 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
114 EXIT_REASON(VMX_EXIT_INVEPT , 50, "Guest attempted to execute INVEPT."),
115 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest attempted to execute RDTSCP."),
116 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
117 EXIT_REASON(VMX_EXIT_INVVPID , 53, "Guest attempted to execute INVVPID."),
118 EXIT_REASON(VMX_EXIT_WBINVD , 54, "Guest attempted to execute WBINVD."),
119 EXIT_REASON(VMX_EXIT_XSETBV , 55, "Guest attempted to execute XSETBV."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_RDRAND , 57, "Guest attempted to execute RDRAND."),
122 EXIT_REASON(VMX_EXIT_INVPCID , 58, "Guest attempted to execute INVPCID."),
123 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "Guest attempted to execute VMFUNC.")
124};
125/** Exit reason descriptions for AMD-V, used to describe statistics. */
126static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
231 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
232 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
252 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
270 EXIT_REASON_NIL()
271};
272# undef EXIT_REASON
273# undef EXIT_REASON_NIL
274#endif /* VBOX_WITH_STATISTICS */
275
276#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
277 do { \
278 if ((allowed1) & (featflag)) \
279 LogRel(("HM: " #featflag "\n")); \
280 else \
281 LogRel(("HM: " #featflag " *must* be cleared\n")); \
282 if ((disallowed0) & (featflag)) \
283 LogRel(("HM: " #featflag " *must* be set\n")); \
284 } while (0)
285
286#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, featflag) \
287 do { \
288 if ((allowed1) & (featflag)) \
289 LogRel(("HM: " #featflag "\n")); \
290 else \
291 LogRel(("HM: " #featflag " not supported\n")); \
292 } while (0)
293
294#define HMVMX_REPORT_CAPABILITY(msrcaps, cap) \
295 do { \
296 if ((msrcaps) & (cap)) \
297 LogRel(("HM: " #cap "\n")); \
298 } while (0)
299
300
301/*******************************************************************************
302* Internal Functions *
303*******************************************************************************/
304static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
305static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
306static int hmR3InitCPU(PVM pVM);
307static int hmR3InitFinalizeR0(PVM pVM);
308static int hmR3InitFinalizeR0Intel(PVM pVM);
309static int hmR3InitFinalizeR0Amd(PVM pVM);
310static int hmR3TermCPU(PVM pVM);
311
312
313
314/**
315 * Initializes the HM.
316 *
317 * This reads the config and check whether VT-x or AMD-V hardware is available
318 * if configured to use it. This is one of the very first components to be
319 * initialized after CFGM, so that we can fall back to raw-mode early in the
320 * initialization process.
321 *
322 * Note that a lot of the set up work is done in ring-0 and thus postponed till
323 * the ring-3 and ring-0 callback to HMR3InitCompleted.
324 *
325 * @returns VBox status code.
326 * @param pVM Pointer to the VM.
327 *
328 * @remarks Be careful with what we call here, since most of the VMM components
329 * are uninitialized.
330 */
331VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
332{
333 LogFlow(("HMR3Init\n"));
334
335 /*
336 * Assert alignment and sizes.
337 */
338 AssertCompileMemberAlignment(VM, hm.s, 32);
339 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
340
341 /*
342 * Register the saved state data unit.
343 */
344 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
345 NULL, NULL, NULL,
346 NULL, hmR3Save, NULL,
347 NULL, hmR3Load, NULL);
348 if (RT_FAILURE(rc))
349 return rc;
350
351 /*
352 * Misc initialisation.
353 */
354 //pVM->hm.s.vmx.fSupported = false;
355 //pVM->hm.s.svm.fSupported = false;
356 //pVM->hm.s.vmx.fEnabled = false;
357 //pVM->hm.s.svm.fEnabled = false;
358 //pVM->hm.s.fNestedPaging = false;
359
360
361 /*
362 * Read configuration.
363 */
364 PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
365
366 /** @cfgm{/HM/HMForced, bool, false}
367 * Forces hardware virtualization, no falling back on raw-mode. HM must be
368 * enabled, i.e. /HMEnabled must be true. */
369 bool fHMForced;
370#ifdef VBOX_WITH_RAW_MODE
371 rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
372 AssertRCReturn(rc, rc);
373 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
374 VERR_INVALID_PARAMETER);
375# if defined(RT_OS_DARWIN)
376 if (pVM->fHMEnabled)
377 fHMForced = true;
378# endif
379 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
380 VERR_INVALID_PARAMETER);
381 if (pVM->cCpus > 1)
382 fHMForced = true;
383#else /* !VBOX_WITH_RAW_MODE */
384 AssertRelease(pVM->fHMEnabled);
385 fHMForced = true;
386#endif /* !VBOX_WITH_RAW_MODE */
387
388 /** @cfgm{/HM/EnableNestedPaging, bool, false}
389 * Enables nested paging (aka extended page tables). */
390 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
391 AssertRCReturn(rc, rc);
392
393 /** @cfgm{/HM/EnableUX, bool, true}
394 * Enables the VT-x unrestricted execution feature. */
395 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
396 AssertRCReturn(rc, rc);
397
398 /** @cfgm{/HM/EnableLargePages, bool, false}
399 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
400 * page table walking and maybe better TLB hit rate in some cases. */
401 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
402 AssertRCReturn(rc, rc);
403
404 /** @cfgm{/HM/EnableVPID, bool, false}
405 * Enables the VT-x VPID feature. */
406 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
407 AssertRCReturn(rc, rc);
408
409 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
410 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
411 rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTRPPatchingAllowed, false);
412 AssertRCReturn(rc, rc);
413
414 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
415 * Enables AMD64 cpu features.
416 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
417 * already have the support. */
418#ifdef VBOX_ENABLE_64_BITS_GUESTS
419 rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
420 AssertLogRelRCReturn(rc, rc);
421#else
422 pVM->hm.s.fAllow64BitGuests = false;
423#endif
424
425 /** @cfgm{/HM/Exclusive, bool}
426 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
427 * global init for each host CPU. If false, we do local init each time we wish
428 * to execute guest code.
429 *
430 * Default is false for Mac OS X and Windows due to the higher risk of conflicts
431 * with other hypervisors.
432 */
433 rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
434#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
435 false
436#else
437 true
438#endif
439 );
440 AssertLogRelRCReturn(rc, rc);
441
442 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
443 * The number of times to resume guest execution before we forcibly return to
444 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445 * determines the default value. */
446 rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
447 AssertLogRelRCReturn(rc, rc);
448
449 /*
450 * Check if VT-x or AMD-v support according to the users wishes.
451 */
452 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
453 * VERR_SVM_IN_USE. */
454 if (pVM->fHMEnabled)
455 {
456 uint32_t fCaps;
457 rc = SUPR3QueryVTCaps(&fCaps);
458 if (RT_SUCCESS(rc))
459 {
460 if (fCaps & SUPVTCAPS_AMD_V)
461 LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
462 else if (fCaps & SUPVTCAPS_VT_X)
463 {
464 rc = SUPR3QueryVTxSupported();
465 if (RT_SUCCESS(rc))
466 LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
467 else
468 {
469#ifdef RT_OS_LINUX
470 const char *pszMinReq = " Linux 2.6.13 or newer required!";
471#else
472 const char *pszMinReq = "";
473#endif
474 if (fHMForced)
475 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
476
477 /* Fall back to raw-mode. */
478 LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
479 pVM->fHMEnabled = false;
480 }
481 }
482 else
483 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
484 VERR_INTERNAL_ERROR_5);
485
486 /*
487 * Do we require a little bit or raw-mode for 64-bit guest execution?
488 */
489 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
490 && pVM->fHMEnabled
491 && pVM->hm.s.fAllow64BitGuests;
492 }
493 else
494 {
495 const char *pszMsg;
496 switch (rc)
497 {
498 case VERR_UNSUPPORTED_CPU:
499 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
500 break;
501
502 case VERR_VMX_NO_VMX:
503 pszMsg = "VT-x is not available.";
504 break;
505
506 case VERR_VMX_MSR_VMXON_DISABLED:
507 pszMsg = "VT-x is disabled in the BIOS.";
508 break;
509
510 case VERR_VMX_MSR_SMX_VMXON_DISABLED:
511 pszMsg = "VT-x is disabled in the BIOS for Safer-Mode/Trusted Extensions.";
512 break;
513
514 case VERR_VMX_MSR_LOCKING_FAILED:
515 pszMsg = "Failed to enable and lock VT-x features.";
516 break;
517
518 case VERR_SVM_NO_SVM:
519 pszMsg = "AMD-V is not available.";
520 break;
521
522 case VERR_SVM_DISABLED:
523 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
524 break;
525
526 default:
527 pszMsg = NULL;
528 break;
529 }
530 if (fHMForced && pszMsg)
531 return VM_SET_ERROR(pVM, rc, pszMsg);
532 if (!pszMsg)
533 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
534
535 /* Fall back to raw-mode. */
536 LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
537 pVM->fHMEnabled = false;
538 }
539 }
540
541 /* It's now OK to use the predicate function. */
542 pVM->fHMEnabledFixed = true;
543 return VINF_SUCCESS;
544}
545
546
547/**
548 * Initializes the per-VCPU HM.
549 *
550 * @returns VBox status code.
551 * @param pVM Pointer to the VM.
552 */
553static int hmR3InitCPU(PVM pVM)
554{
555 LogFlow(("HMR3InitCPU\n"));
556
557 if (!HMIsEnabled(pVM))
558 return VINF_SUCCESS;
559
560 for (VMCPUID i = 0; i < pVM->cCpus; i++)
561 {
562 PVMCPU pVCpu = &pVM->aCpus[i];
563 pVCpu->hm.s.fActive = false;
564 }
565
566#ifdef VBOX_WITH_STATISTICS
567 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
568 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
569 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
570 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
571#endif
572
573 /*
574 * Statistics.
575 */
576 for (VMCPUID i = 0; i < pVM->cCpus; i++)
577 {
578 PVMCPU pVCpu = &pVM->aCpus[i];
579 int rc;
580
581#ifdef VBOX_WITH_STATISTICS
582 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
583 "Profiling of RTMpPokeCpu",
584 "/PROF/CPU%d/HM/Poke", i);
585 AssertRC(rc);
586 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
587 "Profiling of poke wait",
588 "/PROF/CPU%d/HM/PokeWait", i);
589 AssertRC(rc);
590 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
591 "Profiling of poke wait when RTMpPokeCpu fails",
592 "/PROF/CPU%d/HM/PokeWaitFailed", i);
593 AssertRC(rc);
594 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
595 "Profiling of VMXR0RunGuestCode entry",
596 "/PROF/CPU%d/HM/StatEntry", i);
597 AssertRC(rc);
598 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
599 "Profiling of VMXR0RunGuestCode exit part 1",
600 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
601 AssertRC(rc);
602 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
603 "Profiling of VMXR0RunGuestCode exit part 2",
604 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
605 AssertRC(rc);
606
607 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
608 "I/O",
609 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
610 AssertRC(rc);
611 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
612 "MOV CRx",
613 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
614 AssertRC(rc);
615 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
616 "Exceptions, NMIs",
617 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
618 AssertRC(rc);
619
620 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
621 "Profiling of VMXR0LoadGuestState",
622 "/PROF/CPU%d/HM/StatLoadGuestState", i);
623 AssertRC(rc);
624 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
625 "Profiling of VMLAUNCH/VMRESUME.",
626 "/PROF/CPU%d/HM/InGC", i);
627 AssertRC(rc);
628
629# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
630 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
631 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
632 "/PROF/CPU%d/HM/Switcher3264", i);
633 AssertRC(rc);
634# endif
635
636# ifdef HM_PROFILE_EXIT_DISPATCH
637 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
638 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
639 "/PROF/CPU%d/HM/ExitDispatch", i);
640 AssertRC(rc);
641# endif
642
643#endif
644# define HM_REG_COUNTER(a, b, desc) \
645 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
646 AssertRC(rc);
647
648#ifdef VBOX_WITH_STATISTICS
649 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
650 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
651 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
652 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
653 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
654 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
655 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
656 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
657 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
658 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) execption.");
659 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
660 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
661 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
662 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
663 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
664 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
665 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
666 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
667 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
668 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
669 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
670 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
671 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
672 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
673 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
674 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
675 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
676 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
677 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
678 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
679 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
680 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
681 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
682 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
683 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
684 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
685 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
686 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
687 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
688 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
689 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
690 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
691 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
692 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
693 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
694 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
695 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
696 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
697#endif
698 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
699#ifdef VBOX_WITH_STATISTICS
700 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
701 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
702 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
703 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
704 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
705
706 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
707 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
708 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
709 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
710 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
711
712 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
713 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
714 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
715
716 HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptPreempting, "/HM/CPU%d/Preempt/Preempting", "EMT has been preempted while in HM context.");
717 HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptSaveHostState, "/HM/CPU%d/Preempt/SaveHostState", "Preemption caused us to resave host state.");
718
719 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
720 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
721 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
722 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
724 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
725 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
726 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
727 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
728 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
729 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
730 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
731 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
732 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
733
734 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
735 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
736 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
737
738 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
739 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
740 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
741
742 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
743 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
744
745 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
746 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
747 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
748 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
749 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
750 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
751 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
752 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
753
754#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
755 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
756 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
757#endif
758
759 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
760 {
761 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
762 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
763 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
764 AssertRC(rc);
765 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
766 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
767 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
768 AssertRC(rc);
769 }
770
771#undef HM_REG_COUNTER
772
773 pVCpu->hm.s.paStatExitReason = NULL;
774
775 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT*sizeof(*pVCpu->hm.s.paStatExitReason), 0, MM_TAG_HM,
776 (void **)&pVCpu->hm.s.paStatExitReason);
777 AssertRC(rc);
778 if (RT_SUCCESS(rc))
779 {
780 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
781 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
782 {
783 if (papszDesc[j])
784 {
785 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
786 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
787 AssertRC(rc);
788 }
789 }
790 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
791 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
792 AssertRC(rc);
793 }
794 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
795# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
796 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
797# else
798 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
799# endif
800
801 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
802 AssertRCReturn(rc, rc);
803 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
804# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
805 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
806# else
807 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
808# endif
809 for (unsigned j = 0; j < 255; j++)
810 {
811 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
812 "Injected event.",
813 (j < 0x20) ? "/HM/CPU%d/EventInject/Event/Trap/%02X" : "/HM/CPU%d/EventInject/Event/IRQ/%02X", i, j);
814 }
815
816#endif /* VBOX_WITH_STATISTICS */
817 }
818
819#ifdef VBOX_WITH_CRASHDUMP_MAGIC
820 /*
821 * Magic marker for searching in crash dumps.
822 */
823 for (VMCPUID i = 0; i < pVM->cCpus; i++)
824 {
825 PVMCPU pVCpu = &pVM->aCpus[i];
826
827 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
828 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
829 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
830 }
831#endif
832
833 return VINF_SUCCESS;
834}
835
836
837/**
838 * Called when a init phase has completed.
839 *
840 * @returns VBox status code.
841 * @param pVM The VM.
842 * @param enmWhat The phase that completed.
843 */
844VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
845{
846 switch (enmWhat)
847 {
848 case VMINITCOMPLETED_RING3:
849 return hmR3InitCPU(pVM);
850 case VMINITCOMPLETED_RING0:
851 return hmR3InitFinalizeR0(pVM);
852 default:
853 return VINF_SUCCESS;
854 }
855}
856
857
858/**
859 * Turns off normal raw mode features.
860 *
861 * @param pVM Pointer to the VM.
862 */
863static void hmR3DisableRawMode(PVM pVM)
864{
865 /* Reinit the paging mode to force the new shadow mode. */
866 for (VMCPUID i = 0; i < pVM->cCpus; i++)
867 {
868 PVMCPU pVCpu = &pVM->aCpus[i];
869
870 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
871 }
872}
873
874
875/**
876 * Initialize VT-x or AMD-V.
877 *
878 * @returns VBox status code.
879 * @param pVM Pointer to the VM.
880 */
881static int hmR3InitFinalizeR0(PVM pVM)
882{
883 int rc;
884
885 if (!HMIsEnabled(pVM))
886 return VINF_SUCCESS;
887
888 /*
889 * Hack to allow users to work around broken BIOSes that incorrectly set
890 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
891 */
892 if ( !pVM->hm.s.vmx.fSupported
893 && !pVM->hm.s.svm.fSupported
894 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
895 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
896 {
897 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
898 pVM->hm.s.svm.fSupported = true;
899 pVM->hm.s.svm.fIgnoreInUseError = true;
900 pVM->hm.s.lLastError = VINF_SUCCESS;
901 }
902
903 /*
904 * Report ring-0 init errors.
905 */
906 if ( !pVM->hm.s.vmx.fSupported
907 && !pVM->hm.s.svm.fSupported)
908 {
909 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
910 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
911 switch (pVM->hm.s.lLastError)
912 {
913 case VERR_VMX_IN_VMX_ROOT_MODE:
914 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
915 case VERR_VMX_NO_VMX:
916 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
917 case VERR_VMX_MSR_VMXON_DISABLED:
918 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS.");
919 case VERR_VMX_MSR_SMX_VMXON_DISABLED:
920 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS for Safer-Mode/Trusted Extensions.");
921 case VERR_VMX_MSR_LOCKING_FAILED:
922 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "Failed to enable and lock VT-x features.");
923
924 case VERR_SVM_IN_USE:
925 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
926 case VERR_SVM_NO_SVM:
927 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
928 case VERR_SVM_DISABLED:
929 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
930 }
931 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
932 }
933
934 /*
935 * Enable VT-x or AMD-V on all host CPUs.
936 */
937 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
938 if (RT_FAILURE(rc))
939 {
940 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
941 return rc;
942 }
943
944 /*
945 * No TPR patching is required when the IO-APIC is not enabled for this VM.
946 * (Main should have taken care of this already)
947 */
948 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
949 if (!pVM->hm.s.fHasIoApic)
950 {
951 Assert(!pVM->hm.s.fTRPPatchingAllowed); /* paranoia */
952 pVM->hm.s.fTRPPatchingAllowed = false;
953 }
954
955 /*
956 * Do the vendor specific initalization .
957 * .
958 * Note! We disable release log buffering here since we're doing relatively .
959 * lot of logging and doesn't want to hit the disk with each LogRel .
960 * statement.
961 */
962 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
963 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
964 if (pVM->hm.s.vmx.fSupported)
965 rc = hmR3InitFinalizeR0Intel(pVM);
966 else
967 rc = hmR3InitFinalizeR0Amd(pVM);
968 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
969 RTLogRelSetBuffering(fOldBuffered);
970 pVM->hm.s.fInitialized = true;
971
972 return rc;
973}
974
975
976/**
977 * Finish VT-x initialization (after ring-0 init).
978 *
979 * @returns VBox status code.
980 * @param pVM The cross context VM structure.
981 */
982static int hmR3InitFinalizeR0Intel(PVM pVM)
983{
984 int rc;
985
986 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
987 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
988
989 uint64_t val;
990 uint64_t zap;
991 RTGCPHYS GCPhys = 0;
992
993 LogRel(("HM: Using VT-x implementation 2.0!\n"));
994 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
995 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
996 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
997 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
998 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
999 LogRel(("HM: VMCS size = %u\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1000 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1001 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1002 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1003 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1004 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1005
1006 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1007 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1008 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1009 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1010 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1011 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1012 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1013
1014 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1015 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1016 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1017 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1018 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1019 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1020 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1021 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1022 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1023 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1024 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1025 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1026 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1027 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1028 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1029 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1030 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1031 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1032 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1033 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1034 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1035 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1036 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1037 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1038 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1039 {
1040 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1041 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1042 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1043 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1044 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1045 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1046 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1047 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1048 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1049 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1050 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1051 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1052 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1053 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1054 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1055 }
1056
1057 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1058 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1059 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1060 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1061 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1062 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1063 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1064 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1065 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1066 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1067
1068 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1069 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1070 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1071 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1072 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1073 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1074 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1075 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1076 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1077 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1078 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1079 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1080
1081 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1082 {
1083 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1084 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1085 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1086 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1087 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1088 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1089 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1090 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1091 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1092 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1093 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1094 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1095 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1096 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1097 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1098 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1099 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1100 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1101 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1102 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1103 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1104 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1105 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1106 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1107 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1108 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1109 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1110 }
1111
1112 val = pVM->hm.s.vmx.Msrs.u64Misc;
1113 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1114 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1115 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1116 else
1117 {
1118 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1119 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1120 }
1121
1122 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1123 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1124 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1125 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1126 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1127 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1128 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1129 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1130
1131 /* Paranoia */
1132 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1133
1134 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1135 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1136 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1137 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1138
1139 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1140 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1141 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1142
1143 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1144 if (val)
1145 {
1146 LogRel(("HM: MSR_A32_VMX_VMFUNC = %#RX64\n", val));
1147 HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1148 }
1149
1150 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1151
1152 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1153 {
1154 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1155 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1156 }
1157
1158 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1159 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1160
1161 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1162 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1163
1164 /*
1165 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1166 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1167 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1168 */
1169 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1170 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1171 {
1172 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1173 LogRel(("HM: RDTSCP disabled.\n"));
1174 }
1175
1176 /* Unrestricted guest execution also requires EPT. */
1177 if ( pVM->hm.s.vmx.fAllowUnrestricted
1178 && pVM->hm.s.fNestedPaging
1179 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1180 {
1181 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1182 }
1183
1184 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1185 {
1186 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1187 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1188 if (RT_SUCCESS(rc))
1189 {
1190 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1191 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1192 esp. Figure 20-5.*/
1193 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1194 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1195
1196 /* Bit set to 0 means software interrupts are redirected to the
1197 8086 program interrupt handler rather than switching to
1198 protected-mode handler. */
1199 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1200
1201 /* Allow all port IO, so that port IO instructions do not cause
1202 exceptions and would instead cause a VM-exit (based on VT-x's
1203 IO bitmap which we currently configure to always cause an exit). */
1204 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1205 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1206
1207 /*
1208 * Construct a 1024 element page directory with 4 MB pages for
1209 * the identity mapped page table used in real and protected mode
1210 * without paging with EPT.
1211 */
1212 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1213 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1214 {
1215 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1216 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1217 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1218 | X86_PDE4M_G;
1219 }
1220
1221 /* We convert it here every time as pci regions could be reconfigured. */
1222 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1223 AssertRCReturn(rc, rc);
1224 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1225
1226 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1227 AssertRCReturn(rc, rc);
1228 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1229 }
1230 else
1231 {
1232 /** @todo This cannot possibly work, there are other places which assumes
1233 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1234 * a failure case. */
1235 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1236 pVM->hm.s.vmx.pRealModeTSS = NULL;
1237 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1238 }
1239 }
1240
1241 /*
1242 * Call ring-0 to set up the VM.
1243 */
1244 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1245 if (rc != VINF_SUCCESS)
1246 {
1247 AssertMsgFailed(("%Rrc\n", rc));
1248 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1249 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1250 {
1251 PVMCPU pVCpu = &pVM->aCpus[i];
1252 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1253 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1254 }
1255 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1256 }
1257
1258 LogRel(("HM: VMX enabled!\n"));
1259 pVM->hm.s.vmx.fEnabled = true;
1260
1261 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1262
1263 /*
1264 * Change the CPU features.
1265 */
1266 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1267 if (pVM->hm.s.fAllow64BitGuests)
1268 {
1269 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1270 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1271 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1272 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1273 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1274 }
1275 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1276 (we reuse the host EFER in the switcher). */
1277 /** @todo this needs to be fixed properly!! */
1278 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1279 {
1280 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1281 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1282 else
1283 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest.\n"));
1284 }
1285
1286 /*
1287 * Log configuration details.
1288 */
1289 LogRel((pVM->hm.s.fAllow64BitGuests
1290 ? "HM: Guest support: 32-bit and 64-bit.\n"
1291 : "HM: Guest support: 32-bit only.\n"));
1292 if (pVM->hm.s.fNestedPaging)
1293 {
1294 LogRel(("HM: Nested paging enabled!\n"));
1295 if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_SINGLE_CONTEXT)
1296 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_SINGLE_CONTEXT\n"));
1297 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_ALL_CONTEXTS)
1298 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_ALL_CONTEXTS\n"));
1299 else if (pVM->hm.s.vmx.enmFlushEpt == VMX_FLUSH_EPT_NOT_SUPPORTED)
1300 LogRel(("HM: EPT flush type = VMX_FLUSH_EPT_NOT_SUPPORTED\n"));
1301 else
1302 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1303
1304 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1305 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1306
1307#if HC_ARCH_BITS == 64
1308 if (pVM->hm.s.fLargePages)
1309 {
1310 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1311 PGMSetLargePageUsage(pVM, true);
1312 LogRel(("HM: Large page support enabled!\n"));
1313 }
1314#endif
1315 }
1316 else
1317 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1318
1319 if (pVM->hm.s.vmx.fVpid)
1320 {
1321 LogRel(("HM: VPID enabled!\n"));
1322 if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_INDIV_ADDR)
1323 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_INDIV_ADDR\n"));
1324 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT)
1325 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT\n"));
1326 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_ALL_CONTEXTS)
1327 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_ALL_CONTEXTS\n"));
1328 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1329 LogRel(("HM: VPID flush type = VMX_FLUSH_VPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1330 else
1331 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1332 }
1333 else if (pVM->hm.s.vmx.enmFlushVpid == VMX_FLUSH_VPID_NOT_SUPPORTED)
1334 LogRel(("HM: Ignoring VPID capabilities of CPU.\n"));
1335
1336 /*
1337 * Check for preemption timer config override and log the state of it.
1338 */
1339 if (pVM->hm.s.vmx.fUsePreemptTimer)
1340 {
1341 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1342 rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1343 AssertLogRelRCReturn(rc, rc);
1344 }
1345 if (pVM->hm.s.vmx.fUsePreemptTimer)
1346 LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u).\n", pVM->hm.s.vmx.cPreemptTimerShift));
1347 else
1348 LogRel(("HM: VMX-preemption timer disabled.\n"));
1349
1350 return VINF_SUCCESS;
1351}
1352
1353
1354/**
1355 * Finish AMD-V initialization (after ring-0 init).
1356 *
1357 * @returns VBox status code.
1358 * @param pVM The cross context VM structure.
1359 */
1360static int hmR3InitFinalizeR0Amd(PVM pVM)
1361{
1362 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1363
1364 LogRel(("HM: Using AMD-V implementation 2.0!\n"));
1365
1366 uint32_t u32Family;
1367 uint32_t u32Model;
1368 uint32_t u32Stepping;
1369 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1370 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1371 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1372 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1373 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1374 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1375 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1376 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1377
1378 /*
1379 * Enumerate AMD-V features.
1380 */
1381 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1382 {
1383#define HMSVM_REPORT_FEATURE(a_Define) { a_Define, #a_Define }
1384 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1385 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1386 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1387 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1388 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1389 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1390 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1391 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1392 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1393 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1394 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1395#undef HMSVM_REPORT_FEATURE
1396 };
1397
1398 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1399 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1400 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1401 {
1402 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1403 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1404 }
1405 if (fSvmFeatures)
1406 for (unsigned iBit = 0; iBit < 32; iBit++)
1407 if (RT_BIT_32(iBit) & fSvmFeatures)
1408 LogRel(("HM: Reserved bit %u\n", iBit));
1409
1410 /*
1411 * Adjust feature(s).
1412 */
1413 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1414 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1415
1416 /*
1417 * Call ring-0 to set up the VM.
1418 */
1419 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1420 if (rc != VINF_SUCCESS)
1421 {
1422 AssertMsgFailed(("%Rrc\n", rc));
1423 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1424 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1425 }
1426
1427 LogRel(("HM: AMD-V enabled!\n"));
1428 pVM->hm.s.svm.fEnabled = true;
1429
1430 if (pVM->hm.s.fNestedPaging)
1431 {
1432 LogRel(("HM: Nested paging enabled!\n"));
1433
1434 /*
1435 * Enable large pages (2 MB) if applicable.
1436 */
1437#if HC_ARCH_BITS == 64
1438 if (pVM->hm.s.fLargePages)
1439 {
1440 PGMSetLargePageUsage(pVM, true);
1441 LogRel(("HM: Large page support enabled!\n"));
1442 }
1443#endif
1444 }
1445
1446 hmR3DisableRawMode(pVM);
1447
1448 /*
1449 * Change the CPU features.
1450 */
1451 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1452 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1453 if (pVM->hm.s.fAllow64BitGuests)
1454 {
1455 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1456 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1457 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1458 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1459 }
1460 /* Turn on NXE if PAE has been enabled. */
1461 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1462 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1463
1464 LogRel(("HM: TPR Patching %s.\n", (pVM->hm.s.fTRPPatchingAllowed) ? "enabled" : "disabled"));
1465
1466 LogRel((pVM->hm.s.fAllow64BitGuests
1467 ? "HM: Guest support: 32-bit and 64-bit.\n"
1468 : "HM: Guest support: 32-bit only.\n"));
1469
1470 return VINF_SUCCESS;
1471}
1472
1473
1474/**
1475 * Applies relocations to data and code managed by this
1476 * component. This function will be called at init and
1477 * whenever the VMM need to relocate it self inside the GC.
1478 *
1479 * @param pVM The VM.
1480 */
1481VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1482{
1483 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1484
1485 /* Fetch the current paging mode during the relocate callback during state loading. */
1486 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1487 {
1488 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1489 {
1490 PVMCPU pVCpu = &pVM->aCpus[i];
1491 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1492 }
1493 }
1494#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1495 if (HMIsEnabled(pVM))
1496 {
1497 switch (PGMGetHostMode(pVM))
1498 {
1499 case PGMMODE_32_BIT:
1500 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1501 break;
1502
1503 case PGMMODE_PAE:
1504 case PGMMODE_PAE_NX:
1505 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1506 break;
1507
1508 default:
1509 AssertFailed();
1510 break;
1511 }
1512 }
1513#endif
1514 return;
1515}
1516
1517
1518/**
1519 * Notification callback which is called whenever there is a chance that a CR3
1520 * value might have changed.
1521 *
1522 * This is called by PGM.
1523 *
1524 * @param pVM Pointer to the VM.
1525 * @param pVCpu Pointer to the VMCPU.
1526 * @param enmShadowMode New shadow paging mode.
1527 * @param enmGuestMode New guest paging mode.
1528 */
1529VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1530{
1531 /* Ignore page mode changes during state loading. */
1532 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1533 return;
1534
1535 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1536
1537 /*
1538 * If the guest left protected mode VMX execution, we'll have to be
1539 * extra careful if/when the guest switches back to protected mode.
1540 */
1541 if (enmGuestMode == PGMMODE_REAL)
1542 {
1543 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1544 pVCpu->hm.s.vmx.fWasInRealMode = true;
1545 }
1546
1547 /** @todo r=ramshankar: Disabling for now. If nothing breaks remove it
1548 * eventually. (Test platforms that use the cache ofc). */
1549#if 0
1550#ifdef VMX_USE_CACHED_VMCS_ACCESSES
1551 /* Reset the contents of the read cache. */
1552 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1553 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1554 pCache->Read.aFieldVal[j] = 0;
1555#endif
1556#endif
1557}
1558
1559
1560/**
1561 * Terminates the HM.
1562 *
1563 * Termination means cleaning up and freeing all resources,
1564 * the VM itself is, at this point, powered off or suspended.
1565 *
1566 * @returns VBox status code.
1567 * @param pVM Pointer to the VM.
1568 */
1569VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1570{
1571 if (pVM->hm.s.vmx.pRealModeTSS)
1572 {
1573 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1574 pVM->hm.s.vmx.pRealModeTSS = 0;
1575 }
1576 hmR3TermCPU(pVM);
1577 return 0;
1578}
1579
1580
1581/**
1582 * Terminates the per-VCPU HM.
1583 *
1584 * @returns VBox status code.
1585 * @param pVM Pointer to the VM.
1586 */
1587static int hmR3TermCPU(PVM pVM)
1588{
1589 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1590 {
1591 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1592
1593#ifdef VBOX_WITH_STATISTICS
1594 if (pVCpu->hm.s.paStatExitReason)
1595 {
1596 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1597 pVCpu->hm.s.paStatExitReason = NULL;
1598 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1599 }
1600 if (pVCpu->hm.s.paStatInjectedIrqs)
1601 {
1602 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1603 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1604 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1605 }
1606#endif
1607
1608#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1609 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1610 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1611 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1612#endif
1613 }
1614 return 0;
1615}
1616
1617
1618/**
1619 * Resets a virtual CPU.
1620 *
1621 * Used by HMR3Reset and CPU hot plugging.
1622 *
1623 * @param pVCpu The CPU to reset.
1624 */
1625VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1626{
1627 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
1628 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1629 VMCPU_HMCF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1630
1631 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1632 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1633 pVCpu->hm.s.fActive = false;
1634 pVCpu->hm.s.Event.fPending = false;
1635 pVCpu->hm.s.vmx.fWasInRealMode = true;
1636
1637 /* Reset the contents of the read cache. */
1638 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1639 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1640 pCache->Read.aFieldVal[j] = 0;
1641
1642#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1643 /* Magic marker for searching in crash dumps. */
1644 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1645 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1646#endif
1647}
1648
1649
1650/**
1651 * The VM is being reset.
1652 *
1653 * For the HM component this means that any GDT/LDT/TSS monitors
1654 * needs to be removed.
1655 *
1656 * @param pVM Pointer to the VM.
1657 */
1658VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1659{
1660 LogFlow(("HMR3Reset:\n"));
1661
1662 if (HMIsEnabled(pVM))
1663 hmR3DisableRawMode(pVM);
1664
1665 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1666 {
1667 PVMCPU pVCpu = &pVM->aCpus[i];
1668
1669 HMR3ResetCpu(pVCpu);
1670 }
1671
1672 /* Clear all patch information. */
1673 pVM->hm.s.pGuestPatchMem = 0;
1674 pVM->hm.s.pFreeGuestPatchMem = 0;
1675 pVM->hm.s.cbGuestPatchMem = 0;
1676 pVM->hm.s.cPatches = 0;
1677 pVM->hm.s.PatchTree = 0;
1678 pVM->hm.s.fTPRPatchingActive = false;
1679 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1680}
1681
1682
1683/**
1684 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1685 *
1686 * @returns VBox strict status code.
1687 * @param pVM Pointer to the VM.
1688 * @param pVCpu The VMCPU for the EMT we're being called on.
1689 * @param pvUser Unused.
1690 */
1691DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1692{
1693 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1694
1695 /* Only execute the handler on the VCPU the original patch request was issued. */
1696 if (pVCpu->idCpu != idCpu)
1697 return VINF_SUCCESS;
1698
1699 Log(("hmR3RemovePatches\n"));
1700 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1701 {
1702 uint8_t abInstr[15];
1703 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1704 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1705 int rc;
1706
1707#ifdef LOG_ENABLED
1708 char szOutput[256];
1709
1710 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1711 szOutput, sizeof(szOutput), NULL);
1712 if (RT_SUCCESS(rc))
1713 Log(("Patched instr: %s\n", szOutput));
1714#endif
1715
1716 /* Check if the instruction is still the same. */
1717 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1718 if (rc != VINF_SUCCESS)
1719 {
1720 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1721 continue; /* swapped out or otherwise removed; skip it. */
1722 }
1723
1724 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1725 {
1726 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1727 continue; /* skip it. */
1728 }
1729
1730 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1731 AssertRC(rc);
1732
1733#ifdef LOG_ENABLED
1734 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1735 szOutput, sizeof(szOutput), NULL);
1736 if (RT_SUCCESS(rc))
1737 Log(("Original instr: %s\n", szOutput));
1738#endif
1739 }
1740 pVM->hm.s.cPatches = 0;
1741 pVM->hm.s.PatchTree = 0;
1742 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1743 pVM->hm.s.fTPRPatchingActive = false;
1744 return VINF_SUCCESS;
1745}
1746
1747
1748/**
1749 * Worker for enabling patching in a VT-x/AMD-V guest.
1750 *
1751 * @returns VBox status code.
1752 * @param pVM Pointer to the VM.
1753 * @param idCpu VCPU to execute hmR3RemovePatches on.
1754 * @param pPatchMem Patch memory range.
1755 * @param cbPatchMem Size of the memory range.
1756 */
1757static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1758{
1759 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1760 AssertRC(rc);
1761
1762 pVM->hm.s.pGuestPatchMem = pPatchMem;
1763 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1764 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1765 return VINF_SUCCESS;
1766}
1767
1768
1769/**
1770 * Enable patching in a VT-x/AMD-V guest
1771 *
1772 * @returns VBox status code.
1773 * @param pVM Pointer to the VM.
1774 * @param pPatchMem Patch memory range.
1775 * @param cbPatchMem Size of the memory range.
1776 */
1777VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1778{
1779 VM_ASSERT_EMT(pVM);
1780 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1781 if (pVM->cCpus > 1)
1782 {
1783 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1784 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1785 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1786 AssertRC(rc);
1787 return rc;
1788 }
1789 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1790}
1791
1792
1793/**
1794 * Disable patching in a VT-x/AMD-V guest.
1795 *
1796 * @returns VBox status code.
1797 * @param pVM Pointer to the VM.
1798 * @param pPatchMem Patch memory range.
1799 * @param cbPatchMem Size of the memory range.
1800 */
1801VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1802{
1803 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1804
1805 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1806 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1807
1808 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1809 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1810 (void *)(uintptr_t)VMMGetCpuId(pVM));
1811 AssertRC(rc);
1812
1813 pVM->hm.s.pGuestPatchMem = 0;
1814 pVM->hm.s.pFreeGuestPatchMem = 0;
1815 pVM->hm.s.cbGuestPatchMem = 0;
1816 pVM->hm.s.fTPRPatchingActive = false;
1817 return VINF_SUCCESS;
1818}
1819
1820
1821/**
1822 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1823 *
1824 * @returns VBox strict status code.
1825 * @param pVM Pointer to the VM.
1826 * @param pVCpu The VMCPU for the EMT we're being called on.
1827 * @param pvUser User specified CPU context.
1828 *
1829 */
1830DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1831{
1832 /*
1833 * Only execute the handler on the VCPU the original patch request was
1834 * issued. (The other CPU(s) might not yet have switched to protected
1835 * mode, nor have the correct memory context.)
1836 */
1837 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1838 if (pVCpu->idCpu != idCpu)
1839 return VINF_SUCCESS;
1840
1841 /*
1842 * We're racing other VCPUs here, so don't try patch the instruction twice
1843 * and make sure there is still room for our patch record.
1844 */
1845 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1846 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1847 if (pPatch)
1848 {
1849 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1850 return VINF_SUCCESS;
1851 }
1852 uint32_t const idx = pVM->hm.s.cPatches;
1853 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1854 {
1855 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1856 return VINF_SUCCESS;
1857 }
1858 pPatch = &pVM->hm.s.aPatches[idx];
1859
1860 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1861
1862 /*
1863 * Disassembler the instruction and get cracking.
1864 */
1865 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1866 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1867 uint32_t cbOp;
1868 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1869 AssertRC(rc);
1870 if ( rc == VINF_SUCCESS
1871 && pDis->pCurInstr->uOpcode == OP_MOV
1872 && cbOp >= 3)
1873 {
1874 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1875
1876 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1877 AssertRC(rc);
1878
1879 pPatch->cbOp = cbOp;
1880
1881 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1882 {
1883 /* write. */
1884 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1885 {
1886 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1887 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1888 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1889 }
1890 else
1891 {
1892 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1893 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1894 pPatch->uSrcOperand = pDis->Param2.uValue;
1895 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1896 }
1897 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1898 AssertRC(rc);
1899
1900 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1901 pPatch->cbNewOp = sizeof(s_abVMMCall);
1902 }
1903 else
1904 {
1905 /*
1906 * TPR Read.
1907 *
1908 * Found:
1909 * mov eax, dword [fffe0080] (5 bytes)
1910 * Check if next instruction is:
1911 * shr eax, 4
1912 */
1913 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1914
1915 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1916 uint8_t const cbOpMmio = cbOp;
1917 uint64_t const uSavedRip = pCtx->rip;
1918
1919 pCtx->rip += cbOp;
1920 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1921 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1922 pCtx->rip = uSavedRip;
1923
1924 if ( rc == VINF_SUCCESS
1925 && pDis->pCurInstr->uOpcode == OP_SHR
1926 && pDis->Param1.fUse == DISUSE_REG_GEN32
1927 && pDis->Param1.Base.idxGenReg == idxMmioReg
1928 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1929 && pDis->Param2.uValue == 4
1930 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1931 {
1932 uint8_t abInstr[15];
1933
1934 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
1935 access CR8 in 32-bit mode and not cause a #VMEXIT. */
1936 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1937 AssertRC(rc);
1938
1939 pPatch->cbOp = cbOpMmio + cbOp;
1940
1941 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1942 abInstr[0] = 0xF0;
1943 abInstr[1] = 0x0F;
1944 abInstr[2] = 0x20;
1945 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1946 for (unsigned i = 4; i < pPatch->cbOp; i++)
1947 abInstr[i] = 0x90; /* nop */
1948
1949 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1950 AssertRC(rc);
1951
1952 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1953 pPatch->cbNewOp = pPatch->cbOp;
1954
1955 Log(("Acceptable read/shr candidate!\n"));
1956 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1957 }
1958 else
1959 {
1960 pPatch->enmType = HMTPRINSTR_READ;
1961 pPatch->uDstOperand = idxMmioReg;
1962
1963 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1964 AssertRC(rc);
1965
1966 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1967 pPatch->cbNewOp = sizeof(s_abVMMCall);
1968 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1969 }
1970 }
1971
1972 pPatch->Core.Key = pCtx->eip;
1973 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1974 AssertRC(rc);
1975
1976 pVM->hm.s.cPatches++;
1977 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1978 return VINF_SUCCESS;
1979 }
1980
1981 /*
1982 * Save invalid patch, so we will not try again.
1983 */
1984 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1985 pPatch->Core.Key = pCtx->eip;
1986 pPatch->enmType = HMTPRINSTR_INVALID;
1987 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1988 AssertRC(rc);
1989 pVM->hm.s.cPatches++;
1990 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1991 return VINF_SUCCESS;
1992}
1993
1994
1995/**
1996 * Callback to patch a TPR instruction (jump to generated code).
1997 *
1998 * @returns VBox strict status code.
1999 * @param pVM Pointer to the VM.
2000 * @param pVCpu The VMCPU for the EMT we're being called on.
2001 * @param pvUser User specified CPU context.
2002 *
2003 */
2004DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2005{
2006 /*
2007 * Only execute the handler on the VCPU the original patch request was
2008 * issued. (The other CPU(s) might not yet have switched to protected
2009 * mode, nor have the correct memory context.)
2010 */
2011 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2012 if (pVCpu->idCpu != idCpu)
2013 return VINF_SUCCESS;
2014
2015 /*
2016 * We're racing other VCPUs here, so don't try patch the instruction twice
2017 * and make sure there is still room for our patch record.
2018 */
2019 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2020 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2021 if (pPatch)
2022 {
2023 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2024 return VINF_SUCCESS;
2025 }
2026 uint32_t const idx = pVM->hm.s.cPatches;
2027 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2028 {
2029 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2030 return VINF_SUCCESS;
2031 }
2032 pPatch = &pVM->hm.s.aPatches[idx];
2033
2034 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2035 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2036
2037 /*
2038 * Disassemble the instruction and get cracking.
2039 */
2040 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2041 uint32_t cbOp;
2042 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2043 AssertRC(rc);
2044 if ( rc == VINF_SUCCESS
2045 && pDis->pCurInstr->uOpcode == OP_MOV
2046 && cbOp >= 5)
2047 {
2048 uint8_t aPatch[64];
2049 uint32_t off = 0;
2050
2051 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2052 AssertRC(rc);
2053
2054 pPatch->cbOp = cbOp;
2055 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2056
2057 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2058 {
2059 /*
2060 * TPR write:
2061 *
2062 * push ECX [51]
2063 * push EDX [52]
2064 * push EAX [50]
2065 * xor EDX,EDX [31 D2]
2066 * mov EAX,EAX [89 C0]
2067 * or
2068 * mov EAX,0000000CCh [B8 CC 00 00 00]
2069 * mov ECX,0C0000082h [B9 82 00 00 C0]
2070 * wrmsr [0F 30]
2071 * pop EAX [58]
2072 * pop EDX [5A]
2073 * pop ECX [59]
2074 * jmp return_address [E9 return_address]
2075 *
2076 */
2077 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2078
2079 aPatch[off++] = 0x51; /* push ecx */
2080 aPatch[off++] = 0x52; /* push edx */
2081 if (!fUsesEax)
2082 aPatch[off++] = 0x50; /* push eax */
2083 aPatch[off++] = 0x31; /* xor edx, edx */
2084 aPatch[off++] = 0xD2;
2085 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2086 {
2087 if (!fUsesEax)
2088 {
2089 aPatch[off++] = 0x89; /* mov eax, src_reg */
2090 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2091 }
2092 }
2093 else
2094 {
2095 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2096 aPatch[off++] = 0xB8; /* mov eax, immediate */
2097 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2098 off += sizeof(uint32_t);
2099 }
2100 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2101 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2102 off += sizeof(uint32_t);
2103
2104 aPatch[off++] = 0x0F; /* wrmsr */
2105 aPatch[off++] = 0x30;
2106 if (!fUsesEax)
2107 aPatch[off++] = 0x58; /* pop eax */
2108 aPatch[off++] = 0x5A; /* pop edx */
2109 aPatch[off++] = 0x59; /* pop ecx */
2110 }
2111 else
2112 {
2113 /*
2114 * TPR read:
2115 *
2116 * push ECX [51]
2117 * push EDX [52]
2118 * push EAX [50]
2119 * mov ECX,0C0000082h [B9 82 00 00 C0]
2120 * rdmsr [0F 32]
2121 * mov EAX,EAX [89 C0]
2122 * pop EAX [58]
2123 * pop EDX [5A]
2124 * pop ECX [59]
2125 * jmp return_address [E9 return_address]
2126 *
2127 */
2128 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2129
2130 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2131 aPatch[off++] = 0x51; /* push ecx */
2132 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2133 aPatch[off++] = 0x52; /* push edx */
2134 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2135 aPatch[off++] = 0x50; /* push eax */
2136
2137 aPatch[off++] = 0x31; /* xor edx, edx */
2138 aPatch[off++] = 0xD2;
2139
2140 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2141 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2142 off += sizeof(uint32_t);
2143
2144 aPatch[off++] = 0x0F; /* rdmsr */
2145 aPatch[off++] = 0x32;
2146
2147 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2148 {
2149 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2150 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2151 }
2152
2153 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2154 aPatch[off++] = 0x58; /* pop eax */
2155 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2156 aPatch[off++] = 0x5A; /* pop edx */
2157 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2158 aPatch[off++] = 0x59; /* pop ecx */
2159 }
2160 aPatch[off++] = 0xE9; /* jmp return_address */
2161 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2162 off += sizeof(RTRCUINTPTR);
2163
2164 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2165 {
2166 /* Write new code to the patch buffer. */
2167 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2168 AssertRC(rc);
2169
2170#ifdef LOG_ENABLED
2171 uint32_t cbCurInstr;
2172 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2173 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2174 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2175 {
2176 char szOutput[256];
2177 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2178 szOutput, sizeof(szOutput), &cbCurInstr);
2179 if (RT_SUCCESS(rc))
2180 Log(("Patch instr %s\n", szOutput));
2181 else
2182 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2183 }
2184#endif
2185
2186 pPatch->aNewOpcode[0] = 0xE9;
2187 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2188
2189 /* Overwrite the TPR instruction with a jump. */
2190 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2191 AssertRC(rc);
2192
2193 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2194
2195 pVM->hm.s.pFreeGuestPatchMem += off;
2196 pPatch->cbNewOp = 5;
2197
2198 pPatch->Core.Key = pCtx->eip;
2199 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2200 AssertRC(rc);
2201
2202 pVM->hm.s.cPatches++;
2203 pVM->hm.s.fTPRPatchingActive = true;
2204 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2205 return VINF_SUCCESS;
2206 }
2207
2208 Log(("Ran out of space in our patch buffer!\n"));
2209 }
2210 else
2211 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2212
2213
2214 /*
2215 * Save invalid patch, so we will not try again.
2216 */
2217 pPatch = &pVM->hm.s.aPatches[idx];
2218 pPatch->Core.Key = pCtx->eip;
2219 pPatch->enmType = HMTPRINSTR_INVALID;
2220 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2221 AssertRC(rc);
2222 pVM->hm.s.cPatches++;
2223 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2224 return VINF_SUCCESS;
2225}
2226
2227
2228/**
2229 * Attempt to patch TPR mmio instructions.
2230 *
2231 * @returns VBox status code.
2232 * @param pVM Pointer to the VM.
2233 * @param pVCpu Pointer to the VMCPU.
2234 * @param pCtx Pointer to the guest CPU context.
2235 */
2236VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2237{
2238 NOREF(pCtx);
2239 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2240 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2241 (void *)(uintptr_t)pVCpu->idCpu);
2242 AssertRC(rc);
2243 return rc;
2244}
2245
2246
2247/**
2248 * Checks if a code selector (CS) is suitable for execution
2249 * within VMX when unrestricted execution isn't available.
2250 *
2251 * @returns true if selector is suitable for VMX, otherwise
2252 * false.
2253 * @param pSel Pointer to the selector to check (CS).
2254 * uStackDpl The CPL, aka the DPL of the stack segment.
2255 */
2256static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2257{
2258 /*
2259 * Segment must be an accessed code segment, it must be present and it must
2260 * be usable.
2261 * Note! These are all standard requirements and if CS holds anything else
2262 * we've got buggy code somewhere!
2263 */
2264 AssertCompile(X86DESCATTR_TYPE == 0xf);
2265 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2266 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2267 ("%#x\n", pSel->Attr.u),
2268 false);
2269
2270 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2271 must equal SS.DPL for non-confroming segments.
2272 Note! This is also a hard requirement like above. */
2273 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2274 ? pSel->Attr.n.u2Dpl <= uStackDpl
2275 : pSel->Attr.n.u2Dpl == uStackDpl,
2276 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2277 false);
2278
2279 /*
2280 * The following two requirements are VT-x specific:
2281 * - G bit must be set if any high limit bits are set.
2282 * - G bit must be clear if any low limit bits are clear.
2283 */
2284 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2285 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2286 return true;
2287 return false;
2288}
2289
2290
2291/**
2292 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2293 * execution within VMX when unrestricted execution isn't
2294 * available.
2295 *
2296 * @returns true if selector is suitable for VMX, otherwise
2297 * false.
2298 * @param pSel Pointer to the selector to check
2299 * (DS/ES/FS/GS).
2300 */
2301static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2302{
2303 /*
2304 * Unusable segments are OK. These days they should be marked as such, as
2305 * but as an alternative we for old saved states and AMD<->VT-x migration
2306 * we also treat segments with all the attributes cleared as unusable.
2307 */
2308 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2309 return true;
2310
2311 /** @todo tighten these checks. Will require CPUM load adjusting. */
2312
2313 /* Segment must be accessed. */
2314 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2315 {
2316 /* Code segments must also be readable. */
2317 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2318 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2319 {
2320 /* The S bit must be set. */
2321 if (pSel->Attr.n.u1DescType)
2322 {
2323 /* Except for conforming segments, DPL >= RPL. */
2324 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2325 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2326 {
2327 /* Segment must be present. */
2328 if (pSel->Attr.n.u1Present)
2329 {
2330 /*
2331 * The following two requirements are VT-x specific:
2332 * - G bit must be set if any high limit bits are set.
2333 * - G bit must be clear if any low limit bits are clear.
2334 */
2335 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2336 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2337 return true;
2338 }
2339 }
2340 }
2341 }
2342 }
2343
2344 return false;
2345}
2346
2347
2348/**
2349 * Checks if the stack selector (SS) is suitable for execution
2350 * within VMX when unrestricted execution isn't available.
2351 *
2352 * @returns true if selector is suitable for VMX, otherwise
2353 * false.
2354 * @param pSel Pointer to the selector to check (SS).
2355 */
2356static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2357{
2358 /*
2359 * Unusable segments are OK. These days they should be marked as such, as
2360 * but as an alternative we for old saved states and AMD<->VT-x migration
2361 * we also treat segments with all the attributes cleared as unusable.
2362 */
2363 /** @todo r=bird: actually all zeros isn't gonna cut it... SS.DPL == CPL. */
2364 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2365 return true;
2366
2367 /*
2368 * Segment must be an accessed writable segment, it must be present.
2369 * Note! These are all standard requirements and if SS holds anything else
2370 * we've got buggy code somewhere!
2371 */
2372 AssertCompile(X86DESCATTR_TYPE == 0xf);
2373 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2374 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2375 ("%#x\n", pSel->Attr.u),
2376 false);
2377
2378 /* DPL must equal RPL.
2379 Note! This is also a hard requirement like above. */
2380 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2381 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2382 false);
2383
2384 /*
2385 * The following two requirements are VT-x specific:
2386 * - G bit must be set if any high limit bits are set.
2387 * - G bit must be clear if any low limit bits are clear.
2388 */
2389 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2390 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2391 return true;
2392 return false;
2393}
2394
2395
2396/**
2397 * Force execution of the current IO code in the recompiler.
2398 *
2399 * @returns VBox status code.
2400 * @param pVM Pointer to the VM.
2401 * @param pCtx Partial VM execution context.
2402 */
2403VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2404{
2405 PVMCPU pVCpu = VMMGetCpu(pVM);
2406
2407 Assert(HMIsEnabled(pVM));
2408 Log(("HMR3EmulateIoBlock\n"));
2409
2410 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2411 if (HMCanEmulateIoBlockEx(pCtx))
2412 {
2413 Log(("HMR3EmulateIoBlock -> enabled\n"));
2414 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2415 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2416 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2417 return VINF_EM_RESCHEDULE_REM;
2418 }
2419 return VINF_SUCCESS;
2420}
2421
2422
2423/**
2424 * Checks if we can currently use hardware accelerated raw mode.
2425 *
2426 * @returns true if we can currently use hardware acceleration, otherwise false.
2427 * @param pVM Pointer to the VM.
2428 * @param pCtx Partial VM execution context.
2429 */
2430VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2431{
2432 PVMCPU pVCpu = VMMGetCpu(pVM);
2433
2434 Assert(HMIsEnabled(pVM));
2435
2436 /* If we're still executing the IO code, then return false. */
2437 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2438 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2439 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2440 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2441 return false;
2442
2443 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2444
2445 /* AMD-V supports real & protected mode with or without paging. */
2446 if (pVM->hm.s.svm.fEnabled)
2447 {
2448 pVCpu->hm.s.fActive = true;
2449 return true;
2450 }
2451
2452 pVCpu->hm.s.fActive = false;
2453
2454 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2455 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2456 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2457
2458 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2459 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2460 {
2461 /*
2462 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2463 * guest execution feature i missing (VT-x only).
2464 */
2465 if (fSupportsRealMode)
2466 {
2467 if (CPUMIsGuestInRealModeEx(pCtx))
2468 {
2469 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2470 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2471 * If this is not true, we cannot execute real mode as V86 and have to fall
2472 * back to emulation.
2473 */
2474 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2475 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2476 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2477 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2478 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2479 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2480 {
2481 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2482 return false;
2483 }
2484 if ( (pCtx->cs.u32Limit != 0xffff)
2485 || (pCtx->ds.u32Limit != 0xffff)
2486 || (pCtx->es.u32Limit != 0xffff)
2487 || (pCtx->ss.u32Limit != 0xffff)
2488 || (pCtx->fs.u32Limit != 0xffff)
2489 || (pCtx->gs.u32Limit != 0xffff))
2490 {
2491 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2492 return false;
2493 }
2494 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2495 }
2496 else
2497 {
2498 /* Verify the requirements for executing code in protected
2499 mode. VT-x can't handle the CPU state right after a switch
2500 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2501 if (pVCpu->hm.s.vmx.fWasInRealMode)
2502 {
2503 /** @todo If guest is in V86 mode, these checks should be different! */
2504 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2505 {
2506 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2507 return false;
2508 }
2509 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2510 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2511 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2512 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2513 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2514 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2515 {
2516 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2517 return false;
2518 }
2519 }
2520 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2521 if (pCtx->gdtr.cbGdt)
2522 {
2523 if (pCtx->tr.Sel > pCtx->gdtr.cbGdt)
2524 {
2525 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2526 return false;
2527 }
2528 else if (pCtx->ldtr.Sel > pCtx->gdtr.cbGdt)
2529 {
2530 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2531 return false;
2532 }
2533 }
2534 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2535 }
2536 }
2537 else
2538 {
2539 if ( !CPUMIsGuestInLongModeEx(pCtx)
2540 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2541 {
2542 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2543 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2544 return false;
2545
2546 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2547 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2548 return false;
2549
2550 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2551 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2552 * hidden registers (possible recompiler bug; see load_seg_vm) */
2553 if (pCtx->cs.Attr.n.u1Present == 0)
2554 return false;
2555 if (pCtx->ss.Attr.n.u1Present == 0)
2556 return false;
2557
2558 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2559 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2560 /** @todo This check is actually wrong, it doesn't take the direction of the
2561 * stack segment into account. But, it does the job for now. */
2562 if (pCtx->rsp >= pCtx->ss.u32Limit)
2563 return false;
2564 }
2565 }
2566 }
2567
2568 if (pVM->hm.s.vmx.fEnabled)
2569 {
2570 uint32_t mask;
2571
2572 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2573 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2574 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2575 mask &= ~X86_CR0_NE;
2576
2577 if (fSupportsRealMode)
2578 {
2579 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2580 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2581 }
2582 else
2583 {
2584 /* We support protected mode without paging using identity mapping. */
2585 mask &= ~X86_CR0_PG;
2586 }
2587 if ((pCtx->cr0 & mask) != mask)
2588 return false;
2589
2590 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2591 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2592 if ((pCtx->cr0 & mask) != 0)
2593 return false;
2594
2595 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2596 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2597 mask &= ~X86_CR4_VMXE;
2598 if ((pCtx->cr4 & mask) != mask)
2599 return false;
2600
2601 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2602 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2603 if ((pCtx->cr4 & mask) != 0)
2604 return false;
2605
2606 pVCpu->hm.s.fActive = true;
2607 return true;
2608 }
2609
2610 return false;
2611}
2612
2613
2614/**
2615 * Checks if we need to reschedule due to VMM device heap changes.
2616 *
2617 * @returns true if a reschedule is required, otherwise false.
2618 * @param pVM Pointer to the VM.
2619 * @param pCtx VM execution context.
2620 */
2621VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2622{
2623 /*
2624 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2625 * when the unrestricted guest execution feature is missing (VT-x only).
2626 */
2627 if ( pVM->hm.s.vmx.fEnabled
2628 && !pVM->hm.s.vmx.fUnrestrictedGuest
2629 && CPUMIsGuestInRealModeEx(pCtx)
2630 && !PDMVmmDevHeapIsEnabled(pVM))
2631 {
2632 return true;
2633 }
2634
2635 return false;
2636}
2637
2638
2639/**
2640 * Notification from EM about a rescheduling into hardware assisted execution
2641 * mode.
2642 *
2643 * @param pVCpu Pointer to the current VMCPU.
2644 */
2645VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2646{
2647 VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2648}
2649
2650
2651/**
2652 * Notification from EM about returning from instruction emulation (REM / EM).
2653 *
2654 * @param pVCpu Pointer to the VMCPU.
2655 */
2656VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2657{
2658 VMCPU_HMCF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2659}
2660
2661
2662/**
2663 * Checks if we are currently using hardware accelerated raw mode.
2664 *
2665 * @returns true if hardware acceleration is being used, otherwise false.
2666 * @param pVCpu Pointer to the VMCPU.
2667 */
2668VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2669{
2670 return pVCpu->hm.s.fActive;
2671}
2672
2673
2674/**
2675 * External interface for querying whether hardware accelerated raw mode is
2676 * enabled.
2677 *
2678 * @returns true if VT-x or AMD-V is being used, otherwise false.
2679 * @param pUVM The user mode VM handle.
2680 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2681 */
2682VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2683{
2684 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2685 PVM pVM = pUVM->pVM;
2686 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2687 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2688}
2689
2690
2691/**
2692 * External interface for querying whether VT-x is being used.
2693 *
2694 * @returns true if VT-x is being used, otherwise false.
2695 * @param pUVM The user mode VM handle.
2696 * @sa HMR3IsSvmEnabled, HMIsEnabled
2697 */
2698VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2699{
2700 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2701 PVM pVM = pUVM->pVM;
2702 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2703 return pVM->hm.s.vmx.fEnabled
2704 && pVM->hm.s.vmx.fSupported
2705 && pVM->fHMEnabled;
2706}
2707
2708
2709/**
2710 * External interface for querying whether AMD-V is being used.
2711 *
2712 * @returns true if VT-x is being used, otherwise false.
2713 * @param pUVM The user mode VM handle.
2714 * @sa HMR3IsVmxEnabled, HMIsEnabled
2715 */
2716VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2717{
2718 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2719 PVM pVM = pUVM->pVM;
2720 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2721 return pVM->hm.s.svm.fEnabled
2722 && pVM->hm.s.svm.fSupported
2723 && pVM->fHMEnabled;
2724}
2725
2726
2727/**
2728 * Checks if we are currently using nested paging.
2729 *
2730 * @returns true if nested paging is being used, otherwise false.
2731 * @param pUVM The user mode VM handle.
2732 */
2733VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2734{
2735 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2736 PVM pVM = pUVM->pVM;
2737 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2738 return pVM->hm.s.fNestedPaging;
2739}
2740
2741
2742/**
2743 * Checks if we are currently using VPID in VT-x mode.
2744 *
2745 * @returns true if VPID is being used, otherwise false.
2746 * @param pUVM The user mode VM handle.
2747 */
2748VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2749{
2750 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2751 PVM pVM = pUVM->pVM;
2752 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2753 return pVM->hm.s.vmx.fVpid;
2754}
2755
2756
2757/**
2758 * Checks if we are currently using VT-x unrestricted execution,
2759 * aka UX.
2760 *
2761 * @returns true if UX is being used, otherwise false.
2762 * @param pUVM The user mode VM handle.
2763 */
2764VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2765{
2766 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2767 PVM pVM = pUVM->pVM;
2768 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2769 return pVM->hm.s.vmx.fUnrestrictedGuest;
2770}
2771
2772
2773/**
2774 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2775 *
2776 * @returns true if an internal event is pending, otherwise false.
2777 * @param pVM Pointer to the VM.
2778 */
2779VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2780{
2781 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2782}
2783
2784
2785/**
2786 * Checks if the VMX-preemption timer is being used.
2787 *
2788 * @returns true if the VMX-preemption timer is being used, otherwise false.
2789 * @param pVM Pointer to the VM.
2790 */
2791VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2792{
2793 return HMIsEnabled(pVM)
2794 && pVM->hm.s.vmx.fEnabled
2795 && pVM->hm.s.vmx.fUsePreemptTimer;
2796}
2797
2798
2799/**
2800 * Restart an I/O instruction that was refused in ring-0
2801 *
2802 * @returns Strict VBox status code. Informational status codes other than the one documented
2803 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2804 * @retval VINF_SUCCESS Success.
2805 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2806 * status code must be passed on to EM.
2807 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2808 *
2809 * @param pVM Pointer to the VM.
2810 * @param pVCpu Pointer to the VMCPU.
2811 * @param pCtx Pointer to the guest CPU context.
2812 */
2813VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2814{
2815 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2816
2817 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2818
2819 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2820 || enmType == HMPENDINGIO_INVALID)
2821 return VERR_NOT_FOUND;
2822
2823 VBOXSTRICTRC rcStrict;
2824 switch (enmType)
2825 {
2826 case HMPENDINGIO_PORT_READ:
2827 {
2828 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2829 uint32_t u32Val = 0;
2830
2831 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2832 &u32Val,
2833 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2834 if (IOM_SUCCESS(rcStrict))
2835 {
2836 /* Write back to the EAX register. */
2837 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2838 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2839 }
2840 break;
2841 }
2842
2843 case HMPENDINGIO_PORT_WRITE:
2844 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2845 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2846 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2847 if (IOM_SUCCESS(rcStrict))
2848 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2849 break;
2850
2851 default:
2852 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2853 }
2854
2855 if (IOM_SUCCESS(rcStrict))
2856 {
2857 /*
2858 * Check for I/O breakpoints.
2859 */
2860 uint32_t const uDr7 = pCtx->dr[7];
2861 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
2862 && X86_DR7_ANY_RW_IO(uDr7)
2863 && (pCtx->cr4 & X86_CR4_DE))
2864 || DBGFBpIsHwIoArmed(pVM))
2865 {
2866 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
2867 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2868 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
2869 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
2870 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
2871 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
2872 rcStrict = rcStrict2;
2873 }
2874 }
2875 return rcStrict;
2876}
2877
2878
2879/**
2880 * Check fatal VT-x/AMD-V error and produce some meaningful
2881 * log release message.
2882 *
2883 * @param pVM Pointer to the VM.
2884 * @param iStatusCode VBox status code.
2885 */
2886VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2887{
2888 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2889 {
2890 PVMCPU pVCpu = &pVM->aCpus[i];
2891 switch (iStatusCode)
2892 {
2893 case VERR_VMX_INVALID_VMCS_FIELD:
2894 break;
2895
2896 case VERR_VMX_INVALID_VMCS_PTR:
2897 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2898 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
2899 pVCpu->hm.s.vmx.HCPhysVmcs));
2900 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
2901 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2902 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2903 break;
2904
2905 case VERR_VMX_UNABLE_TO_START_VM:
2906 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2907 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
2908 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2909
2910 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
2911 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
2912 {
2913 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2914 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2915 }
2916 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2917 {
2918 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
2919 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
2920 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
2921 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
2922 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
2923 LogRel(("HM: CPU[%u] MSRBitmapPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
2924#ifdef VBOX_WITH_AUTO_MSR_LOAD_RESTORE
2925 LogRel(("HM: CPU[%u] GuestMSRPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
2926 LogRel(("HM: CPU[%u] HostMsrPhys %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
2927 LogRel(("HM: CPU[%u] cGuestMSRs %u\n", i, pVCpu->hm.s.vmx.cGuestMsrs));
2928#endif
2929 }
2930 /** @todo Log VM-entry event injection control fields
2931 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2932 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2933 break;
2934
2935 case VERR_VMX_INVALID_VMXON_PTR:
2936 break;
2937
2938 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
2939 case VERR_VMX_INVALID_GUEST_STATE:
2940 case VERR_VMX_UNEXPECTED_EXIT_CODE:
2941 case VERR_SVM_UNKNOWN_EXIT:
2942 case VERR_SVM_UNEXPECTED_EXIT:
2943 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
2944 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
2945 {
2946 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
2947 break;
2948 }
2949 }
2950 }
2951
2952 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2953 {
2954 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
2955 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
2956 }
2957}
2958
2959
2960/**
2961 * Execute state save operation.
2962 *
2963 * @returns VBox status code.
2964 * @param pVM Pointer to the VM.
2965 * @param pSSM SSM operation handle.
2966 */
2967static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2968{
2969 int rc;
2970
2971 Log(("hmR3Save:\n"));
2972
2973 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2974 {
2975 /*
2976 * Save the basic bits - fortunately all the other things can be resynced on load.
2977 */
2978 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2979 AssertRCReturn(rc, rc);
2980 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2981 AssertRCReturn(rc, rc);
2982 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntrInfo);
2983 AssertRCReturn(rc, rc);
2984
2985 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
2986 * perhaps not even that (the initial value of @c true is safe. */
2987 uint32_t u32Dummy = PGMMODE_REAL;
2988 rc = SSMR3PutU32(pSSM, u32Dummy);
2989 AssertRCReturn(rc, rc);
2990 rc = SSMR3PutU32(pSSM, u32Dummy);
2991 AssertRCReturn(rc, rc);
2992 rc = SSMR3PutU32(pSSM, u32Dummy);
2993 AssertRCReturn(rc, rc);
2994 }
2995
2996#ifdef VBOX_HM_WITH_GUEST_PATCHING
2997 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
2998 AssertRCReturn(rc, rc);
2999 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3000 AssertRCReturn(rc, rc);
3001 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3002 AssertRCReturn(rc, rc);
3003
3004 /* Store all the guest patch records too. */
3005 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3006 AssertRCReturn(rc, rc);
3007
3008 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3009 {
3010 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3011
3012 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3013 AssertRCReturn(rc, rc);
3014
3015 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3016 AssertRCReturn(rc, rc);
3017
3018 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3019 AssertRCReturn(rc, rc);
3020
3021 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3022 AssertRCReturn(rc, rc);
3023
3024 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3025 AssertRCReturn(rc, rc);
3026
3027 AssertCompileSize(HMTPRINSTR, 4);
3028 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3029 AssertRCReturn(rc, rc);
3030
3031 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3032 AssertRCReturn(rc, rc);
3033
3034 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3035 AssertRCReturn(rc, rc);
3036
3037 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3038 AssertRCReturn(rc, rc);
3039
3040 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3041 AssertRCReturn(rc, rc);
3042 }
3043#endif
3044 return VINF_SUCCESS;
3045}
3046
3047
3048/**
3049 * Execute state load operation.
3050 *
3051 * @returns VBox status code.
3052 * @param pVM Pointer to the VM.
3053 * @param pSSM SSM operation handle.
3054 * @param uVersion Data layout version.
3055 * @param uPass The data pass.
3056 */
3057static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3058{
3059 int rc;
3060
3061 Log(("hmR3Load:\n"));
3062 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3063
3064 /*
3065 * Validate version.
3066 */
3067 if ( uVersion != HM_SSM_VERSION
3068 && uVersion != HM_SSM_VERSION_NO_PATCHING
3069 && uVersion != HM_SSM_VERSION_2_0_X)
3070 {
3071 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3072 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3073 }
3074 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3075 {
3076 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3077 AssertRCReturn(rc, rc);
3078 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3079 AssertRCReturn(rc, rc);
3080 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntrInfo);
3081 AssertRCReturn(rc, rc);
3082
3083 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
3084 {
3085 uint32_t val;
3086 /** @todo See note in hmR3Save(). */
3087 rc = SSMR3GetU32(pSSM, &val);
3088 AssertRCReturn(rc, rc);
3089 rc = SSMR3GetU32(pSSM, &val);
3090 AssertRCReturn(rc, rc);
3091 rc = SSMR3GetU32(pSSM, &val);
3092 AssertRCReturn(rc, rc);
3093 }
3094 }
3095#ifdef VBOX_HM_WITH_GUEST_PATCHING
3096 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
3097 {
3098 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3099 AssertRCReturn(rc, rc);
3100 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3101 AssertRCReturn(rc, rc);
3102 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3103 AssertRCReturn(rc, rc);
3104
3105 /* Fetch all TPR patch records. */
3106 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3107 AssertRCReturn(rc, rc);
3108
3109 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3110 {
3111 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3112
3113 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3114 AssertRCReturn(rc, rc);
3115
3116 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3117 AssertRCReturn(rc, rc);
3118
3119 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3120 AssertRCReturn(rc, rc);
3121
3122 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3123 AssertRCReturn(rc, rc);
3124
3125 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3126 AssertRCReturn(rc, rc);
3127
3128 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3129 AssertRCReturn(rc, rc);
3130
3131 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3132 pVM->hm.s.fTPRPatchingActive = true;
3133
3134 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3135
3136 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3137 AssertRCReturn(rc, rc);
3138
3139 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3140 AssertRCReturn(rc, rc);
3141
3142 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3143 AssertRCReturn(rc, rc);
3144
3145 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3146 AssertRCReturn(rc, rc);
3147
3148 Log(("hmR3Load: patch %d\n", i));
3149 Log(("Key = %x\n", pPatch->Core.Key));
3150 Log(("cbOp = %d\n", pPatch->cbOp));
3151 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3152 Log(("type = %d\n", pPatch->enmType));
3153 Log(("srcop = %d\n", pPatch->uSrcOperand));
3154 Log(("dstop = %d\n", pPatch->uDstOperand));
3155 Log(("cFaults = %d\n", pPatch->cFaults));
3156 Log(("target = %x\n", pPatch->pJumpTarget));
3157 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3158 AssertRC(rc);
3159 }
3160 }
3161#endif
3162
3163 return VINF_SUCCESS;
3164}
3165
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