VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 52041

Last change on this file since 52041 was 52041, checked in by vboxsync, 11 years ago

VMM: Fix NMI handling.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 138.5 KB
Line 
1/* $Id: HM.cpp 52041 2014-07-15 15:43:30Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2013 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18
19/*******************************************************************************
20* Header Files *
21*******************************************************************************/
22#define LOG_GROUP LOG_GROUP_HM
23#include <VBox/vmm/cpum.h>
24#include <VBox/vmm/stam.h>
25#include <VBox/vmm/mm.h>
26#include <VBox/vmm/pdmapi.h>
27#include <VBox/vmm/pgm.h>
28#include <VBox/vmm/ssm.h>
29#include <VBox/vmm/trpm.h>
30#include <VBox/vmm/dbgf.h>
31#include <VBox/vmm/iom.h>
32#include <VBox/vmm/patm.h>
33#include <VBox/vmm/csam.h>
34#include <VBox/vmm/selm.h>
35#ifdef VBOX_WITH_REM
36# include <VBox/vmm/rem.h>
37#endif
38#include <VBox/vmm/hm_vmx.h>
39#include <VBox/vmm/hm_svm.h>
40#include "HMInternal.h"
41#include <VBox/vmm/vm.h>
42#include <VBox/vmm/uvm.h>
43#include <VBox/err.h>
44#include <VBox/param.h>
45
46#include <iprt/assert.h>
47#include <VBox/log.h>
48#include <iprt/asm.h>
49#include <iprt/asm-amd64-x86.h>
50#include <iprt/string.h>
51#include <iprt/env.h>
52#include <iprt/thread.h>
53
54
55/*******************************************************************************
56* Global Variables *
57*******************************************************************************/
58#ifdef VBOX_WITH_STATISTICS
59# define EXIT_REASON(def, val, str) #def " - " #val " - " str
60# define EXIT_REASON_NIL() NULL
61/** Exit reason descriptions for VT-x, used to describe statistics. */
62static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
63{
64 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
65 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
66 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
67 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
68 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
69 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
70 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
71 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
72 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
73 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
74 EXIT_REASON(VMX_EXIT_CPUID , 10, "Guest attempted to execute CPUID."),
75 EXIT_REASON_NIL(),
76 EXIT_REASON(VMX_EXIT_HLT , 12, "Guest attempted to execute HLT."),
77 EXIT_REASON(VMX_EXIT_INVD , 13, "Guest attempted to execute INVD."),
78 EXIT_REASON(VMX_EXIT_INVLPG , 14, "Guest attempted to execute INVLPG."),
79 EXIT_REASON(VMX_EXIT_RDPMC , 15, "Guest attempted to execute RDPMC."),
80 EXIT_REASON(VMX_EXIT_RDTSC , 16, "Guest attempted to execute RDTSC."),
81 EXIT_REASON(VMX_EXIT_RSM , 17, "Guest attempted to execute RSM in SMM."),
82 EXIT_REASON(VMX_EXIT_VMCALL , 18, "Guest attempted to execute VMCALL."),
83 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "Guest attempted to execute VMCLEAR."),
84 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "Guest attempted to execute VMLAUNCH."),
85 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "Guest attempted to execute VMPTRLD."),
86 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "Guest attempted to execute VMPTRST."),
87 EXIT_REASON(VMX_EXIT_VMREAD , 23, "Guest attempted to execute VMREAD."),
88 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "Guest attempted to execute VMRESUME."),
89 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "Guest attempted to execute VMWRITE."),
90 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "Guest attempted to execute VMXOFF."),
91 EXIT_REASON(VMX_EXIT_VMXON , 27, "Guest attempted to execute VMXON."),
92 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
93 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
94 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
95 EXIT_REASON(VMX_EXIT_RDMSR , 31, "Guest attempted to execute RDMSR."),
96 EXIT_REASON(VMX_EXIT_WRMSR , 32, "Guest attempted to execute WRMSR."),
97 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
98 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
99 EXIT_REASON_NIL(),
100 EXIT_REASON(VMX_EXIT_MWAIT , 36, "Guest executed MWAIT."),
101 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
102 EXIT_REASON_NIL(),
103 EXIT_REASON(VMX_EXIT_MONITOR , 39, "Guest attempted to execute MONITOR."),
104 EXIT_REASON(VMX_EXIT_PAUSE , 40, "Guest attempted to execute PAUSE."),
105 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
106 EXIT_REASON_NIL(),
107 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold. Guest attempted to execute MOV to CR8."),
108 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access. Guest attempted to access memory at a physical address on the APIC-access page."),
109 EXIT_REASON_NIL(),
110 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR. Guest attempted to execute LGDT, LIDT, SGDT, or SIDT."),
111 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR. Guest attempted to execute LLDT, LTR, SLDT, or STR."),
112 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation. An attempt to access memory with a guest-physical address was disallowed by the configuration of the EPT paging structures."),
113 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration. An attempt to access memory with a guest-physical address encountered a misconfigured EPT paging-structure entry."),
114 EXIT_REASON(VMX_EXIT_INVEPT , 50, "Guest attempted to execute INVEPT."),
115 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "Guest attempted to execute RDTSCP."),
116 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
117 EXIT_REASON(VMX_EXIT_INVVPID , 53, "Guest attempted to execute INVVPID."),
118 EXIT_REASON(VMX_EXIT_WBINVD , 54, "Guest attempted to execute WBINVD."),
119 EXIT_REASON(VMX_EXIT_XSETBV , 55, "Guest attempted to execute XSETBV."),
120 EXIT_REASON_NIL(),
121 EXIT_REASON(VMX_EXIT_RDRAND , 57, "Guest attempted to execute RDRAND."),
122 EXIT_REASON(VMX_EXIT_INVPCID , 58, "Guest attempted to execute INVPCID."),
123 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "Guest attempted to execute VMFUNC.")
124};
125/** Exit reason descriptions for AMD-V, used to describe statistics. */
126static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
127{
128 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
129 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
130 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
131 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
132 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
133 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
134 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
135 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
136 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
137 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
138 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
139 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
140 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
141 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
142 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
143 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
144 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
145 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
146 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
147 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
148 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
149 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
150 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
151 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
152 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
153 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
154 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
155 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
156 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
157 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
158 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
159 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
160 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
161 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
162 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
163 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
164 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
165 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
166 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
167 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
168 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
169 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
170 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
171 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
172 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
173 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
174 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
175 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
176 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
177 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
178 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
179 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
180 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
181 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
182 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
183 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
184 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
185 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
186 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
187 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
188 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
189 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
190 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
191 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
192 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
193 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
194 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
195 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
196 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
197 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
198 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
199 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
200 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
201 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
202 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
203 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
204 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
205 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
206 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
207 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
208 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
209 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
210 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
211 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
212 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
213 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
214 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
215 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
216 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
217 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
218 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
224 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
225 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
226 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
227 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
228 EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
229 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
230 EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
231 EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
232 EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
233 EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
234 EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
235 EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
236 EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
237 EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
238 EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
239 EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
240 EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
241 EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
242 EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
243 EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
244 EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
245 EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
246 EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
247 EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
248 EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
249 EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
250 EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
251 EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
252 EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
253 EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
254 EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
255 EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
256 EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
257 EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
258 EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
259 EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
260 EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
261 EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
262 EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
263 EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
264 EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
265 EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
266 EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
267 EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
268 EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
269 EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
270 EXIT_REASON_NIL()
271};
272# undef EXIT_REASON
273# undef EXIT_REASON_NIL
274#endif /* VBOX_WITH_STATISTICS */
275
276#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
277 do { \
278 if ((allowed1) & (featflag)) \
279 LogRel(("HM: " #featflag "\n")); \
280 else \
281 LogRel(("HM: " #featflag " (must be cleared)\n")); \
282 if ((disallowed0) & (featflag)) \
283 LogRel(("HM: " #featflag " (must be set)\n")); \
284 } while (0)
285
286#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, featflag) \
287 do { \
288 if ((allowed1) & (featflag)) \
289 LogRel(("HM: " #featflag "\n")); \
290 else \
291 LogRel(("HM: " #featflag " not supported\n")); \
292 } while (0)
293
294#define HMVMX_REPORT_CAPABILITY(msrcaps, cap) \
295 do { \
296 if ((msrcaps) & (cap)) \
297 LogRel(("HM: " #cap "\n")); \
298 } while (0)
299
300
301/*******************************************************************************
302* Internal Functions *
303*******************************************************************************/
304static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
305static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
306static int hmR3InitCPU(PVM pVM);
307static int hmR3InitFinalizeR0(PVM pVM);
308static int hmR3InitFinalizeR0Intel(PVM pVM);
309static int hmR3InitFinalizeR0Amd(PVM pVM);
310static int hmR3TermCPU(PVM pVM);
311
312
313
314/**
315 * Initializes the HM.
316 *
317 * This reads the config and check whether VT-x or AMD-V hardware is available
318 * if configured to use it. This is one of the very first components to be
319 * initialized after CFGM, so that we can fall back to raw-mode early in the
320 * initialization process.
321 *
322 * Note that a lot of the set up work is done in ring-0 and thus postponed till
323 * the ring-3 and ring-0 callback to HMR3InitCompleted.
324 *
325 * @returns VBox status code.
326 * @param pVM Pointer to the VM.
327 *
328 * @remarks Be careful with what we call here, since most of the VMM components
329 * are uninitialized.
330 */
331VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
332{
333 LogFlow(("HMR3Init\n"));
334
335 /*
336 * Assert alignment and sizes.
337 */
338 AssertCompileMemberAlignment(VM, hm.s, 32);
339 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
340
341 /*
342 * Register the saved state data unit.
343 */
344 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SSM_VERSION, sizeof(HM),
345 NULL, NULL, NULL,
346 NULL, hmR3Save, NULL,
347 NULL, hmR3Load, NULL);
348 if (RT_FAILURE(rc))
349 return rc;
350
351 /*
352 * Misc initialisation.
353 */
354#if 0
355 pVM->hm.s.vmx.fSupported = false;
356 pVM->hm.s.svm.fSupported = false;
357 pVM->hm.s.vmx.fEnabled = false;
358 pVM->hm.s.svm.fEnabled = false;
359 pVM->hm.s.fNestedPaging = false;
360#endif
361
362 /*
363 * Read configuration.
364 */
365 PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
366
367 /** @cfgm{/HM/HMForced, bool, false}
368 * Forces hardware virtualization, no falling back on raw-mode. HM must be
369 * enabled, i.e. /HMEnabled must be true. */
370 bool fHMForced;
371#ifdef VBOX_WITH_RAW_MODE
372 rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
373 AssertRCReturn(rc, rc);
374 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
375 VERR_INVALID_PARAMETER);
376# if defined(RT_OS_DARWIN)
377 if (pVM->fHMEnabled)
378 fHMForced = true;
379# endif
380 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
381 VERR_INVALID_PARAMETER);
382 if (pVM->cCpus > 1)
383 fHMForced = true;
384#else /* !VBOX_WITH_RAW_MODE */
385 AssertRelease(pVM->fHMEnabled);
386 fHMForced = true;
387#endif /* !VBOX_WITH_RAW_MODE */
388
389 /** @cfgm{/HM/EnableNestedPaging, bool, false}
390 * Enables nested paging (aka extended page tables). */
391 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
392 AssertRCReturn(rc, rc);
393
394 /** @cfgm{/HM/EnableUX, bool, true}
395 * Enables the VT-x unrestricted execution feature. */
396 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
397 AssertRCReturn(rc, rc);
398
399 /** @cfgm{/HM/EnableLargePages, bool, false}
400 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
401 * page table walking and maybe better TLB hit rate in some cases. */
402 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
403 AssertRCReturn(rc, rc);
404
405 /** @cfgm{/HM/EnableVPID, bool, false}
406 * Enables the VT-x VPID feature. */
407 rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
408 AssertRCReturn(rc, rc);
409
410 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
411 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
412 rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
413 AssertRCReturn(rc, rc);
414
415 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
416 * Enables AMD64 cpu features.
417 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
418 * already have the support. */
419#ifdef VBOX_ENABLE_64_BITS_GUESTS
420 rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
421 AssertLogRelRCReturn(rc, rc);
422#else
423 pVM->hm.s.fAllow64BitGuests = false;
424#endif
425
426 /** @cfgm{/HM/Exclusive, bool}
427 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
428 * global init for each host CPU. If false, we do local init each time we wish
429 * to execute guest code.
430 *
431 * Default is false for Mac OS X and Windows due to the higher risk of conflicts
432 * with other hypervisors.
433 */
434 rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
435#if defined(RT_OS_DARWIN) || defined(RT_OS_WINDOWS)
436 false
437#else
438 true
439#endif
440 );
441 AssertLogRelRCReturn(rc, rc);
442
443 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
444 * The number of times to resume guest execution before we forcibly return to
445 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
446 * determines the default value. */
447 rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
448 AssertLogRelRCReturn(rc, rc);
449
450 /*
451 * Check if VT-x or AMD-v support according to the users wishes.
452 */
453 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
454 * VERR_SVM_IN_USE. */
455 if (pVM->fHMEnabled)
456 {
457 uint32_t fCaps;
458 rc = SUPR3QueryVTCaps(&fCaps);
459 if (RT_SUCCESS(rc))
460 {
461 if (fCaps & SUPVTCAPS_AMD_V)
462 LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
463 else if (fCaps & SUPVTCAPS_VT_X)
464 {
465 rc = SUPR3QueryVTxSupported();
466 if (RT_SUCCESS(rc))
467 LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
468 else
469 {
470#ifdef RT_OS_LINUX
471 const char *pszMinReq = " Linux 2.6.13 or newer required!";
472#else
473 const char *pszMinReq = "";
474#endif
475 if (fHMForced)
476 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
477
478 /* Fall back to raw-mode. */
479 LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
480 pVM->fHMEnabled = false;
481 }
482 }
483 else
484 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
485 VERR_INTERNAL_ERROR_5);
486
487 /*
488 * Do we require a little bit or raw-mode for 64-bit guest execution?
489 */
490 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
491 && pVM->fHMEnabled
492 && pVM->hm.s.fAllow64BitGuests;
493 }
494 else
495 {
496 const char *pszMsg;
497 switch (rc)
498 {
499 case VERR_UNSUPPORTED_CPU:
500 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
501 break;
502
503 case VERR_VMX_NO_VMX:
504 pszMsg = "VT-x is not available.";
505 break;
506
507 case VERR_VMX_MSR_VMXON_DISABLED:
508 pszMsg = "VT-x is disabled in the BIOS.";
509 break;
510
511 case VERR_VMX_MSR_ALL_VMXON_DISABLED:
512 pszMsg = "VT-x is disabled in the BIOS for all CPU modes.";
513 break;
514
515 case VERR_VMX_MSR_LOCKING_FAILED:
516 pszMsg = "Failed to enable and lock VT-x features.";
517 break;
518
519 case VERR_SVM_NO_SVM:
520 pszMsg = "AMD-V is not available.";
521 break;
522
523 case VERR_SVM_DISABLED:
524 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
525 break;
526
527 default:
528 pszMsg = NULL;
529 break;
530 }
531 if (fHMForced && pszMsg)
532 return VM_SET_ERROR(pVM, rc, pszMsg);
533 if (!pszMsg)
534 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
535
536 /* Fall back to raw-mode. */
537 LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
538 pVM->fHMEnabled = false;
539 }
540 }
541
542 /* It's now OK to use the predicate function. */
543 pVM->fHMEnabledFixed = true;
544 return VINF_SUCCESS;
545}
546
547
548/**
549 * Initializes the per-VCPU HM.
550 *
551 * @returns VBox status code.
552 * @param pVM Pointer to the VM.
553 */
554static int hmR3InitCPU(PVM pVM)
555{
556 LogFlow(("HMR3InitCPU\n"));
557
558 if (!HMIsEnabled(pVM))
559 return VINF_SUCCESS;
560
561 for (VMCPUID i = 0; i < pVM->cCpus; i++)
562 {
563 PVMCPU pVCpu = &pVM->aCpus[i];
564 pVCpu->hm.s.fActive = false;
565 }
566
567#ifdef VBOX_WITH_STATISTICS
568 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
569 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
570 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
571 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
572#endif
573
574 /*
575 * Statistics.
576 */
577 for (VMCPUID i = 0; i < pVM->cCpus; i++)
578 {
579 PVMCPU pVCpu = &pVM->aCpus[i];
580 int rc;
581
582#ifdef VBOX_WITH_STATISTICS
583 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
584 "Profiling of RTMpPokeCpu",
585 "/PROF/CPU%d/HM/Poke", i);
586 AssertRC(rc);
587 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
588 "Profiling of poke wait",
589 "/PROF/CPU%d/HM/PokeWait", i);
590 AssertRC(rc);
591 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
592 "Profiling of poke wait when RTMpPokeCpu fails",
593 "/PROF/CPU%d/HM/PokeWaitFailed", i);
594 AssertRC(rc);
595 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
596 "Profiling of VMXR0RunGuestCode entry",
597 "/PROF/CPU%d/HM/StatEntry", i);
598 AssertRC(rc);
599 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
600 "Profiling of VMXR0RunGuestCode exit part 1",
601 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
602 AssertRC(rc);
603 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
604 "Profiling of VMXR0RunGuestCode exit part 2",
605 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
606 AssertRC(rc);
607
608 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
609 "I/O",
610 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
611 AssertRC(rc);
612 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
613 "MOV CRx",
614 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
615 AssertRC(rc);
616 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
617 "Exceptions, NMIs",
618 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
619 AssertRC(rc);
620
621 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
622 "Profiling of VMXR0LoadGuestState",
623 "/PROF/CPU%d/HM/StatLoadGuestState", i);
624 AssertRC(rc);
625 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
626 "Profiling of VMLAUNCH/VMRESUME.",
627 "/PROF/CPU%d/HM/InGC", i);
628 AssertRC(rc);
629
630# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
631 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
632 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
633 "/PROF/CPU%d/HM/Switcher3264", i);
634 AssertRC(rc);
635# endif
636
637# ifdef HM_PROFILE_EXIT_DISPATCH
638 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
639 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
640 "/PROF/CPU%d/HM/ExitDispatch", i);
641 AssertRC(rc);
642# endif
643
644#endif
645# define HM_REG_COUNTER(a, b, desc) \
646 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
647 AssertRC(rc);
648
649#ifdef VBOX_WITH_STATISTICS
650 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
651 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
652 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
653 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
654 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
655 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
656 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
657 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
658 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
659 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
660 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
661 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
662 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
663 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
664 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
665 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
666 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
667 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
668 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
669 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
670 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
671 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
672 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
673 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
674 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
675 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
676 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
677 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
678 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
679 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
680 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
681 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
682 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
683 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
684 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
685 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
686 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
687 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
688 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
689 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
690 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
691 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
692 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
693 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
694 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
695 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
696 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
697 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
698#endif
699 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
700#ifdef VBOX_WITH_STATISTICS
701 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
702 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
703 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
704 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
705 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
706
707 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
708 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
709 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
710 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
711 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
712
713 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
714 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
715 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
716
717 HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptPreempting, "/HM/CPU%d/Preempt/Preempting", "EMT has been preempted while in HM context.");
718 HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptSaveHostState, "/HM/CPU%d/Preempt/SaveHostState", "Preemption caused us to resave host state.");
719
720 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
721 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
722 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
723 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
724 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
725 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
726 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
727 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
728 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
729 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
730 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
731 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
732 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
733 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
734
735 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffsetAdjusted, "/HM/CPU%d/TSC/OffsetAdjusted", "TSC offset overflowed for paravirt. TSC. Fudged.");
736 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
737 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
738 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
739 HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
740
741 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
742 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
743 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
744
745 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
746 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
747
748 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
749 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
750 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
751 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
752 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
753 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
754 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
755 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
756
757#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
758 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
759 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
760#endif
761
762 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
763 {
764 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
765 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
766 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
767 AssertRC(rc);
768 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
769 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
770 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
771 AssertRC(rc);
772 }
773
774#undef HM_REG_COUNTER
775
776 pVCpu->hm.s.paStatExitReason = NULL;
777
778 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
779 (void **)&pVCpu->hm.s.paStatExitReason);
780 AssertRC(rc);
781 if (RT_SUCCESS(rc))
782 {
783 const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
784 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
785 {
786 if (papszDesc[j])
787 {
788 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
789 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
790 AssertRC(rc);
791 }
792 }
793 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
794 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
795 AssertRC(rc);
796 }
797 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
798# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
799 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
800# else
801 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
802# endif
803
804 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
805 AssertRCReturn(rc, rc);
806 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
807# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
808 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
809# else
810 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
811# endif
812 for (unsigned j = 0; j < 255; j++)
813 {
814 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
815 "Injected event.",
816 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
817 }
818
819#endif /* VBOX_WITH_STATISTICS */
820 }
821
822#ifdef VBOX_WITH_CRASHDUMP_MAGIC
823 /*
824 * Magic marker for searching in crash dumps.
825 */
826 for (VMCPUID i = 0; i < pVM->cCpus; i++)
827 {
828 PVMCPU pVCpu = &pVM->aCpus[i];
829
830 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
831 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
832 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
833 }
834#endif
835
836 return VINF_SUCCESS;
837}
838
839
840/**
841 * Called when a init phase has completed.
842 *
843 * @returns VBox status code.
844 * @param pVM The VM.
845 * @param enmWhat The phase that completed.
846 */
847VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
848{
849 switch (enmWhat)
850 {
851 case VMINITCOMPLETED_RING3:
852 return hmR3InitCPU(pVM);
853 case VMINITCOMPLETED_RING0:
854 return hmR3InitFinalizeR0(pVM);
855 default:
856 return VINF_SUCCESS;
857 }
858}
859
860
861/**
862 * Turns off normal raw mode features.
863 *
864 * @param pVM Pointer to the VM.
865 */
866static void hmR3DisableRawMode(PVM pVM)
867{
868 /* Reinit the paging mode to force the new shadow mode. */
869 for (VMCPUID i = 0; i < pVM->cCpus; i++)
870 {
871 PVMCPU pVCpu = &pVM->aCpus[i];
872
873 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
874 }
875}
876
877
878/**
879 * Initialize VT-x or AMD-V.
880 *
881 * @returns VBox status code.
882 * @param pVM Pointer to the VM.
883 */
884static int hmR3InitFinalizeR0(PVM pVM)
885{
886 int rc;
887
888 if (!HMIsEnabled(pVM))
889 return VINF_SUCCESS;
890
891 /*
892 * Hack to allow users to work around broken BIOSes that incorrectly set
893 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
894 */
895 if ( !pVM->hm.s.vmx.fSupported
896 && !pVM->hm.s.svm.fSupported
897 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
898 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
899 {
900 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
901 pVM->hm.s.svm.fSupported = true;
902 pVM->hm.s.svm.fIgnoreInUseError = true;
903 pVM->hm.s.lLastError = VINF_SUCCESS;
904 }
905
906 /*
907 * Report ring-0 init errors.
908 */
909 if ( !pVM->hm.s.vmx.fSupported
910 && !pVM->hm.s.svm.fSupported)
911 {
912 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
913 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
914 switch (pVM->hm.s.lLastError)
915 {
916 case VERR_VMX_IN_VMX_ROOT_MODE:
917 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
918 case VERR_VMX_NO_VMX:
919 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
920 case VERR_VMX_MSR_VMXON_DISABLED:
921 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS.");
922 case VERR_VMX_MSR_ALL_VMXON_DISABLED:
923 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS for all CPU modes.");
924 case VERR_VMX_MSR_LOCKING_FAILED:
925 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "Failed to enable and lock VT-x features.");
926
927 case VERR_SVM_IN_USE:
928 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
929 case VERR_SVM_NO_SVM:
930 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
931 case VERR_SVM_DISABLED:
932 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
933 }
934 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
935 }
936
937 /*
938 * Enable VT-x or AMD-V on all host CPUs.
939 */
940 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
941 if (RT_FAILURE(rc))
942 {
943 LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
944 return rc;
945 }
946
947 /*
948 * No TPR patching is required when the IO-APIC is not enabled for this VM.
949 * (Main should have taken care of this already)
950 */
951 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
952 if (!pVM->hm.s.fHasIoApic)
953 {
954 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
955 pVM->hm.s.fTprPatchingAllowed = false;
956 }
957
958 /*
959 * Do the vendor specific initalization .
960 * .
961 * Note! We disable release log buffering here since we're doing relatively .
962 * lot of logging and doesn't want to hit the disk with each LogRel .
963 * statement.
964 */
965 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
966 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
967 if (pVM->hm.s.vmx.fSupported)
968 rc = hmR3InitFinalizeR0Intel(pVM);
969 else
970 rc = hmR3InitFinalizeR0Amd(pVM);
971 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
972 RTLogRelSetBuffering(fOldBuffered);
973 pVM->hm.s.fInitialized = true;
974
975 return rc;
976}
977
978
979/**
980 * Finish VT-x initialization (after ring-0 init).
981 *
982 * @returns VBox status code.
983 * @param pVM The cross context VM structure.
984 */
985static int hmR3InitFinalizeR0Intel(PVM pVM)
986{
987 int rc;
988
989 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
990 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
991
992 uint64_t val;
993 uint64_t zap;
994 RTGCPHYS GCPhys = 0;
995
996 LogRel(("HM: Using VT-x implementation 2.0!\n"));
997 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
998 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
999 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1000 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1001 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1002 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1003 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1004 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1005 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1006 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1007 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1008
1009 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1010 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1011 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1012 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1013 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1014 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1015 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1016
1017 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1018 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1019 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1020 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1021 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1022 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1023 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1024 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1025 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1026 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1027 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1028 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1029 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1030 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1031 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1032 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1033 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1034 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1035 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1036 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1037 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1038 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1039 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1040 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1041 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1042 {
1043 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1044 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1045 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1046 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1047 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1048 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1049 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1050 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1051 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1052 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1053 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1054 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1055 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1056 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1057 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1058 }
1059
1060 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1061 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1062 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1063 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1064 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1065 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1066 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1067 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1068 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1069 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1070
1071 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1072 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1073 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1074 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1075 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1076 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1077 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1078 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1079 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1080 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1081 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1082 HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1083
1084 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1085 {
1086 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1087 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1088 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1089 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1090 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1091 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1092 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1093 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1094 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1095 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1096 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1097 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1098 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1099 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1100 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1101 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1102 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1103 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1104 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1105 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1106 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1107 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1108 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1109 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1110 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1111 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1112 HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1113 }
1114
1115 val = pVM->hm.s.vmx.Msrs.u64Misc;
1116 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1117 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1118 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1119 else
1120 {
1121 LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1122 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1123 }
1124
1125 LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1126 LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1127 LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1128 LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1129 LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1130 LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1131 LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1132 LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1133
1134 /* Paranoia */
1135 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1136
1137 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1138 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1139 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1140 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1141
1142 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1143 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1144 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1145
1146 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1147 if (val)
1148 {
1149 LogRel(("HM: MSR_A32_VMX_VMFUNC = %#RX64\n", val));
1150 HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1151 }
1152
1153 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1154
1155 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1156 {
1157 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1158 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1159 }
1160
1161 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1162 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1163
1164 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1165 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1166
1167 /*
1168 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1169 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1170 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1171 */
1172 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1173 && CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1174 {
1175 CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1176 LogRel(("HM: RDTSCP disabled\n"));
1177 }
1178
1179 /* Unrestricted guest execution also requires EPT. */
1180 if ( pVM->hm.s.vmx.fAllowUnrestricted
1181 && pVM->hm.s.fNestedPaging
1182 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1183 {
1184 pVM->hm.s.vmx.fUnrestrictedGuest = true;
1185 }
1186
1187 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1188 {
1189 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1190 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1191 if (RT_SUCCESS(rc))
1192 {
1193 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1194 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1195 esp. Figure 20-5.*/
1196 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1197 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1198
1199 /* Bit set to 0 means software interrupts are redirected to the
1200 8086 program interrupt handler rather than switching to
1201 protected-mode handler. */
1202 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1203
1204 /* Allow all port IO, so that port IO instructions do not cause
1205 exceptions and would instead cause a VM-exit (based on VT-x's
1206 IO bitmap which we currently configure to always cause an exit). */
1207 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1208 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1209
1210 /*
1211 * Construct a 1024 element page directory with 4 MB pages for
1212 * the identity mapped page table used in real and protected mode
1213 * without paging with EPT.
1214 */
1215 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1216 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1217 {
1218 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1219 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1220 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1221 | X86_PDE4M_G;
1222 }
1223
1224 /* We convert it here every time as pci regions could be reconfigured. */
1225 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1226 AssertRCReturn(rc, rc);
1227 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1228
1229 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1230 AssertRCReturn(rc, rc);
1231 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1232 }
1233 else
1234 {
1235 /** @todo This cannot possibly work, there are other places which assumes
1236 * this allocation cannot fail (see HMR3CanExecuteGuest()). Make this
1237 * a failure case. */
1238 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1239 pVM->hm.s.vmx.pRealModeTSS = NULL;
1240 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1241 }
1242 }
1243
1244 LogRel((pVM->hm.s.fAllow64BitGuests
1245 ? "HM: Guest support: 32-bit and 64-bit\n"
1246 : "HM: Guest support: 32-bit only\n"));
1247
1248 /*
1249 * Call ring-0 to set up the VM.
1250 */
1251 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1252 if (rc != VINF_SUCCESS)
1253 {
1254 AssertMsgFailed(("%Rrc\n", rc));
1255 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1256 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1257 {
1258 PVMCPU pVCpu = &pVM->aCpus[i];
1259 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1260 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1261 }
1262 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1263 }
1264
1265 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1266 LogRel(("HM: VMX enabled!\n"));
1267 pVM->hm.s.vmx.fEnabled = true;
1268
1269 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1270
1271 /*
1272 * Change the CPU features.
1273 */
1274 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1275 if (pVM->hm.s.fAllow64BitGuests)
1276 {
1277 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1278 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1279 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1280 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1281 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1282 }
1283 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1284 (we reuse the host EFER in the switcher). */
1285 /** @todo this needs to be fixed properly!! */
1286 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1287 {
1288 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1289 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1290 else
1291 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1292 }
1293
1294 /*
1295 * Log configuration details.
1296 */
1297 if (pVM->hm.s.fNestedPaging)
1298 {
1299 LogRel(("HM: Nested paging enabled!\n"));
1300 if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1301 LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1302 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1303 LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1304 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1305 LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1306 else
1307 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1308
1309 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1310 LogRel(("HM: Unrestricted guest execution enabled!\n"));
1311
1312#if HC_ARCH_BITS == 64
1313 if (pVM->hm.s.fLargePages)
1314 {
1315 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1316 PGMSetLargePageUsage(pVM, true);
1317 LogRel(("HM: Large page support enabled\n"));
1318 }
1319#endif
1320 }
1321 else
1322 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1323
1324 if (pVM->hm.s.vmx.fVpid)
1325 {
1326 LogRel(("HM: VPID enabled!\n"));
1327 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1328 LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1329 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1330 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1331 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1332 LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1333 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1334 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1335 else
1336 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1337 }
1338 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1339 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1340
1341 /*
1342 * Check for preemption timer config override and log the state of it.
1343 */
1344 if (pVM->hm.s.vmx.fUsePreemptTimer)
1345 {
1346 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1347 rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1348 AssertLogRelRCReturn(rc, rc);
1349 }
1350 if (pVM->hm.s.vmx.fUsePreemptTimer)
1351 LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1352 else
1353 LogRel(("HM: VMX-preemption timer disabled\n"));
1354
1355 return VINF_SUCCESS;
1356}
1357
1358
1359/**
1360 * Finish AMD-V initialization (after ring-0 init).
1361 *
1362 * @returns VBox status code.
1363 * @param pVM The cross context VM structure.
1364 */
1365static int hmR3InitFinalizeR0Amd(PVM pVM)
1366{
1367 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1368
1369 LogRel(("HM: Using AMD-V implementation 2.0!\n"));
1370
1371 uint32_t u32Family;
1372 uint32_t u32Model;
1373 uint32_t u32Stepping;
1374 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1375 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1376 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1377 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1378 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1379 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1380 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1381 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1382
1383 /*
1384 * Enumerate AMD-V features.
1385 */
1386 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1387 {
1388#define HMSVM_REPORT_FEATURE(a_Define) { a_Define, #a_Define }
1389 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1390 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1391 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1392 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1393 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1394 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1395 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1396 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1397 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1398 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1399 HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1400#undef HMSVM_REPORT_FEATURE
1401 };
1402
1403 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1404 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1405 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1406 {
1407 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1408 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1409 }
1410 if (fSvmFeatures)
1411 for (unsigned iBit = 0; iBit < 32; iBit++)
1412 if (RT_BIT_32(iBit) & fSvmFeatures)
1413 LogRel(("HM: Reserved bit %u\n", iBit));
1414
1415 /*
1416 * Adjust feature(s).
1417 */
1418 if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1419 pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1420
1421 /*
1422 * Call ring-0 to set up the VM.
1423 */
1424 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1425 if (rc != VINF_SUCCESS)
1426 {
1427 AssertMsgFailed(("%Rrc\n", rc));
1428 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1429 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1430 }
1431
1432 LogRel(("HM: AMD-V enabled!\n"));
1433 pVM->hm.s.svm.fEnabled = true;
1434
1435 if (pVM->hm.s.fNestedPaging)
1436 {
1437 LogRel(("HM: Nested paging enabled!\n"));
1438
1439 /*
1440 * Enable large pages (2 MB) if applicable.
1441 */
1442#if HC_ARCH_BITS == 64
1443 if (pVM->hm.s.fLargePages)
1444 {
1445 PGMSetLargePageUsage(pVM, true);
1446 LogRel(("HM: Large page support enabled!\n"));
1447 }
1448#endif
1449 }
1450
1451 hmR3DisableRawMode(pVM);
1452
1453 /*
1454 * Change the CPU features.
1455 */
1456 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1457 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1458 if (pVM->hm.s.fAllow64BitGuests)
1459 {
1460 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1461 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1462 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1463 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1464 }
1465 /* Turn on NXE if PAE has been enabled. */
1466 else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1467 CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1468
1469 LogRel(("HM: TPR patching %s\n", (pVM->hm.s.fTprPatchingAllowed) ? "enabled" : "disabled"));
1470
1471 LogRel((pVM->hm.s.fAllow64BitGuests
1472 ? "HM: Guest support: 32-bit and 64-bit\n"
1473 : "HM: Guest support: 32-bit only\n"));
1474
1475 return VINF_SUCCESS;
1476}
1477
1478
1479/**
1480 * Applies relocations to data and code managed by this
1481 * component. This function will be called at init and
1482 * whenever the VMM need to relocate it self inside the GC.
1483 *
1484 * @param pVM The VM.
1485 */
1486VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1487{
1488 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1489
1490 /* Fetch the current paging mode during the relocate callback during state loading. */
1491 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1492 {
1493 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1494 {
1495 PVMCPU pVCpu = &pVM->aCpus[i];
1496 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1497 }
1498 }
1499#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1500 if (HMIsEnabled(pVM))
1501 {
1502 switch (PGMGetHostMode(pVM))
1503 {
1504 case PGMMODE_32_BIT:
1505 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1506 break;
1507
1508 case PGMMODE_PAE:
1509 case PGMMODE_PAE_NX:
1510 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1511 break;
1512
1513 default:
1514 AssertFailed();
1515 break;
1516 }
1517 }
1518#endif
1519 return;
1520}
1521
1522
1523/**
1524 * Notification callback which is called whenever there is a chance that a CR3
1525 * value might have changed.
1526 *
1527 * This is called by PGM.
1528 *
1529 * @param pVM Pointer to the VM.
1530 * @param pVCpu Pointer to the VMCPU.
1531 * @param enmShadowMode New shadow paging mode.
1532 * @param enmGuestMode New guest paging mode.
1533 */
1534VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1535{
1536 /* Ignore page mode changes during state loading. */
1537 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1538 return;
1539
1540 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1541
1542 /*
1543 * If the guest left protected mode VMX execution, we'll have to be
1544 * extra careful if/when the guest switches back to protected mode.
1545 */
1546 if (enmGuestMode == PGMMODE_REAL)
1547 {
1548 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1549 pVCpu->hm.s.vmx.fWasInRealMode = true;
1550 }
1551
1552 /** @todo r=ramshankar: Disabling for now. If nothing breaks remove it
1553 * eventually. (Test platforms that use the cache ofc). */
1554#if 0
1555#ifdef VMX_USE_CACHED_VMCS_ACCESSES
1556 /* Reset the contents of the read cache. */
1557 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1558 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1559 pCache->Read.aFieldVal[j] = 0;
1560#endif
1561#endif
1562}
1563
1564
1565/**
1566 * Terminates the HM.
1567 *
1568 * Termination means cleaning up and freeing all resources,
1569 * the VM itself is, at this point, powered off or suspended.
1570 *
1571 * @returns VBox status code.
1572 * @param pVM Pointer to the VM.
1573 */
1574VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1575{
1576 if (pVM->hm.s.vmx.pRealModeTSS)
1577 {
1578 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1579 pVM->hm.s.vmx.pRealModeTSS = 0;
1580 }
1581 hmR3TermCPU(pVM);
1582 return 0;
1583}
1584
1585
1586/**
1587 * Terminates the per-VCPU HM.
1588 *
1589 * @returns VBox status code.
1590 * @param pVM Pointer to the VM.
1591 */
1592static int hmR3TermCPU(PVM pVM)
1593{
1594 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1595 {
1596 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1597
1598#ifdef VBOX_WITH_STATISTICS
1599 if (pVCpu->hm.s.paStatExitReason)
1600 {
1601 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1602 pVCpu->hm.s.paStatExitReason = NULL;
1603 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1604 }
1605 if (pVCpu->hm.s.paStatInjectedIrqs)
1606 {
1607 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1608 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1609 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1610 }
1611#endif
1612
1613#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1614 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1615 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1616 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1617#endif
1618 }
1619 return 0;
1620}
1621
1622
1623/**
1624 * Resets a virtual CPU.
1625 *
1626 * Used by HMR3Reset and CPU hot plugging.
1627 *
1628 * @param pVCpu The CPU to reset.
1629 */
1630VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1631{
1632 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
1633 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1634 HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1635
1636 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1637 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1638 pVCpu->hm.s.fActive = false;
1639 pVCpu->hm.s.Event.fPending = false;
1640 pVCpu->hm.s.vmx.fWasInRealMode = true;
1641 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
1642
1643 /* Reset the contents of the read cache. */
1644 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1645 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1646 pCache->Read.aFieldVal[j] = 0;
1647
1648#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1649 /* Magic marker for searching in crash dumps. */
1650 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1651 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1652#endif
1653}
1654
1655
1656/**
1657 * The VM is being reset.
1658 *
1659 * For the HM component this means that any GDT/LDT/TSS monitors
1660 * needs to be removed.
1661 *
1662 * @param pVM Pointer to the VM.
1663 */
1664VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1665{
1666 LogFlow(("HMR3Reset:\n"));
1667
1668 if (HMIsEnabled(pVM))
1669 hmR3DisableRawMode(pVM);
1670
1671 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1672 {
1673 PVMCPU pVCpu = &pVM->aCpus[i];
1674
1675 HMR3ResetCpu(pVCpu);
1676 }
1677
1678 /* Clear all patch information. */
1679 pVM->hm.s.pGuestPatchMem = 0;
1680 pVM->hm.s.pFreeGuestPatchMem = 0;
1681 pVM->hm.s.cbGuestPatchMem = 0;
1682 pVM->hm.s.cPatches = 0;
1683 pVM->hm.s.PatchTree = 0;
1684 pVM->hm.s.fTPRPatchingActive = false;
1685 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1686}
1687
1688
1689/**
1690 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1691 *
1692 * @returns VBox strict status code.
1693 * @param pVM Pointer to the VM.
1694 * @param pVCpu The VMCPU for the EMT we're being called on.
1695 * @param pvUser Unused.
1696 */
1697DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1698{
1699 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1700
1701 /* Only execute the handler on the VCPU the original patch request was issued. */
1702 if (pVCpu->idCpu != idCpu)
1703 return VINF_SUCCESS;
1704
1705 Log(("hmR3RemovePatches\n"));
1706 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1707 {
1708 uint8_t abInstr[15];
1709 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1710 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1711 int rc;
1712
1713#ifdef LOG_ENABLED
1714 char szOutput[256];
1715
1716 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1717 szOutput, sizeof(szOutput), NULL);
1718 if (RT_SUCCESS(rc))
1719 Log(("Patched instr: %s\n", szOutput));
1720#endif
1721
1722 /* Check if the instruction is still the same. */
1723 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1724 if (rc != VINF_SUCCESS)
1725 {
1726 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1727 continue; /* swapped out or otherwise removed; skip it. */
1728 }
1729
1730 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1731 {
1732 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1733 continue; /* skip it. */
1734 }
1735
1736 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1737 AssertRC(rc);
1738
1739#ifdef LOG_ENABLED
1740 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1741 szOutput, sizeof(szOutput), NULL);
1742 if (RT_SUCCESS(rc))
1743 Log(("Original instr: %s\n", szOutput));
1744#endif
1745 }
1746 pVM->hm.s.cPatches = 0;
1747 pVM->hm.s.PatchTree = 0;
1748 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1749 pVM->hm.s.fTPRPatchingActive = false;
1750 return VINF_SUCCESS;
1751}
1752
1753
1754/**
1755 * Worker for enabling patching in a VT-x/AMD-V guest.
1756 *
1757 * @returns VBox status code.
1758 * @param pVM Pointer to the VM.
1759 * @param idCpu VCPU to execute hmR3RemovePatches on.
1760 * @param pPatchMem Patch memory range.
1761 * @param cbPatchMem Size of the memory range.
1762 */
1763static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1764{
1765 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1766 AssertRC(rc);
1767
1768 pVM->hm.s.pGuestPatchMem = pPatchMem;
1769 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1770 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1771 return VINF_SUCCESS;
1772}
1773
1774
1775/**
1776 * Enable patching in a VT-x/AMD-V guest
1777 *
1778 * @returns VBox status code.
1779 * @param pVM Pointer to the VM.
1780 * @param pPatchMem Patch memory range.
1781 * @param cbPatchMem Size of the memory range.
1782 */
1783VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1784{
1785 VM_ASSERT_EMT(pVM);
1786 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1787 if (pVM->cCpus > 1)
1788 {
1789 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1790 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1791 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1792 AssertRC(rc);
1793 return rc;
1794 }
1795 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1796}
1797
1798
1799/**
1800 * Disable patching in a VT-x/AMD-V guest.
1801 *
1802 * @returns VBox status code.
1803 * @param pVM Pointer to the VM.
1804 * @param pPatchMem Patch memory range.
1805 * @param cbPatchMem Size of the memory range.
1806 */
1807VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1808{
1809 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1810
1811 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1812 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1813
1814 /* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1815 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1816 (void *)(uintptr_t)VMMGetCpuId(pVM));
1817 AssertRC(rc);
1818
1819 pVM->hm.s.pGuestPatchMem = 0;
1820 pVM->hm.s.pFreeGuestPatchMem = 0;
1821 pVM->hm.s.cbGuestPatchMem = 0;
1822 pVM->hm.s.fTPRPatchingActive = false;
1823 return VINF_SUCCESS;
1824}
1825
1826
1827/**
1828 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1829 *
1830 * @returns VBox strict status code.
1831 * @param pVM Pointer to the VM.
1832 * @param pVCpu The VMCPU for the EMT we're being called on.
1833 * @param pvUser User specified CPU context.
1834 *
1835 */
1836DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1837{
1838 /*
1839 * Only execute the handler on the VCPU the original patch request was
1840 * issued. (The other CPU(s) might not yet have switched to protected
1841 * mode, nor have the correct memory context.)
1842 */
1843 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1844 if (pVCpu->idCpu != idCpu)
1845 return VINF_SUCCESS;
1846
1847 /*
1848 * We're racing other VCPUs here, so don't try patch the instruction twice
1849 * and make sure there is still room for our patch record.
1850 */
1851 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1852 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1853 if (pPatch)
1854 {
1855 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1856 return VINF_SUCCESS;
1857 }
1858 uint32_t const idx = pVM->hm.s.cPatches;
1859 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1860 {
1861 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1862 return VINF_SUCCESS;
1863 }
1864 pPatch = &pVM->hm.s.aPatches[idx];
1865
1866 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1867
1868 /*
1869 * Disassembler the instruction and get cracking.
1870 */
1871 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1872 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1873 uint32_t cbOp;
1874 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1875 AssertRC(rc);
1876 if ( rc == VINF_SUCCESS
1877 && pDis->pCurInstr->uOpcode == OP_MOV
1878 && cbOp >= 3)
1879 {
1880 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1881
1882 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1883 AssertRC(rc);
1884
1885 pPatch->cbOp = cbOp;
1886
1887 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1888 {
1889 /* write. */
1890 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1891 {
1892 pPatch->enmType = HMTPRINSTR_WRITE_REG;
1893 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1894 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1895 }
1896 else
1897 {
1898 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1899 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1900 pPatch->uSrcOperand = pDis->Param2.uValue;
1901 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1902 }
1903 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1904 AssertRC(rc);
1905
1906 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1907 pPatch->cbNewOp = sizeof(s_abVMMCall);
1908 }
1909 else
1910 {
1911 /*
1912 * TPR Read.
1913 *
1914 * Found:
1915 * mov eax, dword [fffe0080] (5 bytes)
1916 * Check if next instruction is:
1917 * shr eax, 4
1918 */
1919 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1920
1921 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1922 uint8_t const cbOpMmio = cbOp;
1923 uint64_t const uSavedRip = pCtx->rip;
1924
1925 pCtx->rip += cbOp;
1926 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1927 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1928 pCtx->rip = uSavedRip;
1929
1930 if ( rc == VINF_SUCCESS
1931 && pDis->pCurInstr->uOpcode == OP_SHR
1932 && pDis->Param1.fUse == DISUSE_REG_GEN32
1933 && pDis->Param1.Base.idxGenReg == idxMmioReg
1934 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
1935 && pDis->Param2.uValue == 4
1936 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1937 {
1938 uint8_t abInstr[15];
1939
1940 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
1941 access CR8 in 32-bit mode and not cause a #VMEXIT. */
1942 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1943 AssertRC(rc);
1944
1945 pPatch->cbOp = cbOpMmio + cbOp;
1946
1947 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1948 abInstr[0] = 0xF0;
1949 abInstr[1] = 0x0F;
1950 abInstr[2] = 0x20;
1951 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
1952 for (unsigned i = 4; i < pPatch->cbOp; i++)
1953 abInstr[i] = 0x90; /* nop */
1954
1955 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1956 AssertRC(rc);
1957
1958 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1959 pPatch->cbNewOp = pPatch->cbOp;
1960
1961 Log(("Acceptable read/shr candidate!\n"));
1962 pPatch->enmType = HMTPRINSTR_READ_SHR4;
1963 }
1964 else
1965 {
1966 pPatch->enmType = HMTPRINSTR_READ;
1967 pPatch->uDstOperand = idxMmioReg;
1968
1969 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1970 AssertRC(rc);
1971
1972 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1973 pPatch->cbNewOp = sizeof(s_abVMMCall);
1974 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1975 }
1976 }
1977
1978 pPatch->Core.Key = pCtx->eip;
1979 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1980 AssertRC(rc);
1981
1982 pVM->hm.s.cPatches++;
1983 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1984 return VINF_SUCCESS;
1985 }
1986
1987 /*
1988 * Save invalid patch, so we will not try again.
1989 */
1990 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1991 pPatch->Core.Key = pCtx->eip;
1992 pPatch->enmType = HMTPRINSTR_INVALID;
1993 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1994 AssertRC(rc);
1995 pVM->hm.s.cPatches++;
1996 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1997 return VINF_SUCCESS;
1998}
1999
2000
2001/**
2002 * Callback to patch a TPR instruction (jump to generated code).
2003 *
2004 * @returns VBox strict status code.
2005 * @param pVM Pointer to the VM.
2006 * @param pVCpu The VMCPU for the EMT we're being called on.
2007 * @param pvUser User specified CPU context.
2008 *
2009 */
2010DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2011{
2012 /*
2013 * Only execute the handler on the VCPU the original patch request was
2014 * issued. (The other CPU(s) might not yet have switched to protected
2015 * mode, nor have the correct memory context.)
2016 */
2017 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2018 if (pVCpu->idCpu != idCpu)
2019 return VINF_SUCCESS;
2020
2021 /*
2022 * We're racing other VCPUs here, so don't try patch the instruction twice
2023 * and make sure there is still room for our patch record.
2024 */
2025 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2026 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2027 if (pPatch)
2028 {
2029 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2030 return VINF_SUCCESS;
2031 }
2032 uint32_t const idx = pVM->hm.s.cPatches;
2033 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2034 {
2035 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2036 return VINF_SUCCESS;
2037 }
2038 pPatch = &pVM->hm.s.aPatches[idx];
2039
2040 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2041 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2042
2043 /*
2044 * Disassemble the instruction and get cracking.
2045 */
2046 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2047 uint32_t cbOp;
2048 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2049 AssertRC(rc);
2050 if ( rc == VINF_SUCCESS
2051 && pDis->pCurInstr->uOpcode == OP_MOV
2052 && cbOp >= 5)
2053 {
2054 uint8_t aPatch[64];
2055 uint32_t off = 0;
2056
2057 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2058 AssertRC(rc);
2059
2060 pPatch->cbOp = cbOp;
2061 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2062
2063 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2064 {
2065 /*
2066 * TPR write:
2067 *
2068 * push ECX [51]
2069 * push EDX [52]
2070 * push EAX [50]
2071 * xor EDX,EDX [31 D2]
2072 * mov EAX,EAX [89 C0]
2073 * or
2074 * mov EAX,0000000CCh [B8 CC 00 00 00]
2075 * mov ECX,0C0000082h [B9 82 00 00 C0]
2076 * wrmsr [0F 30]
2077 * pop EAX [58]
2078 * pop EDX [5A]
2079 * pop ECX [59]
2080 * jmp return_address [E9 return_address]
2081 *
2082 */
2083 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2084
2085 aPatch[off++] = 0x51; /* push ecx */
2086 aPatch[off++] = 0x52; /* push edx */
2087 if (!fUsesEax)
2088 aPatch[off++] = 0x50; /* push eax */
2089 aPatch[off++] = 0x31; /* xor edx, edx */
2090 aPatch[off++] = 0xD2;
2091 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2092 {
2093 if (!fUsesEax)
2094 {
2095 aPatch[off++] = 0x89; /* mov eax, src_reg */
2096 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2097 }
2098 }
2099 else
2100 {
2101 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2102 aPatch[off++] = 0xB8; /* mov eax, immediate */
2103 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2104 off += sizeof(uint32_t);
2105 }
2106 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2107 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2108 off += sizeof(uint32_t);
2109
2110 aPatch[off++] = 0x0F; /* wrmsr */
2111 aPatch[off++] = 0x30;
2112 if (!fUsesEax)
2113 aPatch[off++] = 0x58; /* pop eax */
2114 aPatch[off++] = 0x5A; /* pop edx */
2115 aPatch[off++] = 0x59; /* pop ecx */
2116 }
2117 else
2118 {
2119 /*
2120 * TPR read:
2121 *
2122 * push ECX [51]
2123 * push EDX [52]
2124 * push EAX [50]
2125 * mov ECX,0C0000082h [B9 82 00 00 C0]
2126 * rdmsr [0F 32]
2127 * mov EAX,EAX [89 C0]
2128 * pop EAX [58]
2129 * pop EDX [5A]
2130 * pop ECX [59]
2131 * jmp return_address [E9 return_address]
2132 *
2133 */
2134 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2135
2136 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2137 aPatch[off++] = 0x51; /* push ecx */
2138 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2139 aPatch[off++] = 0x52; /* push edx */
2140 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2141 aPatch[off++] = 0x50; /* push eax */
2142
2143 aPatch[off++] = 0x31; /* xor edx, edx */
2144 aPatch[off++] = 0xD2;
2145
2146 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2147 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2148 off += sizeof(uint32_t);
2149
2150 aPatch[off++] = 0x0F; /* rdmsr */
2151 aPatch[off++] = 0x32;
2152
2153 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2154 {
2155 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2156 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2157 }
2158
2159 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2160 aPatch[off++] = 0x58; /* pop eax */
2161 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2162 aPatch[off++] = 0x5A; /* pop edx */
2163 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2164 aPatch[off++] = 0x59; /* pop ecx */
2165 }
2166 aPatch[off++] = 0xE9; /* jmp return_address */
2167 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2168 off += sizeof(RTRCUINTPTR);
2169
2170 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2171 {
2172 /* Write new code to the patch buffer. */
2173 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2174 AssertRC(rc);
2175
2176#ifdef LOG_ENABLED
2177 uint32_t cbCurInstr;
2178 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2179 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2180 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2181 {
2182 char szOutput[256];
2183 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2184 szOutput, sizeof(szOutput), &cbCurInstr);
2185 if (RT_SUCCESS(rc))
2186 Log(("Patch instr %s\n", szOutput));
2187 else
2188 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2189 }
2190#endif
2191
2192 pPatch->aNewOpcode[0] = 0xE9;
2193 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2194
2195 /* Overwrite the TPR instruction with a jump. */
2196 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2197 AssertRC(rc);
2198
2199 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2200
2201 pVM->hm.s.pFreeGuestPatchMem += off;
2202 pPatch->cbNewOp = 5;
2203
2204 pPatch->Core.Key = pCtx->eip;
2205 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2206 AssertRC(rc);
2207
2208 pVM->hm.s.cPatches++;
2209 pVM->hm.s.fTPRPatchingActive = true;
2210 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2211 return VINF_SUCCESS;
2212 }
2213
2214 Log(("Ran out of space in our patch buffer!\n"));
2215 }
2216 else
2217 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2218
2219
2220 /*
2221 * Save invalid patch, so we will not try again.
2222 */
2223 pPatch = &pVM->hm.s.aPatches[idx];
2224 pPatch->Core.Key = pCtx->eip;
2225 pPatch->enmType = HMTPRINSTR_INVALID;
2226 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2227 AssertRC(rc);
2228 pVM->hm.s.cPatches++;
2229 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2230 return VINF_SUCCESS;
2231}
2232
2233
2234/**
2235 * Attempt to patch TPR mmio instructions.
2236 *
2237 * @returns VBox status code.
2238 * @param pVM Pointer to the VM.
2239 * @param pVCpu Pointer to the VMCPU.
2240 * @param pCtx Pointer to the guest CPU context.
2241 */
2242VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2243{
2244 NOREF(pCtx);
2245 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2246 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2247 (void *)(uintptr_t)pVCpu->idCpu);
2248 AssertRC(rc);
2249 return rc;
2250}
2251
2252
2253/**
2254 * Checks if a code selector (CS) is suitable for execution
2255 * within VMX when unrestricted execution isn't available.
2256 *
2257 * @returns true if selector is suitable for VMX, otherwise
2258 * false.
2259 * @param pSel Pointer to the selector to check (CS).
2260 * uStackDpl The CPL, aka the DPL of the stack segment.
2261 */
2262static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2263{
2264 /*
2265 * Segment must be an accessed code segment, it must be present and it must
2266 * be usable.
2267 * Note! These are all standard requirements and if CS holds anything else
2268 * we've got buggy code somewhere!
2269 */
2270 AssertCompile(X86DESCATTR_TYPE == 0xf);
2271 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2272 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2273 ("%#x\n", pSel->Attr.u),
2274 false);
2275
2276 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2277 must equal SS.DPL for non-confroming segments.
2278 Note! This is also a hard requirement like above. */
2279 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2280 ? pSel->Attr.n.u2Dpl <= uStackDpl
2281 : pSel->Attr.n.u2Dpl == uStackDpl,
2282 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2283 false);
2284
2285 /*
2286 * The following two requirements are VT-x specific:
2287 * - G bit must be set if any high limit bits are set.
2288 * - G bit must be clear if any low limit bits are clear.
2289 */
2290 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2291 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2292 return true;
2293 return false;
2294}
2295
2296
2297/**
2298 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2299 * execution within VMX when unrestricted execution isn't
2300 * available.
2301 *
2302 * @returns true if selector is suitable for VMX, otherwise
2303 * false.
2304 * @param pSel Pointer to the selector to check
2305 * (DS/ES/FS/GS).
2306 */
2307static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2308{
2309 /*
2310 * Unusable segments are OK. These days they should be marked as such, as
2311 * but as an alternative we for old saved states and AMD<->VT-x migration
2312 * we also treat segments with all the attributes cleared as unusable.
2313 */
2314 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2315 return true;
2316
2317 /** @todo tighten these checks. Will require CPUM load adjusting. */
2318
2319 /* Segment must be accessed. */
2320 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2321 {
2322 /* Code segments must also be readable. */
2323 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2324 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2325 {
2326 /* The S bit must be set. */
2327 if (pSel->Attr.n.u1DescType)
2328 {
2329 /* Except for conforming segments, DPL >= RPL. */
2330 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2331 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2332 {
2333 /* Segment must be present. */
2334 if (pSel->Attr.n.u1Present)
2335 {
2336 /*
2337 * The following two requirements are VT-x specific:
2338 * - G bit must be set if any high limit bits are set.
2339 * - G bit must be clear if any low limit bits are clear.
2340 */
2341 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2342 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2343 return true;
2344 }
2345 }
2346 }
2347 }
2348 }
2349
2350 return false;
2351}
2352
2353
2354/**
2355 * Checks if the stack selector (SS) is suitable for execution
2356 * within VMX when unrestricted execution isn't available.
2357 *
2358 * @returns true if selector is suitable for VMX, otherwise
2359 * false.
2360 * @param pSel Pointer to the selector to check (SS).
2361 */
2362static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2363{
2364 /*
2365 * Unusable segments are OK. These days they should be marked as such, as
2366 * but as an alternative we for old saved states and AMD<->VT-x migration
2367 * we also treat segments with all the attributes cleared as unusable.
2368 */
2369 /** @todo r=bird: actually all zeros isn't gonna cut it... SS.DPL == CPL. */
2370 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2371 return true;
2372
2373 /*
2374 * Segment must be an accessed writable segment, it must be present.
2375 * Note! These are all standard requirements and if SS holds anything else
2376 * we've got buggy code somewhere!
2377 */
2378 AssertCompile(X86DESCATTR_TYPE == 0xf);
2379 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2380 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2381 ("%#x\n", pSel->Attr.u),
2382 false);
2383
2384 /* DPL must equal RPL.
2385 Note! This is also a hard requirement like above. */
2386 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2387 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2388 false);
2389
2390 /*
2391 * The following two requirements are VT-x specific:
2392 * - G bit must be set if any high limit bits are set.
2393 * - G bit must be clear if any low limit bits are clear.
2394 */
2395 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2396 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2397 return true;
2398 return false;
2399}
2400
2401
2402/**
2403 * Force execution of the current IO code in the recompiler.
2404 *
2405 * @returns VBox status code.
2406 * @param pVM Pointer to the VM.
2407 * @param pCtx Partial VM execution context.
2408 */
2409VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2410{
2411 PVMCPU pVCpu = VMMGetCpu(pVM);
2412
2413 Assert(HMIsEnabled(pVM));
2414 Log(("HMR3EmulateIoBlock\n"));
2415
2416 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2417 if (HMCanEmulateIoBlockEx(pCtx))
2418 {
2419 Log(("HMR3EmulateIoBlock -> enabled\n"));
2420 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2421 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2422 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2423 return VINF_EM_RESCHEDULE_REM;
2424 }
2425 return VINF_SUCCESS;
2426}
2427
2428
2429/**
2430 * Checks if we can currently use hardware accelerated raw mode.
2431 *
2432 * @returns true if we can currently use hardware acceleration, otherwise false.
2433 * @param pVM Pointer to the VM.
2434 * @param pCtx Partial VM execution context.
2435 */
2436VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2437{
2438 PVMCPU pVCpu = VMMGetCpu(pVM);
2439
2440 Assert(HMIsEnabled(pVM));
2441
2442 /* If we're still executing the IO code, then return false. */
2443 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2444 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2445 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2446 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2447 return false;
2448
2449 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2450
2451 /* AMD-V supports real & protected mode with or without paging. */
2452 if (pVM->hm.s.svm.fEnabled)
2453 {
2454 pVCpu->hm.s.fActive = true;
2455 return true;
2456 }
2457
2458 pVCpu->hm.s.fActive = false;
2459
2460 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2461 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2462 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2463
2464 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2465 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2466 {
2467 /*
2468 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2469 * guest execution feature i missing (VT-x only).
2470 */
2471 if (fSupportsRealMode)
2472 {
2473 if (CPUMIsGuestInRealModeEx(pCtx))
2474 {
2475 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2476 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2477 * If this is not true, we cannot execute real mode as V86 and have to fall
2478 * back to emulation.
2479 */
2480 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2481 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2482 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2483 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2484 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2485 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2486 {
2487 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2488 return false;
2489 }
2490 if ( (pCtx->cs.u32Limit != 0xffff)
2491 || (pCtx->ds.u32Limit != 0xffff)
2492 || (pCtx->es.u32Limit != 0xffff)
2493 || (pCtx->ss.u32Limit != 0xffff)
2494 || (pCtx->fs.u32Limit != 0xffff)
2495 || (pCtx->gs.u32Limit != 0xffff))
2496 {
2497 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2498 return false;
2499 }
2500 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2501 }
2502 else
2503 {
2504 /* Verify the requirements for executing code in protected
2505 mode. VT-x can't handle the CPU state right after a switch
2506 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2507 if (pVCpu->hm.s.vmx.fWasInRealMode)
2508 {
2509 /** @todo If guest is in V86 mode, these checks should be different! */
2510 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2511 {
2512 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2513 return false;
2514 }
2515 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2516 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2517 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2518 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2519 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2520 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2521 {
2522 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2523 return false;
2524 }
2525 }
2526 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2527 if (pCtx->gdtr.cbGdt)
2528 {
2529 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2530 {
2531 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2532 return false;
2533 }
2534 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2535 {
2536 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2537 return false;
2538 }
2539 }
2540 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2541 }
2542 }
2543 else
2544 {
2545 if ( !CPUMIsGuestInLongModeEx(pCtx)
2546 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2547 {
2548 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2549 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2550 return false;
2551
2552 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2553 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2554 return false;
2555
2556 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2557 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2558 * hidden registers (possible recompiler bug; see load_seg_vm) */
2559 if (pCtx->cs.Attr.n.u1Present == 0)
2560 return false;
2561 if (pCtx->ss.Attr.n.u1Present == 0)
2562 return false;
2563
2564 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2565 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2566 /** @todo This check is actually wrong, it doesn't take the direction of the
2567 * stack segment into account. But, it does the job for now. */
2568 if (pCtx->rsp >= pCtx->ss.u32Limit)
2569 return false;
2570 }
2571 }
2572 }
2573
2574 if (pVM->hm.s.vmx.fEnabled)
2575 {
2576 uint32_t mask;
2577
2578 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2579 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2580 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2581 mask &= ~X86_CR0_NE;
2582
2583 if (fSupportsRealMode)
2584 {
2585 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2586 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2587 }
2588 else
2589 {
2590 /* We support protected mode without paging using identity mapping. */
2591 mask &= ~X86_CR0_PG;
2592 }
2593 if ((pCtx->cr0 & mask) != mask)
2594 return false;
2595
2596 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2597 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2598 if ((pCtx->cr0 & mask) != 0)
2599 return false;
2600
2601 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2602 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2603 mask &= ~X86_CR4_VMXE;
2604 if ((pCtx->cr4 & mask) != mask)
2605 return false;
2606
2607 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2608 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2609 if ((pCtx->cr4 & mask) != 0)
2610 return false;
2611
2612 pVCpu->hm.s.fActive = true;
2613 return true;
2614 }
2615
2616 return false;
2617}
2618
2619
2620/**
2621 * Checks if we need to reschedule due to VMM device heap changes.
2622 *
2623 * @returns true if a reschedule is required, otherwise false.
2624 * @param pVM Pointer to the VM.
2625 * @param pCtx VM execution context.
2626 */
2627VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2628{
2629 /*
2630 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2631 * when the unrestricted guest execution feature is missing (VT-x only).
2632 */
2633 if ( pVM->hm.s.vmx.fEnabled
2634 && !pVM->hm.s.vmx.fUnrestrictedGuest
2635 && CPUMIsGuestInRealModeEx(pCtx)
2636 && !PDMVmmDevHeapIsEnabled(pVM))
2637 {
2638 return true;
2639 }
2640
2641 return false;
2642}
2643
2644
2645/**
2646 * Notification from EM about a rescheduling into hardware assisted execution
2647 * mode.
2648 *
2649 * @param pVCpu Pointer to the current VMCPU.
2650 */
2651VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2652{
2653 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2654}
2655
2656
2657/**
2658 * Notification from EM about returning from instruction emulation (REM / EM).
2659 *
2660 * @param pVCpu Pointer to the VMCPU.
2661 */
2662VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2663{
2664 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2665}
2666
2667
2668/**
2669 * Checks if we are currently using hardware accelerated raw mode.
2670 *
2671 * @returns true if hardware acceleration is being used, otherwise false.
2672 * @param pVCpu Pointer to the VMCPU.
2673 */
2674VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2675{
2676 return pVCpu->hm.s.fActive;
2677}
2678
2679
2680/**
2681 * External interface for querying whether hardware accelerated raw mode is
2682 * enabled.
2683 *
2684 * @returns true if VT-x or AMD-V is being used, otherwise false.
2685 * @param pUVM The user mode VM handle.
2686 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2687 */
2688VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2689{
2690 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2691 PVM pVM = pUVM->pVM;
2692 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2693 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2694}
2695
2696
2697/**
2698 * External interface for querying whether VT-x is being used.
2699 *
2700 * @returns true if VT-x is being used, otherwise false.
2701 * @param pUVM The user mode VM handle.
2702 * @sa HMR3IsSvmEnabled, HMIsEnabled
2703 */
2704VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2705{
2706 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2707 PVM pVM = pUVM->pVM;
2708 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2709 return pVM->hm.s.vmx.fEnabled
2710 && pVM->hm.s.vmx.fSupported
2711 && pVM->fHMEnabled;
2712}
2713
2714
2715/**
2716 * External interface for querying whether AMD-V is being used.
2717 *
2718 * @returns true if VT-x is being used, otherwise false.
2719 * @param pUVM The user mode VM handle.
2720 * @sa HMR3IsVmxEnabled, HMIsEnabled
2721 */
2722VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2723{
2724 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2725 PVM pVM = pUVM->pVM;
2726 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2727 return pVM->hm.s.svm.fEnabled
2728 && pVM->hm.s.svm.fSupported
2729 && pVM->fHMEnabled;
2730}
2731
2732
2733/**
2734 * Checks if we are currently using nested paging.
2735 *
2736 * @returns true if nested paging is being used, otherwise false.
2737 * @param pUVM The user mode VM handle.
2738 */
2739VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2740{
2741 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2742 PVM pVM = pUVM->pVM;
2743 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2744 return pVM->hm.s.fNestedPaging;
2745}
2746
2747
2748/**
2749 * Checks if we are currently using VPID in VT-x mode.
2750 *
2751 * @returns true if VPID is being used, otherwise false.
2752 * @param pUVM The user mode VM handle.
2753 */
2754VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2755{
2756 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2757 PVM pVM = pUVM->pVM;
2758 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2759 return pVM->hm.s.vmx.fVpid;
2760}
2761
2762
2763/**
2764 * Checks if we are currently using VT-x unrestricted execution,
2765 * aka UX.
2766 *
2767 * @returns true if UX is being used, otherwise false.
2768 * @param pUVM The user mode VM handle.
2769 */
2770VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2771{
2772 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2773 PVM pVM = pUVM->pVM;
2774 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2775 return pVM->hm.s.vmx.fUnrestrictedGuest;
2776}
2777
2778
2779/**
2780 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2781 *
2782 * @returns true if an internal event is pending, otherwise false.
2783 * @param pVM Pointer to the VM.
2784 */
2785VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2786{
2787 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2788}
2789
2790
2791/**
2792 * Checks if the VMX-preemption timer is being used.
2793 *
2794 * @returns true if the VMX-preemption timer is being used, otherwise false.
2795 * @param pVM Pointer to the VM.
2796 */
2797VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2798{
2799 return HMIsEnabled(pVM)
2800 && pVM->hm.s.vmx.fEnabled
2801 && pVM->hm.s.vmx.fUsePreemptTimer;
2802}
2803
2804
2805/**
2806 * Restart an I/O instruction that was refused in ring-0
2807 *
2808 * @returns Strict VBox status code. Informational status codes other than the one documented
2809 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2810 * @retval VINF_SUCCESS Success.
2811 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2812 * status code must be passed on to EM.
2813 * @retval VERR_NOT_FOUND if no pending I/O instruction.
2814 *
2815 * @param pVM Pointer to the VM.
2816 * @param pVCpu Pointer to the VMCPU.
2817 * @param pCtx Pointer to the guest CPU context.
2818 */
2819VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2820{
2821 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2822
2823 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2824
2825 if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2826 || enmType == HMPENDINGIO_INVALID)
2827 return VERR_NOT_FOUND;
2828
2829 VBOXSTRICTRC rcStrict;
2830 switch (enmType)
2831 {
2832 case HMPENDINGIO_PORT_READ:
2833 {
2834 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2835 uint32_t u32Val = 0;
2836
2837 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2838 &u32Val,
2839 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2840 if (IOM_SUCCESS(rcStrict))
2841 {
2842 /* Write back to the EAX register. */
2843 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
2844 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2845 }
2846 break;
2847 }
2848
2849 case HMPENDINGIO_PORT_WRITE:
2850 rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2851 pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2852 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2853 if (IOM_SUCCESS(rcStrict))
2854 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2855 break;
2856
2857 default:
2858 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2859 }
2860
2861 if (IOM_SUCCESS(rcStrict))
2862 {
2863 /*
2864 * Check for I/O breakpoints.
2865 */
2866 uint32_t const uDr7 = pCtx->dr[7];
2867 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
2868 && X86_DR7_ANY_RW_IO(uDr7)
2869 && (pCtx->cr4 & X86_CR4_DE))
2870 || DBGFBpIsHwIoArmed(pVM))
2871 {
2872 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
2873 pVCpu->hm.s.PendingIO.s.Port.cbSize);
2874 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
2875 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
2876 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
2877 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
2878 rcStrict = rcStrict2;
2879 }
2880 }
2881 return rcStrict;
2882}
2883
2884
2885/**
2886 * Check fatal VT-x/AMD-V error and produce some meaningful
2887 * log release message.
2888 *
2889 * @param pVM Pointer to the VM.
2890 * @param iStatusCode VBox status code.
2891 */
2892VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2893{
2894 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2895 {
2896 PVMCPU pVCpu = &pVM->aCpus[i];
2897 switch (iStatusCode)
2898 {
2899 case VERR_VMX_INVALID_VMCS_FIELD:
2900 break;
2901
2902 case VERR_VMX_INVALID_VMCS_PTR:
2903 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2904 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
2905 pVCpu->hm.s.vmx.HCPhysVmcs));
2906 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
2907 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2908 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2909 break;
2910
2911 case VERR_VMX_UNABLE_TO_START_VM:
2912 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2913 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
2914 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2915
2916 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
2917 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
2918 {
2919 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2920 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2921 }
2922 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2923 {
2924 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
2925 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
2926 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
2927 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
2928 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
2929 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
2930 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
2931 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
2932 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
2933 }
2934 /** @todo Log VM-entry event injection control fields
2935 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2936 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2937 break;
2938
2939 case VERR_VMX_INVALID_VMXON_PTR:
2940 break;
2941
2942 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
2943 case VERR_VMX_INVALID_GUEST_STATE:
2944 case VERR_VMX_UNEXPECTED_EXIT:
2945 case VERR_SVM_UNKNOWN_EXIT:
2946 case VERR_SVM_UNEXPECTED_EXIT:
2947 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
2948 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
2949 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
2950 {
2951 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
2952 break;
2953 }
2954 }
2955 }
2956
2957 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2958 {
2959 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
2960 LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
2961 }
2962}
2963
2964
2965/**
2966 * Execute state save operation.
2967 *
2968 * @returns VBox status code.
2969 * @param pVM Pointer to the VM.
2970 * @param pSSM SSM operation handle.
2971 */
2972static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2973{
2974 int rc;
2975
2976 Log(("hmR3Save:\n"));
2977
2978 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2979 {
2980 /*
2981 * Save the basic bits - fortunately all the other things can be resynced on load.
2982 */
2983 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2984 AssertRCReturn(rc, rc);
2985 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2986 AssertRCReturn(rc, rc);
2987 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
2988 AssertRCReturn(rc, rc);
2989 /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
2990
2991 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
2992 * perhaps not even that (the initial value of @c true is safe. */
2993 uint32_t u32Dummy = PGMMODE_REAL;
2994 rc = SSMR3PutU32(pSSM, u32Dummy);
2995 AssertRCReturn(rc, rc);
2996 rc = SSMR3PutU32(pSSM, u32Dummy);
2997 AssertRCReturn(rc, rc);
2998 rc = SSMR3PutU32(pSSM, u32Dummy);
2999 AssertRCReturn(rc, rc);
3000 }
3001
3002#ifdef VBOX_HM_WITH_GUEST_PATCHING
3003 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3004 AssertRCReturn(rc, rc);
3005 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3006 AssertRCReturn(rc, rc);
3007 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3008 AssertRCReturn(rc, rc);
3009
3010 /* Store all the guest patch records too. */
3011 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3012 AssertRCReturn(rc, rc);
3013
3014 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3015 {
3016 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3017
3018 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3019 AssertRCReturn(rc, rc);
3020
3021 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3022 AssertRCReturn(rc, rc);
3023
3024 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3025 AssertRCReturn(rc, rc);
3026
3027 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3028 AssertRCReturn(rc, rc);
3029
3030 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3031 AssertRCReturn(rc, rc);
3032
3033 AssertCompileSize(HMTPRINSTR, 4);
3034 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3035 AssertRCReturn(rc, rc);
3036
3037 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3038 AssertRCReturn(rc, rc);
3039
3040 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3041 AssertRCReturn(rc, rc);
3042
3043 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3044 AssertRCReturn(rc, rc);
3045
3046 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3047 AssertRCReturn(rc, rc);
3048 }
3049#endif
3050 return VINF_SUCCESS;
3051}
3052
3053
3054/**
3055 * Execute state load operation.
3056 *
3057 * @returns VBox status code.
3058 * @param pVM Pointer to the VM.
3059 * @param pSSM SSM operation handle.
3060 * @param uVersion Data layout version.
3061 * @param uPass The data pass.
3062 */
3063static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3064{
3065 int rc;
3066
3067 Log(("hmR3Load:\n"));
3068 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3069
3070 /*
3071 * Validate version.
3072 */
3073 if ( uVersion != HM_SSM_VERSION
3074 && uVersion != HM_SSM_VERSION_NO_PATCHING
3075 && uVersion != HM_SSM_VERSION_2_0_X)
3076 {
3077 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3078 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3079 }
3080 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3081 {
3082 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3083 AssertRCReturn(rc, rc);
3084 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3085 AssertRCReturn(rc, rc);
3086 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3087 AssertRCReturn(rc, rc);
3088
3089 if (uVersion >= HM_SSM_VERSION_NO_PATCHING)
3090 {
3091 uint32_t val;
3092 /** @todo See note in hmR3Save(). */
3093 rc = SSMR3GetU32(pSSM, &val);
3094 AssertRCReturn(rc, rc);
3095 rc = SSMR3GetU32(pSSM, &val);
3096 AssertRCReturn(rc, rc);
3097 rc = SSMR3GetU32(pSSM, &val);
3098 AssertRCReturn(rc, rc);
3099 }
3100 }
3101#ifdef VBOX_HM_WITH_GUEST_PATCHING
3102 if (uVersion > HM_SSM_VERSION_NO_PATCHING)
3103 {
3104 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3105 AssertRCReturn(rc, rc);
3106 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3107 AssertRCReturn(rc, rc);
3108 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3109 AssertRCReturn(rc, rc);
3110
3111 /* Fetch all TPR patch records. */
3112 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3113 AssertRCReturn(rc, rc);
3114
3115 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3116 {
3117 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3118
3119 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3120 AssertRCReturn(rc, rc);
3121
3122 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3123 AssertRCReturn(rc, rc);
3124
3125 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3126 AssertRCReturn(rc, rc);
3127
3128 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3129 AssertRCReturn(rc, rc);
3130
3131 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3132 AssertRCReturn(rc, rc);
3133
3134 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3135 AssertRCReturn(rc, rc);
3136
3137 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3138 pVM->hm.s.fTPRPatchingActive = true;
3139
3140 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3141
3142 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3143 AssertRCReturn(rc, rc);
3144
3145 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3146 AssertRCReturn(rc, rc);
3147
3148 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3149 AssertRCReturn(rc, rc);
3150
3151 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3152 AssertRCReturn(rc, rc);
3153
3154 Log(("hmR3Load: patch %d\n", i));
3155 Log(("Key = %x\n", pPatch->Core.Key));
3156 Log(("cbOp = %d\n", pPatch->cbOp));
3157 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3158 Log(("type = %d\n", pPatch->enmType));
3159 Log(("srcop = %d\n", pPatch->uSrcOperand));
3160 Log(("dstop = %d\n", pPatch->uDstOperand));
3161 Log(("cFaults = %d\n", pPatch->cFaults));
3162 Log(("target = %x\n", pPatch->pJumpTarget));
3163 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3164 AssertRC(rc);
3165 }
3166 }
3167#endif
3168
3169 return VINF_SUCCESS;
3170}
3171
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