HM.cpp@ 53349

Last change on this file since 53349 was 52766, checked in by vboxsync, 10 years ago
VMM/HM: Fixing source of ambiguity.
Property svn:eol-style set to `native` Property svn:keywords set to `Id Revision`
File size: 138.7 KB

Line
1	/* $Id: HM.cpp 52766 2014-09-16 16:21:44Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2014 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18
19	/*******************************************************************************
20	* Header Files *
21	*******************************************************************************/
22	#define LOG_GROUP LOG_GROUP_HM
23	#include <VBox/vmm/cpum.h>
24	#include <VBox/vmm/stam.h>
25	#include <VBox/vmm/mm.h>
26	#include <VBox/vmm/pdmapi.h>
27	#include <VBox/vmm/pgm.h>
28	#include <VBox/vmm/ssm.h>
29	#include <VBox/vmm/trpm.h>
30	#include <VBox/vmm/dbgf.h>
31	#include <VBox/vmm/iom.h>
32	#include <VBox/vmm/patm.h>
33	#include <VBox/vmm/csam.h>
34	#include <VBox/vmm/selm.h>
35	#ifdef VBOX_WITH_REM
36	# include <VBox/vmm/rem.h>
37	#endif
38	#include <VBox/vmm/hm_vmx.h>
39	#include <VBox/vmm/hm_svm.h>
40	#include "HMInternal.h"
41	#include <VBox/vmm/vm.h>
42	#include <VBox/vmm/uvm.h>
43	#include <VBox/err.h>
44	#include <VBox/param.h>
45
46	#include <iprt/assert.h>
47	#include <VBox/log.h>
48	#include <iprt/asm.h>
49	#include <iprt/asm-amd64-x86.h>
50	#include <iprt/env.h>
51	#include <iprt/thread.h>
52
53
54	/*******************************************************************************
55	* Global Variables *
56	*******************************************************************************/
57	#ifdef VBOX_WITH_STATISTICS
58	# define EXIT_REASON(def, val, str) #def " - " #val " - " str
59	# define EXIT_REASON_NIL() NULL
60	/** Exit reason descriptions for VT-x, used to describe statistics. */
61	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
62	{
63	EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
64	EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
65	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
66	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
67	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
68	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
69	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
70	EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
71	EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
72	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
73	EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
74	EXIT_REASON_NIL(),
75	EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
76	EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
77	EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
78	EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
79	EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
80	EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
81	EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
82	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
83	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
84	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
85	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
86	EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
87	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
88	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
89	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
90	EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
91	EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
92	EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
93	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
94	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
95	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
96	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
97	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
98	EXIT_REASON_NIL(),
99	EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
100	EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
101	EXIT_REASON_NIL(),
102	EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
103	EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
104	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
105	EXIT_REASON_NIL(),
106	EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD, 43, "TPR below threshold (MOV to CR8)."),
107	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
108	EXIT_REASON_NIL(),
109	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "Access to GDTR or IDTR using LGDT, LIDT, SGDT, or SIDT."),
110	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "Access to LDTR or TR using LLDT, LTR, SLDT, or STR."),
111	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
112	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
113	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
114	EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
115	EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
116	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
117	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
118	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
119	EXIT_REASON_NIL(),
120	EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
121	EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
122	EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction.")
123	};
124	/** Exit reason descriptions for AMD-V, used to describe statistics. */
125	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
126	{
127	EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
128	EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
129	EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
130	EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
131	EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
132	EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
133	EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
134	EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
135	EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
136	EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
137	EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
138	EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
139	EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
140	EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
141	EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
142	EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
143	EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
144	EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
145	EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
146	EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
147	EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
148	EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
149	EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
150	EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
151	EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
152	EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
153	EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
154	EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
155	EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
156	EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
157	EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
158	EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
159	EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
160	EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
161	EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
162	EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
163	EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
164	EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
165	EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
166	EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
167	EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
168	EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
169	EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
170	EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
171	EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
172	EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
173	EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
174	EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
175	EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
176	EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
177	EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
178	EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
179	EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
180	EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
181	EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
182	EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
183	EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
184	EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
185	EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
186	EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
187	EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
188	EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
189	EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
190	EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
191	EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
192	EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
193	EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
194	EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
195	EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
196	EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
197	EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
198	EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
199	EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
200	EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
201	EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
202	EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
203	EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
204	EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
205	EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
206	EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
207	EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
208	EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
209	EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
210	EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
211	EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
212	EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
213	EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
214	EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
215	EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
216	EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
217	EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
218	EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
219	EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
220	EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
221	EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
222	EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
223	EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
224	EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
225	EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
226	EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
227	EXIT_REASON(SVM_EXIT_VINTR ,100, "Virtual interrupt-window exit."),
228	EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE ,101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
229	EXIT_REASON(SVM_EXIT_IDTR_READ ,102, "Read IDTR"),
230	EXIT_REASON(SVM_EXIT_GDTR_READ ,103, "Read GDTR"),
231	EXIT_REASON(SVM_EXIT_LDTR_READ ,104, "Read LDTR."),
232	EXIT_REASON(SVM_EXIT_TR_READ ,105, "Read TR."),
233	EXIT_REASON(SVM_EXIT_TR_READ ,106, "Write IDTR."),
234	EXIT_REASON(SVM_EXIT_TR_READ ,107, "Write GDTR."),
235	EXIT_REASON(SVM_EXIT_TR_READ ,108, "Write LDTR."),
236	EXIT_REASON(SVM_EXIT_TR_READ ,109, "Write TR."),
237	EXIT_REASON(SVM_EXIT_RDTSC ,110, "RDTSC instruction."),
238	EXIT_REASON(SVM_EXIT_RDPMC ,111, "RDPMC instruction."),
239	EXIT_REASON(SVM_EXIT_PUSHF ,112, "PUSHF instruction."),
240	EXIT_REASON(SVM_EXIT_POPF ,113, "POPF instruction."),
241	EXIT_REASON(SVM_EXIT_CPUID ,114, "CPUID instruction."),
242	EXIT_REASON(SVM_EXIT_RSM ,115, "RSM instruction."),
243	EXIT_REASON(SVM_EXIT_IRET ,116, "IRET instruction."),
244	EXIT_REASON(SVM_EXIT_SWINT ,117, "Software interrupt (INTn instructions)."),
245	EXIT_REASON(SVM_EXIT_INVD ,118, "INVD instruction."),
246	EXIT_REASON(SVM_EXIT_PAUSE ,119, "PAUSE instruction."),
247	EXIT_REASON(SVM_EXIT_HLT ,120, "HLT instruction."),
248	EXIT_REASON(SVM_EXIT_INVLPG ,121, "INVLPG instruction."),
249	EXIT_REASON(SVM_EXIT_INVLPGA ,122, "INVLPGA instruction."),
250	EXIT_REASON(SVM_EXIT_IOIO ,123, "IN/OUT accessing protected port."),
251	EXIT_REASON(SVM_EXIT_MSR ,124, "RDMSR or WRMSR access to protected MSR."),
252	EXIT_REASON(SVM_EXIT_TASK_SWITCH ,125, "Task switch."),
253	EXIT_REASON(SVM_EXIT_FERR_FREEZE ,126, "Legacy FPU handling enabled; processor is frozen in an x87/mmx instruction waiting for an interrupt"),
254	EXIT_REASON(SVM_EXIT_SHUTDOWN ,127, "Shutdown."),
255	EXIT_REASON(SVM_EXIT_VMRUN ,128, "VMRUN instruction."),
256	EXIT_REASON(SVM_EXIT_VMMCALL ,129, "VMCALL instruction."),
257	EXIT_REASON(SVM_EXIT_VMLOAD ,130, "VMLOAD instruction."),
258	EXIT_REASON(SVM_EXIT_VMSAVE ,131, "VMSAVE instruction."),
259	EXIT_REASON(SVM_EXIT_STGI ,132, "STGI instruction."),
260	EXIT_REASON(SVM_EXIT_CLGI ,133, "CLGI instruction."),
261	EXIT_REASON(SVM_EXIT_SKINIT ,134, "SKINIT instruction."),
262	EXIT_REASON(SVM_EXIT_RDTSCP ,135, "RDTSCP instruction."),
263	EXIT_REASON(SVM_EXIT_ICEBP ,136, "ICEBP instruction."),
264	EXIT_REASON(SVM_EXIT_WBINVD ,137, "WBINVD instruction."),
265	EXIT_REASON(SVM_EXIT_MONITOR ,138, "MONITOR instruction."),
266	EXIT_REASON(SVM_EXIT_MWAIT ,139, "MWAIT instruction."),
267	EXIT_REASON(SVM_EXIT_MWAIT_ARMED ,140, "MWAIT instruction when armed."),
268	EXIT_REASON(SVM_EXIT_NPF ,1024, "Nested paging fault."),
269	EXIT_REASON_NIL()
270	};
271	# undef EXIT_REASON
272	# undef EXIT_REASON_NIL
273	#endif /* VBOX_WITH_STATISTICS */
274
275	#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, featflag) \
276	do { \
277	if ((allowed1) & (featflag)) \
278	LogRel(("HM: " #featflag "\n")); \
279	else \
280	LogRel(("HM: " #featflag " (must be cleared)\n")); \
281	if ((disallowed0) & (featflag)) \
282	LogRel(("HM: " #featflag " (must be set)\n")); \
283	} while (0)
284
285	#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, featflag) \
286	do { \
287	if ((allowed1) & (featflag)) \
288	LogRel(("HM: " #featflag "\n")); \
289	else \
290	LogRel(("HM: " #featflag " not supported\n")); \
291	} while (0)
292
293	#define HMVMX_REPORT_CAPABILITY(msrcaps, cap) \
294	do { \
295	if ((msrcaps) & (cap)) \
296	LogRel(("HM: " #cap "\n")); \
297	} while (0)
298
299
300	/*******************************************************************************
301	* Internal Functions *
302	*******************************************************************************/
303	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
304	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
305	static int hmR3InitCPU(PVM pVM);
306	static int hmR3InitFinalizeR0(PVM pVM);
307	static int hmR3InitFinalizeR0Intel(PVM pVM);
308	static int hmR3InitFinalizeR0Amd(PVM pVM);
309	static int hmR3TermCPU(PVM pVM);
310
311
312
313	/**
314	* Initializes the HM.
315	*
316	* This reads the config and check whether VT-x or AMD-V hardware is available
317	* if configured to use it. This is one of the very first components to be
318	* initialized after CFGM, so that we can fall back to raw-mode early in the
319	* initialization process.
320	*
321	* Note that a lot of the set up work is done in ring-0 and thus postponed till
322	* the ring-3 and ring-0 callback to HMR3InitCompleted.
323	*
324	* @returns VBox status code.
325	* @param pVM Pointer to the VM.
326	*
327	* @remarks Be careful with what we call here, since most of the VMM components
328	* are uninitialized.
329	*/
330	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
331	{
332	LogFlow(("HMR3Init\n"));
333
334	/*
335	* Assert alignment and sizes.
336	*/
337	AssertCompileMemberAlignment(VM, hm.s, 32);
338	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
339
340	/*
341	* Register the saved state data unit.
342	*/
343	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
344	NULL, NULL, NULL,
345	NULL, hmR3Save, NULL,
346	NULL, hmR3Load, NULL);
347	if (RT_FAILURE(rc))
348	return rc;
349
350	/*
351	* Misc initialisation.
352	*/
353	#if 0
354	pVM->hm.s.vmx.fSupported = false;
355	pVM->hm.s.svm.fSupported = false;
356	pVM->hm.s.vmx.fEnabled = false;
357	pVM->hm.s.svm.fEnabled = false;
358	pVM->hm.s.fNestedPaging = false;
359	#endif
360
361	/*
362	* Read configuration.
363	*/
364	PCFGMNODE pCfgHM = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
365
366	/** @cfgm{/HM/HMForced, bool, false}
367	* Forces hardware virtualization, no falling back on raw-mode. HM must be
368	* enabled, i.e. /HMEnabled must be true. */
369	bool fHMForced;
370	#ifdef VBOX_WITH_RAW_MODE
371	rc = CFGMR3QueryBoolDef(pCfgHM, "HMForced", &fHMForced, false);
372	AssertRCReturn(rc, rc);
373	AssertLogRelMsgReturn(!fHMForced \|\| pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
374	VERR_INVALID_PARAMETER);
375	# if defined(RT_OS_DARWIN)
376	if (pVM->fHMEnabled)
377	fHMForced = true;
378	# endif
379	AssertLogRelMsgReturn(pVM->cCpus == 1 \|\| pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
380	VERR_INVALID_PARAMETER);
381	if (pVM->cCpus > 1)
382	fHMForced = true;
383	#else /* !VBOX_WITH_RAW_MODE */
384	AssertRelease(pVM->fHMEnabled);
385	fHMForced = true;
386	#endif /* !VBOX_WITH_RAW_MODE */
387
388	/** @cfgm{/HM/EnableNestedPaging, bool, false}
389	* Enables nested paging (aka extended page tables). */
390	rc = CFGMR3QueryBoolDef(pCfgHM, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
391	AssertRCReturn(rc, rc);
392
393	/** @cfgm{/HM/EnableUX, bool, true}
394	* Enables the VT-x unrestricted execution feature. */
395	rc = CFGMR3QueryBoolDef(pCfgHM, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
396	AssertRCReturn(rc, rc);
397
398	/** @cfgm{/HM/EnableLargePages, bool, false}
399	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
400	* page table walking and maybe better TLB hit rate in some cases. */
401	rc = CFGMR3QueryBoolDef(pCfgHM, "EnableLargePages", &pVM->hm.s.fLargePages, false);
402	AssertRCReturn(rc, rc);
403
404	/** @cfgm{/HM/EnableVPID, bool, false}
405	* Enables the VT-x VPID feature. */
406	rc = CFGMR3QueryBoolDef(pCfgHM, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
407	AssertRCReturn(rc, rc);
408
409	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
410	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
411	rc = CFGMR3QueryBoolDef(pCfgHM, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
412	AssertRCReturn(rc, rc);
413
414	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
415	* Enables AMD64 cpu features.
416	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
417	* already have the support. */
418	#ifdef VBOX_ENABLE_64_BITS_GUESTS
419	rc = CFGMR3QueryBoolDef(pCfgHM, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
420	AssertLogRelRCReturn(rc, rc);
421	#else
422	pVM->hm.s.fAllow64BitGuests = false;
423	#endif
424
425	/** @cfgm{/HM/Exclusive, bool}
426	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
427	* global init for each host CPU. If false, we do local init each time we wish
428	* to execute guest code.
429	*
430	* Default is false for Mac OS X and Windows due to the higher risk of conflicts
431	* with other hypervisors.
432	*/
433	rc = CFGMR3QueryBoolDef(pCfgHM, "Exclusive", &pVM->hm.s.fGlobalInit,
434	#if defined(RT_OS_DARWIN) \|\| defined(RT_OS_WINDOWS)
435	false
436	#else
437	true
438	#endif
439	);
440	AssertLogRelRCReturn(rc, rc);
441
442	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
443	* The number of times to resume guest execution before we forcibly return to
444	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
445	* determines the default value. */
446	rc = CFGMR3QueryU32Def(pCfgHM, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
447	AssertLogRelRCReturn(rc, rc);
448
449	/*
450	* Check if VT-x or AMD-v support according to the users wishes.
451	*/
452	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
453	* VERR_SVM_IN_USE. */
454	if (pVM->fHMEnabled)
455	{
456	uint32_t fCaps;
457	rc = SUPR3QueryVTCaps(&fCaps);
458	if (RT_SUCCESS(rc))
459	{
460	if (fCaps & SUPVTCAPS_AMD_V)
461	LogRel(("HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
462	else if (fCaps & SUPVTCAPS_VT_X)
463	{
464	rc = SUPR3QueryVTxSupported();
465	if (RT_SUCCESS(rc))
466	LogRel(("HMR3Init: VT-x%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
467	else
468	{
469	#ifdef RT_OS_LINUX
470	const char *pszMinReq = " Linux 2.6.13 or newer required!";
471	#else
472	const char *pszMinReq = "";
473	#endif
474	if (fHMForced)
475	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
476
477	/* Fall back to raw-mode. */
478	LogRel(("HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
479	pVM->fHMEnabled = false;
480	}
481	}
482	else
483	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
484	VERR_INTERNAL_ERROR_5);
485
486	/*
487	* Do we require a little bit or raw-mode for 64-bit guest execution?
488	*/
489	pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
490	&& pVM->fHMEnabled
491	&& pVM->hm.s.fAllow64BitGuests;
492	}
493	else
494	{
495	const char *pszMsg;
496	switch (rc)
497	{
498	case VERR_UNSUPPORTED_CPU:
499	pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained.";
500	break;
501
502	case VERR_VMX_NO_VMX:
503	pszMsg = "VT-x is not available.";
504	break;
505
506	case VERR_VMX_MSR_VMXON_DISABLED:
507	pszMsg = "VT-x is disabled in the BIOS.";
508	break;
509
510	case VERR_VMX_MSR_ALL_VMXON_DISABLED:
511	pszMsg = "VT-x is disabled in the BIOS for all CPU modes.";
512	break;
513
514	case VERR_VMX_MSR_LOCKING_FAILED:
515	pszMsg = "Failed to enable and lock VT-x features.";
516	break;
517
518	case VERR_SVM_NO_SVM:
519	pszMsg = "AMD-V is not available.";
520	break;
521
522	case VERR_SVM_DISABLED:
523	pszMsg = "AMD-V is disabled in the BIOS (or by the host OS).";
524	break;
525
526	default:
527	pszMsg = NULL;
528	break;
529	}
530	if (fHMForced && pszMsg)
531	return VM_SET_ERROR(pVM, rc, pszMsg);
532	if (!pszMsg)
533	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
534
535	/* Fall back to raw-mode. */
536	LogRel(("HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
537	pVM->fHMEnabled = false;
538	}
539	}
540
541	/* It's now OK to use the predicate function. */
542	pVM->fHMEnabledFixed = true;
543	return VINF_SUCCESS;
544	}
545
546
547	/**
548	* Initializes the per-VCPU HM.
549	*
550	* @returns VBox status code.
551	* @param pVM Pointer to the VM.
552	*/
553	static int hmR3InitCPU(PVM pVM)
554	{
555	LogFlow(("HMR3InitCPU\n"));
556
557	if (!HMIsEnabled(pVM))
558	return VINF_SUCCESS;
559
560	for (VMCPUID i = 0; i < pVM->cCpus; i++)
561	{
562	PVMCPU pVCpu = &pVM->aCpus[i];
563	pVCpu->hm.s.fActive = false;
564	}
565
566	#ifdef VBOX_WITH_STATISTICS
567	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
568	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
569	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccess, STAMTYPE_COUNTER, "/HM/TPR/Replace/Success",STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
570	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
571	#endif
572
573	/*
574	* Statistics.
575	*/
576	for (VMCPUID i = 0; i < pVM->cCpus; i++)
577	{
578	PVMCPU pVCpu = &pVM->aCpus[i];
579	int rc;
580
581	#ifdef VBOX_WITH_STATISTICS
582	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
583	"Profiling of RTMpPokeCpu",
584	"/PROF/CPU%d/HM/Poke", i);
585	AssertRC(rc);
586	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
587	"Profiling of poke wait",
588	"/PROF/CPU%d/HM/PokeWait", i);
589	AssertRC(rc);
590	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
591	"Profiling of poke wait when RTMpPokeCpu fails",
592	"/PROF/CPU%d/HM/PokeWaitFailed", i);
593	AssertRC(rc);
594	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
595	"Profiling of VMXR0RunGuestCode entry",
596	"/PROF/CPU%d/HM/StatEntry", i);
597	AssertRC(rc);
598	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
599	"Profiling of VMXR0RunGuestCode exit part 1",
600	"/PROF/CPU%d/HM/SwitchFromGC_1", i);
601	AssertRC(rc);
602	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
603	"Profiling of VMXR0RunGuestCode exit part 2",
604	"/PROF/CPU%d/HM/SwitchFromGC_2", i);
605	AssertRC(rc);
606
607	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
608	"I/O",
609	"/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
610	AssertRC(rc);
611	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
612	"MOV CRx",
613	"/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
614	AssertRC(rc);
615	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
616	"Exceptions, NMIs",
617	"/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
618	AssertRC(rc);
619
620	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
621	"Profiling of VMXR0LoadGuestState",
622	"/PROF/CPU%d/HM/StatLoadGuestState", i);
623	AssertRC(rc);
624	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
625	"Profiling of VMLAUNCH/VMRESUME.",
626	"/PROF/CPU%d/HM/InGC", i);
627	AssertRC(rc);
628
629	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
630	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
631	STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
632	"/PROF/CPU%d/HM/Switcher3264", i);
633	AssertRC(rc);
634	# endif
635
636	# ifdef HM_PROFILE_EXIT_DISPATCH
637	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
638	STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
639	"/PROF/CPU%d/HM/ExitDispatch", i);
640	AssertRC(rc);
641	# endif
642
643	#endif
644	# define HM_REG_COUNTER(a, b, desc) \
645	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
646	AssertRC(rc);
647
648	#ifdef VBOX_WITH_STATISTICS
649	HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
650	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
651	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
652	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
653	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
654	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
655	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
656	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
657	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
658	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
659	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
660	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
661	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
662	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
663	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
664	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
665	HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
666	HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
667	HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
668	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
669	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
670	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
671	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
672	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
673	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
674	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
675	HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
676	HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
677	HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
678	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
679	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
680	HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
681	HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
682	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
683	HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
684	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
685	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
686	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
687	HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
688	HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
689	HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
690	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
691	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
692	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
693	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
694	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
695	HM_REG_COUNTER(&pVCpu->hm.s.StatExitMaxResume, "/HM/CPU%d/Exit/MaxResume", "Maximum VMRESUME inner-loop counter reached.");
696	HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
697	#endif
698	HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
699	#ifdef VBOX_WITH_STATISTICS
700	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
701	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
702	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
703	HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
704	HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
705	HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccessToR3, "/HM/CPU%d/Exit/ApicAccessToR3", "APIC access causing us to go to ring-3.");
706
707	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
708	HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
709	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
710	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
711	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
712
713	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
714	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
715	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception back to the guest.");
716
717	HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptPreempting, "/HM/CPU%d/Preempt/Preempting", "EMT has been preempted while in HM context.");
718	HM_REG_COUNTER(&pVCpu->hm.s.StatPreemptSaveHostState, "/HM/CPU%d/Preempt/SaveHostState", "Preemption caused us to resave host state.");
719
720	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
721	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
722	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
723	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
724	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
725	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
726	HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
727	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
728	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
729	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
730	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
731	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
732	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
733	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
734
735	HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffsetAdjusted, "/HM/CPU%d/TSC/OffsetAdjusted", "TSC offset overflowed for paravirt. TSC. Fudged.");
736	HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
737	HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
738	HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Guest is in catchup mode, intercept TSC accesses.");
739	HM_REG_COUNTER(&pVCpu->hm.s.StatTscInterceptOverFlow, "/HM/CPU%d/TSC/InterceptOverflow", "TSC offset overflow, fallback to intercept TSC accesses.");
740
741	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
742	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
743	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
744
745	HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
746	HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
747
748	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
749	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
750	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
751	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
752	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
753	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
754	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
755	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
756
757	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
758	HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
759	HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
760	#endif
761
762	for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
763	{
764	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
765	STAMUNIT_OCCURENCES, "Profiling of CRx writes",
766	"/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
767	AssertRC(rc);
768	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
769	STAMUNIT_OCCURENCES, "Profiling of CRx reads",
770	"/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
771	AssertRC(rc);
772	}
773
774	#undef HM_REG_COUNTER
775
776	pVCpu->hm.s.paStatExitReason = NULL;
777
778	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pVCpu->hm.s.paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
779	(void **)&pVCpu->hm.s.paStatExitReason);
780	AssertRC(rc);
781	if (RT_SUCCESS(rc))
782	{
783	const char * const *papszDesc = ASMIsIntelCpu() ? &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
784	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
785	{
786	if (papszDesc[j])
787	{
788	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
789	STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
790	AssertRC(rc);
791	}
792	}
793	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
794	"Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
795	AssertRC(rc);
796	}
797	pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
798	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
799	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
800	# else
801	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
802	# endif
803
804	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
805	AssertRCReturn(rc, rc);
806	pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
807	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
808	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
809	# else
810	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
811	# endif
812	for (unsigned j = 0; j < 255; j++)
813	{
814	STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
815	"Injected event.",
816	(j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
817	}
818
819	#endif /* VBOX_WITH_STATISTICS */
820	}
821
822	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
823	/*
824	* Magic marker for searching in crash dumps.
825	*/
826	for (VMCPUID i = 0; i < pVM->cCpus; i++)
827	{
828	PVMCPU pVCpu = &pVM->aCpus[i];
829
830	PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
831	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
832	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
833	}
834	#endif
835
836	return VINF_SUCCESS;
837	}
838
839
840	/**
841	* Called when a init phase has completed.
842	*
843	* @returns VBox status code.
844	* @param pVM The VM.
845	* @param enmWhat The phase that completed.
846	*/
847	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
848	{
849	switch (enmWhat)
850	{
851	case VMINITCOMPLETED_RING3:
852	return hmR3InitCPU(pVM);
853	case VMINITCOMPLETED_RING0:
854	return hmR3InitFinalizeR0(pVM);
855	default:
856	return VINF_SUCCESS;
857	}
858	}
859
860
861	/**
862	* Turns off normal raw mode features.
863	*
864	* @param pVM Pointer to the VM.
865	*/
866	static void hmR3DisableRawMode(PVM pVM)
867	{
868	/* Reinit the paging mode to force the new shadow mode. */
869	for (VMCPUID i = 0; i < pVM->cCpus; i++)
870	{
871	PVMCPU pVCpu = &pVM->aCpus[i];
872
873	PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
874	}
875	}
876
877
878	/**
879	* Initialize VT-x or AMD-V.
880	*
881	* @returns VBox status code.
882	* @param pVM Pointer to the VM.
883	*/
884	static int hmR3InitFinalizeR0(PVM pVM)
885	{
886	int rc;
887
888	if (!HMIsEnabled(pVM))
889	return VINF_SUCCESS;
890
891	/*
892	* Hack to allow users to work around broken BIOSes that incorrectly set
893	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
894	*/
895	if ( !pVM->hm.s.vmx.fSupported
896	&& !pVM->hm.s.svm.fSupported
897	&& pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
898	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
899	{
900	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
901	pVM->hm.s.svm.fSupported = true;
902	pVM->hm.s.svm.fIgnoreInUseError = true;
903	pVM->hm.s.lLastError = VINF_SUCCESS;
904	}
905
906	/*
907	* Report ring-0 init errors.
908	*/
909	if ( !pVM->hm.s.vmx.fSupported
910	&& !pVM->hm.s.svm.fSupported)
911	{
912	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
913	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
914	switch (pVM->hm.s.lLastError)
915	{
916	case VERR_VMX_IN_VMX_ROOT_MODE:
917	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor.");
918	case VERR_VMX_NO_VMX:
919	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available.");
920	case VERR_VMX_MSR_VMXON_DISABLED:
921	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS.");
922	case VERR_VMX_MSR_ALL_VMXON_DISABLED:
923	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is disabled in the BIOS for all CPU modes.");
924	case VERR_VMX_MSR_LOCKING_FAILED:
925	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "Failed to enable and lock VT-x features.");
926
927	case VERR_SVM_IN_USE:
928	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor.");
929	case VERR_SVM_NO_SVM:
930	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available.");
931	case VERR_SVM_DISABLED:
932	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS.");
933	}
934	return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
935	}
936
937	/*
938	* Enable VT-x or AMD-V on all host CPUs.
939	*/
940	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
941	if (RT_FAILURE(rc))
942	{
943	LogRel(("HMR3InitFinalize: SUPR3CallVMMR0Ex VMMR0_DO_HM_ENABLE failed with %Rrc\n", rc));
944	return rc;
945	}
946
947	/*
948	* No TPR patching is required when the IO-APIC is not enabled for this VM.
949	* (Main should have taken care of this already)
950	*/
951	pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
952	if (!pVM->hm.s.fHasIoApic)
953	{
954	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
955	pVM->hm.s.fTprPatchingAllowed = false;
956	}
957
958	/*
959	* Do the vendor specific initalization .
960	* .
961	* Note! We disable release log buffering here since we're doing relatively .
962	* lot of logging and doesn't want to hit the disk with each LogRel .
963	* statement.
964	*/
965	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
966	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
967	if (pVM->hm.s.vmx.fSupported)
968	rc = hmR3InitFinalizeR0Intel(pVM);
969	else
970	rc = hmR3InitFinalizeR0Amd(pVM);
971	LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
972	RTLogRelSetBuffering(fOldBuffered);
973	pVM->hm.s.fInitialized = true;
974
975	return rc;
976	}
977
978
979	/**
980	* Finish VT-x initialization (after ring-0 init).
981	*
982	* @returns VBox status code.
983	* @param pVM The cross context VM structure.
984	*/
985	static int hmR3InitFinalizeR0Intel(PVM pVM)
986	{
987	int rc;
988
989	Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
990	AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
991
992	uint64_t val;
993	uint64_t zap;
994	RTGCPHYS GCPhys = 0;
995
996	LogRel(("HM: Using VT-x implementation 2.0!\n"));
997	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
998	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
999	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1000	LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1001	LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1002	LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1003	LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1004	LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1005	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1006	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", RT_BOOL(MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo))));
1007	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1008
1009	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1010	val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1011	zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1012	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1013	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1014	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1015	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1016
1017	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1018	val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1019	zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1020	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1021	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1022	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1023	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1024	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1025	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1026	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1027	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1028	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1029	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1030	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1031	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1032	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1033	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1034	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1035	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1036	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1037	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1038	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1039	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1040	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1041	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1042	{
1043	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1044	val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1045	zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1046	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1047	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1048	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1049	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1050	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1051	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1052	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1053	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1054	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1055	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1056	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1057	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1058	}
1059
1060	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1061	val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1062	zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1063	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1064	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1065	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1066	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1067	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1068	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1069	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1070
1071	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1072	val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1073	zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1074	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1075	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1076	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1077	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1078	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1079	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1080	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1081	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1082	HMVMX_REPORT_FEATURE(val, zap, VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1083
1084	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1085	{
1086	val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1087	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1088	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1089	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_W_ONLY);
1090	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_RWX_WX_ONLY);
1091	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_21_BITS);
1092	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_30_BITS);
1093	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_39_BITS);
1094	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_48_BITS);
1095	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_GAW_57_BITS);
1096	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1097	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WC);
1098	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WT);
1099	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WP);
1100	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1101	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_21_BITS);
1102	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_30_BITS);
1103	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_39_BITS);
1104	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_SP_48_BITS);
1105	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1106	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1107	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1108	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1109	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1110	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1111	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1112	HMVMX_REPORT_CAPABILITY(val, MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1113	}
1114
1115	val = pVM->hm.s.vmx.Msrs.u64Misc;
1116	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1117	if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1118	LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1119	else
1120	{
1121	LogRel(("HM: MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1122	MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1123	}
1124
1125	LogRel(("HM: MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1126	LogRel(("HM: MSR_IA32_VMX_MISC_ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1127	LogRel(("HM: MSR_IA32_VMX_MISC_CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1128	LogRel(("HM: MSR_IA32_VMX_MISC_MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1129	LogRel(("HM: MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1130	LogRel(("HM: MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1131	LogRel(("HM: MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1132	LogRel(("HM: MSR_IA32_VMX_MISC_MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1133
1134	/* Paranoia */
1135	AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1136
1137	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1138	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1139	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1140	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1141
1142	val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1143	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1144	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1145
1146	val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1147	if (val)
1148	{
1149	LogRel(("HM: MSR_A32_VMX_VMFUNC = %#RX64\n", val));
1150	HMVMX_REPORT_ALLOWED_FEATURE(val, VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1151	}
1152
1153	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1154
1155	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1156	{
1157	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1158	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1159	}
1160
1161	if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT)
1162	pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1163
1164	if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1165	pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1166
1167	/*
1168	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1169	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1170	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1171	*/
1172	if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1173	&& CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1174	{
1175	CPUMClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1176	LogRel(("HM: RDTSCP disabled\n"));
1177	}
1178
1179	/* Unrestricted guest execution also requires EPT. */
1180	if ( pVM->hm.s.vmx.fAllowUnrestricted
1181	&& pVM->hm.s.fNestedPaging
1182	&& (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST))
1183	{
1184	pVM->hm.s.vmx.fUnrestrictedGuest = true;
1185	}
1186
1187	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1188	{
1189	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1190	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1191	if (RT_SUCCESS(rc))
1192	{
1193	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1194	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1195	esp. Figure 20-5.*/
1196	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1197	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1198
1199	/* Bit set to 0 means software interrupts are redirected to the
1200	8086 program interrupt handler rather than switching to
1201	protected-mode handler. */
1202	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1203
1204	/* Allow all port IO, so that port IO instructions do not cause
1205	exceptions and would instead cause a VM-exit (based on VT-x's
1206	IO bitmap which we currently configure to always cause an exit). */
1207	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1208	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1209
1210	/*
1211	* Construct a 1024 element page directory with 4 MB pages for
1212	* the identity mapped page table used in real and protected mode
1213	* without paging with EPT.
1214	*/
1215	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1216	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1217	{
1218	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1219	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1220	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1221	\| X86_PDE4M_G;
1222	}
1223
1224	/* We convert it here every time as pci regions could be reconfigured. */
1225	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1226	AssertRCReturn(rc, rc);
1227	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1228
1229	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1230	AssertRCReturn(rc, rc);
1231	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1232	}
1233	else
1234	{
1235	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1236	pVM->hm.s.vmx.pRealModeTSS = NULL;
1237	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1238	return VMSetError(pVM, rc, RT_SRC_POS,
1239	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1240	}
1241	}
1242
1243	LogRel((pVM->hm.s.fAllow64BitGuests
1244	? "HM: Guest support: 32-bit and 64-bit\n"
1245	: "HM: Guest support: 32-bit only\n"));
1246
1247	/*
1248	* Call ring-0 to set up the VM.
1249	*/
1250	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1251	if (rc != VINF_SUCCESS)
1252	{
1253	AssertMsgFailed(("%Rrc\n", rc));
1254	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1255	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1256	{
1257	PVMCPU pVCpu = &pVM->aCpus[i];
1258	LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1259	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1260	}
1261	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1262	}
1263
1264	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1265	LogRel(("HM: VMX enabled!\n"));
1266	pVM->hm.s.vmx.fEnabled = true;
1267
1268	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1269
1270	/*
1271	* Change the CPU features.
1272	*/
1273	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1274	if (pVM->hm.s.fAllow64BitGuests)
1275	{
1276	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1277	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1278	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1279	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1280	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1281	}
1282	/* Turn on NXE if PAE has been enabled and the host has turned on NXE
1283	(we reuse the host EFER in the switcher). */
1284	/** @todo this needs to be fixed properly!! */
1285	else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1286	{
1287	if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1288	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1289	else
1290	LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1291	}
1292
1293	/*
1294	* Log configuration details.
1295	*/
1296	if (pVM->hm.s.fNestedPaging)
1297	{
1298	LogRel(("HM: Nested paging enabled!\n"));
1299	if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1300	LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1301	else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1302	LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1303	else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1304	LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1305	else
1306	LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1307
1308	if (pVM->hm.s.vmx.fUnrestrictedGuest)
1309	LogRel(("HM: Unrestricted guest execution enabled!\n"));
1310
1311	#if HC_ARCH_BITS == 64
1312	if (pVM->hm.s.fLargePages)
1313	{
1314	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1315	PGMSetLargePageUsage(pVM, true);
1316	LogRel(("HM: Large page support enabled\n"));
1317	}
1318	#endif
1319	}
1320	else
1321	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1322
1323	if (pVM->hm.s.vmx.fVpid)
1324	{
1325	LogRel(("HM: VPID enabled!\n"));
1326	if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1327	LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1328	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1329	LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1330	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1331	LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1332	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1333	LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1334	else
1335	LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1336	}
1337	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1338	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1339
1340	/*
1341	* Check for preemption timer config override and log the state of it.
1342	*/
1343	if (pVM->hm.s.vmx.fUsePreemptTimer)
1344	{
1345	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM");
1346	rc = CFGMR3QueryBoolDef(pCfgHm, "UsePreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
1347	AssertLogRelRCReturn(rc, rc);
1348	}
1349	if (pVM->hm.s.vmx.fUsePreemptTimer)
1350	LogRel(("HM: VMX-preemption timer enabled (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1351	else
1352	LogRel(("HM: VMX-preemption timer disabled\n"));
1353
1354	return VINF_SUCCESS;
1355	}
1356
1357
1358	/**
1359	* Finish AMD-V initialization (after ring-0 init).
1360	*
1361	* @returns VBox status code.
1362	* @param pVM The cross context VM structure.
1363	*/
1364	static int hmR3InitFinalizeR0Amd(PVM pVM)
1365	{
1366	Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1367
1368	LogRel(("HM: Using AMD-V implementation 2.0!\n"));
1369
1370	uint32_t u32Family;
1371	uint32_t u32Model;
1372	uint32_t u32Stepping;
1373	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1374	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1375	LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1376	LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1377	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1378	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1379	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1380	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1381
1382	/*
1383	* Enumerate AMD-V features.
1384	*/
1385	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1386	{
1387	#define HMSVM_REPORT_FEATURE(a_Define) { a_Define, #a_Define }
1388	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1389	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1390	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1391	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1392	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1393	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1394	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1395	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1396	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1397	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1398	HMSVM_REPORT_FEATURE(AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1399	#undef HMSVM_REPORT_FEATURE
1400	};
1401
1402	uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1403	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1404	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1405	{
1406	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1407	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1408	}
1409	if (fSvmFeatures)
1410	for (unsigned iBit = 0; iBit < 32; iBit++)
1411	if (RT_BIT_32(iBit) & fSvmFeatures)
1412	LogRel(("HM: Reserved bit %u\n", iBit));
1413
1414	/*
1415	* Adjust feature(s).
1416	*/
1417	if (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING)
1418	pVM->hm.s.fNestedPaging = pVM->hm.s.fAllowNestedPaging;
1419
1420	/*
1421	* Call ring-0 to set up the VM.
1422	*/
1423	int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1424	if (rc != VINF_SUCCESS)
1425	{
1426	AssertMsgFailed(("%Rrc\n", rc));
1427	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1428	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1429	}
1430
1431	LogRel(("HM: AMD-V enabled!\n"));
1432	pVM->hm.s.svm.fEnabled = true;
1433
1434	if (pVM->hm.s.fNestedPaging)
1435	{
1436	LogRel(("HM: Nested paging enabled!\n"));
1437
1438	/*
1439	* Enable large pages (2 MB) if applicable.
1440	*/
1441	#if HC_ARCH_BITS == 64
1442	if (pVM->hm.s.fLargePages)
1443	{
1444	PGMSetLargePageUsage(pVM, true);
1445	LogRel(("HM: Large page support enabled!\n"));
1446	}
1447	#endif
1448	}
1449
1450	hmR3DisableRawMode(pVM);
1451
1452	/*
1453	* Change the CPU features.
1454	*/
1455	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1456	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1457	if (pVM->hm.s.fAllow64BitGuests)
1458	{
1459	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1460	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1461	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1462	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1463	}
1464	/* Turn on NXE if PAE has been enabled. */
1465	else if (CPUMGetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1466	CPUMSetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1467
1468	LogRel(("HM: TPR patching %s\n", (pVM->hm.s.fTprPatchingAllowed) ? "enabled" : "disabled"));
1469
1470	LogRel((pVM->hm.s.fAllow64BitGuests
1471	? "HM: Guest support: 32-bit and 64-bit\n"
1472	: "HM: Guest support: 32-bit only\n"));
1473
1474	return VINF_SUCCESS;
1475	}
1476
1477
1478	/**
1479	* Applies relocations to data and code managed by this
1480	* component. This function will be called at init and
1481	* whenever the VMM need to relocate it self inside the GC.
1482	*
1483	* @param pVM The VM.
1484	*/
1485	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1486	{
1487	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1488
1489	/* Fetch the current paging mode during the relocate callback during state loading. */
1490	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1491	{
1492	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1493	{
1494	PVMCPU pVCpu = &pVM->aCpus[i];
1495	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1496	}
1497	}
1498	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS) && !defined(VBOX_WITH_HYBRID_32BIT_KERNEL)
1499	if (HMIsEnabled(pVM))
1500	{
1501	switch (PGMGetHostMode(pVM))
1502	{
1503	case PGMMODE_32_BIT:
1504	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1505	break;
1506
1507	case PGMMODE_PAE:
1508	case PGMMODE_PAE_NX:
1509	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1510	break;
1511
1512	default:
1513	AssertFailed();
1514	break;
1515	}
1516	}
1517	#endif
1518	return;
1519	}
1520
1521
1522	/**
1523	* Notification callback which is called whenever there is a chance that a CR3
1524	* value might have changed.
1525	*
1526	* This is called by PGM.
1527	*
1528	* @param pVM Pointer to the VM.
1529	* @param pVCpu Pointer to the VMCPU.
1530	* @param enmShadowMode New shadow paging mode.
1531	* @param enmGuestMode New guest paging mode.
1532	*/
1533	VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1534	{
1535	/* Ignore page mode changes during state loading. */
1536	if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1537	return;
1538
1539	pVCpu->hm.s.enmShadowMode = enmShadowMode;
1540
1541	/*
1542	* If the guest left protected mode VMX execution, we'll have to be
1543	* extra careful if/when the guest switches back to protected mode.
1544	*/
1545	if (enmGuestMode == PGMMODE_REAL)
1546	{
1547	Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1548	pVCpu->hm.s.vmx.fWasInRealMode = true;
1549	}
1550
1551	/** @todo r=ramshankar: Disabling for now. If nothing breaks remove it
1552	* eventually. (Test platforms that use the cache ofc). */
1553	#if 0
1554	#ifdef VMX_USE_CACHED_VMCS_ACCESSES
1555	/* Reset the contents of the read cache. */
1556	PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1557	for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1558	pCache->Read.aFieldVal[j] = 0;
1559	#endif
1560	#endif
1561	}
1562
1563
1564	/**
1565	* Terminates the HM.
1566	*
1567	* Termination means cleaning up and freeing all resources,
1568	* the VM itself is, at this point, powered off or suspended.
1569	*
1570	* @returns VBox status code.
1571	* @param pVM Pointer to the VM.
1572	*/
1573	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1574	{
1575	if (pVM->hm.s.vmx.pRealModeTSS)
1576	{
1577	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1578	pVM->hm.s.vmx.pRealModeTSS = 0;
1579	}
1580	hmR3TermCPU(pVM);
1581	return 0;
1582	}
1583
1584
1585	/**
1586	* Terminates the per-VCPU HM.
1587	*
1588	* @returns VBox status code.
1589	* @param pVM Pointer to the VM.
1590	*/
1591	static int hmR3TermCPU(PVM pVM)
1592	{
1593	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1594	{
1595	PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1596
1597	#ifdef VBOX_WITH_STATISTICS
1598	if (pVCpu->hm.s.paStatExitReason)
1599	{
1600	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1601	pVCpu->hm.s.paStatExitReason = NULL;
1602	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1603	}
1604	if (pVCpu->hm.s.paStatInjectedIrqs)
1605	{
1606	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1607	pVCpu->hm.s.paStatInjectedIrqs = NULL;
1608	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1609	}
1610	#endif
1611
1612	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1613	memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1614	pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1615	pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1616	#endif
1617	}
1618	return 0;
1619	}
1620
1621
1622	/**
1623	* Resets a virtual CPU.
1624	*
1625	* Used by HMR3Reset and CPU hot plugging.
1626	*
1627	* @param pVCpu The CPU to reset.
1628	*/
1629	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1630	{
1631	/* Sync. entire state on VM reset R0-reentry. It's safe to reset
1632	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1633	HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1634
1635	pVCpu->hm.s.vmx.u32CR0Mask = 0;
1636	pVCpu->hm.s.vmx.u32CR4Mask = 0;
1637	pVCpu->hm.s.fActive = false;
1638	pVCpu->hm.s.Event.fPending = false;
1639	pVCpu->hm.s.vmx.fWasInRealMode = true;
1640	pVCpu->hm.s.vmx.u64MsrApicBase = 0;
1641
1642	/* Reset the contents of the read cache. */
1643	PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1644	for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1645	pCache->Read.aFieldVal[j] = 0;
1646
1647	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1648	/* Magic marker for searching in crash dumps. */
1649	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1650	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1651	#endif
1652	}
1653
1654
1655	/**
1656	* The VM is being reset.
1657	*
1658	* For the HM component this means that any GDT/LDT/TSS monitors
1659	* needs to be removed.
1660	*
1661	* @param pVM Pointer to the VM.
1662	*/
1663	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1664	{
1665	LogFlow(("HMR3Reset:\n"));
1666
1667	if (HMIsEnabled(pVM))
1668	hmR3DisableRawMode(pVM);
1669
1670	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1671	{
1672	PVMCPU pVCpu = &pVM->aCpus[i];
1673
1674	HMR3ResetCpu(pVCpu);
1675	}
1676
1677	/* Clear all patch information. */
1678	pVM->hm.s.pGuestPatchMem = 0;
1679	pVM->hm.s.pFreeGuestPatchMem = 0;
1680	pVM->hm.s.cbGuestPatchMem = 0;
1681	pVM->hm.s.cPatches = 0;
1682	pVM->hm.s.PatchTree = 0;
1683	pVM->hm.s.fTPRPatchingActive = false;
1684	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1685	}
1686
1687
1688	/**
1689	* Callback to patch a TPR instruction (vmmcall or mov cr8).
1690	*
1691	* @returns VBox strict status code.
1692	* @param pVM Pointer to the VM.
1693	* @param pVCpu The VMCPU for the EMT we're being called on.
1694	* @param pvUser Unused.
1695	*/
1696	DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1697	{
1698	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1699
1700	/* Only execute the handler on the VCPU the original patch request was issued. */
1701	if (pVCpu->idCpu != idCpu)
1702	return VINF_SUCCESS;
1703
1704	Log(("hmR3RemovePatches\n"));
1705	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1706	{
1707	uint8_t abInstr[15];
1708	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1709	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1710	int rc;
1711
1712	#ifdef LOG_ENABLED
1713	char szOutput[256];
1714
1715	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1716	szOutput, sizeof(szOutput), NULL);
1717	if (RT_SUCCESS(rc))
1718	Log(("Patched instr: %s\n", szOutput));
1719	#endif
1720
1721	/* Check if the instruction is still the same. */
1722	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1723	if (rc != VINF_SUCCESS)
1724	{
1725	Log(("Patched code removed? (rc=%Rrc0\n", rc));
1726	continue; /* swapped out or otherwise removed; skip it. */
1727	}
1728
1729	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1730	{
1731	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1732	continue; /* skip it. */
1733	}
1734
1735	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1736	AssertRC(rc);
1737
1738	#ifdef LOG_ENABLED
1739	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1740	szOutput, sizeof(szOutput), NULL);
1741	if (RT_SUCCESS(rc))
1742	Log(("Original instr: %s\n", szOutput));
1743	#endif
1744	}
1745	pVM->hm.s.cPatches = 0;
1746	pVM->hm.s.PatchTree = 0;
1747	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1748	pVM->hm.s.fTPRPatchingActive = false;
1749	return VINF_SUCCESS;
1750	}
1751
1752
1753	/**
1754	* Worker for enabling patching in a VT-x/AMD-V guest.
1755	*
1756	* @returns VBox status code.
1757	* @param pVM Pointer to the VM.
1758	* @param idCpu VCPU to execute hmR3RemovePatches on.
1759	* @param pPatchMem Patch memory range.
1760	* @param cbPatchMem Size of the memory range.
1761	*/
1762	static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
1763	{
1764	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
1765	AssertRC(rc);
1766
1767	pVM->hm.s.pGuestPatchMem = pPatchMem;
1768	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
1769	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
1770	return VINF_SUCCESS;
1771	}
1772
1773
1774	/**
1775	* Enable patching in a VT-x/AMD-V guest
1776	*
1777	* @returns VBox status code.
1778	* @param pVM Pointer to the VM.
1779	* @param pPatchMem Patch memory range.
1780	* @param cbPatchMem Size of the memory range.
1781	*/
1782	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1783	{
1784	VM_ASSERT_EMT(pVM);
1785	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1786	if (pVM->cCpus > 1)
1787	{
1788	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
1789	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
1790	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1791	AssertRC(rc);
1792	return rc;
1793	}
1794	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
1795	}
1796
1797
1798	/**
1799	* Disable patching in a VT-x/AMD-V guest.
1800	*
1801	* @returns VBox status code.
1802	* @param pVM Pointer to the VM.
1803	* @param pPatchMem Patch memory range.
1804	* @param cbPatchMem Size of the memory range.
1805	*/
1806	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
1807	{
1808	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
1809
1810	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
1811	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
1812
1813	/* @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
1814	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
1815	(void *)(uintptr_t)VMMGetCpuId(pVM));
1816	AssertRC(rc);
1817
1818	pVM->hm.s.pGuestPatchMem = 0;
1819	pVM->hm.s.pFreeGuestPatchMem = 0;
1820	pVM->hm.s.cbGuestPatchMem = 0;
1821	pVM->hm.s.fTPRPatchingActive = false;
1822	return VINF_SUCCESS;
1823	}
1824
1825
1826	/**
1827	* Callback to patch a TPR instruction (vmmcall or mov cr8).
1828	*
1829	* @returns VBox strict status code.
1830	* @param pVM Pointer to the VM.
1831	* @param pVCpu The VMCPU for the EMT we're being called on.
1832	* @param pvUser User specified CPU context.
1833	*
1834	*/
1835	DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
1836	{
1837	/*
1838	* Only execute the handler on the VCPU the original patch request was
1839	* issued. (The other CPU(s) might not yet have switched to protected
1840	* mode, nor have the correct memory context.)
1841	*/
1842	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1843	if (pVCpu->idCpu != idCpu)
1844	return VINF_SUCCESS;
1845
1846	/*
1847	* We're racing other VCPUs here, so don't try patch the instruction twice
1848	* and make sure there is still room for our patch record.
1849	*/
1850	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
1851	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
1852	if (pPatch)
1853	{
1854	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
1855	return VINF_SUCCESS;
1856	}
1857	uint32_t const idx = pVM->hm.s.cPatches;
1858	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
1859	{
1860	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
1861	return VINF_SUCCESS;
1862	}
1863	pPatch = &pVM->hm.s.aPatches[idx];
1864
1865	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
1866
1867	/*
1868	* Disassembler the instruction and get cracking.
1869	*/
1870	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
1871	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
1872	uint32_t cbOp;
1873	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1874	AssertRC(rc);
1875	if ( rc == VINF_SUCCESS
1876	&& pDis->pCurInstr->uOpcode == OP_MOV
1877	&& cbOp >= 3)
1878	{
1879	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
1880
1881	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
1882	AssertRC(rc);
1883
1884	pPatch->cbOp = cbOp;
1885
1886	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
1887	{
1888	/* write. */
1889	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
1890	{
1891	pPatch->enmType = HMTPRINSTR_WRITE_REG;
1892	pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
1893	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
1894	}
1895	else
1896	{
1897	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
1898	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
1899	pPatch->uSrcOperand = pDis->Param2.uValue;
1900	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
1901	}
1902	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1903	AssertRC(rc);
1904
1905	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1906	pPatch->cbNewOp = sizeof(s_abVMMCall);
1907	}
1908	else
1909	{
1910	/*
1911	* TPR Read.
1912	*
1913	* Found:
1914	* mov eax, dword [fffe0080] (5 bytes)
1915	* Check if next instruction is:
1916	* shr eax, 4
1917	*/
1918	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
1919
1920	uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
1921	uint8_t const cbOpMmio = cbOp;
1922	uint64_t const uSavedRip = pCtx->rip;
1923
1924	pCtx->rip += cbOp;
1925	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
1926	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
1927	pCtx->rip = uSavedRip;
1928
1929	if ( rc == VINF_SUCCESS
1930	&& pDis->pCurInstr->uOpcode == OP_SHR
1931	&& pDis->Param1.fUse == DISUSE_REG_GEN32
1932	&& pDis->Param1.Base.idxGenReg == idxMmioReg
1933	&& pDis->Param2.fUse == DISUSE_IMMEDIATE8
1934	&& pDis->Param2.uValue == 4
1935	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
1936	{
1937	uint8_t abInstr[15];
1938
1939	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
1940	access CR8 in 32-bit mode and not cause a #VMEXIT. */
1941	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
1942	AssertRC(rc);
1943
1944	pPatch->cbOp = cbOpMmio + cbOp;
1945
1946	/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
1947	abInstr[0] = 0xF0;
1948	abInstr[1] = 0x0F;
1949	abInstr[2] = 0x20;
1950	abInstr[3] = 0xC0 \| pDis->Param1.Base.idxGenReg;
1951	for (unsigned i = 4; i < pPatch->cbOp; i++)
1952	abInstr[i] = 0x90; /* nop */
1953
1954	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
1955	AssertRC(rc);
1956
1957	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
1958	pPatch->cbNewOp = pPatch->cbOp;
1959
1960	Log(("Acceptable read/shr candidate!\n"));
1961	pPatch->enmType = HMTPRINSTR_READ_SHR4;
1962	}
1963	else
1964	{
1965	pPatch->enmType = HMTPRINSTR_READ;
1966	pPatch->uDstOperand = idxMmioReg;
1967
1968	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
1969	AssertRC(rc);
1970
1971	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
1972	pPatch->cbNewOp = sizeof(s_abVMMCall);
1973	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
1974	}
1975	}
1976
1977	pPatch->Core.Key = pCtx->eip;
1978	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1979	AssertRC(rc);
1980
1981	pVM->hm.s.cPatches++;
1982	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccess);
1983	return VINF_SUCCESS;
1984	}
1985
1986	/*
1987	* Save invalid patch, so we will not try again.
1988	*/
1989	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
1990	pPatch->Core.Key = pCtx->eip;
1991	pPatch->enmType = HMTPRINSTR_INVALID;
1992	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
1993	AssertRC(rc);
1994	pVM->hm.s.cPatches++;
1995	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
1996	return VINF_SUCCESS;
1997	}
1998
1999
2000	/**
2001	* Callback to patch a TPR instruction (jump to generated code).
2002	*
2003	* @returns VBox strict status code.
2004	* @param pVM Pointer to the VM.
2005	* @param pVCpu The VMCPU for the EMT we're being called on.
2006	* @param pvUser User specified CPU context.
2007	*
2008	*/
2009	DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2010	{
2011	/*
2012	* Only execute the handler on the VCPU the original patch request was
2013	* issued. (The other CPU(s) might not yet have switched to protected
2014	* mode, nor have the correct memory context.)
2015	*/
2016	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2017	if (pVCpu->idCpu != idCpu)
2018	return VINF_SUCCESS;
2019
2020	/*
2021	* We're racing other VCPUs here, so don't try patch the instruction twice
2022	* and make sure there is still room for our patch record.
2023	*/
2024	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2025	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2026	if (pPatch)
2027	{
2028	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2029	return VINF_SUCCESS;
2030	}
2031	uint32_t const idx = pVM->hm.s.cPatches;
2032	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2033	{
2034	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2035	return VINF_SUCCESS;
2036	}
2037	pPatch = &pVM->hm.s.aPatches[idx];
2038
2039	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2040	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2041
2042	/*
2043	* Disassemble the instruction and get cracking.
2044	*/
2045	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2046	uint32_t cbOp;
2047	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2048	AssertRC(rc);
2049	if ( rc == VINF_SUCCESS
2050	&& pDis->pCurInstr->uOpcode == OP_MOV
2051	&& cbOp >= 5)
2052	{
2053	uint8_t aPatch[64];
2054	uint32_t off = 0;
2055
2056	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2057	AssertRC(rc);
2058
2059	pPatch->cbOp = cbOp;
2060	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2061
2062	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2063	{
2064	/*
2065	* TPR write:
2066	*
2067	* push ECX [51]
2068	* push EDX [52]
2069	* push EAX [50]
2070	* xor EDX,EDX [31 D2]
2071	* mov EAX,EAX [89 C0]
2072	* or
2073	* mov EAX,0000000CCh [B8 CC 00 00 00]
2074	* mov ECX,0C0000082h [B9 82 00 00 C0]
2075	* wrmsr [0F 30]
2076	* pop EAX [58]
2077	* pop EDX [5A]
2078	* pop ECX [59]
2079	* jmp return_address [E9 return_address]
2080	*
2081	*/
2082	bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2083
2084	aPatch[off++] = 0x51; /* push ecx */
2085	aPatch[off++] = 0x52; /* push edx */
2086	if (!fUsesEax)
2087	aPatch[off++] = 0x50; /* push eax */
2088	aPatch[off++] = 0x31; /* xor edx, edx */
2089	aPatch[off++] = 0xD2;
2090	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2091	{
2092	if (!fUsesEax)
2093	{
2094	aPatch[off++] = 0x89; /* mov eax, src_reg */
2095	aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2096	}
2097	}
2098	else
2099	{
2100	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2101	aPatch[off++] = 0xB8; /* mov eax, immediate */
2102	(uint32_t )&aPatch[off] = pDis->Param2.uValue;
2103	off += sizeof(uint32_t);
2104	}
2105	aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2106	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2107	off += sizeof(uint32_t);
2108
2109	aPatch[off++] = 0x0F; /* wrmsr */
2110	aPatch[off++] = 0x30;
2111	if (!fUsesEax)
2112	aPatch[off++] = 0x58; /* pop eax */
2113	aPatch[off++] = 0x5A; /* pop edx */
2114	aPatch[off++] = 0x59; /* pop ecx */
2115	}
2116	else
2117	{
2118	/*
2119	* TPR read:
2120	*
2121	* push ECX [51]
2122	* push EDX [52]
2123	* push EAX [50]
2124	* mov ECX,0C0000082h [B9 82 00 00 C0]
2125	* rdmsr [0F 32]
2126	* mov EAX,EAX [89 C0]
2127	* pop EAX [58]
2128	* pop EDX [5A]
2129	* pop ECX [59]
2130	* jmp return_address [E9 return_address]
2131	*
2132	*/
2133	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2134
2135	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2136	aPatch[off++] = 0x51; /* push ecx */
2137	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2138	aPatch[off++] = 0x52; /* push edx */
2139	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2140	aPatch[off++] = 0x50; /* push eax */
2141
2142	aPatch[off++] = 0x31; /* xor edx, edx */
2143	aPatch[off++] = 0xD2;
2144
2145	aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2146	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2147	off += sizeof(uint32_t);
2148
2149	aPatch[off++] = 0x0F; /* rdmsr */
2150	aPatch[off++] = 0x32;
2151
2152	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2153	{
2154	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2155	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2156	}
2157
2158	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2159	aPatch[off++] = 0x58; /* pop eax */
2160	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2161	aPatch[off++] = 0x5A; /* pop edx */
2162	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2163	aPatch[off++] = 0x59; /* pop ecx */
2164	}
2165	aPatch[off++] = 0xE9; /* jmp return_address */
2166	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2167	off += sizeof(RTRCUINTPTR);
2168
2169	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2170	{
2171	/* Write new code to the patch buffer. */
2172	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2173	AssertRC(rc);
2174
2175	#ifdef LOG_ENABLED
2176	uint32_t cbCurInstr;
2177	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2178	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2179	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2180	{
2181	char szOutput[256];
2182	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2183	szOutput, sizeof(szOutput), &cbCurInstr);
2184	if (RT_SUCCESS(rc))
2185	Log(("Patch instr %s\n", szOutput));
2186	else
2187	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2188	}
2189	#endif
2190
2191	pPatch->aNewOpcode[0] = 0xE9;
2192	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2193
2194	/* Overwrite the TPR instruction with a jump. */
2195	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2196	AssertRC(rc);
2197
2198	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2199
2200	pVM->hm.s.pFreeGuestPatchMem += off;
2201	pPatch->cbNewOp = 5;
2202
2203	pPatch->Core.Key = pCtx->eip;
2204	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2205	AssertRC(rc);
2206
2207	pVM->hm.s.cPatches++;
2208	pVM->hm.s.fTPRPatchingActive = true;
2209	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2210	return VINF_SUCCESS;
2211	}
2212
2213	Log(("Ran out of space in our patch buffer!\n"));
2214	}
2215	else
2216	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2217
2218
2219	/*
2220	* Save invalid patch, so we will not try again.
2221	*/
2222	pPatch = &pVM->hm.s.aPatches[idx];
2223	pPatch->Core.Key = pCtx->eip;
2224	pPatch->enmType = HMTPRINSTR_INVALID;
2225	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2226	AssertRC(rc);
2227	pVM->hm.s.cPatches++;
2228	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2229	return VINF_SUCCESS;
2230	}
2231
2232
2233	/**
2234	* Attempt to patch TPR mmio instructions.
2235	*
2236	* @returns VBox status code.
2237	* @param pVM Pointer to the VM.
2238	* @param pVCpu Pointer to the VMCPU.
2239	* @param pCtx Pointer to the guest CPU context.
2240	*/
2241	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2242	{
2243	NOREF(pCtx);
2244	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2245	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2246	(void *)(uintptr_t)pVCpu->idCpu);
2247	AssertRC(rc);
2248	return rc;
2249	}
2250
2251
2252	/**
2253	* Checks if a code selector (CS) is suitable for execution
2254	* within VMX when unrestricted execution isn't available.
2255	*
2256	* @returns true if selector is suitable for VMX, otherwise
2257	* false.
2258	* @param pSel Pointer to the selector to check (CS).
2259	* uStackDpl The CPL, aka the DPL of the stack segment.
2260	*/
2261	static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2262	{
2263	/*
2264	* Segment must be an accessed code segment, it must be present and it must
2265	* be usable.
2266	* Note! These are all standard requirements and if CS holds anything else
2267	* we've got buggy code somewhere!
2268	*/
2269	AssertCompile(X86DESCATTR_TYPE == 0xf);
2270	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
2271	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
2272	("%#x\n", pSel->Attr.u),
2273	false);
2274
2275	/* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2276	must equal SS.DPL for non-confroming segments.
2277	Note! This is also a hard requirement like above. */
2278	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2279	? pSel->Attr.n.u2Dpl <= uStackDpl
2280	: pSel->Attr.n.u2Dpl == uStackDpl,
2281	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2282	false);
2283
2284	/*
2285	* The following two requirements are VT-x specific:
2286	* - G bit must be set if any high limit bits are set.
2287	* - G bit must be clear if any low limit bits are clear.
2288	*/
2289	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
2290	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity) )
2291	return true;
2292	return false;
2293	}
2294
2295
2296	/**
2297	* Checks if a data selector (DS/ES/FS/GS) is suitable for
2298	* execution within VMX when unrestricted execution isn't
2299	* available.
2300	*
2301	* @returns true if selector is suitable for VMX, otherwise
2302	* false.
2303	* @param pSel Pointer to the selector to check
2304	* (DS/ES/FS/GS).
2305	*/
2306	static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2307	{
2308	/*
2309	* Unusable segments are OK. These days they should be marked as such, as
2310	* but as an alternative we for old saved states and AMD<->VT-x migration
2311	* we also treat segments with all the attributes cleared as unusable.
2312	*/
2313	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
2314	return true;
2315
2316	/** @todo tighten these checks. Will require CPUM load adjusting. */
2317
2318	/* Segment must be accessed. */
2319	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2320	{
2321	/* Code segments must also be readable. */
2322	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2323	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
2324	{
2325	/* The S bit must be set. */
2326	if (pSel->Attr.n.u1DescType)
2327	{
2328	/* Except for conforming segments, DPL >= RPL. */
2329	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2330	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2331	{
2332	/* Segment must be present. */
2333	if (pSel->Attr.n.u1Present)
2334	{
2335	/*
2336	* The following two requirements are VT-x specific:
2337	* - G bit must be set if any high limit bits are set.
2338	* - G bit must be clear if any low limit bits are clear.
2339	*/
2340	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
2341	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity) )
2342	return true;
2343	}
2344	}
2345	}
2346	}
2347	}
2348
2349	return false;
2350	}
2351
2352
2353	/**
2354	* Checks if the stack selector (SS) is suitable for execution
2355	* within VMX when unrestricted execution isn't available.
2356	*
2357	* @returns true if selector is suitable for VMX, otherwise
2358	* false.
2359	* @param pSel Pointer to the selector to check (SS).
2360	*/
2361	static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2362	{
2363	/*
2364	* Unusable segments are OK. These days they should be marked as such, as
2365	* but as an alternative we for old saved states and AMD<->VT-x migration
2366	* we also treat segments with all the attributes cleared as unusable.
2367	*/
2368	/** @todo r=bird: actually all zeros isn't gonna cut it... SS.DPL == CPL. */
2369	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
2370	return true;
2371
2372	/*
2373	* Segment must be an accessed writable segment, it must be present.
2374	* Note! These are all standard requirements and if SS holds anything else
2375	* we've got buggy code somewhere!
2376	*/
2377	AssertCompile(X86DESCATTR_TYPE == 0xf);
2378	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
2379	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
2380	("%#x\n", pSel->Attr.u),
2381	false);
2382
2383	/* DPL must equal RPL.
2384	Note! This is also a hard requirement like above. */
2385	AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2386	("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2387	false);
2388
2389	/*
2390	* The following two requirements are VT-x specific:
2391	* - G bit must be set if any high limit bits are set.
2392	* - G bit must be clear if any low limit bits are clear.
2393	*/
2394	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
2395	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity) )
2396	return true;
2397	return false;
2398	}
2399
2400
2401	/**
2402	* Force execution of the current IO code in the recompiler.
2403	*
2404	* @returns VBox status code.
2405	* @param pVM Pointer to the VM.
2406	* @param pCtx Partial VM execution context.
2407	*/
2408	VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2409	{
2410	PVMCPU pVCpu = VMMGetCpu(pVM);
2411
2412	Assert(HMIsEnabled(pVM));
2413	Log(("HMR3EmulateIoBlock\n"));
2414
2415	/* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2416	if (HMCanEmulateIoBlockEx(pCtx))
2417	{
2418	Log(("HMR3EmulateIoBlock -> enabled\n"));
2419	pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2420	pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2421	pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2422	return VINF_EM_RESCHEDULE_REM;
2423	}
2424	return VINF_SUCCESS;
2425	}
2426
2427
2428	/**
2429	* Checks if we can currently use hardware accelerated raw mode.
2430	*
2431	* @returns true if we can currently use hardware acceleration, otherwise false.
2432	* @param pVM Pointer to the VM.
2433	* @param pCtx Partial VM execution context.
2434	*/
2435	VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2436	{
2437	PVMCPU pVCpu = VMMGetCpu(pVM);
2438
2439	Assert(HMIsEnabled(pVM));
2440
2441	/* If we're still executing the IO code, then return false. */
2442	if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2443	&& pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2444	&& pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2445	&& pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2446	return false;
2447
2448	pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2449
2450	/* AMD-V supports real & protected mode with or without paging. */
2451	if (pVM->hm.s.svm.fEnabled)
2452	{
2453	pVCpu->hm.s.fActive = true;
2454	return true;
2455	}
2456
2457	pVCpu->hm.s.fActive = false;
2458
2459	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2460	Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2461	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2462
2463	bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
2464	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2465	{
2466	/*
2467	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2468	* guest execution feature is missing (VT-x only).
2469	*/
2470	if (fSupportsRealMode)
2471	{
2472	if (CPUMIsGuestInRealModeEx(pCtx))
2473	{
2474	/* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2475	* bases and limits, i.e. limit must be 64K and base must be selector * 16.
2476	* If this is not true, we cannot execute real mode as V86 and have to fall
2477	* back to emulation.
2478	*/
2479	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2480	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2481	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2482	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2483	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2484	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2485	{
2486	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2487	return false;
2488	}
2489	if ( (pCtx->cs.u32Limit != 0xffff)
2490	\|\| (pCtx->ds.u32Limit != 0xffff)
2491	\|\| (pCtx->es.u32Limit != 0xffff)
2492	\|\| (pCtx->ss.u32Limit != 0xffff)
2493	\|\| (pCtx->fs.u32Limit != 0xffff)
2494	\|\| (pCtx->gs.u32Limit != 0xffff))
2495	{
2496	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2497	return false;
2498	}
2499	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2500	}
2501	else
2502	{
2503	/* Verify the requirements for executing code in protected
2504	mode. VT-x can't handle the CPU state right after a switch
2505	from real to protected mode. (all sorts of RPL & DPL assumptions). */
2506	if (pVCpu->hm.s.vmx.fWasInRealMode)
2507	{
2508	/** @todo If guest is in V86 mode, these checks should be different! */
2509	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2510	{
2511	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2512	return false;
2513	}
2514	if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2515	\|\| !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2516	\|\| !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2517	\|\| !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2518	\|\| !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2519	\|\| !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2520	{
2521	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2522	return false;
2523	}
2524	}
2525	/* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2526	if (pCtx->gdtr.cbGdt)
2527	{
2528	if ((pCtx->tr.Sel \| X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2529	{
2530	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2531	return false;
2532	}
2533	else if ((pCtx->ldtr.Sel \| X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2534	{
2535	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2536	return false;
2537	}
2538	}
2539	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2540	}
2541	}
2542	else
2543	{
2544	if ( !CPUMIsGuestInLongModeEx(pCtx)
2545	&& !pVM->hm.s.vmx.fUnrestrictedGuest)
2546	{
2547	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
2548	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2549	return false;
2550
2551	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2552	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
2553	return false;
2554
2555	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2556	/* Windows XP; switch to protected mode; all selectors are marked not present in the
2557	* hidden registers (possible recompiler bug; see load_seg_vm) */
2558	if (pCtx->cs.Attr.n.u1Present == 0)
2559	return false;
2560	if (pCtx->ss.Attr.n.u1Present == 0)
2561	return false;
2562
2563	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
2564	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2565	/** @todo This check is actually wrong, it doesn't take the direction of the
2566	* stack segment into account. But, it does the job for now. */
2567	if (pCtx->rsp >= pCtx->ss.u32Limit)
2568	return false;
2569	}
2570	}
2571	}
2572
2573	if (pVM->hm.s.vmx.fEnabled)
2574	{
2575	uint32_t mask;
2576
2577	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2578	mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2579	/* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2580	mask &= ~X86_CR0_NE;
2581
2582	if (fSupportsRealMode)
2583	{
2584	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2585	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
2586	}
2587	else
2588	{
2589	/* We support protected mode without paging using identity mapping. */
2590	mask &= ~X86_CR0_PG;
2591	}
2592	if ((pCtx->cr0 & mask) != mask)
2593	return false;
2594
2595	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2596	mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2597	if ((pCtx->cr0 & mask) != 0)
2598	return false;
2599
2600	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2601	mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2602	mask &= ~X86_CR4_VMXE;
2603	if ((pCtx->cr4 & mask) != mask)
2604	return false;
2605
2606	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2607	mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2608	if ((pCtx->cr4 & mask) != 0)
2609	return false;
2610
2611	pVCpu->hm.s.fActive = true;
2612	return true;
2613	}
2614
2615	return false;
2616	}
2617
2618
2619	/**
2620	* Checks if we need to reschedule due to VMM device heap changes.
2621	*
2622	* @returns true if a reschedule is required, otherwise false.
2623	* @param pVM Pointer to the VM.
2624	* @param pCtx VM execution context.
2625	*/
2626	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2627	{
2628	/*
2629	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2630	* when the unrestricted guest execution feature is missing (VT-x only).
2631	*/
2632	if ( pVM->hm.s.vmx.fEnabled
2633	&& !pVM->hm.s.vmx.fUnrestrictedGuest
2634	&& CPUMIsGuestInRealModeEx(pCtx)
2635	&& !PDMVmmDevHeapIsEnabled(pVM))
2636	{
2637	return true;
2638	}
2639
2640	return false;
2641	}
2642
2643
2644	/**
2645	* Notification from EM about a rescheduling into hardware assisted execution
2646	* mode.
2647	*
2648	* @param pVCpu Pointer to the current VMCPU.
2649	*/
2650	VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2651	{
2652	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2653	}
2654
2655
2656	/**
2657	* Notification from EM about returning from instruction emulation (REM / EM).
2658	*
2659	* @param pVCpu Pointer to the VMCPU.
2660	*/
2661	VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2662	{
2663	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2664	}
2665
2666
2667	/**
2668	* Checks if we are currently using hardware acceleration.
2669	*
2670	* @returns true if hardware acceleration is being used, otherwise false.
2671	* @param pVCpu Pointer to the VMCPU.
2672	*/
2673	VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2674	{
2675	return pVCpu->hm.s.fActive;
2676	}
2677
2678
2679	/**
2680	* External interface for querying whether hardware acceleration is enabled.
2681	*
2682	* @returns true if VT-x or AMD-V is being used, otherwise false.
2683	* @param pUVM The user mode VM handle.
2684	* @sa HMIsEnabled, HMIsEnabledNotMacro.
2685	*/
2686	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2687	{
2688	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2689	PVM pVM = pUVM->pVM;
2690	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2691	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2692	}
2693
2694
2695	/**
2696	* External interface for querying whether VT-x is being used.
2697	*
2698	* @returns true if VT-x is being used, otherwise false.
2699	* @param pUVM The user mode VM handle.
2700	* @sa HMR3IsSvmEnabled, HMIsEnabled
2701	*/
2702	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
2703	{
2704	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2705	PVM pVM = pUVM->pVM;
2706	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2707	return pVM->hm.s.vmx.fEnabled
2708	&& pVM->hm.s.vmx.fSupported
2709	&& pVM->fHMEnabled;
2710	}
2711
2712
2713	/**
2714	* External interface for querying whether AMD-V is being used.
2715	*
2716	* @returns true if VT-x is being used, otherwise false.
2717	* @param pUVM The user mode VM handle.
2718	* @sa HMR3IsVmxEnabled, HMIsEnabled
2719	*/
2720	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
2721	{
2722	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2723	PVM pVM = pUVM->pVM;
2724	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2725	return pVM->hm.s.svm.fEnabled
2726	&& pVM->hm.s.svm.fSupported
2727	&& pVM->fHMEnabled;
2728	}
2729
2730
2731	/**
2732	* Checks if we are currently using nested paging.
2733	*
2734	* @returns true if nested paging is being used, otherwise false.
2735	* @param pUVM The user mode VM handle.
2736	*/
2737	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
2738	{
2739	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2740	PVM pVM = pUVM->pVM;
2741	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2742	return pVM->hm.s.fNestedPaging;
2743	}
2744
2745
2746	/**
2747	* Checks if we are currently using VPID in VT-x mode.
2748	*
2749	* @returns true if VPID is being used, otherwise false.
2750	* @param pUVM The user mode VM handle.
2751	*/
2752	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
2753	{
2754	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2755	PVM pVM = pUVM->pVM;
2756	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2757	return pVM->hm.s.vmx.fVpid;
2758	}
2759
2760
2761	/**
2762	* Checks if we are currently using VT-x unrestricted execution,
2763	* aka UX.
2764	*
2765	* @returns true if UX is being used, otherwise false.
2766	* @param pUVM The user mode VM handle.
2767	*/
2768	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
2769	{
2770	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2771	PVM pVM = pUVM->pVM;
2772	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2773	return pVM->hm.s.vmx.fUnrestrictedGuest;
2774	}
2775
2776
2777	/**
2778	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
2779	*
2780	* @returns true if an internal event is pending, otherwise false.
2781	* @param pVM Pointer to the VM.
2782	*/
2783	VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
2784	{
2785	return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
2786	}
2787
2788
2789	/**
2790	* Checks if the VMX-preemption timer is being used.
2791	*
2792	* @returns true if the VMX-preemption timer is being used, otherwise false.
2793	* @param pVM Pointer to the VM.
2794	*/
2795	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
2796	{
2797	return HMIsEnabled(pVM)
2798	&& pVM->hm.s.vmx.fEnabled
2799	&& pVM->hm.s.vmx.fUsePreemptTimer;
2800	}
2801
2802
2803	/**
2804	* Restart an I/O instruction that was refused in ring-0
2805	*
2806	* @returns Strict VBox status code. Informational status codes other than the one documented
2807	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
2808	* @retval VINF_SUCCESS Success.
2809	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
2810	* status code must be passed on to EM.
2811	* @retval VERR_NOT_FOUND if no pending I/O instruction.
2812	*
2813	* @param pVM Pointer to the VM.
2814	* @param pVCpu Pointer to the VMCPU.
2815	* @param pCtx Pointer to the guest CPU context.
2816	*/
2817	VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2818	{
2819	HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
2820
2821	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
2822
2823	if ( pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip
2824	\|\| enmType == HMPENDINGIO_INVALID)
2825	return VERR_NOT_FOUND;
2826
2827	VBOXSTRICTRC rcStrict;
2828	switch (enmType)
2829	{
2830	case HMPENDINGIO_PORT_READ:
2831	{
2832	uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
2833	uint32_t u32Val = 0;
2834
2835	rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2836	&u32Val,
2837	pVCpu->hm.s.PendingIO.s.Port.cbSize);
2838	if (IOM_SUCCESS(rcStrict))
2839	{
2840	/* Write back to the EAX register. */
2841	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
2842	pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2843	}
2844	break;
2845	}
2846
2847	case HMPENDINGIO_PORT_WRITE:
2848	rcStrict = IOMIOPortWrite(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort,
2849	pCtx->eax & pVCpu->hm.s.PendingIO.s.Port.uAndVal,
2850	pVCpu->hm.s.PendingIO.s.Port.cbSize);
2851	if (IOM_SUCCESS(rcStrict))
2852	pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
2853	break;
2854
2855	default:
2856	AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
2857	}
2858
2859	if (IOM_SUCCESS(rcStrict))
2860	{
2861	/*
2862	* Check for I/O breakpoints.
2863	*/
2864	uint32_t const uDr7 = pCtx->dr[7];
2865	if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
2866	&& X86_DR7_ANY_RW_IO(uDr7)
2867	&& (pCtx->cr4 & X86_CR4_DE))
2868	\|\| DBGFBpIsHwIoArmed(pVM))
2869	{
2870	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
2871	pVCpu->hm.s.PendingIO.s.Port.cbSize);
2872	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
2873	rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
2874	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
2875	else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
2876	rcStrict = rcStrict2;
2877	}
2878	}
2879	return rcStrict;
2880	}
2881
2882
2883	/**
2884	* Check fatal VT-x/AMD-V error and produce some meaningful
2885	* log release message.
2886	*
2887	* @param pVM Pointer to the VM.
2888	* @param iStatusCode VBox status code.
2889	*/
2890	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
2891	{
2892	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2893	{
2894	PVMCPU pVCpu = &pVM->aCpus[i];
2895	switch (iStatusCode)
2896	{
2897	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
2898	* might be getting inaccurate values for non-guru'ing EMTs. */
2899	case VERR_VMX_INVALID_VMCS_FIELD:
2900	break;
2901
2902	case VERR_VMX_INVALID_VMCS_PTR:
2903	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
2904	LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
2905	pVCpu->hm.s.vmx.HCPhysVmcs));
2906	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
2907	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2908	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2909	break;
2910
2911	case VERR_VMX_UNABLE_TO_START_VM:
2912	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
2913	LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
2914	LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
2915
2916	if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
2917	\|\| pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
2918	{
2919	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
2920	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
2921	}
2922	else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
2923	{
2924	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
2925	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
2926	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
2927	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
2928	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
2929	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
2930	LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
2931	LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
2932	LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
2933	}
2934	/** @todo Log VM-entry event injection control fields
2935	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
2936	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
2937	break;
2938
2939	case VERR_VMX_INVALID_VMXON_PTR:
2940	break;
2941
2942	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
2943	case VERR_VMX_INVALID_GUEST_STATE:
2944	case VERR_VMX_UNEXPECTED_EXIT:
2945	case VERR_SVM_UNKNOWN_EXIT:
2946	case VERR_SVM_UNEXPECTED_EXIT:
2947	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
2948	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
2949	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
2950	{
2951	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
2952	LogRel(("HM: CPU[%u] idxExitHistoryFree %u\n", i, pVCpu->hm.s.idxExitHistoryFree));
2953	unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
2954	pVCpu->hm.s.idxExitHistoryFree - 1 :
2955	RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
2956	for (unsigned k = 0; k < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); k++)
2957	{
2958	LogRel(("HM: CPU[%u] auExitHistory[%2u] = %#x (%u) %s\n", i, k, pVCpu->hm.s.auExitHistory[k],
2959	pVCpu->hm.s.auExitHistory[k], idxLast == k ? "<-- Last" : ""));
2960	}
2961	break;
2962	}
2963	}
2964	}
2965
2966	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
2967	{
2968	LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
2969	LogRel(("VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
2970	}
2971	}
2972
2973
2974	/**
2975	* Execute state save operation.
2976	*
2977	* @returns VBox status code.
2978	* @param pVM Pointer to the VM.
2979	* @param pSSM SSM operation handle.
2980	*/
2981	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
2982	{
2983	int rc;
2984
2985	Log(("hmR3Save:\n"));
2986
2987	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2988	{
2989	/*
2990	* Save the basic bits - fortunately all the other things can be resynced on load.
2991	*/
2992	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
2993	AssertRCReturn(rc, rc);
2994	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
2995	AssertRCReturn(rc, rc);
2996	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
2997	AssertRCReturn(rc, rc);
2998	/** @todo Shouldn't we be saving GCPtrFaultAddress too? */
2999
3000	/** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3001	* perhaps not even that (the initial value of @c true is safe. */
3002	uint32_t u32Dummy = PGMMODE_REAL;
3003	rc = SSMR3PutU32(pSSM, u32Dummy);
3004	AssertRCReturn(rc, rc);
3005	rc = SSMR3PutU32(pSSM, u32Dummy);
3006	AssertRCReturn(rc, rc);
3007	rc = SSMR3PutU32(pSSM, u32Dummy);
3008	AssertRCReturn(rc, rc);
3009	}
3010
3011	#ifdef VBOX_HM_WITH_GUEST_PATCHING
3012	rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3013	AssertRCReturn(rc, rc);
3014	rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3015	AssertRCReturn(rc, rc);
3016	rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3017	AssertRCReturn(rc, rc);
3018
3019	/* Store all the guest patch records too. */
3020	rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3021	AssertRCReturn(rc, rc);
3022
3023	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3024	{
3025	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3026
3027	rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3028	AssertRCReturn(rc, rc);
3029
3030	rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3031	AssertRCReturn(rc, rc);
3032
3033	rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3034	AssertRCReturn(rc, rc);
3035
3036	rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3037	AssertRCReturn(rc, rc);
3038
3039	rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3040	AssertRCReturn(rc, rc);
3041
3042	AssertCompileSize(HMTPRINSTR, 4);
3043	rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3044	AssertRCReturn(rc, rc);
3045
3046	rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3047	AssertRCReturn(rc, rc);
3048
3049	rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3050	AssertRCReturn(rc, rc);
3051
3052	rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3053	AssertRCReturn(rc, rc);
3054
3055	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3056	AssertRCReturn(rc, rc);
3057	}
3058	#endif
3059	return VINF_SUCCESS;
3060	}
3061
3062
3063	/**
3064	* Execute state load operation.
3065	*
3066	* @returns VBox status code.
3067	* @param pVM Pointer to the VM.
3068	* @param pSSM SSM operation handle.
3069	* @param uVersion Data layout version.
3070	* @param uPass The data pass.
3071	*/
3072	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3073	{
3074	int rc;
3075
3076	Log(("hmR3Load:\n"));
3077	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3078
3079	/*
3080	* Validate version.
3081	*/
3082	if ( uVersion != HM_SAVED_STATE_VERSION
3083	&& uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3084	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3085	{
3086	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3087	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3088	}
3089	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3090	{
3091	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3092	AssertRCReturn(rc, rc);
3093	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3094	AssertRCReturn(rc, rc);
3095	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3096	AssertRCReturn(rc, rc);
3097
3098	if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3099	{
3100	uint32_t val;
3101	/** @todo See note in hmR3Save(). */
3102	rc = SSMR3GetU32(pSSM, &val);
3103	AssertRCReturn(rc, rc);
3104	rc = SSMR3GetU32(pSSM, &val);
3105	AssertRCReturn(rc, rc);
3106	rc = SSMR3GetU32(pSSM, &val);
3107	AssertRCReturn(rc, rc);
3108	}
3109	}
3110	#ifdef VBOX_HM_WITH_GUEST_PATCHING
3111	if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3112	{
3113	rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3114	AssertRCReturn(rc, rc);
3115	rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3116	AssertRCReturn(rc, rc);
3117	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3118	AssertRCReturn(rc, rc);
3119
3120	/* Fetch all TPR patch records. */
3121	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3122	AssertRCReturn(rc, rc);
3123
3124	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3125	{
3126	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3127
3128	rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3129	AssertRCReturn(rc, rc);
3130
3131	rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3132	AssertRCReturn(rc, rc);
3133
3134	rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3135	AssertRCReturn(rc, rc);
3136
3137	rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3138	AssertRCReturn(rc, rc);
3139
3140	rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3141	AssertRCReturn(rc, rc);
3142
3143	rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3144	AssertRCReturn(rc, rc);
3145
3146	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3147	pVM->hm.s.fTPRPatchingActive = true;
3148
3149	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTPRPatchingActive == false);
3150
3151	rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3152	AssertRCReturn(rc, rc);
3153
3154	rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3155	AssertRCReturn(rc, rc);
3156
3157	rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3158	AssertRCReturn(rc, rc);
3159
3160	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3161	AssertRCReturn(rc, rc);
3162
3163	Log(("hmR3Load: patch %d\n", i));
3164	Log(("Key = %x\n", pPatch->Core.Key));
3165	Log(("cbOp = %d\n", pPatch->cbOp));
3166	Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3167	Log(("type = %d\n", pPatch->enmType));
3168	Log(("srcop = %d\n", pPatch->uSrcOperand));
3169	Log(("dstop = %d\n", pPatch->uDstOperand));
3170	Log(("cFaults = %d\n", pPatch->cFaults));
3171	Log(("target = %x\n", pPatch->pJumpTarget));
3172	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3173	AssertRC(rc);
3174	}
3175	}
3176	#endif
3177
3178	return VINF_SUCCESS;
3179	}
3180

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 53349

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