VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 65299

Last change on this file since 65299 was 64855, checked in by vboxsync, 8 years ago

VMM/HM: Added hmeventpending dbginfo command.
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File size: 158.4 KB
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1/* $Id: HM.cpp 64855 2016-12-13 17:13:47Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2016 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#include <VBox/vmm/cpum.h>
41#include <VBox/vmm/stam.h>
42#include <VBox/vmm/mm.h>
43#include <VBox/vmm/pdmapi.h>
44#include <VBox/vmm/pgm.h>
45#include <VBox/vmm/ssm.h>
46#include <VBox/vmm/trpm.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/iom.h>
49#include <VBox/vmm/patm.h>
50#include <VBox/vmm/csam.h>
51#include <VBox/vmm/selm.h>
52#ifdef VBOX_WITH_REM
53# include <VBox/vmm/rem.h>
54#endif
55#include <VBox/vmm/hm_vmx.h>
56#include <VBox/vmm/hm_svm.h>
57#include "HMInternal.h"
58#include <VBox/vmm/vm.h>
59#include <VBox/vmm/uvm.h>
60#include <VBox/err.h>
61#include <VBox/param.h>
62
63#include <iprt/assert.h>
64#include <VBox/log.h>
65#include <iprt/asm.h>
66#include <iprt/asm-amd64-x86.h>
67#include <iprt/env.h>
68#include <iprt/thread.h>
69
70
71/*********************************************************************************************************************************
72* Global Variables *
73*********************************************************************************************************************************/
74#define EXIT_REASON(def, val, str) #def " - " #val " - " str
75#define EXIT_REASON_NIL() NULL
76/** Exit reason descriptions for VT-x, used to describe statistics. */
77static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
78{
79 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
80 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
81 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
82 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
83 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
84 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
85 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
86 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
87 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
88 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
89 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
90 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
91 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
92 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
93 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
94 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
95 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
96 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
97 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
98 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
99 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
100 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
101 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
102 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
103 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
104 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
105 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
106 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
107 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
108 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
109 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
110 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
111 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
112 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
113 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
114 EXIT_REASON_NIL(),
115 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
116 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
117 EXIT_REASON_NIL(),
118 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
119 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
120 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
121 EXIT_REASON_NIL(),
122 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
123 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
124 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
125 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
126 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
127 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
128 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
129 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
130 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
131 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
132 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
133 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
134 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
135 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
136 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
137 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
138 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instrunction."),
139 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
140 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
141 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
142 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
143};
144/** Array index of the last valid VT-x exit reason. */
145#define MAX_EXITREASON_VTX 64
146
147/** A partial list of Exit reason descriptions for AMD-V, used to describe
148 * statistics.
149 *
150 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
151 * this array doesn't contain the entire set of exit reasons, we
152 * handle them via hmSvmGetSpecialExitReasonDesc(). */
153static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
154{
155 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
156 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
157 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
158 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
159 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
160 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
161 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
162 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
163 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
164 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
165 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
166 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
167 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
168 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
169 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
170 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
171 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
172 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
173 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
174 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
187 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
188 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
189 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
190 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
191 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
192 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
193 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
194 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
195 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
196 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
197 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
198 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
199 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
200 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
201 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
202 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
203 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
204 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
205 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
206 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
219 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
233 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
234 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
235 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
236 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
237 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
238 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
239 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
240 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
241 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
242 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
243 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
244 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
245 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
246 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
247 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
248 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
249 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
250 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
251 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
252 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
253 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
254 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
255 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
256 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
257 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR"),
258 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR"),
259 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
260 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
261 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
262 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
263 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
264 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
265 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
266 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
267 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
268 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
269 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
270 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
271 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
272 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
273 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
274 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
275 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
276 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
277 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
278 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT accessing protected port."),
279 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
280 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
281 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
282 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
283 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
284 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
285 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
286 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
287 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
288 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
289 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
290 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
291 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
292 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
293 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
294 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
295 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
296 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
297};
298/** Array index of the last valid AMD-V exit reason. */
299#define MAX_EXITREASON_AMDV 141
300
301/** Special exit reasons not covered in the array above. */
302#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
303#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
304#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
305
306/**
307 * Gets the SVM exit reason if it's one of the reasons not present in the @c
308 * g_apszAmdVExitReasons array.
309 *
310 * @returns The exit reason or NULL if unknown.
311 * @param uExit The exit.
312 */
313DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
314{
315 switch (uExit)
316 {
317 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
318 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
319 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
320 }
321 return EXIT_REASON_NIL();
322}
323#undef EXIT_REASON_NIL
324#undef EXIT_REASON
325
326/** @def HMVMX_REPORT_FEATURE
327 * Reports VT-x feature to the release log.
328 *
329 * @param allowed1 Mask of allowed feature bits.
330 * @param disallowed0 Mask of disallowed feature bits.
331 * @param strdesc The description string to report.
332 * @param featflag Mask of the feature to report.
333 */
334#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
335 do { \
336 if ((allowed1) & (featflag)) \
337 { \
338 if ((disallowed0) & (featflag)) \
339 LogRel(("HM: " strdesc " (must be set)\n")); \
340 else \
341 LogRel(("HM: " strdesc "\n")); \
342 } \
343 else \
344 LogRel(("HM: " strdesc " (must be cleared)\n")); \
345 } while (0)
346
347/** @def HMVMX_REPORT_ALLOWED_FEATURE
348 * Reports an allowed VT-x feature to the release log.
349 *
350 * @param allowed1 Mask of allowed feature bits.
351 * @param strdesc The description string to report.
352 * @param featflag Mask of the feature to report.
353 */
354#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
355 do { \
356 if ((allowed1) & (featflag)) \
357 LogRel(("HM: " strdesc "\n")); \
358 else \
359 LogRel(("HM: " strdesc " not supported\n")); \
360 } while (0)
361
362/** @def HMVMX_REPORT_MSR_CAPABILITY
363 * Reports MSR feature capability.
364 *
365 * @param msrcaps Mask of MSR feature bits.
366 * @param strdesc The description string to report.
367 * @param cap Mask of the feature to report.
368 */
369#define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
370 do { \
371 if ((msrcaps) & (cap)) \
372 LogRel(("HM: " strdesc "\n")); \
373 } while (0)
374
375
376/*********************************************************************************************************************************
377* Internal Functions *
378*********************************************************************************************************************************/
379static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
380static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
381static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
382static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
383static int hmR3InitCPU(PVM pVM);
384static int hmR3InitFinalizeR0(PVM pVM);
385static int hmR3InitFinalizeR0Intel(PVM pVM);
386static int hmR3InitFinalizeR0Amd(PVM pVM);
387static int hmR3TermCPU(PVM pVM);
388
389
390
391/**
392 * Initializes the HM.
393 *
394 * This reads the config and check whether VT-x or AMD-V hardware is available
395 * if configured to use it. This is one of the very first components to be
396 * initialized after CFGM, so that we can fall back to raw-mode early in the
397 * initialization process.
398 *
399 * Note that a lot of the set up work is done in ring-0 and thus postponed till
400 * the ring-3 and ring-0 callback to HMR3InitCompleted.
401 *
402 * @returns VBox status code.
403 * @param pVM The cross context VM structure.
404 *
405 * @remarks Be careful with what we call here, since most of the VMM components
406 * are uninitialized.
407 */
408VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
409{
410 LogFlow(("HMR3Init\n"));
411
412 /*
413 * Assert alignment and sizes.
414 */
415 AssertCompileMemberAlignment(VM, hm.s, 32);
416 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
417
418 /*
419 * Register the saved state data unit.
420 */
421 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
422 NULL, NULL, NULL,
423 NULL, hmR3Save, NULL,
424 NULL, hmR3Load, NULL);
425 if (RT_FAILURE(rc))
426 return rc;
427
428 /*
429 * Register info handlers.
430 */
431 rc = DBGFR3InfoRegisterInternalEx(pVM, "exithistory", "Dumps the HM VM-exit history.", hmR3InfoExitHistory,
432 DBGFINFO_FLAGS_ALL_EMTS);
433 AssertRCReturn(rc, rc);
434
435 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
436 DBGFINFO_FLAGS_ALL_EMTS);
437 AssertRCReturn(rc, rc);
438
439 /*
440 * Read configuration.
441 */
442 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
443
444 /*
445 * Validate the HM settings.
446 */
447 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
448 "HMForced"
449 "|EnableNestedPaging"
450 "|EnableUX"
451 "|EnableLargePages"
452 "|EnableVPID"
453 "|TPRPatchingEnabled"
454 "|64bitEnabled"
455 "|VmxPleGap"
456 "|VmxPleWindow"
457 "|SvmPauseFilter"
458 "|SvmPauseFilterThreshold"
459 "|Exclusive"
460 "|MaxResumeLoops"
461 "|UseVmxPreemptTimer",
462 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
463 if (RT_FAILURE(rc))
464 return rc;
465
466 /** @cfgm{/HM/HMForced, bool, false}
467 * Forces hardware virtualization, no falling back on raw-mode. HM must be
468 * enabled, i.e. /HMEnabled must be true. */
469 bool fHMForced;
470#ifdef VBOX_WITH_RAW_MODE
471 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
472 AssertRCReturn(rc, rc);
473 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
474 VERR_INVALID_PARAMETER);
475# if defined(RT_OS_DARWIN)
476 if (pVM->fHMEnabled)
477 fHMForced = true;
478# endif
479 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
480 VERR_INVALID_PARAMETER);
481 if (pVM->cCpus > 1)
482 fHMForced = true;
483#else /* !VBOX_WITH_RAW_MODE */
484 AssertRelease(pVM->fHMEnabled);
485 fHMForced = true;
486#endif /* !VBOX_WITH_RAW_MODE */
487
488 /** @cfgm{/HM/EnableNestedPaging, bool, false}
489 * Enables nested paging (aka extended page tables). */
490 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
491 AssertRCReturn(rc, rc);
492
493 /** @cfgm{/HM/EnableUX, bool, true}
494 * Enables the VT-x unrestricted execution feature. */
495 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
496 AssertRCReturn(rc, rc);
497
498 /** @cfgm{/HM/EnableLargePages, bool, false}
499 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
500 * page table walking and maybe better TLB hit rate in some cases. */
501 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
502 AssertRCReturn(rc, rc);
503
504 /** @cfgm{/HM/EnableVPID, bool, false}
505 * Enables the VT-x VPID feature. */
506 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
507 AssertRCReturn(rc, rc);
508
509 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
510 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
511 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
512 AssertRCReturn(rc, rc);
513
514 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
515 * Enables AMD64 cpu features.
516 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
517 * already have the support. */
518#ifdef VBOX_ENABLE_64_BITS_GUESTS
519 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
520 AssertLogRelRCReturn(rc, rc);
521#else
522 pVM->hm.s.fAllow64BitGuests = false;
523#endif
524
525 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
526 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
527 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
528 * latest PAUSE instruction to be start of a new PAUSE loop.
529 */
530 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
531 AssertRCReturn(rc, rc);
532
533 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
534 * The pause-filter exiting window in TSC ticks. When the number of ticks
535 * between the current PAUSE instruction and first PAUSE of a loop exceeds
536 * VmxPleWindow, a VM-exit is triggered.
537 *
538 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
539 */
540 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
541 AssertRCReturn(rc, rc);
542
543 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
544 * A counter that is decrement each time a PAUSE instruction is executed by the
545 * guest. When the counter is 0, a \#VMEXIT is triggered.
546 */
547 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
548 AssertRCReturn(rc, rc);
549
550 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
551 * The pause filter threshold in ticks. When the elapsed time between two
552 * successive PAUSE instructions exceeds SvmPauseFilterThreshold, the PauseFilter
553 * count is reset to its initial value. However, if PAUSE is executed PauseFilter
554 * times within PauseFilterThreshold ticks, a VM-exit will be triggered.
555 *
556 * Setting both SvmPauseFilterCount and SvmPauseFilterCount to 0 disables
557 * pause-filter exiting.
558 */
559 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
560 AssertRCReturn(rc, rc);
561
562 /** @cfgm{/HM/Exclusive, bool}
563 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
564 * global init for each host CPU. If false, we do local init each time we wish
565 * to execute guest code.
566 *
567 * On Windows, default is false due to the higher risk of conflicts with other
568 * hypervisors.
569 *
570 * On Mac OS X, this setting is ignored since the code does not handle local
571 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
572 */
573#if defined(RT_OS_DARWIN)
574 pVM->hm.s.fGlobalInit = true;
575#else
576 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
577# if defined(RT_OS_WINDOWS)
578 false
579# else
580 true
581# endif
582 );
583 AssertLogRelRCReturn(rc, rc);
584#endif
585
586 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
587 * The number of times to resume guest execution before we forcibly return to
588 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
589 * determines the default value. */
590 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
591 AssertLogRelRCReturn(rc, rc);
592
593 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
594 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
595 * available. */
596 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
597 AssertLogRelRCReturn(rc, rc);
598
599 /*
600 * Check if VT-x or AMD-v support according to the users wishes.
601 */
602 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
603 * VERR_SVM_IN_USE. */
604 if (pVM->fHMEnabled)
605 {
606 uint32_t fCaps;
607 rc = SUPR3QueryVTCaps(&fCaps);
608 if (RT_SUCCESS(rc))
609 {
610 if (fCaps & SUPVTCAPS_AMD_V)
611 {
612 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
613 pVM->hm.s.svm.fSupported = true;
614 }
615 else if (fCaps & SUPVTCAPS_VT_X)
616 {
617 rc = SUPR3QueryVTxSupported();
618 if (RT_SUCCESS(rc))
619 {
620 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
621 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
622 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
623 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
624 pVM->hm.s.vmx.fSupported = true;
625 }
626 else
627 {
628#ifdef RT_OS_LINUX
629 const char *pszMinReq = " Linux 2.6.13 or newer required!";
630#else
631 const char *pszMinReq = "";
632#endif
633 if (fHMForced)
634 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
635
636 /* Fall back to raw-mode. */
637 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
638 pVM->fHMEnabled = false;
639 }
640 }
641 else
642 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
643 VERR_INTERNAL_ERROR_5);
644
645 /*
646 * Do we require a little bit or raw-mode for 64-bit guest execution?
647 */
648 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
649 && pVM->fHMEnabled
650 && pVM->hm.s.fAllow64BitGuests;
651
652 /*
653 * Disable nested paging and unrestricted guest execution now if they're
654 * configured so that CPUM can make decisions based on our configuration.
655 */
656 Assert(!pVM->hm.s.fNestedPaging);
657 if (pVM->hm.s.fAllowNestedPaging)
658 {
659 if (fCaps & SUPVTCAPS_NESTED_PAGING)
660 pVM->hm.s.fNestedPaging = true;
661 else
662 pVM->hm.s.fAllowNestedPaging = false;
663 }
664
665 if (fCaps & SUPVTCAPS_VT_X)
666 {
667 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
668 if (pVM->hm.s.vmx.fAllowUnrestricted)
669 {
670 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
671 && pVM->hm.s.fNestedPaging)
672 pVM->hm.s.vmx.fUnrestrictedGuest = true;
673 else
674 pVM->hm.s.vmx.fAllowUnrestricted = false;
675 }
676 }
677 }
678 else
679 {
680 const char *pszMsg;
681 switch (rc)
682 {
683 case VERR_UNSUPPORTED_CPU:
684 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained";
685 break;
686
687 case VERR_VMX_NO_VMX:
688 pszMsg = "VT-x is not available";
689 break;
690
691 case VERR_VMX_MSR_VMX_DISABLED:
692 pszMsg = "VT-x is disabled in the BIOS";
693 break;
694
695 case VERR_VMX_MSR_ALL_VMX_DISABLED:
696 pszMsg = "VT-x is disabled in the BIOS for all CPU modes";
697 break;
698
699 case VERR_VMX_MSR_LOCKING_FAILED:
700 pszMsg = "Failed to enable and lock VT-x features";
701 break;
702
703 case VERR_SVM_NO_SVM:
704 pszMsg = "AMD-V is not available";
705 break;
706
707 case VERR_SVM_DISABLED:
708 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)";
709 break;
710
711 default:
712 pszMsg = NULL;
713 break;
714 }
715 if (fHMForced && pszMsg)
716 return VM_SET_ERROR(pVM, rc, pszMsg);
717 if (!pszMsg)
718 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
719
720 /* Fall back to raw-mode. */
721 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
722 pVM->fHMEnabled = false;
723 }
724 }
725
726 /* It's now OK to use the predicate function. */
727 pVM->fHMEnabledFixed = true;
728 return VINF_SUCCESS;
729}
730
731
732/**
733 * Initializes the per-VCPU HM.
734 *
735 * @returns VBox status code.
736 * @param pVM The cross context VM structure.
737 */
738static int hmR3InitCPU(PVM pVM)
739{
740 LogFlow(("HMR3InitCPU\n"));
741
742 if (!HMIsEnabled(pVM))
743 return VINF_SUCCESS;
744
745 for (VMCPUID i = 0; i < pVM->cCpus; i++)
746 {
747 PVMCPU pVCpu = &pVM->aCpus[i];
748 pVCpu->hm.s.fActive = false;
749 }
750
751#ifdef VBOX_WITH_STATISTICS
752 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
753 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
754 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
755 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
756 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
757#endif
758
759 /*
760 * Statistics.
761 */
762 for (VMCPUID i = 0; i < pVM->cCpus; i++)
763 {
764 PVMCPU pVCpu = &pVM->aCpus[i];
765 int rc;
766
767#ifdef VBOX_WITH_STATISTICS
768 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
769 "Profiling of RTMpPokeCpu",
770 "/PROF/CPU%d/HM/Poke", i);
771 AssertRC(rc);
772 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
773 "Profiling of poke wait",
774 "/PROF/CPU%d/HM/PokeWait", i);
775 AssertRC(rc);
776 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
777 "Profiling of poke wait when RTMpPokeCpu fails",
778 "/PROF/CPU%d/HM/PokeWaitFailed", i);
779 AssertRC(rc);
780 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
781 "Profiling of VMXR0RunGuestCode entry",
782 "/PROF/CPU%d/HM/StatEntry", i);
783 AssertRC(rc);
784 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
785 "Profiling of VMXR0RunGuestCode exit part 1",
786 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
787 AssertRC(rc);
788 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
789 "Profiling of VMXR0RunGuestCode exit part 2",
790 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
791 AssertRC(rc);
792
793 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
794 "I/O",
795 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
796 AssertRC(rc);
797 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
798 "MOV CRx",
799 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
800 AssertRC(rc);
801 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
802 "Exceptions, NMIs",
803 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
804 AssertRC(rc);
805
806 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
807 "Profiling of VMXR0LoadGuestState",
808 "/PROF/CPU%d/HM/StatLoadGuestState", i);
809 AssertRC(rc);
810 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
811 "Profiling of VMLAUNCH/VMRESUME.",
812 "/PROF/CPU%d/HM/InGC", i);
813 AssertRC(rc);
814
815# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
816 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
817 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
818 "/PROF/CPU%d/HM/Switcher3264", i);
819 AssertRC(rc);
820# endif
821
822# ifdef HM_PROFILE_EXIT_DISPATCH
823 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
824 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
825 "/PROF/CPU%d/HM/ExitDispatch", i);
826 AssertRC(rc);
827# endif
828
829#endif
830# define HM_REG_COUNTER(a, b, desc) \
831 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
832 AssertRC(rc);
833
834#ifdef VBOX_WITH_STATISTICS
835 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
836 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
837 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
838 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
839 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
840 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
841 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
842 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
843 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
844 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
845 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
846 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
847 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
848 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
849 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
850 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
851 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
852 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
853 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
854 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
855 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
856 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
857 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
858 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
859 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
860 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
861 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
862 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
863 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
864 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
865 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
866 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
867 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
868 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
869 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
870 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
871 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
872 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
873 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
874 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
875 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
876 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
877 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
878 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
879 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
880 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
881 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
882#endif
883 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
884#ifdef VBOX_WITH_STATISTICS
885 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
886 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
887 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
888 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
889 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
890
891 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
892 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
893 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
894 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
895 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
896 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
897 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
898 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
899 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
900#endif
901 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
902#ifdef VBOX_WITH_STATISTICS
903 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
904
905 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
906 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
907 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
908 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
909
910 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
911 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
912 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
913 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
914 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
915 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
916 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
917 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
918 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
919 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
920 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
921 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
922 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
923 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
924
925 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
926 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
927 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
928
929 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
930 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
931 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
932
933 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
934 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
935
936 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
937 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
938 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
939 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
940 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
941 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
942 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
943 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
944
945#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
946 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
947 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
948#endif
949
950 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
951 {
952 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
953 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
954 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
955 AssertRC(rc);
956 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
957 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
958 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
959 AssertRC(rc);
960 }
961
962#undef HM_REG_COUNTER
963
964 pVCpu->hm.s.paStatExitReason = NULL;
965
966 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
967 (void **)&pVCpu->hm.s.paStatExitReason);
968 AssertRC(rc);
969 if (RT_SUCCESS(rc))
970 {
971 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ?
972 &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
973 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
974 {
975 if (papszDesc[j])
976 {
977 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
978 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
979 AssertRC(rc);
980 }
981 }
982 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
983 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
984 AssertRC(rc);
985 }
986 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
987# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
988 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
989# else
990 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
991# endif
992
993 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
994 AssertRCReturn(rc, rc);
995 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
996# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
997 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
998# else
999 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1000# endif
1001 for (unsigned j = 0; j < 255; j++)
1002 {
1003 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1004 "Injected event.",
1005 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1006 }
1007
1008#endif /* VBOX_WITH_STATISTICS */
1009 }
1010
1011#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1012 /*
1013 * Magic marker for searching in crash dumps.
1014 */
1015 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1016 {
1017 PVMCPU pVCpu = &pVM->aCpus[i];
1018
1019 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1020 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1021 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1022 }
1023#endif
1024
1025 return VINF_SUCCESS;
1026}
1027
1028
1029/**
1030 * Called when a init phase has completed.
1031 *
1032 * @returns VBox status code.
1033 * @param pVM The cross context VM structure.
1034 * @param enmWhat The phase that completed.
1035 */
1036VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1037{
1038 switch (enmWhat)
1039 {
1040 case VMINITCOMPLETED_RING3:
1041 return hmR3InitCPU(pVM);
1042 case VMINITCOMPLETED_RING0:
1043 return hmR3InitFinalizeR0(pVM);
1044 default:
1045 return VINF_SUCCESS;
1046 }
1047}
1048
1049
1050/**
1051 * Turns off normal raw mode features.
1052 *
1053 * @param pVM The cross context VM structure.
1054 */
1055static void hmR3DisableRawMode(PVM pVM)
1056{
1057 /* Reinit the paging mode to force the new shadow mode. */
1058 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1059 {
1060 PVMCPU pVCpu = &pVM->aCpus[i];
1061
1062 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1063 }
1064}
1065
1066
1067/**
1068 * Initialize VT-x or AMD-V.
1069 *
1070 * @returns VBox status code.
1071 * @param pVM The cross context VM structure.
1072 */
1073static int hmR3InitFinalizeR0(PVM pVM)
1074{
1075 int rc;
1076
1077 if (!HMIsEnabled(pVM))
1078 return VINF_SUCCESS;
1079
1080 /*
1081 * Hack to allow users to work around broken BIOSes that incorrectly set
1082 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1083 */
1084 if ( !pVM->hm.s.vmx.fSupported
1085 && !pVM->hm.s.svm.fSupported
1086 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
1087 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1088 {
1089 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1090 pVM->hm.s.svm.fSupported = true;
1091 pVM->hm.s.svm.fIgnoreInUseError = true;
1092 pVM->hm.s.lLastError = VINF_SUCCESS;
1093 }
1094
1095 /*
1096 * Report ring-0 init errors.
1097 */
1098 if ( !pVM->hm.s.vmx.fSupported
1099 && !pVM->hm.s.svm.fSupported)
1100 {
1101 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
1102 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1103 switch (pVM->hm.s.lLastError)
1104 {
1105 case VERR_VMX_IN_VMX_ROOT_MODE:
1106 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1107 case VERR_VMX_NO_VMX:
1108 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1109 case VERR_VMX_MSR_VMX_DISABLED:
1110 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1111 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1112 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1113 case VERR_VMX_MSR_LOCKING_FAILED:
1114 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1115 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1116 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1117 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1118 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1119
1120 case VERR_SVM_IN_USE:
1121 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1122 case VERR_SVM_NO_SVM:
1123 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1124 case VERR_SVM_DISABLED:
1125 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1126 }
1127 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
1128 }
1129
1130 /*
1131 * Enable VT-x or AMD-V on all host CPUs.
1132 */
1133 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1134 if (RT_FAILURE(rc))
1135 {
1136 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1137 HMR3CheckError(pVM, rc);
1138 return rc;
1139 }
1140
1141 /*
1142 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1143 * (Main should have taken care of this already)
1144 */
1145 pVM->hm.s.fHasIoApic = PDMHasIoApic(pVM);
1146 if (!pVM->hm.s.fHasIoApic)
1147 {
1148 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1149 pVM->hm.s.fTprPatchingAllowed = false;
1150 }
1151
1152 /*
1153 * Do the vendor specific initialization .
1154 * .
1155 * Note! We disable release log buffering here since we're doing relatively .
1156 * lot of logging and doesn't want to hit the disk with each LogRel .
1157 * statement.
1158 */
1159 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1160 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1161 if (pVM->hm.s.vmx.fSupported)
1162 rc = hmR3InitFinalizeR0Intel(pVM);
1163 else
1164 rc = hmR3InitFinalizeR0Amd(pVM);
1165 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1166 RTLogRelSetBuffering(fOldBuffered);
1167 pVM->hm.s.fInitialized = true;
1168
1169 return rc;
1170}
1171
1172
1173/**
1174 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1175 */
1176static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1177{
1178 NOREF(pVM);
1179 NOREF(pvAllocation);
1180 NOREF(GCPhysAllocation);
1181}
1182
1183
1184/**
1185 * Finish VT-x initialization (after ring-0 init).
1186 *
1187 * @returns VBox status code.
1188 * @param pVM The cross context VM structure.
1189 */
1190static int hmR3InitFinalizeR0Intel(PVM pVM)
1191{
1192 int rc;
1193
1194 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1195 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1196
1197 uint64_t val;
1198 uint64_t zap;
1199
1200 LogRel(("HM: Using VT-x implementation 2.0\n"));
1201 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1202 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1203 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1204 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1205 if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1206 LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1207 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1208 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1209 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1210 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1211 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1212 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1213 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1214 LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1215 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1216
1217 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1218 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1219 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1220 HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1221 HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1222 HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1223 HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1224 HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1225
1226 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1227 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1228 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1229 HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1230 HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1231 HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1232 HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1233 HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1234 HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1235 HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1236 HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1237 HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1238 HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1239 HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1240 HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1241 HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1242 HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1243 HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1244 HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1245 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1246 HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1247 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1248 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1249 HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1250 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1251 {
1252 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1253 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1254 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1255 HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1256 HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1257 HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1258 HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1259 HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1260 HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1261 HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1262 HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1263 HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1264 HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1265 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1266 HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1267 HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1268 HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1269 HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1270 HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1271 HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1272 HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1273 HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1274 HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1275 HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1276 HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1277 }
1278
1279 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1280 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1281 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1282 HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1283 HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1284 HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1285 HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1286 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1287 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1288 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1289
1290 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1291 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1292 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1293 HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1294 HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1295 HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1296 HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1297 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1298 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1299 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1300 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1301 HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1302
1303 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1304 {
1305 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1306 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1307 HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1308 HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1309 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1310 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1311 HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1312 HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1313 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1314 HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1315 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1316 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1317 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1318 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1319 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1320 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1321 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1322 }
1323
1324 val = pVM->hm.s.vmx.Msrs.u64Misc;
1325 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1326 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1327 LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1328 else
1329 {
1330 LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1331 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1332 }
1333
1334 LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1335 LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1336 LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1337 LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1338 LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1339 LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1340 LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1341 LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1342
1343 /* Paranoia */
1344 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1345
1346 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1347 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1348 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1349 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1350
1351 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1352 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1353 LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1354
1355 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1356 if (val)
1357 {
1358 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
1359 HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1360 }
1361
1362 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1363
1364 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1365 {
1366 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1367 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1368 }
1369
1370 /*
1371 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1372 */
1373 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1374 || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1375 VERR_HM_IPE_1);
1376 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1377 || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1378 && pVM->hm.s.fNestedPaging),
1379 VERR_HM_IPE_1);
1380
1381 /*
1382 * Enable VPID if configured and supported.
1383 */
1384 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1385 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1386
1387#if 0
1388 /*
1389 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1390 */
1391 if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1392 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1393 pVM->hm.s.fVirtApicRegs = true;
1394
1395 /*
1396 * Enable posted-interrupt processing if supported.
1397 */
1398 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1399 * here. */
1400 if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1401 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1402 pVM->hm.s.fPostedIntrs = true;
1403#endif
1404
1405 /*
1406 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1407 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1408 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1409 */
1410 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1411 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1412 {
1413 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1414 LogRel(("HM: Disabled RDTSCP\n"));
1415 }
1416
1417 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1418 {
1419 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1420 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1421 if (RT_SUCCESS(rc))
1422 {
1423 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1424 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1425 esp. Figure 20-5.*/
1426 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1427 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1428
1429 /* Bit set to 0 means software interrupts are redirected to the
1430 8086 program interrupt handler rather than switching to
1431 protected-mode handler. */
1432 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1433
1434 /* Allow all port IO, so that port IO instructions do not cause
1435 exceptions and would instead cause a VM-exit (based on VT-x's
1436 IO bitmap which we currently configure to always cause an exit). */
1437 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1438 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1439
1440 /*
1441 * Construct a 1024 element page directory with 4 MB pages for
1442 * the identity mapped page table used in real and protected mode
1443 * without paging with EPT.
1444 */
1445 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1446 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1447 {
1448 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1449 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1450 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1451 | X86_PDE4M_G;
1452 }
1453
1454 /* We convert it here every time as PCI regions could be reconfigured. */
1455 if (PDMVmmDevHeapIsEnabled(pVM))
1456 {
1457 RTGCPHYS GCPhys;
1458 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1459 AssertRCReturn(rc, rc);
1460 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1461
1462 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1463 AssertRCReturn(rc, rc);
1464 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1465 }
1466 }
1467 else
1468 {
1469 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1470 pVM->hm.s.vmx.pRealModeTSS = NULL;
1471 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1472 return VMSetError(pVM, rc, RT_SRC_POS,
1473 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1474 }
1475 }
1476
1477 LogRel((pVM->hm.s.fAllow64BitGuests
1478 ? "HM: Guest support: 32-bit and 64-bit\n"
1479 : "HM: Guest support: 32-bit only\n"));
1480
1481 /*
1482 * Call ring-0 to set up the VM.
1483 */
1484 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1485 if (rc != VINF_SUCCESS)
1486 {
1487 AssertMsgFailed(("%Rrc\n", rc));
1488 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1489 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1490 {
1491 PVMCPU pVCpu = &pVM->aCpus[i];
1492 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1493 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1494 }
1495 HMR3CheckError(pVM, rc);
1496 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1497 }
1498
1499 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1500 LogRel(("HM: Enabled VMX\n"));
1501 pVM->hm.s.vmx.fEnabled = true;
1502
1503 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1504
1505 /*
1506 * Change the CPU features.
1507 */
1508 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1509 if (pVM->hm.s.fAllow64BitGuests)
1510 {
1511 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1512 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1513 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1514 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1515 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1516 }
1517 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1518 (we reuse the host EFER in the switcher). */
1519 /** @todo this needs to be fixed properly!! */
1520 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1521 {
1522 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1523 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1524 else
1525 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1526 }
1527
1528 /*
1529 * Log configuration details.
1530 */
1531 if (pVM->hm.s.fNestedPaging)
1532 {
1533 LogRel(("HM: Enabled nested paging\n"));
1534 if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1535 LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1536 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1537 LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1538 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1539 LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1540 else
1541 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1542
1543 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1544 LogRel(("HM: Enabled unrestricted guest execution\n"));
1545
1546#if HC_ARCH_BITS == 64
1547 if (pVM->hm.s.fLargePages)
1548 {
1549 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1550 PGMSetLargePageUsage(pVM, true);
1551 LogRel(("HM: Enabled large page support\n"));
1552 }
1553#endif
1554 }
1555 else
1556 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1557
1558 if (pVM->hm.s.fVirtApicRegs)
1559 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1560
1561 if (pVM->hm.s.fPostedIntrs)
1562 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1563
1564 if (pVM->hm.s.vmx.fVpid)
1565 {
1566 LogRel(("HM: Enabled VPID\n"));
1567 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1568 LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1569 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1570 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1571 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1572 LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1573 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1574 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1575 else
1576 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1577 }
1578 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1579 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1580
1581 if (pVM->hm.s.vmx.fUsePreemptTimer)
1582 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1583 else
1584 LogRel(("HM: Disabled VMX-preemption timer\n"));
1585
1586 return VINF_SUCCESS;
1587}
1588
1589
1590/**
1591 * Finish AMD-V initialization (after ring-0 init).
1592 *
1593 * @returns VBox status code.
1594 * @param pVM The cross context VM structure.
1595 */
1596static int hmR3InitFinalizeR0Amd(PVM pVM)
1597{
1598 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1599
1600 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1601
1602 uint32_t u32Family;
1603 uint32_t u32Model;
1604 uint32_t u32Stepping;
1605 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1606 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1607 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1608 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1609 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1610 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1611 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1612 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1613 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1614
1615 /*
1616 * Enumerate AMD-V features.
1617 */
1618 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1619 {
1620#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1621 HMSVM_REPORT_FEATURE("NESTED_PAGING", AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1622 HMSVM_REPORT_FEATURE("LBR_VIRT", AMD_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1623 HMSVM_REPORT_FEATURE("SVM_LOCK", AMD_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1624 HMSVM_REPORT_FEATURE("NRIP_SAVE", AMD_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1625 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", AMD_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1626 HMSVM_REPORT_FEATURE("VMCB_CLEAN", AMD_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1627 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", AMD_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1628 HMSVM_REPORT_FEATURE("DECODE_ASSIST", AMD_CPUID_SVM_FEATURE_EDX_DECODE_ASSIST),
1629 HMSVM_REPORT_FEATURE("PAUSE_FILTER", AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1630 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", AMD_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1631 HMSVM_REPORT_FEATURE("AVIC", AMD_CPUID_SVM_FEATURE_EDX_AVIC),
1632#undef HMSVM_REPORT_FEATURE
1633 };
1634
1635 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1636 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1637 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1638 {
1639 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1640 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1641 }
1642 if (fSvmFeatures)
1643 for (unsigned iBit = 0; iBit < 32; iBit++)
1644 if (RT_BIT_32(iBit) & fSvmFeatures)
1645 LogRel(("HM: Reserved bit %u\n", iBit));
1646
1647 /*
1648 * Nested paging is determined in HMR3Init, verify the sanity of that.
1649 */
1650 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1651 || (pVM->hm.s.svm.u32Features & AMD_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1652 VERR_HM_IPE_1);
1653
1654#if 0
1655 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1656 * here. */
1657 if (RTR0IsPostIpiSupport())
1658 pVM->hm.s.fPostedIntrs = true;
1659#endif
1660
1661 /*
1662 * Call ring-0 to set up the VM.
1663 */
1664 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1665 if (rc != VINF_SUCCESS)
1666 {
1667 AssertMsgFailed(("%Rrc\n", rc));
1668 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1669 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1670 }
1671
1672 LogRel(("HM: Enabled SVM\n"));
1673 pVM->hm.s.svm.fEnabled = true;
1674
1675 if (pVM->hm.s.fNestedPaging)
1676 {
1677 LogRel(("HM: Enabled nested paging\n"));
1678
1679 /*
1680 * Enable large pages (2 MB) if applicable.
1681 */
1682#if HC_ARCH_BITS == 64
1683 if (pVM->hm.s.fLargePages)
1684 {
1685 PGMSetLargePageUsage(pVM, true);
1686 LogRel(("HM: Enabled large page support\n"));
1687 }
1688#endif
1689 }
1690
1691 if (pVM->hm.s.fVirtApicRegs)
1692 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1693
1694 if (pVM->hm.s.fPostedIntrs)
1695 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1696
1697 hmR3DisableRawMode(pVM);
1698
1699 /*
1700 * Change the CPU features.
1701 */
1702 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1703 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1704 if (pVM->hm.s.fAllow64BitGuests)
1705 {
1706 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1707 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1708 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1709 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1710 }
1711 /* Turn on NXE if PAE has been enabled. */
1712 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1713 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1714
1715 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1716
1717 LogRel((pVM->hm.s.fAllow64BitGuests
1718 ? "HM: Guest support: 32-bit and 64-bit\n"
1719 : "HM: Guest support: 32-bit only\n"));
1720
1721 return VINF_SUCCESS;
1722}
1723
1724
1725/**
1726 * Applies relocations to data and code managed by this
1727 * component. This function will be called at init and
1728 * whenever the VMM need to relocate it self inside the GC.
1729 *
1730 * @param pVM The cross context VM structure.
1731 */
1732VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1733{
1734 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1735
1736 /* Fetch the current paging mode during the relocate callback during state loading. */
1737 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1738 {
1739 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1740 {
1741 PVMCPU pVCpu = &pVM->aCpus[i];
1742 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1743 }
1744 }
1745#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1746 if (HMIsEnabled(pVM))
1747 {
1748 switch (PGMGetHostMode(pVM))
1749 {
1750 case PGMMODE_32_BIT:
1751 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1752 break;
1753
1754 case PGMMODE_PAE:
1755 case PGMMODE_PAE_NX:
1756 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1757 break;
1758
1759 default:
1760 AssertFailed();
1761 break;
1762 }
1763 }
1764#endif
1765 return;
1766}
1767
1768
1769/**
1770 * Notification callback which is called whenever there is a chance that a CR3
1771 * value might have changed.
1772 *
1773 * This is called by PGM.
1774 *
1775 * @param pVM The cross context VM structure.
1776 * @param pVCpu The cross context virtual CPU structure.
1777 * @param enmShadowMode New shadow paging mode.
1778 * @param enmGuestMode New guest paging mode.
1779 */
1780VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1781{
1782 RT_NOREF_PV(pVM);
1783
1784 /* Ignore page mode changes during state loading. */
1785 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1786 return;
1787
1788 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1789
1790 /*
1791 * If the guest left protected mode VMX execution, we'll have to be
1792 * extra careful if/when the guest switches back to protected mode.
1793 */
1794 if (enmGuestMode == PGMMODE_REAL)
1795 {
1796 Log(("HMR3PagingModeChanged indicates real mode execution\n"));
1797 pVCpu->hm.s.vmx.fWasInRealMode = true;
1798 }
1799}
1800
1801
1802/**
1803 * Terminates the HM.
1804 *
1805 * Termination means cleaning up and freeing all resources,
1806 * the VM itself is, at this point, powered off or suspended.
1807 *
1808 * @returns VBox status code.
1809 * @param pVM The cross context VM structure.
1810 */
1811VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1812{
1813 if (pVM->hm.s.vmx.pRealModeTSS)
1814 {
1815 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1816 pVM->hm.s.vmx.pRealModeTSS = 0;
1817 }
1818 hmR3TermCPU(pVM);
1819 return 0;
1820}
1821
1822
1823/**
1824 * Terminates the per-VCPU HM.
1825 *
1826 * @returns VBox status code.
1827 * @param pVM The cross context VM structure.
1828 */
1829static int hmR3TermCPU(PVM pVM)
1830{
1831 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1832 {
1833 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1834
1835#ifdef VBOX_WITH_STATISTICS
1836 if (pVCpu->hm.s.paStatExitReason)
1837 {
1838 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1839 pVCpu->hm.s.paStatExitReason = NULL;
1840 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1841 }
1842 if (pVCpu->hm.s.paStatInjectedIrqs)
1843 {
1844 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1845 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1846 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1847 }
1848#endif
1849
1850#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1851 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1852 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1853 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1854#endif
1855 }
1856 return 0;
1857}
1858
1859
1860/**
1861 * Resets a virtual CPU.
1862 *
1863 * Used by HMR3Reset and CPU hot plugging.
1864 *
1865 * @param pVCpu The cross context virtual CPU structure to reset.
1866 */
1867VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1868{
1869 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
1870 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1871 HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1872
1873 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1874 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1875 pVCpu->hm.s.fActive = false;
1876 pVCpu->hm.s.Event.fPending = false;
1877 pVCpu->hm.s.vmx.fWasInRealMode = true;
1878 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
1879 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
1880
1881
1882
1883 /* Reset the contents of the read cache. */
1884 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1885 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1886 pCache->Read.aFieldVal[j] = 0;
1887
1888#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1889 /* Magic marker for searching in crash dumps. */
1890 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1891 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1892#endif
1893}
1894
1895
1896/**
1897 * The VM is being reset.
1898 *
1899 * For the HM component this means that any GDT/LDT/TSS monitors
1900 * needs to be removed.
1901 *
1902 * @param pVM The cross context VM structure.
1903 */
1904VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1905{
1906 LogFlow(("HMR3Reset:\n"));
1907
1908 if (HMIsEnabled(pVM))
1909 hmR3DisableRawMode(pVM);
1910
1911 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1912 {
1913 PVMCPU pVCpu = &pVM->aCpus[i];
1914
1915 HMR3ResetCpu(pVCpu);
1916 }
1917
1918 /* Clear all patch information. */
1919 pVM->hm.s.pGuestPatchMem = 0;
1920 pVM->hm.s.pFreeGuestPatchMem = 0;
1921 pVM->hm.s.cbGuestPatchMem = 0;
1922 pVM->hm.s.cPatches = 0;
1923 pVM->hm.s.PatchTree = 0;
1924 pVM->hm.s.fTPRPatchingActive = false;
1925 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1926}
1927
1928
1929/**
1930 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1931 *
1932 * @returns VBox strict status code.
1933 * @param pVM The cross context VM structure.
1934 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1935 * @param pvUser Unused.
1936 */
1937static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1938{
1939 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1940
1941 /* Only execute the handler on the VCPU the original patch request was issued. */
1942 if (pVCpu->idCpu != idCpu)
1943 return VINF_SUCCESS;
1944
1945 Log(("hmR3RemovePatches\n"));
1946 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1947 {
1948 uint8_t abInstr[15];
1949 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1950 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1951 int rc;
1952
1953#ifdef LOG_ENABLED
1954 char szOutput[256];
1955
1956 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1957 szOutput, sizeof(szOutput), NULL);
1958 if (RT_SUCCESS(rc))
1959 Log(("Patched instr: %s\n", szOutput));
1960#endif
1961
1962 /* Check if the instruction is still the same. */
1963 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1964 if (rc != VINF_SUCCESS)
1965 {
1966 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1967 continue; /* swapped out or otherwise removed; skip it. */
1968 }
1969
1970 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1971 {
1972 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1973 continue; /* skip it. */
1974 }
1975
1976 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1977 AssertRC(rc);
1978
1979#ifdef LOG_ENABLED
1980 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1981 szOutput, sizeof(szOutput), NULL);
1982 if (RT_SUCCESS(rc))
1983 Log(("Original instr: %s\n", szOutput));
1984#endif
1985 }
1986 pVM->hm.s.cPatches = 0;
1987 pVM->hm.s.PatchTree = 0;
1988 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1989 pVM->hm.s.fTPRPatchingActive = false;
1990 return VINF_SUCCESS;
1991}
1992
1993
1994/**
1995 * Worker for enabling patching in a VT-x/AMD-V guest.
1996 *
1997 * @returns VBox status code.
1998 * @param pVM The cross context VM structure.
1999 * @param idCpu VCPU to execute hmR3RemovePatches on.
2000 * @param pPatchMem Patch memory range.
2001 * @param cbPatchMem Size of the memory range.
2002 */
2003static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2004{
2005 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2006 AssertRC(rc);
2007
2008 pVM->hm.s.pGuestPatchMem = pPatchMem;
2009 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2010 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2011 return VINF_SUCCESS;
2012}
2013
2014
2015/**
2016 * Enable patching in a VT-x/AMD-V guest
2017 *
2018 * @returns VBox status code.
2019 * @param pVM The cross context VM structure.
2020 * @param pPatchMem Patch memory range.
2021 * @param cbPatchMem Size of the memory range.
2022 */
2023VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2024{
2025 VM_ASSERT_EMT(pVM);
2026 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2027 if (pVM->cCpus > 1)
2028 {
2029 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2030 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2031 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2032 AssertRC(rc);
2033 return rc;
2034 }
2035 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2036}
2037
2038
2039/**
2040 * Disable patching in a VT-x/AMD-V guest.
2041 *
2042 * @returns VBox status code.
2043 * @param pVM The cross context VM structure.
2044 * @param pPatchMem Patch memory range.
2045 * @param cbPatchMem Size of the memory range.
2046 */
2047VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2048{
2049 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2050 RT_NOREF2(pPatchMem, cbPatchMem);
2051
2052 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2053 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2054
2055 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2056 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2057 (void *)(uintptr_t)VMMGetCpuId(pVM));
2058 AssertRC(rc);
2059
2060 pVM->hm.s.pGuestPatchMem = 0;
2061 pVM->hm.s.pFreeGuestPatchMem = 0;
2062 pVM->hm.s.cbGuestPatchMem = 0;
2063 pVM->hm.s.fTPRPatchingActive = false;
2064 return VINF_SUCCESS;
2065}
2066
2067
2068/**
2069 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2070 *
2071 * @returns VBox strict status code.
2072 * @param pVM The cross context VM structure.
2073 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2074 * @param pvUser User specified CPU context.
2075 *
2076 */
2077static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2078{
2079 /*
2080 * Only execute the handler on the VCPU the original patch request was
2081 * issued. (The other CPU(s) might not yet have switched to protected
2082 * mode, nor have the correct memory context.)
2083 */
2084 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2085 if (pVCpu->idCpu != idCpu)
2086 return VINF_SUCCESS;
2087
2088 /*
2089 * We're racing other VCPUs here, so don't try patch the instruction twice
2090 * and make sure there is still room for our patch record.
2091 */
2092 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2093 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2094 if (pPatch)
2095 {
2096 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2097 return VINF_SUCCESS;
2098 }
2099 uint32_t const idx = pVM->hm.s.cPatches;
2100 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2101 {
2102 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2103 return VINF_SUCCESS;
2104 }
2105 pPatch = &pVM->hm.s.aPatches[idx];
2106
2107 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2108
2109 /*
2110 * Disassembler the instruction and get cracking.
2111 */
2112 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2113 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2114 uint32_t cbOp;
2115 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2116 AssertRC(rc);
2117 if ( rc == VINF_SUCCESS
2118 && pDis->pCurInstr->uOpcode == OP_MOV
2119 && cbOp >= 3)
2120 {
2121 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2122
2123 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2124 AssertRC(rc);
2125
2126 pPatch->cbOp = cbOp;
2127
2128 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2129 {
2130 /* write. */
2131 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2132 {
2133 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2134 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2135 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2136 }
2137 else
2138 {
2139 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2140 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2141 pPatch->uSrcOperand = pDis->Param2.uValue;
2142 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2143 }
2144 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2145 AssertRC(rc);
2146
2147 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2148 pPatch->cbNewOp = sizeof(s_abVMMCall);
2149 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2150 }
2151 else
2152 {
2153 /*
2154 * TPR Read.
2155 *
2156 * Found:
2157 * mov eax, dword [fffe0080] (5 bytes)
2158 * Check if next instruction is:
2159 * shr eax, 4
2160 */
2161 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2162
2163 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2164 uint8_t const cbOpMmio = cbOp;
2165 uint64_t const uSavedRip = pCtx->rip;
2166
2167 pCtx->rip += cbOp;
2168 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2169 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2170 pCtx->rip = uSavedRip;
2171
2172 if ( rc == VINF_SUCCESS
2173 && pDis->pCurInstr->uOpcode == OP_SHR
2174 && pDis->Param1.fUse == DISUSE_REG_GEN32
2175 && pDis->Param1.Base.idxGenReg == idxMmioReg
2176 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2177 && pDis->Param2.uValue == 4
2178 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2179 {
2180 uint8_t abInstr[15];
2181
2182 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2183 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2184 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2185 AssertRC(rc);
2186
2187 pPatch->cbOp = cbOpMmio + cbOp;
2188
2189 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2190 abInstr[0] = 0xF0;
2191 abInstr[1] = 0x0F;
2192 abInstr[2] = 0x20;
2193 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2194 for (unsigned i = 4; i < pPatch->cbOp; i++)
2195 abInstr[i] = 0x90; /* nop */
2196
2197 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2198 AssertRC(rc);
2199
2200 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2201 pPatch->cbNewOp = pPatch->cbOp;
2202 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2203
2204 Log(("Acceptable read/shr candidate!\n"));
2205 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2206 }
2207 else
2208 {
2209 pPatch->enmType = HMTPRINSTR_READ;
2210 pPatch->uDstOperand = idxMmioReg;
2211
2212 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2213 AssertRC(rc);
2214
2215 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2216 pPatch->cbNewOp = sizeof(s_abVMMCall);
2217 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2218 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2219 }
2220 }
2221
2222 pPatch->Core.Key = pCtx->eip;
2223 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2224 AssertRC(rc);
2225
2226 pVM->hm.s.cPatches++;
2227 return VINF_SUCCESS;
2228 }
2229
2230 /*
2231 * Save invalid patch, so we will not try again.
2232 */
2233 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2234 pPatch->Core.Key = pCtx->eip;
2235 pPatch->enmType = HMTPRINSTR_INVALID;
2236 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2237 AssertRC(rc);
2238 pVM->hm.s.cPatches++;
2239 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2240 return VINF_SUCCESS;
2241}
2242
2243
2244/**
2245 * Callback to patch a TPR instruction (jump to generated code).
2246 *
2247 * @returns VBox strict status code.
2248 * @param pVM The cross context VM structure.
2249 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2250 * @param pvUser User specified CPU context.
2251 *
2252 */
2253static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2254{
2255 /*
2256 * Only execute the handler on the VCPU the original patch request was
2257 * issued. (The other CPU(s) might not yet have switched to protected
2258 * mode, nor have the correct memory context.)
2259 */
2260 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2261 if (pVCpu->idCpu != idCpu)
2262 return VINF_SUCCESS;
2263
2264 /*
2265 * We're racing other VCPUs here, so don't try patch the instruction twice
2266 * and make sure there is still room for our patch record.
2267 */
2268 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2269 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2270 if (pPatch)
2271 {
2272 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2273 return VINF_SUCCESS;
2274 }
2275 uint32_t const idx = pVM->hm.s.cPatches;
2276 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2277 {
2278 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2279 return VINF_SUCCESS;
2280 }
2281 pPatch = &pVM->hm.s.aPatches[idx];
2282
2283 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2284 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2285
2286 /*
2287 * Disassemble the instruction and get cracking.
2288 */
2289 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2290 uint32_t cbOp;
2291 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2292 AssertRC(rc);
2293 if ( rc == VINF_SUCCESS
2294 && pDis->pCurInstr->uOpcode == OP_MOV
2295 && cbOp >= 5)
2296 {
2297 uint8_t aPatch[64];
2298 uint32_t off = 0;
2299
2300 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2301 AssertRC(rc);
2302
2303 pPatch->cbOp = cbOp;
2304 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2305
2306 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2307 {
2308 /*
2309 * TPR write:
2310 *
2311 * push ECX [51]
2312 * push EDX [52]
2313 * push EAX [50]
2314 * xor EDX,EDX [31 D2]
2315 * mov EAX,EAX [89 C0]
2316 * or
2317 * mov EAX,0000000CCh [B8 CC 00 00 00]
2318 * mov ECX,0C0000082h [B9 82 00 00 C0]
2319 * wrmsr [0F 30]
2320 * pop EAX [58]
2321 * pop EDX [5A]
2322 * pop ECX [59]
2323 * jmp return_address [E9 return_address]
2324 *
2325 */
2326 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2327
2328 aPatch[off++] = 0x51; /* push ecx */
2329 aPatch[off++] = 0x52; /* push edx */
2330 if (!fUsesEax)
2331 aPatch[off++] = 0x50; /* push eax */
2332 aPatch[off++] = 0x31; /* xor edx, edx */
2333 aPatch[off++] = 0xD2;
2334 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2335 {
2336 if (!fUsesEax)
2337 {
2338 aPatch[off++] = 0x89; /* mov eax, src_reg */
2339 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2340 }
2341 }
2342 else
2343 {
2344 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2345 aPatch[off++] = 0xB8; /* mov eax, immediate */
2346 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2347 off += sizeof(uint32_t);
2348 }
2349 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2350 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2351 off += sizeof(uint32_t);
2352
2353 aPatch[off++] = 0x0F; /* wrmsr */
2354 aPatch[off++] = 0x30;
2355 if (!fUsesEax)
2356 aPatch[off++] = 0x58; /* pop eax */
2357 aPatch[off++] = 0x5A; /* pop edx */
2358 aPatch[off++] = 0x59; /* pop ecx */
2359 }
2360 else
2361 {
2362 /*
2363 * TPR read:
2364 *
2365 * push ECX [51]
2366 * push EDX [52]
2367 * push EAX [50]
2368 * mov ECX,0C0000082h [B9 82 00 00 C0]
2369 * rdmsr [0F 32]
2370 * mov EAX,EAX [89 C0]
2371 * pop EAX [58]
2372 * pop EDX [5A]
2373 * pop ECX [59]
2374 * jmp return_address [E9 return_address]
2375 *
2376 */
2377 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2378
2379 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2380 aPatch[off++] = 0x51; /* push ecx */
2381 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2382 aPatch[off++] = 0x52; /* push edx */
2383 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2384 aPatch[off++] = 0x50; /* push eax */
2385
2386 aPatch[off++] = 0x31; /* xor edx, edx */
2387 aPatch[off++] = 0xD2;
2388
2389 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2390 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2391 off += sizeof(uint32_t);
2392
2393 aPatch[off++] = 0x0F; /* rdmsr */
2394 aPatch[off++] = 0x32;
2395
2396 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2397 {
2398 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2399 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2400 }
2401
2402 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2403 aPatch[off++] = 0x58; /* pop eax */
2404 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2405 aPatch[off++] = 0x5A; /* pop edx */
2406 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2407 aPatch[off++] = 0x59; /* pop ecx */
2408 }
2409 aPatch[off++] = 0xE9; /* jmp return_address */
2410 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2411 off += sizeof(RTRCUINTPTR);
2412
2413 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2414 {
2415 /* Write new code to the patch buffer. */
2416 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2417 AssertRC(rc);
2418
2419#ifdef LOG_ENABLED
2420 uint32_t cbCurInstr;
2421 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2422 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2423 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2424 {
2425 char szOutput[256];
2426 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2427 szOutput, sizeof(szOutput), &cbCurInstr);
2428 if (RT_SUCCESS(rc))
2429 Log(("Patch instr %s\n", szOutput));
2430 else
2431 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2432 }
2433#endif
2434
2435 pPatch->aNewOpcode[0] = 0xE9;
2436 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2437
2438 /* Overwrite the TPR instruction with a jump. */
2439 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2440 AssertRC(rc);
2441
2442 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2443
2444 pVM->hm.s.pFreeGuestPatchMem += off;
2445 pPatch->cbNewOp = 5;
2446
2447 pPatch->Core.Key = pCtx->eip;
2448 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2449 AssertRC(rc);
2450
2451 pVM->hm.s.cPatches++;
2452 pVM->hm.s.fTPRPatchingActive = true;
2453 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2454 return VINF_SUCCESS;
2455 }
2456
2457 Log(("Ran out of space in our patch buffer!\n"));
2458 }
2459 else
2460 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2461
2462
2463 /*
2464 * Save invalid patch, so we will not try again.
2465 */
2466 pPatch = &pVM->hm.s.aPatches[idx];
2467 pPatch->Core.Key = pCtx->eip;
2468 pPatch->enmType = HMTPRINSTR_INVALID;
2469 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2470 AssertRC(rc);
2471 pVM->hm.s.cPatches++;
2472 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2473 return VINF_SUCCESS;
2474}
2475
2476
2477/**
2478 * Attempt to patch TPR mmio instructions.
2479 *
2480 * @returns VBox status code.
2481 * @param pVM The cross context VM structure.
2482 * @param pVCpu The cross context virtual CPU structure.
2483 * @param pCtx Pointer to the guest CPU context.
2484 */
2485VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2486{
2487 NOREF(pCtx);
2488 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2489 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2490 (void *)(uintptr_t)pVCpu->idCpu);
2491 AssertRC(rc);
2492 return rc;
2493}
2494
2495
2496/**
2497 * Checks if a code selector (CS) is suitable for execution
2498 * within VMX when unrestricted execution isn't available.
2499 *
2500 * @returns true if selector is suitable for VMX, otherwise
2501 * false.
2502 * @param pSel Pointer to the selector to check (CS).
2503 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2504 */
2505static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2506{
2507 /*
2508 * Segment must be an accessed code segment, it must be present and it must
2509 * be usable.
2510 * Note! These are all standard requirements and if CS holds anything else
2511 * we've got buggy code somewhere!
2512 */
2513 AssertCompile(X86DESCATTR_TYPE == 0xf);
2514 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2515 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2516 ("%#x\n", pSel->Attr.u),
2517 false);
2518
2519 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2520 must equal SS.DPL for non-confroming segments.
2521 Note! This is also a hard requirement like above. */
2522 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2523 ? pSel->Attr.n.u2Dpl <= uStackDpl
2524 : pSel->Attr.n.u2Dpl == uStackDpl,
2525 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2526 false);
2527
2528 /*
2529 * The following two requirements are VT-x specific:
2530 * - G bit must be set if any high limit bits are set.
2531 * - G bit must be clear if any low limit bits are clear.
2532 */
2533 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2534 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2535 return true;
2536 return false;
2537}
2538
2539
2540/**
2541 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2542 * execution within VMX when unrestricted execution isn't
2543 * available.
2544 *
2545 * @returns true if selector is suitable for VMX, otherwise
2546 * false.
2547 * @param pSel Pointer to the selector to check
2548 * (DS/ES/FS/GS).
2549 */
2550static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2551{
2552 /*
2553 * Unusable segments are OK. These days they should be marked as such, as
2554 * but as an alternative we for old saved states and AMD<->VT-x migration
2555 * we also treat segments with all the attributes cleared as unusable.
2556 */
2557 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2558 return true;
2559
2560 /** @todo tighten these checks. Will require CPUM load adjusting. */
2561
2562 /* Segment must be accessed. */
2563 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2564 {
2565 /* Code segments must also be readable. */
2566 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2567 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2568 {
2569 /* The S bit must be set. */
2570 if (pSel->Attr.n.u1DescType)
2571 {
2572 /* Except for conforming segments, DPL >= RPL. */
2573 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2574 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2575 {
2576 /* Segment must be present. */
2577 if (pSel->Attr.n.u1Present)
2578 {
2579 /*
2580 * The following two requirements are VT-x specific:
2581 * - G bit must be set if any high limit bits are set.
2582 * - G bit must be clear if any low limit bits are clear.
2583 */
2584 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2585 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2586 return true;
2587 }
2588 }
2589 }
2590 }
2591 }
2592
2593 return false;
2594}
2595
2596
2597/**
2598 * Checks if the stack selector (SS) is suitable for execution
2599 * within VMX when unrestricted execution isn't available.
2600 *
2601 * @returns true if selector is suitable for VMX, otherwise
2602 * false.
2603 * @param pSel Pointer to the selector to check (SS).
2604 */
2605static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2606{
2607 /*
2608 * Unusable segments are OK. These days they should be marked as such, as
2609 * but as an alternative we for old saved states and AMD<->VT-x migration
2610 * we also treat segments with all the attributes cleared as unusable.
2611 */
2612 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2613 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2614 return true;
2615
2616 /*
2617 * Segment must be an accessed writable segment, it must be present.
2618 * Note! These are all standard requirements and if SS holds anything else
2619 * we've got buggy code somewhere!
2620 */
2621 AssertCompile(X86DESCATTR_TYPE == 0xf);
2622 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2623 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2624 ("%#x\n", pSel->Attr.u),
2625 false);
2626
2627 /* DPL must equal RPL.
2628 Note! This is also a hard requirement like above. */
2629 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2630 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2631 false);
2632
2633 /*
2634 * The following two requirements are VT-x specific:
2635 * - G bit must be set if any high limit bits are set.
2636 * - G bit must be clear if any low limit bits are clear.
2637 */
2638 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2639 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2640 return true;
2641 return false;
2642}
2643
2644
2645/**
2646 * Force execution of the current IO code in the recompiler.
2647 *
2648 * @returns VBox status code.
2649 * @param pVM The cross context VM structure.
2650 * @param pCtx Partial VM execution context.
2651 */
2652VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2653{
2654 PVMCPU pVCpu = VMMGetCpu(pVM);
2655
2656 Assert(HMIsEnabled(pVM));
2657 Log(("HMR3EmulateIoBlock\n"));
2658
2659 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2660 if (HMCanEmulateIoBlockEx(pCtx))
2661 {
2662 Log(("HMR3EmulateIoBlock -> enabled\n"));
2663 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2664 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2665 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2666 return VINF_EM_RESCHEDULE_REM;
2667 }
2668 return VINF_SUCCESS;
2669}
2670
2671
2672/**
2673 * Checks if we can currently use hardware accelerated raw mode.
2674 *
2675 * @returns true if we can currently use hardware acceleration, otherwise false.
2676 * @param pVM The cross context VM structure.
2677 * @param pCtx Partial VM execution context.
2678 */
2679VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2680{
2681 PVMCPU pVCpu = VMMGetCpu(pVM);
2682
2683 Assert(HMIsEnabled(pVM));
2684
2685 /* If we're still executing the IO code, then return false. */
2686 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2687 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2688 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2689 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2690 return false;
2691
2692 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2693
2694 /* AMD-V supports real & protected mode with or without paging. */
2695 if (pVM->hm.s.svm.fEnabled)
2696 {
2697 pVCpu->hm.s.fActive = true;
2698 return true;
2699 }
2700
2701 pVCpu->hm.s.fActive = false;
2702
2703 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2704 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2705 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2706
2707 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2708 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2709 {
2710 /*
2711 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2712 * guest execution feature is missing (VT-x only).
2713 */
2714 if (fSupportsRealMode)
2715 {
2716 if (CPUMIsGuestInRealModeEx(pCtx))
2717 {
2718 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2719 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2720 * If this is not true, we cannot execute real mode as V86 and have to fall
2721 * back to emulation.
2722 */
2723 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2724 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2725 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2726 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2727 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2728 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2729 {
2730 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2731 return false;
2732 }
2733 if ( (pCtx->cs.u32Limit != 0xffff)
2734 || (pCtx->ds.u32Limit != 0xffff)
2735 || (pCtx->es.u32Limit != 0xffff)
2736 || (pCtx->ss.u32Limit != 0xffff)
2737 || (pCtx->fs.u32Limit != 0xffff)
2738 || (pCtx->gs.u32Limit != 0xffff))
2739 {
2740 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2741 return false;
2742 }
2743 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2744 }
2745 else
2746 {
2747 /* Verify the requirements for executing code in protected
2748 mode. VT-x can't handle the CPU state right after a switch
2749 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2750 if (pVCpu->hm.s.vmx.fWasInRealMode)
2751 {
2752 /** @todo If guest is in V86 mode, these checks should be different! */
2753 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2754 {
2755 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2756 return false;
2757 }
2758 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2759 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2760 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2761 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2762 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2763 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2764 {
2765 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2766 return false;
2767 }
2768 }
2769 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2770 if (pCtx->gdtr.cbGdt)
2771 {
2772 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2773 {
2774 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2775 return false;
2776 }
2777 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2778 {
2779 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2780 return false;
2781 }
2782 }
2783 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2784 }
2785 }
2786 else
2787 {
2788 if ( !CPUMIsGuestInLongModeEx(pCtx)
2789 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2790 {
2791 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2792 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2793 return false;
2794
2795 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2796 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2797 return false;
2798
2799 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2800 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2801 * hidden registers (possible recompiler bug; see load_seg_vm) */
2802 if (pCtx->cs.Attr.n.u1Present == 0)
2803 return false;
2804 if (pCtx->ss.Attr.n.u1Present == 0)
2805 return false;
2806
2807 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2808 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2809 /** @todo This check is actually wrong, it doesn't take the direction of the
2810 * stack segment into account. But, it does the job for now. */
2811 if (pCtx->rsp >= pCtx->ss.u32Limit)
2812 return false;
2813 }
2814 }
2815 }
2816
2817 if (pVM->hm.s.vmx.fEnabled)
2818 {
2819 uint32_t mask;
2820
2821 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2822 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2823 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2824 mask &= ~X86_CR0_NE;
2825
2826 if (fSupportsRealMode)
2827 {
2828 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2829 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2830 }
2831 else
2832 {
2833 /* We support protected mode without paging using identity mapping. */
2834 mask &= ~X86_CR0_PG;
2835 }
2836 if ((pCtx->cr0 & mask) != mask)
2837 return false;
2838
2839 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2840 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2841 if ((pCtx->cr0 & mask) != 0)
2842 return false;
2843
2844 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2845 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2846 mask &= ~X86_CR4_VMXE;
2847 if ((pCtx->cr4 & mask) != mask)
2848 return false;
2849
2850 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2851 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2852 if ((pCtx->cr4 & mask) != 0)
2853 return false;
2854
2855 pVCpu->hm.s.fActive = true;
2856 return true;
2857 }
2858
2859 return false;
2860}
2861
2862
2863/**
2864 * Checks if we need to reschedule due to VMM device heap changes.
2865 *
2866 * @returns true if a reschedule is required, otherwise false.
2867 * @param pVM The cross context VM structure.
2868 * @param pCtx VM execution context.
2869 */
2870VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2871{
2872 /*
2873 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2874 * when the unrestricted guest execution feature is missing (VT-x only).
2875 */
2876 if ( pVM->hm.s.vmx.fEnabled
2877 && !pVM->hm.s.vmx.fUnrestrictedGuest
2878 && CPUMIsGuestInRealModeEx(pCtx)
2879 && !PDMVmmDevHeapIsEnabled(pVM))
2880 {
2881 return true;
2882 }
2883
2884 return false;
2885}
2886
2887
2888/**
2889 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2890 * event settings changes.
2891 *
2892 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2893 * function is just updating the VM globals.
2894 *
2895 * @param pVM The VM cross context VM structure.
2896 * @thread EMT(0)
2897 */
2898VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2899{
2900 /* Interrupts. */
2901 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2902 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2903
2904 /* CPU Exceptions. */
2905 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2906 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2907 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2908 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2909
2910 /* Common VM exits. */
2911 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2912 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2913 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2914 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2915
2916 /* Vendor specific VM exits. */
2917 if (HMR3IsVmxEnabled(pVM->pUVM))
2918 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2919 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2920 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2921 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2922 else
2923 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2924 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2925 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2926 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2927
2928 /* Done. */
2929 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2930}
2931
2932
2933/**
2934 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2935 *
2936 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2937 * per CPU settings.
2938 *
2939 * @param pVM The VM cross context VM structure.
2940 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2941 */
2942VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2943{
2944 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2945}
2946
2947
2948/**
2949 * Notification from EM about a rescheduling into hardware assisted execution
2950 * mode.
2951 *
2952 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2953 */
2954VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2955{
2956 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2957}
2958
2959
2960/**
2961 * Notification from EM about returning from instruction emulation (REM / EM).
2962 *
2963 * @param pVCpu The cross context virtual CPU structure.
2964 */
2965VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2966{
2967 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2968}
2969
2970
2971/**
2972 * Checks if we are currently using hardware acceleration.
2973 *
2974 * @returns true if hardware acceleration is being used, otherwise false.
2975 * @param pVCpu The cross context virtual CPU structure.
2976 */
2977VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2978{
2979 return pVCpu->hm.s.fActive;
2980}
2981
2982
2983/**
2984 * External interface for querying whether hardware acceleration is enabled.
2985 *
2986 * @returns true if VT-x or AMD-V is being used, otherwise false.
2987 * @param pUVM The user mode VM handle.
2988 * @sa HMIsEnabled, HMIsEnabledNotMacro.
2989 */
2990VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
2991{
2992 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
2993 PVM pVM = pUVM->pVM;
2994 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
2995 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
2996}
2997
2998
2999/**
3000 * External interface for querying whether VT-x is being used.
3001 *
3002 * @returns true if VT-x is being used, otherwise false.
3003 * @param pUVM The user mode VM handle.
3004 * @sa HMR3IsSvmEnabled, HMIsEnabled
3005 */
3006VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
3007{
3008 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3009 PVM pVM = pUVM->pVM;
3010 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3011 return pVM->hm.s.vmx.fEnabled
3012 && pVM->hm.s.vmx.fSupported
3013 && pVM->fHMEnabled;
3014}
3015
3016
3017/**
3018 * External interface for querying whether AMD-V is being used.
3019 *
3020 * @returns true if VT-x is being used, otherwise false.
3021 * @param pUVM The user mode VM handle.
3022 * @sa HMR3IsVmxEnabled, HMIsEnabled
3023 */
3024VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3025{
3026 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3027 PVM pVM = pUVM->pVM;
3028 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3029 return pVM->hm.s.svm.fEnabled
3030 && pVM->hm.s.svm.fSupported
3031 && pVM->fHMEnabled;
3032}
3033
3034
3035/**
3036 * Checks if we are currently using nested paging.
3037 *
3038 * @returns true if nested paging is being used, otherwise false.
3039 * @param pUVM The user mode VM handle.
3040 */
3041VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3042{
3043 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3044 PVM pVM = pUVM->pVM;
3045 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3046 return pVM->hm.s.fNestedPaging;
3047}
3048
3049
3050/**
3051 * Checks if virtualized APIC registers is enabled.
3052 *
3053 * When enabled this feature allows the hardware to access most of the
3054 * APIC registers in the virtual-APIC page without causing VM-exits. See
3055 * Intel spec. 29.1.1 "Virtualized APIC Registers".
3056 *
3057 * @returns true if virtualized APIC registers is enabled, otherwise
3058 * false.
3059 * @param pUVM The user mode VM handle.
3060 */
3061VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3062{
3063 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3064 PVM pVM = pUVM->pVM;
3065 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3066 return pVM->hm.s.fVirtApicRegs;
3067}
3068
3069
3070/**
3071 * Checks if APIC posted-interrupt processing is enabled.
3072 *
3073 * This returns whether we can deliver interrupts to the guest without
3074 * leaving guest-context by updating APIC state from host-context.
3075 *
3076 * @returns true if APIC posted-interrupt processing is enabled,
3077 * otherwise false.
3078 * @param pUVM The user mode VM handle.
3079 */
3080VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3081{
3082 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3083 PVM pVM = pUVM->pVM;
3084 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3085 return pVM->hm.s.fPostedIntrs;
3086}
3087
3088
3089/**
3090 * Checks if we are currently using VPID in VT-x mode.
3091 *
3092 * @returns true if VPID is being used, otherwise false.
3093 * @param pUVM The user mode VM handle.
3094 */
3095VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3096{
3097 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3098 PVM pVM = pUVM->pVM;
3099 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3100 return pVM->hm.s.vmx.fVpid;
3101}
3102
3103
3104/**
3105 * Checks if we are currently using VT-x unrestricted execution,
3106 * aka UX.
3107 *
3108 * @returns true if UX is being used, otherwise false.
3109 * @param pUVM The user mode VM handle.
3110 */
3111VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3112{
3113 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3114 PVM pVM = pUVM->pVM;
3115 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3116 return pVM->hm.s.vmx.fUnrestrictedGuest;
3117}
3118
3119
3120/**
3121 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3122 *
3123 * @returns true if an internal event is pending, otherwise false.
3124 * @param pVCpu The cross context virtual CPU structure.
3125 */
3126VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3127{
3128 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3129}
3130
3131
3132/**
3133 * Checks if the VMX-preemption timer is being used.
3134 *
3135 * @returns true if the VMX-preemption timer is being used, otherwise false.
3136 * @param pVM The cross context VM structure.
3137 */
3138VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3139{
3140 return HMIsEnabled(pVM)
3141 && pVM->hm.s.vmx.fEnabled
3142 && pVM->hm.s.vmx.fUsePreemptTimer;
3143}
3144
3145
3146/**
3147 * Restart an I/O instruction that was refused in ring-0
3148 *
3149 * @returns Strict VBox status code. Informational status codes other than the one documented
3150 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3151 * @retval VINF_SUCCESS Success.
3152 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3153 * status code must be passed on to EM.
3154 * @retval VERR_NOT_FOUND if no pending I/O instruction.
3155 *
3156 * @param pVM The cross context VM structure.
3157 * @param pVCpu The cross context virtual CPU structure.
3158 * @param pCtx Pointer to the guest CPU context.
3159 */
3160VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3161{
3162 /*
3163 * Check if we've got relevant data pending.
3164 */
3165 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3166 if (enmType == HMPENDINGIO_INVALID)
3167 return VERR_NOT_FOUND;
3168 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3169 if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
3170 return VERR_NOT_FOUND;
3171
3172 /*
3173 * Execute pending I/O.
3174 */
3175 VBOXSTRICTRC rcStrict;
3176 switch (enmType)
3177 {
3178 case HMPENDINGIO_PORT_READ:
3179 {
3180 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3181 uint32_t u32Val = 0;
3182
3183 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3184 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3185 if (IOM_SUCCESS(rcStrict))
3186 {
3187 /* Write back to the EAX register. */
3188 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3189 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3190 }
3191 break;
3192 }
3193
3194 default:
3195 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3196 }
3197
3198 if (IOM_SUCCESS(rcStrict))
3199 {
3200 /*
3201 * Check for I/O breakpoints.
3202 */
3203 uint32_t const uDr7 = pCtx->dr[7];
3204 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3205 && X86_DR7_ANY_RW_IO(uDr7)
3206 && (pCtx->cr4 & X86_CR4_DE))
3207 || DBGFBpIsHwIoArmed(pVM))
3208 {
3209 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3210 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3211 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3212 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3213 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3214 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
3215 rcStrict = rcStrict2;
3216 }
3217 }
3218 return rcStrict;
3219}
3220
3221
3222/**
3223 * Check fatal VT-x/AMD-V error and produce some meaningful
3224 * log release message.
3225 *
3226 * @param pVM The cross context VM structure.
3227 * @param iStatusCode VBox status code.
3228 */
3229VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3230{
3231 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3232 {
3233 PVMCPU pVCpu = &pVM->aCpus[i];
3234 switch (iStatusCode)
3235 {
3236 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3237 * might be getting inaccurate values for non-guru'ing EMTs. */
3238 case VERR_VMX_INVALID_VMCS_FIELD:
3239 break;
3240
3241 case VERR_VMX_INVALID_VMCS_PTR:
3242 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3243 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3244 pVCpu->hm.s.vmx.HCPhysVmcs));
3245 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3246 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3247 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3248 break;
3249
3250 case VERR_VMX_UNABLE_TO_START_VM:
3251 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3252 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3253 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3254
3255 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3256 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3257 {
3258 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3259 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3260 }
3261 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3262 {
3263 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3264 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3265 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3266 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3267 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3268 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3269 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3270 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3271 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3272 }
3273 /** @todo Log VM-entry event injection control fields
3274 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3275 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3276 break;
3277
3278 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3279 case VERR_VMX_INVALID_VMXON_PTR:
3280 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3281 case VERR_VMX_INVALID_GUEST_STATE:
3282 case VERR_VMX_UNEXPECTED_EXIT:
3283 case VERR_SVM_UNKNOWN_EXIT:
3284 case VERR_SVM_UNEXPECTED_EXIT:
3285 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3286 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3287 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3288 break;
3289 }
3290 }
3291
3292 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3293 {
3294 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3295 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3296 }
3297 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3298 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3299}
3300
3301
3302/**
3303 * Execute state save operation.
3304 *
3305 * @returns VBox status code.
3306 * @param pVM The cross context VM structure.
3307 * @param pSSM SSM operation handle.
3308 */
3309static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3310{
3311 int rc;
3312
3313 Log(("hmR3Save:\n"));
3314
3315 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3316 {
3317 /*
3318 * Save the basic bits - fortunately all the other things can be resynced on load.
3319 */
3320 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3321 AssertRCReturn(rc, rc);
3322 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3323 AssertRCReturn(rc, rc);
3324 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
3325 AssertRCReturn(rc, rc);
3326 /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
3327
3328 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3329 * perhaps not even that (the initial value of @c true is safe. */
3330 uint32_t u32Dummy = PGMMODE_REAL;
3331 rc = SSMR3PutU32(pSSM, u32Dummy);
3332 AssertRCReturn(rc, rc);
3333 rc = SSMR3PutU32(pSSM, u32Dummy);
3334 AssertRCReturn(rc, rc);
3335 rc = SSMR3PutU32(pSSM, u32Dummy);
3336 AssertRCReturn(rc, rc);
3337 }
3338
3339#ifdef VBOX_HM_WITH_GUEST_PATCHING
3340 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3341 AssertRCReturn(rc, rc);
3342 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3343 AssertRCReturn(rc, rc);
3344 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3345 AssertRCReturn(rc, rc);
3346
3347 /* Store all the guest patch records too. */
3348 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3349 AssertRCReturn(rc, rc);
3350
3351 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3352 {
3353 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3354
3355 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3356 AssertRCReturn(rc, rc);
3357
3358 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3359 AssertRCReturn(rc, rc);
3360
3361 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3362 AssertRCReturn(rc, rc);
3363
3364 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3365 AssertRCReturn(rc, rc);
3366
3367 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3368 AssertRCReturn(rc, rc);
3369
3370 AssertCompileSize(HMTPRINSTR, 4);
3371 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3372 AssertRCReturn(rc, rc);
3373
3374 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3375 AssertRCReturn(rc, rc);
3376
3377 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3378 AssertRCReturn(rc, rc);
3379
3380 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3381 AssertRCReturn(rc, rc);
3382
3383 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3384 AssertRCReturn(rc, rc);
3385 }
3386#endif
3387 return VINF_SUCCESS;
3388}
3389
3390
3391/**
3392 * Execute state load operation.
3393 *
3394 * @returns VBox status code.
3395 * @param pVM The cross context VM structure.
3396 * @param pSSM SSM operation handle.
3397 * @param uVersion Data layout version.
3398 * @param uPass The data pass.
3399 */
3400static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3401{
3402 int rc;
3403
3404 Log(("hmR3Load:\n"));
3405 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3406
3407 /*
3408 * Validate version.
3409 */
3410 if ( uVersion != HM_SAVED_STATE_VERSION
3411 && uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3412 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3413 {
3414 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3415 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3416 }
3417 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3418 {
3419 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3420 AssertRCReturn(rc, rc);
3421 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3422 AssertRCReturn(rc, rc);
3423 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3424 AssertRCReturn(rc, rc);
3425
3426 if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3427 {
3428 uint32_t val;
3429 /** @todo See note in hmR3Save(). */
3430 rc = SSMR3GetU32(pSSM, &val);
3431 AssertRCReturn(rc, rc);
3432 rc = SSMR3GetU32(pSSM, &val);
3433 AssertRCReturn(rc, rc);
3434 rc = SSMR3GetU32(pSSM, &val);
3435 AssertRCReturn(rc, rc);
3436 }
3437 }
3438#ifdef VBOX_HM_WITH_GUEST_PATCHING
3439 if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3440 {
3441 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3442 AssertRCReturn(rc, rc);
3443 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3444 AssertRCReturn(rc, rc);
3445 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3446 AssertRCReturn(rc, rc);
3447
3448 /* Fetch all TPR patch records. */
3449 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3450 AssertRCReturn(rc, rc);
3451
3452 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3453 {
3454 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3455
3456 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3457 AssertRCReturn(rc, rc);
3458
3459 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3460 AssertRCReturn(rc, rc);
3461
3462 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3463 AssertRCReturn(rc, rc);
3464
3465 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3466 AssertRCReturn(rc, rc);
3467
3468 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3469 AssertRCReturn(rc, rc);
3470
3471 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3472 AssertRCReturn(rc, rc);
3473
3474 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3475 pVM->hm.s.fTPRPatchingActive = true;
3476
3477 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3478
3479 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3480 AssertRCReturn(rc, rc);
3481
3482 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3483 AssertRCReturn(rc, rc);
3484
3485 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3486 AssertRCReturn(rc, rc);
3487
3488 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3489 AssertRCReturn(rc, rc);
3490
3491 Log(("hmR3Load: patch %d\n", i));
3492 Log(("Key = %x\n", pPatch->Core.Key));
3493 Log(("cbOp = %d\n", pPatch->cbOp));
3494 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3495 Log(("type = %d\n", pPatch->enmType));
3496 Log(("srcop = %d\n", pPatch->uSrcOperand));
3497 Log(("dstop = %d\n", pPatch->uDstOperand));
3498 Log(("cFaults = %d\n", pPatch->cFaults));
3499 Log(("target = %x\n", pPatch->pJumpTarget));
3500 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3501 AssertRC(rc);
3502 }
3503 }
3504#endif
3505
3506 return VINF_SUCCESS;
3507}
3508
3509
3510/**
3511 * Displays the guest VM-exit history.
3512 *
3513 * @param pVM The cross context VM structure.
3514 * @param pHlp The info helper functions.
3515 * @param pszArgs Arguments, ignored.
3516 */
3517static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3518{
3519 NOREF(pszArgs);
3520 PVMCPU pVCpu = VMMGetCpu(pVM);
3521 if (!pVCpu)
3522 pVCpu = &pVM->aCpus[0];
3523
3524 if (HMIsEnabled(pVM))
3525 {
3526 bool const fIsVtx = pVM->hm.s.vmx.fSupported;
3527 const char * const *papszDesc;
3528 unsigned cMaxExitDesc;
3529 if (fIsVtx)
3530 {
3531 cMaxExitDesc = MAX_EXITREASON_VTX;
3532 papszDesc = &g_apszVTxExitReasons[0];
3533 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x VM-exit history:\n", pVCpu->idCpu);
3534 }
3535 else
3536 {
3537 cMaxExitDesc = MAX_EXITREASON_AMDV;
3538 papszDesc = &g_apszAmdVExitReasons[0];
3539 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V #VMEXIT history:\n", pVCpu->idCpu);
3540 }
3541
3542 pHlp->pfnPrintf(pHlp, " idxExitHistoryFree = %u\n", pVCpu->hm.s.idxExitHistoryFree);
3543 unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
3544 pVCpu->hm.s.idxExitHistoryFree - 1 :
3545 RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
3546 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); i++)
3547 {
3548 uint16_t const uExit = pVCpu->hm.s.auExitHistory[i];
3549 const char *pszExit = NULL;
3550 if (uExit <= cMaxExitDesc)
3551 pszExit = papszDesc[uExit];
3552 else if (!fIsVtx)
3553 pszExit = hmSvmGetSpecialExitReasonDesc(uExit);
3554 else
3555 pszExit = NULL;
3556
3557 pHlp->pfnPrintf(pHlp, " auExitHistory[%2u] = 0x%04x %s %s\n", i, uExit, pszExit,
3558 idxLast == i ? "<-- Latest exit" : "");
3559 }
3560 pHlp->pfnPrintf(pHlp, "HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3561 }
3562 else
3563 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3564}
3565
3566
3567/**
3568 * Displays the HM pending event.
3569 *
3570 * @param pVM The cross context VM structure.
3571 * @param pHlp The info helper functions.
3572 * @param pszArgs Arguments, ignored.
3573 */
3574static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3575{
3576 NOREF(pszArgs);
3577 PVMCPU pVCpu = VMMGetCpu(pVM);
3578 if (!pVCpu)
3579 pVCpu = &pVM->aCpus[0];
3580
3581 if (HMIsEnabled(pVM))
3582 {
3583 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3584 if (pVCpu->hm.s.Event.fPending)
3585 {
3586 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3587 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3588 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3589 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3590 }
3591 }
3592 else
3593 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3594}
3595
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