VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 70323

Last change on this file since 70323 was 70299, checked in by vboxsync, 7 years ago

VMM: Moved the SVM dumping functions to where it's logically more correct as we emulate SVM in IEM too.
  • Property svn:eol-style set to native
  • Property svn:keywords set to Id Revision
File size: 159.2 KB
Line 
1/* $Id: HM.cpp 70299 2017-12-22 05:16:03Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#include <VBox/vmm/cpum.h>
41#include <VBox/vmm/stam.h>
42#include <VBox/vmm/mm.h>
43#include <VBox/vmm/pdmapi.h>
44#include <VBox/vmm/pgm.h>
45#include <VBox/vmm/ssm.h>
46#include <VBox/vmm/trpm.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/iom.h>
49#include <VBox/vmm/iem.h>
50#include <VBox/vmm/patm.h>
51#include <VBox/vmm/csam.h>
52#include <VBox/vmm/selm.h>
53#ifdef VBOX_WITH_REM
54# include <VBox/vmm/rem.h>
55#endif
56#include <VBox/vmm/hm_vmx.h>
57#include <VBox/vmm/hm_svm.h>
58#include "HMInternal.h"
59#include <VBox/vmm/vm.h>
60#include <VBox/vmm/uvm.h>
61#include <VBox/err.h>
62#include <VBox/param.h>
63
64#include <iprt/assert.h>
65#include <VBox/log.h>
66#include <iprt/asm.h>
67#include <iprt/asm-amd64-x86.h>
68#include <iprt/env.h>
69#include <iprt/thread.h>
70
71
72/*********************************************************************************************************************************
73* Global Variables *
74*********************************************************************************************************************************/
75#define EXIT_REASON(def, val, str) #def " - " #val " - " str
76#define EXIT_REASON_NIL() NULL
77/** Exit reason descriptions for VT-x, used to describe statistics. */
78static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
79{
80 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
81 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
82 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
83 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
84 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
85 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
86 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
87 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
88 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
89 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
90 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
91 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
92 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
93 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
94 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
95 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
96 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
97 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
98 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
99 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
100 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
101 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
102 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
103 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
104 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
105 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
106 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
107 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
108 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
109 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
110 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
111 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
112 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
113 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
114 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
115 EXIT_REASON_NIL(),
116 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
117 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
118 EXIT_REASON_NIL(),
119 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
120 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
121 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
122 EXIT_REASON_NIL(),
123 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
124 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
125 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
126 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
127 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
128 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
129 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
130 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
131 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
132 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
133 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
134 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
135 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
136 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
137 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
138 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
139 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instrunction."),
140 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
141 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
142 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
143 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
144};
145/** Array index of the last valid VT-x exit reason. */
146#define MAX_EXITREASON_VTX 64
147
148/** A partial list of Exit reason descriptions for AMD-V, used to describe
149 * statistics.
150 *
151 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
152 * this array doesn't contain the entire set of exit reasons, we
153 * handle them via hmSvmGetSpecialExitReasonDesc(). */
154static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
155{
156 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
157 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
158 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
159 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
160 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
161 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
162 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
163 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
164 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
165 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
166 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
167 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
168 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
169 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
170 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
171 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
172 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
173 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
174 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
187 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
188 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
189 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
190 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
191 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
192 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
193 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
194 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
195 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
196 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
197 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
198 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
199 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
200 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
201 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
202 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
203 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
204 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
205 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
206 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
219 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
220 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
221 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
233 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
234 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
235 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
236 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
237 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
238 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
239 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
240 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
241 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
242 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
243 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
244 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
245 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
246 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
247 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
248 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
249 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
250 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
251 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
252 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
253 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
254 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
255 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
256 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
257 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
258 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR"),
259 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR"),
260 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
261 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
262 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
263 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
264 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
265 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
266 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
267 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
268 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
269 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
270 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
271 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
272 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
273 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
274 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
275 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
276 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
277 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
278 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
279 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT accessing protected port."),
280 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
281 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
282 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
283 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
284 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
285 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
286 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
287 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
288 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
289 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
290 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
291 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
292 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
293 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
294 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
295 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
296 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
297 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
298};
299/** Array index of the last valid AMD-V exit reason. */
300#define MAX_EXITREASON_AMDV 141
301
302/** Special exit reasons not covered in the array above. */
303#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
304#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
305#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
306
307/**
308 * Gets the SVM exit reason if it's one of the reasons not present in the @c
309 * g_apszAmdVExitReasons array.
310 *
311 * @returns The exit reason or NULL if unknown.
312 * @param uExit The exit.
313 */
314DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
315{
316 switch (uExit)
317 {
318 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
319 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
320 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
321 }
322 return EXIT_REASON_NIL();
323}
324#undef EXIT_REASON_NIL
325#undef EXIT_REASON
326
327/** @def HMVMX_REPORT_FEATURE
328 * Reports VT-x feature to the release log.
329 *
330 * @param allowed1 Mask of allowed feature bits.
331 * @param disallowed0 Mask of disallowed feature bits.
332 * @param strdesc The description string to report.
333 * @param featflag Mask of the feature to report.
334 */
335#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
336 do { \
337 if ((allowed1) & (featflag)) \
338 { \
339 if ((disallowed0) & (featflag)) \
340 LogRel(("HM: " strdesc " (must be set)\n")); \
341 else \
342 LogRel(("HM: " strdesc "\n")); \
343 } \
344 else \
345 LogRel(("HM: " strdesc " (must be cleared)\n")); \
346 } while (0)
347
348/** @def HMVMX_REPORT_ALLOWED_FEATURE
349 * Reports an allowed VT-x feature to the release log.
350 *
351 * @param allowed1 Mask of allowed feature bits.
352 * @param strdesc The description string to report.
353 * @param featflag Mask of the feature to report.
354 */
355#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
356 do { \
357 if ((allowed1) & (featflag)) \
358 LogRel(("HM: " strdesc "\n")); \
359 else \
360 LogRel(("HM: " strdesc " not supported\n")); \
361 } while (0)
362
363/** @def HMVMX_REPORT_MSR_CAPABILITY
364 * Reports MSR feature capability.
365 *
366 * @param msrcaps Mask of MSR feature bits.
367 * @param strdesc The description string to report.
368 * @param cap Mask of the feature to report.
369 */
370#define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
371 do { \
372 if ((msrcaps) & (cap)) \
373 LogRel(("HM: " strdesc "\n")); \
374 } while (0)
375
376
377/*********************************************************************************************************************************
378* Internal Functions *
379*********************************************************************************************************************************/
380static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
381static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
382static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
383static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
384static int hmR3InitCPU(PVM pVM);
385static int hmR3InitFinalizeR0(PVM pVM);
386static int hmR3InitFinalizeR0Intel(PVM pVM);
387static int hmR3InitFinalizeR0Amd(PVM pVM);
388static int hmR3TermCPU(PVM pVM);
389
390
391
392/**
393 * Initializes the HM.
394 *
395 * This reads the config and check whether VT-x or AMD-V hardware is available
396 * if configured to use it. This is one of the very first components to be
397 * initialized after CFGM, so that we can fall back to raw-mode early in the
398 * initialization process.
399 *
400 * Note that a lot of the set up work is done in ring-0 and thus postponed till
401 * the ring-3 and ring-0 callback to HMR3InitCompleted.
402 *
403 * @returns VBox status code.
404 * @param pVM The cross context VM structure.
405 *
406 * @remarks Be careful with what we call here, since most of the VMM components
407 * are uninitialized.
408 */
409VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
410{
411 LogFlow(("HMR3Init\n"));
412
413 /*
414 * Assert alignment and sizes.
415 */
416 AssertCompileMemberAlignment(VM, hm.s, 32);
417 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
418
419 /*
420 * Register the saved state data unit.
421 */
422 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
423 NULL, NULL, NULL,
424 NULL, hmR3Save, NULL,
425 NULL, hmR3Load, NULL);
426 if (RT_FAILURE(rc))
427 return rc;
428
429 /*
430 * Register info handlers.
431 */
432 rc = DBGFR3InfoRegisterInternalEx(pVM, "exithistory", "Dumps the HM VM-exit history.", hmR3InfoExitHistory,
433 DBGFINFO_FLAGS_ALL_EMTS);
434 AssertRCReturn(rc, rc);
435
436 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
437 DBGFINFO_FLAGS_ALL_EMTS);
438 AssertRCReturn(rc, rc);
439
440 /*
441 * Read configuration.
442 */
443 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
444
445 /*
446 * Validate the HM settings.
447 */
448 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
449 "HMForced"
450 "|EnableNestedPaging"
451 "|EnableUX"
452 "|EnableLargePages"
453 "|EnableVPID"
454 "|TPRPatchingEnabled"
455 "|64bitEnabled"
456 "|VmxPleGap"
457 "|VmxPleWindow"
458 "|SvmPauseFilter"
459 "|SvmPauseFilterThreshold"
460 "|Exclusive"
461 "|MaxResumeLoops"
462 "|UseVmxPreemptTimer",
463 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
464 if (RT_FAILURE(rc))
465 return rc;
466
467 /** @cfgm{/HM/HMForced, bool, false}
468 * Forces hardware virtualization, no falling back on raw-mode. HM must be
469 * enabled, i.e. /HMEnabled must be true. */
470 bool fHMForced;
471#ifdef VBOX_WITH_RAW_MODE
472 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
473 AssertRCReturn(rc, rc);
474 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
475 VERR_INVALID_PARAMETER);
476# if defined(RT_OS_DARWIN)
477 if (pVM->fHMEnabled)
478 fHMForced = true;
479# endif
480 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
481 VERR_INVALID_PARAMETER);
482 if (pVM->cCpus > 1)
483 fHMForced = true;
484#else /* !VBOX_WITH_RAW_MODE */
485 AssertRelease(pVM->fHMEnabled);
486 fHMForced = true;
487#endif /* !VBOX_WITH_RAW_MODE */
488
489 /** @cfgm{/HM/EnableNestedPaging, bool, false}
490 * Enables nested paging (aka extended page tables). */
491 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
492 AssertRCReturn(rc, rc);
493
494 /** @cfgm{/HM/EnableUX, bool, true}
495 * Enables the VT-x unrestricted execution feature. */
496 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
497 AssertRCReturn(rc, rc);
498
499 /** @cfgm{/HM/EnableLargePages, bool, false}
500 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
501 * page table walking and maybe better TLB hit rate in some cases. */
502 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
503 AssertRCReturn(rc, rc);
504
505 /** @cfgm{/HM/EnableVPID, bool, false}
506 * Enables the VT-x VPID feature. */
507 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
508 AssertRCReturn(rc, rc);
509
510 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
511 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
512 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
513 AssertRCReturn(rc, rc);
514
515 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
516 * Enables AMD64 cpu features.
517 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
518 * already have the support. */
519#ifdef VBOX_ENABLE_64_BITS_GUESTS
520 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
521 AssertLogRelRCReturn(rc, rc);
522#else
523 pVM->hm.s.fAllow64BitGuests = false;
524#endif
525
526 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
527 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
528 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
529 * latest PAUSE instruction to be start of a new PAUSE loop.
530 */
531 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
532 AssertRCReturn(rc, rc);
533
534 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
535 * The pause-filter exiting window in TSC ticks. When the number of ticks
536 * between the current PAUSE instruction and first PAUSE of a loop exceeds
537 * VmxPleWindow, a VM-exit is triggered.
538 *
539 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
540 */
541 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
542 AssertRCReturn(rc, rc);
543
544 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
545 * A counter that is decrement each time a PAUSE instruction is executed by the
546 * guest. When the counter is 0, a \#VMEXIT is triggered.
547 */
548 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
549 AssertRCReturn(rc, rc);
550
551 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
552 * The pause filter threshold in ticks. When the elapsed time between two
553 * successive PAUSE instructions exceeds SvmPauseFilterThreshold, the PauseFilter
554 * count is reset to its initial value. However, if PAUSE is executed PauseFilter
555 * times within PauseFilterThreshold ticks, a VM-exit will be triggered.
556 *
557 * Setting both SvmPauseFilterCount and SvmPauseFilterCount to 0 disables
558 * pause-filter exiting.
559 */
560 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
561 AssertRCReturn(rc, rc);
562
563 /** @cfgm{/HM/Exclusive, bool}
564 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
565 * global init for each host CPU. If false, we do local init each time we wish
566 * to execute guest code.
567 *
568 * On Windows, default is false due to the higher risk of conflicts with other
569 * hypervisors.
570 *
571 * On Mac OS X, this setting is ignored since the code does not handle local
572 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
573 */
574#if defined(RT_OS_DARWIN)
575 pVM->hm.s.fGlobalInit = true;
576#else
577 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
578# if defined(RT_OS_WINDOWS)
579 false
580# else
581 true
582# endif
583 );
584 AssertLogRelRCReturn(rc, rc);
585#endif
586
587 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
588 * The number of times to resume guest execution before we forcibly return to
589 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
590 * determines the default value. */
591 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
592 AssertLogRelRCReturn(rc, rc);
593
594 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
595 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
596 * available. */
597 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
598 AssertLogRelRCReturn(rc, rc);
599
600 /*
601 * Check if VT-x or AMD-v support according to the users wishes.
602 */
603 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
604 * VERR_SVM_IN_USE. */
605 if (pVM->fHMEnabled)
606 {
607 uint32_t fCaps;
608 rc = SUPR3QueryVTCaps(&fCaps);
609 if (RT_SUCCESS(rc))
610 {
611 if (fCaps & SUPVTCAPS_AMD_V)
612 {
613 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
614 pVM->hm.s.svm.fSupported = true;
615 }
616 else if (fCaps & SUPVTCAPS_VT_X)
617 {
618 rc = SUPR3QueryVTxSupported();
619 if (RT_SUCCESS(rc))
620 {
621 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
622 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
623 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
624 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
625 pVM->hm.s.vmx.fSupported = true;
626 }
627 else
628 {
629#ifdef RT_OS_LINUX
630 const char *pszMinReq = " Linux 2.6.13 or newer required!";
631#else
632 const char *pszMinReq = "";
633#endif
634 if (fHMForced)
635 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x.%s\n", pszMinReq);
636
637 /* Fall back to raw-mode. */
638 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x.%s\n", pszMinReq));
639 pVM->fHMEnabled = false;
640 }
641 }
642 else
643 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
644 VERR_INTERNAL_ERROR_5);
645
646 /*
647 * Do we require a little bit or raw-mode for 64-bit guest execution?
648 */
649 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
650 && pVM->fHMEnabled
651 && pVM->hm.s.fAllow64BitGuests;
652
653 /*
654 * Disable nested paging and unrestricted guest execution now if they're
655 * configured so that CPUM can make decisions based on our configuration.
656 */
657 Assert(!pVM->hm.s.fNestedPaging);
658 if (pVM->hm.s.fAllowNestedPaging)
659 {
660 if (fCaps & SUPVTCAPS_NESTED_PAGING)
661 pVM->hm.s.fNestedPaging = true;
662 else
663 pVM->hm.s.fAllowNestedPaging = false;
664 }
665
666 if (fCaps & SUPVTCAPS_VT_X)
667 {
668 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
669 if (pVM->hm.s.vmx.fAllowUnrestricted)
670 {
671 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
672 && pVM->hm.s.fNestedPaging)
673 pVM->hm.s.vmx.fUnrestrictedGuest = true;
674 else
675 pVM->hm.s.vmx.fAllowUnrestricted = false;
676 }
677 }
678 }
679 else
680 {
681 const char *pszMsg;
682 switch (rc)
683 {
684 case VERR_UNSUPPORTED_CPU:
685 pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained";
686 break;
687
688 case VERR_VMX_NO_VMX:
689 pszMsg = "VT-x is not available";
690 break;
691
692 case VERR_VMX_MSR_VMX_DISABLED:
693 pszMsg = "VT-x is disabled in the BIOS";
694 break;
695
696 case VERR_VMX_MSR_ALL_VMX_DISABLED:
697 pszMsg = "VT-x is disabled in the BIOS for all CPU modes";
698 break;
699
700 case VERR_VMX_MSR_LOCKING_FAILED:
701 pszMsg = "Failed to enable and lock VT-x features";
702 break;
703
704 case VERR_SVM_NO_SVM:
705 pszMsg = "AMD-V is not available";
706 break;
707
708 case VERR_SVM_DISABLED:
709 pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)";
710 break;
711
712 default:
713 pszMsg = NULL;
714 break;
715 }
716 if (fHMForced && pszMsg)
717 return VM_SET_ERROR(pVM, rc, pszMsg);
718 if (!pszMsg)
719 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
720
721 /* Fall back to raw-mode. */
722 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
723 pVM->fHMEnabled = false;
724 }
725 }
726
727 /* It's now OK to use the predicate function. */
728 pVM->fHMEnabledFixed = true;
729 return VINF_SUCCESS;
730}
731
732
733/**
734 * Initializes the per-VCPU HM.
735 *
736 * @returns VBox status code.
737 * @param pVM The cross context VM structure.
738 */
739static int hmR3InitCPU(PVM pVM)
740{
741 LogFlow(("HMR3InitCPU\n"));
742
743 if (!HMIsEnabled(pVM))
744 return VINF_SUCCESS;
745
746 for (VMCPUID i = 0; i < pVM->cCpus; i++)
747 {
748 PVMCPU pVCpu = &pVM->aCpus[i];
749 pVCpu->hm.s.fActive = false;
750 }
751
752#ifdef VBOX_WITH_STATISTICS
753 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
754 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
755 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
756 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
757 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
758#endif
759
760 /*
761 * Statistics.
762 */
763 for (VMCPUID i = 0; i < pVM->cCpus; i++)
764 {
765 PVMCPU pVCpu = &pVM->aCpus[i];
766 int rc;
767
768#ifdef VBOX_WITH_STATISTICS
769 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
770 "Profiling of RTMpPokeCpu",
771 "/PROF/CPU%d/HM/Poke", i);
772 AssertRC(rc);
773 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
774 "Profiling of poke wait",
775 "/PROF/CPU%d/HM/PokeWait", i);
776 AssertRC(rc);
777 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
778 "Profiling of poke wait when RTMpPokeCpu fails",
779 "/PROF/CPU%d/HM/PokeWaitFailed", i);
780 AssertRC(rc);
781 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
782 "Profiling of VMXR0RunGuestCode entry",
783 "/PROF/CPU%d/HM/StatEntry", i);
784 AssertRC(rc);
785 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
786 "Profiling of VMXR0RunGuestCode exit part 1",
787 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
788 AssertRC(rc);
789 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
790 "Profiling of VMXR0RunGuestCode exit part 2",
791 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
792 AssertRC(rc);
793
794 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
795 "I/O",
796 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
797 AssertRC(rc);
798 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
799 "MOV CRx",
800 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
801 AssertRC(rc);
802 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
803 "Exceptions, NMIs",
804 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
805 AssertRC(rc);
806
807 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
808 "Profiling of VMXR0LoadGuestState",
809 "/PROF/CPU%d/HM/StatLoadGuestState", i);
810 AssertRC(rc);
811 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
812 "Profiling of VMLAUNCH/VMRESUME.",
813 "/PROF/CPU%d/HM/InGC", i);
814 AssertRC(rc);
815
816# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
817 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
818 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
819 "/PROF/CPU%d/HM/Switcher3264", i);
820 AssertRC(rc);
821# endif
822
823# ifdef HM_PROFILE_EXIT_DISPATCH
824 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
825 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
826 "/PROF/CPU%d/HM/ExitDispatch", i);
827 AssertRC(rc);
828# endif
829
830#endif
831# define HM_REG_COUNTER(a, b, desc) \
832 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
833 AssertRC(rc);
834
835#ifdef VBOX_WITH_STATISTICS
836 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
837 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
838 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
839 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
840 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
841 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
842 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
843 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
844 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
845 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
846 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
847 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
848 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
849 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
850 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
851 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
852 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
853 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
854 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
855 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
856 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
857 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
858 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
859 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
860 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
861 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
862 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
863 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
864 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
865 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
866 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
867 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
868 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
869 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
870 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
871 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
872 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
873 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
874 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
875 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
876 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
877 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
878 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
879 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
880 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
881 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
882 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
883#endif
884 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
885#ifdef VBOX_WITH_STATISTICS
886 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
887 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
888 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
889 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
890 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
891
892 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
893 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
894 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
895 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
896 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
897 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
898 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
899 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
900 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
901#endif
902 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
903#ifdef VBOX_WITH_STATISTICS
904 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
905
906 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
907 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
908 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
909 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
910
911 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
912 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
913 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
914 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
915 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
916 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
917 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
918 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
919 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
920 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
921 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
922 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
923 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
924 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
925
926 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
927 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
928 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
929
930 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
931 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
932 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
933
934 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
935 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
936
937 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
938 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
939 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
940 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
941 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
942 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
943 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
944 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
945
946#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
947 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
948 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
949#endif
950
951 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
952 {
953 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
954 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
955 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
956 AssertRC(rc);
957 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
958 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
959 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
960 AssertRC(rc);
961 }
962
963#undef HM_REG_COUNTER
964
965 pVCpu->hm.s.paStatExitReason = NULL;
966
967 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
968 (void **)&pVCpu->hm.s.paStatExitReason);
969 AssertRC(rc);
970 if (RT_SUCCESS(rc))
971 {
972 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ?
973 &g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
974 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
975 {
976 if (papszDesc[j])
977 {
978 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
979 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
980 AssertRC(rc);
981 }
982 }
983 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
984 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
985 AssertRC(rc);
986 }
987 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
988# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
989 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
990# else
991 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
992# endif
993
994 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
995 AssertRCReturn(rc, rc);
996 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
997# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
998 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
999# else
1000 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1001# endif
1002 for (unsigned j = 0; j < 255; j++)
1003 {
1004 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1005 "Injected event.",
1006 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1007 }
1008
1009#endif /* VBOX_WITH_STATISTICS */
1010 }
1011
1012#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1013 /*
1014 * Magic marker for searching in crash dumps.
1015 */
1016 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1017 {
1018 PVMCPU pVCpu = &pVM->aCpus[i];
1019
1020 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1021 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1022 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1023 }
1024#endif
1025
1026 return VINF_SUCCESS;
1027}
1028
1029
1030/**
1031 * Called when a init phase has completed.
1032 *
1033 * @returns VBox status code.
1034 * @param pVM The cross context VM structure.
1035 * @param enmWhat The phase that completed.
1036 */
1037VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1038{
1039 switch (enmWhat)
1040 {
1041 case VMINITCOMPLETED_RING3:
1042 return hmR3InitCPU(pVM);
1043 case VMINITCOMPLETED_RING0:
1044 return hmR3InitFinalizeR0(pVM);
1045 default:
1046 return VINF_SUCCESS;
1047 }
1048}
1049
1050
1051/**
1052 * Turns off normal raw mode features.
1053 *
1054 * @param pVM The cross context VM structure.
1055 */
1056static void hmR3DisableRawMode(PVM pVM)
1057{
1058 /* Reinit the paging mode to force the new shadow mode. */
1059 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1060 {
1061 PVMCPU pVCpu = &pVM->aCpus[i];
1062
1063 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1064 }
1065}
1066
1067
1068/**
1069 * Initialize VT-x or AMD-V.
1070 *
1071 * @returns VBox status code.
1072 * @param pVM The cross context VM structure.
1073 */
1074static int hmR3InitFinalizeR0(PVM pVM)
1075{
1076 int rc;
1077
1078 if (!HMIsEnabled(pVM))
1079 return VINF_SUCCESS;
1080
1081 /*
1082 * Hack to allow users to work around broken BIOSes that incorrectly set
1083 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1084 */
1085 if ( !pVM->hm.s.vmx.fSupported
1086 && !pVM->hm.s.svm.fSupported
1087 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
1088 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1089 {
1090 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1091 pVM->hm.s.svm.fSupported = true;
1092 pVM->hm.s.svm.fIgnoreInUseError = true;
1093 pVM->hm.s.lLastError = VINF_SUCCESS;
1094 }
1095
1096 /*
1097 * Report ring-0 init errors.
1098 */
1099 if ( !pVM->hm.s.vmx.fSupported
1100 && !pVM->hm.s.svm.fSupported)
1101 {
1102 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
1103 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1104 switch (pVM->hm.s.lLastError)
1105 {
1106 case VERR_VMX_IN_VMX_ROOT_MODE:
1107 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1108 case VERR_VMX_NO_VMX:
1109 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1110 case VERR_VMX_MSR_VMX_DISABLED:
1111 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1112 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1113 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1114 case VERR_VMX_MSR_LOCKING_FAILED:
1115 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1116 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1117 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1118 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1119 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1120
1121 case VERR_SVM_IN_USE:
1122 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1123 case VERR_SVM_NO_SVM:
1124 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1125 case VERR_SVM_DISABLED:
1126 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1127 }
1128 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
1129 }
1130
1131 /*
1132 * Enable VT-x or AMD-V on all host CPUs.
1133 */
1134 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1135 if (RT_FAILURE(rc))
1136 {
1137 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1138 HMR3CheckError(pVM, rc);
1139 return rc;
1140 }
1141
1142 /*
1143 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1144 * (Main should have taken care of this already)
1145 */
1146 if (!PDMHasIoApic(pVM))
1147 {
1148 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1149 pVM->hm.s.fTprPatchingAllowed = false;
1150 }
1151
1152 /*
1153 * Do the vendor specific initialization .
1154 * .
1155 * Note! We disable release log buffering here since we're doing relatively .
1156 * lot of logging and doesn't want to hit the disk with each LogRel .
1157 * statement.
1158 */
1159 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1160 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1161 if (pVM->hm.s.vmx.fSupported)
1162 rc = hmR3InitFinalizeR0Intel(pVM);
1163 else
1164 rc = hmR3InitFinalizeR0Amd(pVM);
1165 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1166 RTLogRelSetBuffering(fOldBuffered);
1167 pVM->hm.s.fInitialized = true;
1168
1169 return rc;
1170}
1171
1172
1173/**
1174 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1175 */
1176static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1177{
1178 NOREF(pVM);
1179 NOREF(pvAllocation);
1180 NOREF(GCPhysAllocation);
1181}
1182
1183
1184/**
1185 * Finish VT-x initialization (after ring-0 init).
1186 *
1187 * @returns VBox status code.
1188 * @param pVM The cross context VM structure.
1189 */
1190static int hmR3InitFinalizeR0Intel(PVM pVM)
1191{
1192 int rc;
1193
1194 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1195 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1196
1197 uint64_t val;
1198 uint64_t zap;
1199
1200 LogRel(("HM: Using VT-x implementation 2.0\n"));
1201 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1202 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1203 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1204 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1205 if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1206 LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1207 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1208 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1209 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1210 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1211 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1212 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1213 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1214 LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1215 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1216
1217 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1218 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1219 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1220 HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1221 HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1222 HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1223 HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1224 HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1225
1226 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1227 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1228 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1229 HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1230 HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1231 HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1232 HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1233 HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1234 HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1235 HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1236 HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1237 HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1238 HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1239 HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1240 HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1241 HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1242 HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1243 HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1244 HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1245 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1246 HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1247 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1248 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1249 HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1250 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1251 {
1252 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1253 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1254 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1255 HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1256 HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1257 HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1258 HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1259 HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1260 HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1261 HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1262 HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1263 HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1264 HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1265 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1266 HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1267 HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1268 HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1269 HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1270 HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1271 HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1272 HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1273 HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1274 HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1275 HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1276 HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1277 }
1278
1279 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1280 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1281 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1282 HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1283 HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1284 HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1285 HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1286 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1287 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1288 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1289
1290 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1291 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1292 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1293 HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1294 HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1295 HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1296 HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1297 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1298 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1299 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1300 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1301 HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1302
1303 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1304 {
1305 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1306 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1307 HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1308 HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1309 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1310 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1311 HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1312 HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1313 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1314 HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1315 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1316 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1317 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1318 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1319 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1320 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1321 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1322 }
1323
1324 val = pVM->hm.s.vmx.Msrs.u64Misc;
1325 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1326 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1327 LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1328 else
1329 {
1330 LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1331 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1332 }
1333
1334 LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1335 LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1336 LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1337 LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1338 LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1339 LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1340 LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1341 LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1342
1343 /* Paranoia */
1344 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1345
1346 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1347 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1348 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1349 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1350
1351 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1352 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1353 LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1354
1355 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1356 if (val)
1357 {
1358 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
1359 HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1360 }
1361
1362 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1363
1364 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1365 {
1366 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1367 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1368 }
1369
1370 /*
1371 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1372 */
1373 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1374 || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1375 VERR_HM_IPE_1);
1376 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1377 || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1378 && pVM->hm.s.fNestedPaging),
1379 VERR_HM_IPE_1);
1380
1381 /*
1382 * Enable VPID if configured and supported.
1383 */
1384 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1385 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1386
1387#if 0
1388 /*
1389 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1390 */
1391 if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1392 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1393 pVM->hm.s.fVirtApicRegs = true;
1394
1395 /*
1396 * Enable posted-interrupt processing if supported.
1397 */
1398 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1399 * here. */
1400 if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1401 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1402 pVM->hm.s.fPostedIntrs = true;
1403#endif
1404
1405 /*
1406 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1407 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1408 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1409 */
1410 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1411 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1412 {
1413 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1414 LogRel(("HM: Disabled RDTSCP\n"));
1415 }
1416
1417 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1418 {
1419 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1420 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1421 if (RT_SUCCESS(rc))
1422 {
1423 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1424 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1425 esp. Figure 20-5.*/
1426 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1427 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1428
1429 /* Bit set to 0 means software interrupts are redirected to the
1430 8086 program interrupt handler rather than switching to
1431 protected-mode handler. */
1432 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1433
1434 /* Allow all port IO, so that port IO instructions do not cause
1435 exceptions and would instead cause a VM-exit (based on VT-x's
1436 IO bitmap which we currently configure to always cause an exit). */
1437 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1438 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1439
1440 /*
1441 * Construct a 1024 element page directory with 4 MB pages for
1442 * the identity mapped page table used in real and protected mode
1443 * without paging with EPT.
1444 */
1445 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1446 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1447 {
1448 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1449 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1450 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1451 | X86_PDE4M_G;
1452 }
1453
1454 /* We convert it here every time as PCI regions could be reconfigured. */
1455 if (PDMVmmDevHeapIsEnabled(pVM))
1456 {
1457 RTGCPHYS GCPhys;
1458 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1459 AssertRCReturn(rc, rc);
1460 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1461
1462 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1463 AssertRCReturn(rc, rc);
1464 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1465 }
1466 }
1467 else
1468 {
1469 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1470 pVM->hm.s.vmx.pRealModeTSS = NULL;
1471 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1472 return VMSetError(pVM, rc, RT_SRC_POS,
1473 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1474 }
1475 }
1476
1477 LogRel((pVM->hm.s.fAllow64BitGuests
1478 ? "HM: Guest support: 32-bit and 64-bit\n"
1479 : "HM: Guest support: 32-bit only\n"));
1480
1481 /*
1482 * Call ring-0 to set up the VM.
1483 */
1484 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1485 if (rc != VINF_SUCCESS)
1486 {
1487 AssertMsgFailed(("%Rrc\n", rc));
1488 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1489 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1490 {
1491 PVMCPU pVCpu = &pVM->aCpus[i];
1492 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1493 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1494 }
1495 HMR3CheckError(pVM, rc);
1496 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1497 }
1498
1499 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1500 LogRel(("HM: Enabled VMX\n"));
1501 pVM->hm.s.vmx.fEnabled = true;
1502
1503 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1504
1505 /*
1506 * Change the CPU features.
1507 */
1508 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1509 if (pVM->hm.s.fAllow64BitGuests)
1510 {
1511 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1512 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1513 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1514 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1515 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1516 }
1517 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1518 (we reuse the host EFER in the switcher). */
1519 /** @todo this needs to be fixed properly!! */
1520 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1521 {
1522 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1523 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1524 else
1525 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1526 }
1527
1528 /*
1529 * Log configuration details.
1530 */
1531 if (pVM->hm.s.fNestedPaging)
1532 {
1533 LogRel(("HM: Enabled nested paging\n"));
1534 if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1535 LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1536 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1537 LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1538 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1539 LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1540 else
1541 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1542
1543 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1544 LogRel(("HM: Enabled unrestricted guest execution\n"));
1545
1546#if HC_ARCH_BITS == 64
1547 if (pVM->hm.s.fLargePages)
1548 {
1549 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1550 PGMSetLargePageUsage(pVM, true);
1551 LogRel(("HM: Enabled large page support\n"));
1552 }
1553#endif
1554 }
1555 else
1556 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1557
1558 if (pVM->hm.s.fVirtApicRegs)
1559 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1560
1561 if (pVM->hm.s.fPostedIntrs)
1562 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1563
1564 if (pVM->hm.s.vmx.fVpid)
1565 {
1566 LogRel(("HM: Enabled VPID\n"));
1567 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1568 LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1569 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1570 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1571 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1572 LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1573 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1574 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1575 else
1576 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1577 }
1578 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1579 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1580
1581 if (pVM->hm.s.vmx.fUsePreemptTimer)
1582 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1583 else
1584 LogRel(("HM: Disabled VMX-preemption timer\n"));
1585
1586 return VINF_SUCCESS;
1587}
1588
1589
1590/**
1591 * Finish AMD-V initialization (after ring-0 init).
1592 *
1593 * @returns VBox status code.
1594 * @param pVM The cross context VM structure.
1595 */
1596static int hmR3InitFinalizeR0Amd(PVM pVM)
1597{
1598 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1599
1600 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1601
1602 uint32_t u32Family;
1603 uint32_t u32Model;
1604 uint32_t u32Stepping;
1605 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1606 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1607 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1608 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1609 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1610 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1611 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1612 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1613 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1614
1615 /*
1616 * Enumerate AMD-V features.
1617 */
1618 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1619 {
1620#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1621 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1622 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1623 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1624 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1625 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1626 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1627 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1628 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1629 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1630 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1631 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1632 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1633 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1634#undef HMSVM_REPORT_FEATURE
1635 };
1636
1637 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1638 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1639 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1640 {
1641 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1642 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1643 }
1644 if (fSvmFeatures)
1645 for (unsigned iBit = 0; iBit < 32; iBit++)
1646 if (RT_BIT_32(iBit) & fSvmFeatures)
1647 LogRel(("HM: Reserved bit %u\n", iBit));
1648
1649 /*
1650 * SVM R0 code assumes if the decode-assist feature exists, NRIP feature exists too.
1651 */
1652 AssertLogRelReturn( !(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
1653 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1654 VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
1655
1656 /*
1657 * Nested paging is determined in HMR3Init, verify the sanity of that.
1658 */
1659 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1660 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1661 VERR_HM_IPE_1);
1662
1663#if 0
1664 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1665 * here. */
1666 if (RTR0IsPostIpiSupport())
1667 pVM->hm.s.fPostedIntrs = true;
1668#endif
1669
1670 /*
1671 * Call ring-0 to set up the VM.
1672 */
1673 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1674 if (rc != VINF_SUCCESS)
1675 {
1676 AssertMsgFailed(("%Rrc\n", rc));
1677 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1678 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1679 }
1680
1681 LogRel(("HM: Enabled SVM\n"));
1682 pVM->hm.s.svm.fEnabled = true;
1683
1684 if (pVM->hm.s.fNestedPaging)
1685 {
1686 LogRel(("HM: Enabled nested paging\n"));
1687
1688 /*
1689 * Enable large pages (2 MB) if applicable.
1690 */
1691#if HC_ARCH_BITS == 64
1692 if (pVM->hm.s.fLargePages)
1693 {
1694 PGMSetLargePageUsage(pVM, true);
1695 LogRel(("HM: Enabled large page support\n"));
1696 }
1697#endif
1698 }
1699
1700 if (pVM->hm.s.fVirtApicRegs)
1701 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1702
1703 if (pVM->hm.s.fPostedIntrs)
1704 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1705
1706 hmR3DisableRawMode(pVM);
1707
1708 /*
1709 * Change the CPU features.
1710 */
1711 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1712 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1713 if (pVM->hm.s.fAllow64BitGuests)
1714 {
1715 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1716 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1717 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1718 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1719 }
1720 /* Turn on NXE if PAE has been enabled. */
1721 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1722 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1723
1724 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1725
1726 LogRel((pVM->hm.s.fAllow64BitGuests
1727 ? "HM: Guest support: 32-bit and 64-bit\n"
1728 : "HM: Guest support: 32-bit only\n"));
1729
1730 return VINF_SUCCESS;
1731}
1732
1733
1734/**
1735 * Applies relocations to data and code managed by this
1736 * component. This function will be called at init and
1737 * whenever the VMM need to relocate it self inside the GC.
1738 *
1739 * @param pVM The cross context VM structure.
1740 */
1741VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1742{
1743 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1744
1745 /* Fetch the current paging mode during the relocate callback during state loading. */
1746 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1747 {
1748 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1749 {
1750 PVMCPU pVCpu = &pVM->aCpus[i];
1751 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1752 }
1753 }
1754#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1755 if (HMIsEnabled(pVM))
1756 {
1757 switch (PGMGetHostMode(pVM))
1758 {
1759 case PGMMODE_32_BIT:
1760 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1761 break;
1762
1763 case PGMMODE_PAE:
1764 case PGMMODE_PAE_NX:
1765 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1766 break;
1767
1768 default:
1769 AssertFailed();
1770 break;
1771 }
1772 }
1773#endif
1774 return;
1775}
1776
1777
1778/**
1779 * Notification callback which is called whenever there is a chance that a CR3
1780 * value might have changed.
1781 *
1782 * This is called by PGM.
1783 *
1784 * @param pVM The cross context VM structure.
1785 * @param pVCpu The cross context virtual CPU structure.
1786 * @param enmShadowMode New shadow paging mode.
1787 * @param enmGuestMode New guest paging mode.
1788 */
1789VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1790{
1791 RT_NOREF_PV(pVM);
1792
1793 /* Ignore page mode changes during state loading. */
1794 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1795 return;
1796
1797 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1798
1799 /*
1800 * If the guest left protected mode VMX execution, we'll have to be
1801 * extra careful if/when the guest switches back to protected mode.
1802 */
1803 if (enmGuestMode == PGMMODE_REAL)
1804 pVCpu->hm.s.vmx.fWasInRealMode = true;
1805
1806 Log4(("HMR3PagingModeChanged: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
1807 PGMGetModeName(enmShadowMode)));
1808}
1809
1810
1811/**
1812 * Terminates the HM.
1813 *
1814 * Termination means cleaning up and freeing all resources,
1815 * the VM itself is, at this point, powered off or suspended.
1816 *
1817 * @returns VBox status code.
1818 * @param pVM The cross context VM structure.
1819 */
1820VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1821{
1822 if (pVM->hm.s.vmx.pRealModeTSS)
1823 {
1824 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1825 pVM->hm.s.vmx.pRealModeTSS = 0;
1826 }
1827 hmR3TermCPU(pVM);
1828 return 0;
1829}
1830
1831
1832/**
1833 * Terminates the per-VCPU HM.
1834 *
1835 * @returns VBox status code.
1836 * @param pVM The cross context VM structure.
1837 */
1838static int hmR3TermCPU(PVM pVM)
1839{
1840 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1841 {
1842 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1843
1844#ifdef VBOX_WITH_STATISTICS
1845 if (pVCpu->hm.s.paStatExitReason)
1846 {
1847 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1848 pVCpu->hm.s.paStatExitReason = NULL;
1849 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1850 }
1851 if (pVCpu->hm.s.paStatInjectedIrqs)
1852 {
1853 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1854 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1855 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1856 }
1857#endif
1858
1859#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1860 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1861 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1862 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1863#endif
1864 }
1865 return 0;
1866}
1867
1868
1869/**
1870 * Resets a virtual CPU.
1871 *
1872 * Used by HMR3Reset and CPU hot plugging.
1873 *
1874 * @param pVCpu The cross context virtual CPU structure to reset.
1875 */
1876VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1877{
1878 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
1879 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1880 HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
1881
1882 pVCpu->hm.s.vmx.u32CR0Mask = 0;
1883 pVCpu->hm.s.vmx.u32CR4Mask = 0;
1884 pVCpu->hm.s.fActive = false;
1885 pVCpu->hm.s.Event.fPending = false;
1886 pVCpu->hm.s.vmx.fWasInRealMode = true;
1887 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
1888 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
1889
1890 /* Reset the contents of the read cache. */
1891 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1892 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1893 pCache->Read.aFieldVal[j] = 0;
1894
1895#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1896 /* Magic marker for searching in crash dumps. */
1897 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1898 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1899#endif
1900}
1901
1902
1903/**
1904 * The VM is being reset.
1905 *
1906 * For the HM component this means that any GDT/LDT/TSS monitors
1907 * needs to be removed.
1908 *
1909 * @param pVM The cross context VM structure.
1910 */
1911VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
1912{
1913 LogFlow(("HMR3Reset:\n"));
1914
1915 if (HMIsEnabled(pVM))
1916 hmR3DisableRawMode(pVM);
1917
1918 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1919 {
1920 PVMCPU pVCpu = &pVM->aCpus[i];
1921
1922 HMR3ResetCpu(pVCpu);
1923 }
1924
1925 /* Clear all patch information. */
1926 pVM->hm.s.pGuestPatchMem = 0;
1927 pVM->hm.s.pFreeGuestPatchMem = 0;
1928 pVM->hm.s.cbGuestPatchMem = 0;
1929 pVM->hm.s.cPatches = 0;
1930 pVM->hm.s.PatchTree = 0;
1931 pVM->hm.s.fTPRPatchingActive = false;
1932 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
1933}
1934
1935
1936/**
1937 * Callback to patch a TPR instruction (vmmcall or mov cr8).
1938 *
1939 * @returns VBox strict status code.
1940 * @param pVM The cross context VM structure.
1941 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
1942 * @param pvUser Unused.
1943 */
1944static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
1945{
1946 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
1947
1948 /* Only execute the handler on the VCPU the original patch request was issued. */
1949 if (pVCpu->idCpu != idCpu)
1950 return VINF_SUCCESS;
1951
1952 Log(("hmR3RemovePatches\n"));
1953 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
1954 {
1955 uint8_t abInstr[15];
1956 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
1957 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
1958 int rc;
1959
1960#ifdef LOG_ENABLED
1961 char szOutput[256];
1962
1963 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1964 szOutput, sizeof(szOutput), NULL);
1965 if (RT_SUCCESS(rc))
1966 Log(("Patched instr: %s\n", szOutput));
1967#endif
1968
1969 /* Check if the instruction is still the same. */
1970 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
1971 if (rc != VINF_SUCCESS)
1972 {
1973 Log(("Patched code removed? (rc=%Rrc0\n", rc));
1974 continue; /* swapped out or otherwise removed; skip it. */
1975 }
1976
1977 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
1978 {
1979 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
1980 continue; /* skip it. */
1981 }
1982
1983 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
1984 AssertRC(rc);
1985
1986#ifdef LOG_ENABLED
1987 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
1988 szOutput, sizeof(szOutput), NULL);
1989 if (RT_SUCCESS(rc))
1990 Log(("Original instr: %s\n", szOutput));
1991#endif
1992 }
1993 pVM->hm.s.cPatches = 0;
1994 pVM->hm.s.PatchTree = 0;
1995 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
1996 pVM->hm.s.fTPRPatchingActive = false;
1997 return VINF_SUCCESS;
1998}
1999
2000
2001/**
2002 * Worker for enabling patching in a VT-x/AMD-V guest.
2003 *
2004 * @returns VBox status code.
2005 * @param pVM The cross context VM structure.
2006 * @param idCpu VCPU to execute hmR3RemovePatches on.
2007 * @param pPatchMem Patch memory range.
2008 * @param cbPatchMem Size of the memory range.
2009 */
2010static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2011{
2012 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2013 AssertRC(rc);
2014
2015 pVM->hm.s.pGuestPatchMem = pPatchMem;
2016 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2017 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2018 return VINF_SUCCESS;
2019}
2020
2021
2022/**
2023 * Enable patching in a VT-x/AMD-V guest
2024 *
2025 * @returns VBox status code.
2026 * @param pVM The cross context VM structure.
2027 * @param pPatchMem Patch memory range.
2028 * @param cbPatchMem Size of the memory range.
2029 */
2030VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2031{
2032 VM_ASSERT_EMT(pVM);
2033 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2034 if (pVM->cCpus > 1)
2035 {
2036 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2037 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2038 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2039 AssertRC(rc);
2040 return rc;
2041 }
2042 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2043}
2044
2045
2046/**
2047 * Disable patching in a VT-x/AMD-V guest.
2048 *
2049 * @returns VBox status code.
2050 * @param pVM The cross context VM structure.
2051 * @param pPatchMem Patch memory range.
2052 * @param cbPatchMem Size of the memory range.
2053 */
2054VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2055{
2056 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2057 RT_NOREF2(pPatchMem, cbPatchMem);
2058
2059 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2060 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2061
2062 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2063 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2064 (void *)(uintptr_t)VMMGetCpuId(pVM));
2065 AssertRC(rc);
2066
2067 pVM->hm.s.pGuestPatchMem = 0;
2068 pVM->hm.s.pFreeGuestPatchMem = 0;
2069 pVM->hm.s.cbGuestPatchMem = 0;
2070 pVM->hm.s.fTPRPatchingActive = false;
2071 return VINF_SUCCESS;
2072}
2073
2074
2075/**
2076 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2077 *
2078 * @returns VBox strict status code.
2079 * @param pVM The cross context VM structure.
2080 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2081 * @param pvUser User specified CPU context.
2082 *
2083 */
2084static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2085{
2086 /*
2087 * Only execute the handler on the VCPU the original patch request was
2088 * issued. (The other CPU(s) might not yet have switched to protected
2089 * mode, nor have the correct memory context.)
2090 */
2091 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2092 if (pVCpu->idCpu != idCpu)
2093 return VINF_SUCCESS;
2094
2095 /*
2096 * We're racing other VCPUs here, so don't try patch the instruction twice
2097 * and make sure there is still room for our patch record.
2098 */
2099 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2100 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2101 if (pPatch)
2102 {
2103 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2104 return VINF_SUCCESS;
2105 }
2106 uint32_t const idx = pVM->hm.s.cPatches;
2107 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2108 {
2109 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2110 return VINF_SUCCESS;
2111 }
2112 pPatch = &pVM->hm.s.aPatches[idx];
2113
2114 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2115
2116 /*
2117 * Disassembler the instruction and get cracking.
2118 */
2119 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2120 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2121 uint32_t cbOp;
2122 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2123 AssertRC(rc);
2124 if ( rc == VINF_SUCCESS
2125 && pDis->pCurInstr->uOpcode == OP_MOV
2126 && cbOp >= 3)
2127 {
2128 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2129
2130 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2131 AssertRC(rc);
2132
2133 pPatch->cbOp = cbOp;
2134
2135 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2136 {
2137 /* write. */
2138 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2139 {
2140 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2141 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2142 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2143 }
2144 else
2145 {
2146 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2147 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2148 pPatch->uSrcOperand = pDis->Param2.uValue;
2149 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2150 }
2151 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2152 AssertRC(rc);
2153
2154 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2155 pPatch->cbNewOp = sizeof(s_abVMMCall);
2156 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2157 }
2158 else
2159 {
2160 /*
2161 * TPR Read.
2162 *
2163 * Found:
2164 * mov eax, dword [fffe0080] (5 bytes)
2165 * Check if next instruction is:
2166 * shr eax, 4
2167 */
2168 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2169
2170 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2171 uint8_t const cbOpMmio = cbOp;
2172 uint64_t const uSavedRip = pCtx->rip;
2173
2174 pCtx->rip += cbOp;
2175 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2176 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2177 pCtx->rip = uSavedRip;
2178
2179 if ( rc == VINF_SUCCESS
2180 && pDis->pCurInstr->uOpcode == OP_SHR
2181 && pDis->Param1.fUse == DISUSE_REG_GEN32
2182 && pDis->Param1.Base.idxGenReg == idxMmioReg
2183 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2184 && pDis->Param2.uValue == 4
2185 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2186 {
2187 uint8_t abInstr[15];
2188
2189 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2190 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2191 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2192 AssertRC(rc);
2193
2194 pPatch->cbOp = cbOpMmio + cbOp;
2195
2196 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2197 abInstr[0] = 0xF0;
2198 abInstr[1] = 0x0F;
2199 abInstr[2] = 0x20;
2200 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2201 for (unsigned i = 4; i < pPatch->cbOp; i++)
2202 abInstr[i] = 0x90; /* nop */
2203
2204 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2205 AssertRC(rc);
2206
2207 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2208 pPatch->cbNewOp = pPatch->cbOp;
2209 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2210
2211 Log(("Acceptable read/shr candidate!\n"));
2212 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2213 }
2214 else
2215 {
2216 pPatch->enmType = HMTPRINSTR_READ;
2217 pPatch->uDstOperand = idxMmioReg;
2218
2219 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2220 AssertRC(rc);
2221
2222 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2223 pPatch->cbNewOp = sizeof(s_abVMMCall);
2224 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2225 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2226 }
2227 }
2228
2229 pPatch->Core.Key = pCtx->eip;
2230 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2231 AssertRC(rc);
2232
2233 pVM->hm.s.cPatches++;
2234 return VINF_SUCCESS;
2235 }
2236
2237 /*
2238 * Save invalid patch, so we will not try again.
2239 */
2240 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2241 pPatch->Core.Key = pCtx->eip;
2242 pPatch->enmType = HMTPRINSTR_INVALID;
2243 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2244 AssertRC(rc);
2245 pVM->hm.s.cPatches++;
2246 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2247 return VINF_SUCCESS;
2248}
2249
2250
2251/**
2252 * Callback to patch a TPR instruction (jump to generated code).
2253 *
2254 * @returns VBox strict status code.
2255 * @param pVM The cross context VM structure.
2256 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2257 * @param pvUser User specified CPU context.
2258 *
2259 */
2260static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2261{
2262 /*
2263 * Only execute the handler on the VCPU the original patch request was
2264 * issued. (The other CPU(s) might not yet have switched to protected
2265 * mode, nor have the correct memory context.)
2266 */
2267 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2268 if (pVCpu->idCpu != idCpu)
2269 return VINF_SUCCESS;
2270
2271 /*
2272 * We're racing other VCPUs here, so don't try patch the instruction twice
2273 * and make sure there is still room for our patch record.
2274 */
2275 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2276 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2277 if (pPatch)
2278 {
2279 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2280 return VINF_SUCCESS;
2281 }
2282 uint32_t const idx = pVM->hm.s.cPatches;
2283 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2284 {
2285 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2286 return VINF_SUCCESS;
2287 }
2288 pPatch = &pVM->hm.s.aPatches[idx];
2289
2290 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2291 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2292
2293 /*
2294 * Disassemble the instruction and get cracking.
2295 */
2296 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2297 uint32_t cbOp;
2298 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2299 AssertRC(rc);
2300 if ( rc == VINF_SUCCESS
2301 && pDis->pCurInstr->uOpcode == OP_MOV
2302 && cbOp >= 5)
2303 {
2304 uint8_t aPatch[64];
2305 uint32_t off = 0;
2306
2307 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2308 AssertRC(rc);
2309
2310 pPatch->cbOp = cbOp;
2311 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2312
2313 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2314 {
2315 /*
2316 * TPR write:
2317 *
2318 * push ECX [51]
2319 * push EDX [52]
2320 * push EAX [50]
2321 * xor EDX,EDX [31 D2]
2322 * mov EAX,EAX [89 C0]
2323 * or
2324 * mov EAX,0000000CCh [B8 CC 00 00 00]
2325 * mov ECX,0C0000082h [B9 82 00 00 C0]
2326 * wrmsr [0F 30]
2327 * pop EAX [58]
2328 * pop EDX [5A]
2329 * pop ECX [59]
2330 * jmp return_address [E9 return_address]
2331 *
2332 */
2333 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2334
2335 aPatch[off++] = 0x51; /* push ecx */
2336 aPatch[off++] = 0x52; /* push edx */
2337 if (!fUsesEax)
2338 aPatch[off++] = 0x50; /* push eax */
2339 aPatch[off++] = 0x31; /* xor edx, edx */
2340 aPatch[off++] = 0xD2;
2341 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2342 {
2343 if (!fUsesEax)
2344 {
2345 aPatch[off++] = 0x89; /* mov eax, src_reg */
2346 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2347 }
2348 }
2349 else
2350 {
2351 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2352 aPatch[off++] = 0xB8; /* mov eax, immediate */
2353 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2354 off += sizeof(uint32_t);
2355 }
2356 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2357 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2358 off += sizeof(uint32_t);
2359
2360 aPatch[off++] = 0x0F; /* wrmsr */
2361 aPatch[off++] = 0x30;
2362 if (!fUsesEax)
2363 aPatch[off++] = 0x58; /* pop eax */
2364 aPatch[off++] = 0x5A; /* pop edx */
2365 aPatch[off++] = 0x59; /* pop ecx */
2366 }
2367 else
2368 {
2369 /*
2370 * TPR read:
2371 *
2372 * push ECX [51]
2373 * push EDX [52]
2374 * push EAX [50]
2375 * mov ECX,0C0000082h [B9 82 00 00 C0]
2376 * rdmsr [0F 32]
2377 * mov EAX,EAX [89 C0]
2378 * pop EAX [58]
2379 * pop EDX [5A]
2380 * pop ECX [59]
2381 * jmp return_address [E9 return_address]
2382 *
2383 */
2384 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2385
2386 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2387 aPatch[off++] = 0x51; /* push ecx */
2388 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2389 aPatch[off++] = 0x52; /* push edx */
2390 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2391 aPatch[off++] = 0x50; /* push eax */
2392
2393 aPatch[off++] = 0x31; /* xor edx, edx */
2394 aPatch[off++] = 0xD2;
2395
2396 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2397 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2398 off += sizeof(uint32_t);
2399
2400 aPatch[off++] = 0x0F; /* rdmsr */
2401 aPatch[off++] = 0x32;
2402
2403 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2404 {
2405 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2406 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2407 }
2408
2409 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2410 aPatch[off++] = 0x58; /* pop eax */
2411 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2412 aPatch[off++] = 0x5A; /* pop edx */
2413 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2414 aPatch[off++] = 0x59; /* pop ecx */
2415 }
2416 aPatch[off++] = 0xE9; /* jmp return_address */
2417 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2418 off += sizeof(RTRCUINTPTR);
2419
2420 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2421 {
2422 /* Write new code to the patch buffer. */
2423 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2424 AssertRC(rc);
2425
2426#ifdef LOG_ENABLED
2427 uint32_t cbCurInstr;
2428 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2429 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2430 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2431 {
2432 char szOutput[256];
2433 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2434 szOutput, sizeof(szOutput), &cbCurInstr);
2435 if (RT_SUCCESS(rc))
2436 Log(("Patch instr %s\n", szOutput));
2437 else
2438 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2439 }
2440#endif
2441
2442 pPatch->aNewOpcode[0] = 0xE9;
2443 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2444
2445 /* Overwrite the TPR instruction with a jump. */
2446 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2447 AssertRC(rc);
2448
2449 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2450
2451 pVM->hm.s.pFreeGuestPatchMem += off;
2452 pPatch->cbNewOp = 5;
2453
2454 pPatch->Core.Key = pCtx->eip;
2455 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2456 AssertRC(rc);
2457
2458 pVM->hm.s.cPatches++;
2459 pVM->hm.s.fTPRPatchingActive = true;
2460 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2461 return VINF_SUCCESS;
2462 }
2463
2464 Log(("Ran out of space in our patch buffer!\n"));
2465 }
2466 else
2467 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2468
2469
2470 /*
2471 * Save invalid patch, so we will not try again.
2472 */
2473 pPatch = &pVM->hm.s.aPatches[idx];
2474 pPatch->Core.Key = pCtx->eip;
2475 pPatch->enmType = HMTPRINSTR_INVALID;
2476 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2477 AssertRC(rc);
2478 pVM->hm.s.cPatches++;
2479 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2480 return VINF_SUCCESS;
2481}
2482
2483
2484/**
2485 * Attempt to patch TPR mmio instructions.
2486 *
2487 * @returns VBox status code.
2488 * @param pVM The cross context VM structure.
2489 * @param pVCpu The cross context virtual CPU structure.
2490 * @param pCtx Pointer to the guest CPU context.
2491 */
2492VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2493{
2494 NOREF(pCtx);
2495 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2496 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2497 (void *)(uintptr_t)pVCpu->idCpu);
2498 AssertRC(rc);
2499 return rc;
2500}
2501
2502
2503/**
2504 * Checks if a code selector (CS) is suitable for execution
2505 * within VMX when unrestricted execution isn't available.
2506 *
2507 * @returns true if selector is suitable for VMX, otherwise
2508 * false.
2509 * @param pSel Pointer to the selector to check (CS).
2510 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2511 */
2512static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2513{
2514 /*
2515 * Segment must be an accessed code segment, it must be present and it must
2516 * be usable.
2517 * Note! These are all standard requirements and if CS holds anything else
2518 * we've got buggy code somewhere!
2519 */
2520 AssertCompile(X86DESCATTR_TYPE == 0xf);
2521 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2522 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2523 ("%#x\n", pSel->Attr.u),
2524 false);
2525
2526 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2527 must equal SS.DPL for non-confroming segments.
2528 Note! This is also a hard requirement like above. */
2529 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2530 ? pSel->Attr.n.u2Dpl <= uStackDpl
2531 : pSel->Attr.n.u2Dpl == uStackDpl,
2532 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2533 false);
2534
2535 /*
2536 * The following two requirements are VT-x specific:
2537 * - G bit must be set if any high limit bits are set.
2538 * - G bit must be clear if any low limit bits are clear.
2539 */
2540 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2541 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2542 return true;
2543 return false;
2544}
2545
2546
2547/**
2548 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2549 * execution within VMX when unrestricted execution isn't
2550 * available.
2551 *
2552 * @returns true if selector is suitable for VMX, otherwise
2553 * false.
2554 * @param pSel Pointer to the selector to check
2555 * (DS/ES/FS/GS).
2556 */
2557static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2558{
2559 /*
2560 * Unusable segments are OK. These days they should be marked as such, as
2561 * but as an alternative we for old saved states and AMD<->VT-x migration
2562 * we also treat segments with all the attributes cleared as unusable.
2563 */
2564 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2565 return true;
2566
2567 /** @todo tighten these checks. Will require CPUM load adjusting. */
2568
2569 /* Segment must be accessed. */
2570 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2571 {
2572 /* Code segments must also be readable. */
2573 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2574 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2575 {
2576 /* The S bit must be set. */
2577 if (pSel->Attr.n.u1DescType)
2578 {
2579 /* Except for conforming segments, DPL >= RPL. */
2580 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2581 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2582 {
2583 /* Segment must be present. */
2584 if (pSel->Attr.n.u1Present)
2585 {
2586 /*
2587 * The following two requirements are VT-x specific:
2588 * - G bit must be set if any high limit bits are set.
2589 * - G bit must be clear if any low limit bits are clear.
2590 */
2591 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2592 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2593 return true;
2594 }
2595 }
2596 }
2597 }
2598 }
2599
2600 return false;
2601}
2602
2603
2604/**
2605 * Checks if the stack selector (SS) is suitable for execution
2606 * within VMX when unrestricted execution isn't available.
2607 *
2608 * @returns true if selector is suitable for VMX, otherwise
2609 * false.
2610 * @param pSel Pointer to the selector to check (SS).
2611 */
2612static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2613{
2614 /*
2615 * Unusable segments are OK. These days they should be marked as such, as
2616 * but as an alternative we for old saved states and AMD<->VT-x migration
2617 * we also treat segments with all the attributes cleared as unusable.
2618 */
2619 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2620 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2621 return true;
2622
2623 /*
2624 * Segment must be an accessed writable segment, it must be present.
2625 * Note! These are all standard requirements and if SS holds anything else
2626 * we've got buggy code somewhere!
2627 */
2628 AssertCompile(X86DESCATTR_TYPE == 0xf);
2629 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2630 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2631 ("%#x\n", pSel->Attr.u),
2632 false);
2633
2634 /* DPL must equal RPL.
2635 Note! This is also a hard requirement like above. */
2636 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2637 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2638 false);
2639
2640 /*
2641 * The following two requirements are VT-x specific:
2642 * - G bit must be set if any high limit bits are set.
2643 * - G bit must be clear if any low limit bits are clear.
2644 */
2645 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2646 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2647 return true;
2648 return false;
2649}
2650
2651
2652/**
2653 * Force execution of the current IO code in the recompiler.
2654 *
2655 * @returns VBox status code.
2656 * @param pVM The cross context VM structure.
2657 * @param pCtx Partial VM execution context.
2658 */
2659VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2660{
2661 PVMCPU pVCpu = VMMGetCpu(pVM);
2662
2663 Assert(HMIsEnabled(pVM));
2664 Log(("HMR3EmulateIoBlock\n"));
2665
2666 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2667 if (HMCanEmulateIoBlockEx(pCtx))
2668 {
2669 Log(("HMR3EmulateIoBlock -> enabled\n"));
2670 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2671 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2672 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2673 return VINF_EM_RESCHEDULE_REM;
2674 }
2675 return VINF_SUCCESS;
2676}
2677
2678
2679/**
2680 * Checks if we can currently use hardware accelerated raw mode.
2681 *
2682 * @returns true if we can currently use hardware acceleration, otherwise false.
2683 * @param pVM The cross context VM structure.
2684 * @param pCtx Partial VM execution context.
2685 */
2686VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2687{
2688 PVMCPU pVCpu = VMMGetCpu(pVM);
2689
2690 Assert(HMIsEnabled(pVM));
2691
2692#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
2693 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
2694 {
2695 Log(("HMR3CanExecuteGuest: In nested-guest mode - returning false"));
2696 return false;
2697 }
2698#endif
2699
2700 /* If we're still executing the IO code, then return false. */
2701 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2702 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2703 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2704 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2705 return false;
2706
2707 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2708
2709 /* AMD-V supports real & protected mode with or without paging. */
2710 if (pVM->hm.s.svm.fEnabled)
2711 {
2712 pVCpu->hm.s.fActive = true;
2713 return true;
2714 }
2715
2716 pVCpu->hm.s.fActive = false;
2717
2718 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2719 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2720 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2721
2722 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2723 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2724 {
2725 /*
2726 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2727 * guest execution feature is missing (VT-x only).
2728 */
2729 if (fSupportsRealMode)
2730 {
2731 if (CPUMIsGuestInRealModeEx(pCtx))
2732 {
2733 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2734 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2735 * If this is not true, we cannot execute real mode as V86 and have to fall
2736 * back to emulation.
2737 */
2738 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2739 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2740 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2741 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2742 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2743 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2744 {
2745 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2746 return false;
2747 }
2748 if ( (pCtx->cs.u32Limit != 0xffff)
2749 || (pCtx->ds.u32Limit != 0xffff)
2750 || (pCtx->es.u32Limit != 0xffff)
2751 || (pCtx->ss.u32Limit != 0xffff)
2752 || (pCtx->fs.u32Limit != 0xffff)
2753 || (pCtx->gs.u32Limit != 0xffff))
2754 {
2755 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2756 return false;
2757 }
2758 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2759 }
2760 else
2761 {
2762 /* Verify the requirements for executing code in protected
2763 mode. VT-x can't handle the CPU state right after a switch
2764 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2765 if (pVCpu->hm.s.vmx.fWasInRealMode)
2766 {
2767 /** @todo If guest is in V86 mode, these checks should be different! */
2768 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2769 {
2770 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2771 return false;
2772 }
2773 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2774 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2775 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2776 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2777 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2778 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2779 {
2780 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2781 return false;
2782 }
2783 }
2784 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2785 if (pCtx->gdtr.cbGdt)
2786 {
2787 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2788 {
2789 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2790 return false;
2791 }
2792 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2793 {
2794 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2795 return false;
2796 }
2797 }
2798 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2799 }
2800 }
2801 else
2802 {
2803 if ( !CPUMIsGuestInLongModeEx(pCtx)
2804 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2805 {
2806 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2807 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2808 return false;
2809
2810 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2811 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2812 return false;
2813
2814 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2815 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2816 * hidden registers (possible recompiler bug; see load_seg_vm) */
2817 if (pCtx->cs.Attr.n.u1Present == 0)
2818 return false;
2819 if (pCtx->ss.Attr.n.u1Present == 0)
2820 return false;
2821
2822 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2823 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2824 /** @todo This check is actually wrong, it doesn't take the direction of the
2825 * stack segment into account. But, it does the job for now. */
2826 if (pCtx->rsp >= pCtx->ss.u32Limit)
2827 return false;
2828 }
2829 }
2830 }
2831
2832 if (pVM->hm.s.vmx.fEnabled)
2833 {
2834 uint32_t mask;
2835
2836 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2837 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2838 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2839 mask &= ~X86_CR0_NE;
2840
2841 if (fSupportsRealMode)
2842 {
2843 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2844 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2845 }
2846 else
2847 {
2848 /* We support protected mode without paging using identity mapping. */
2849 mask &= ~X86_CR0_PG;
2850 }
2851 if ((pCtx->cr0 & mask) != mask)
2852 return false;
2853
2854 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2855 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2856 if ((pCtx->cr0 & mask) != 0)
2857 return false;
2858
2859 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2860 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2861 mask &= ~X86_CR4_VMXE;
2862 if ((pCtx->cr4 & mask) != mask)
2863 return false;
2864
2865 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2866 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2867 if ((pCtx->cr4 & mask) != 0)
2868 return false;
2869
2870 pVCpu->hm.s.fActive = true;
2871 return true;
2872 }
2873
2874 return false;
2875}
2876
2877
2878/**
2879 * Checks if we need to reschedule due to VMM device heap changes.
2880 *
2881 * @returns true if a reschedule is required, otherwise false.
2882 * @param pVM The cross context VM structure.
2883 * @param pCtx VM execution context.
2884 */
2885VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2886{
2887 /*
2888 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2889 * when the unrestricted guest execution feature is missing (VT-x only).
2890 */
2891 if ( pVM->hm.s.vmx.fEnabled
2892 && !pVM->hm.s.vmx.fUnrestrictedGuest
2893 && CPUMIsGuestInRealModeEx(pCtx)
2894 && !PDMVmmDevHeapIsEnabled(pVM))
2895 {
2896 return true;
2897 }
2898
2899 return false;
2900}
2901
2902
2903/**
2904 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
2905 * event settings changes.
2906 *
2907 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
2908 * function is just updating the VM globals.
2909 *
2910 * @param pVM The VM cross context VM structure.
2911 * @thread EMT(0)
2912 */
2913VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
2914{
2915 /* Interrupts. */
2916 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
2917 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
2918
2919 /* CPU Exceptions. */
2920 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
2921 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
2922 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2923 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2924
2925 /* Common VM exits. */
2926 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
2927 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
2928 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2929 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2930
2931 /* Vendor specific VM exits. */
2932 if (HMR3IsVmxEnabled(pVM->pUVM))
2933 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
2934 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
2935 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2936 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2937 else
2938 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
2939 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
2940 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
2941 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
2942
2943 /* Done. */
2944 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
2945}
2946
2947
2948/**
2949 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
2950 *
2951 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
2952 * per CPU settings.
2953 *
2954 * @param pVM The VM cross context VM structure.
2955 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2956 */
2957VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
2958{
2959 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
2960}
2961
2962
2963/**
2964 * Notification from EM about a rescheduling into hardware assisted execution
2965 * mode.
2966 *
2967 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2968 */
2969VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
2970{
2971 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2972}
2973
2974
2975/**
2976 * Notification from EM about returning from instruction emulation (REM / EM).
2977 *
2978 * @param pVCpu The cross context virtual CPU structure.
2979 */
2980VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
2981{
2982 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
2983}
2984
2985
2986/**
2987 * Checks if we are currently using hardware acceleration.
2988 *
2989 * @returns true if hardware acceleration is being used, otherwise false.
2990 * @param pVCpu The cross context virtual CPU structure.
2991 */
2992VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
2993{
2994 return pVCpu->hm.s.fActive;
2995}
2996
2997
2998/**
2999 * External interface for querying whether hardware acceleration is enabled.
3000 *
3001 * @returns true if VT-x or AMD-V is being used, otherwise false.
3002 * @param pUVM The user mode VM handle.
3003 * @sa HMIsEnabled, HMIsEnabledNotMacro.
3004 */
3005VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
3006{
3007 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3008 PVM pVM = pUVM->pVM;
3009 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3010 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
3011}
3012
3013
3014/**
3015 * External interface for querying whether VT-x is being used.
3016 *
3017 * @returns true if VT-x is being used, otherwise false.
3018 * @param pUVM The user mode VM handle.
3019 * @sa HMR3IsSvmEnabled, HMIsEnabled
3020 */
3021VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
3022{
3023 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3024 PVM pVM = pUVM->pVM;
3025 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3026 return pVM->hm.s.vmx.fEnabled
3027 && pVM->hm.s.vmx.fSupported
3028 && pVM->fHMEnabled;
3029}
3030
3031
3032/**
3033 * External interface for querying whether AMD-V is being used.
3034 *
3035 * @returns true if VT-x is being used, otherwise false.
3036 * @param pUVM The user mode VM handle.
3037 * @sa HMR3IsVmxEnabled, HMIsEnabled
3038 */
3039VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3040{
3041 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3042 PVM pVM = pUVM->pVM;
3043 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3044 return pVM->hm.s.svm.fEnabled
3045 && pVM->hm.s.svm.fSupported
3046 && pVM->fHMEnabled;
3047}
3048
3049
3050/**
3051 * Checks if we are currently using nested paging.
3052 *
3053 * @returns true if nested paging is being used, otherwise false.
3054 * @param pUVM The user mode VM handle.
3055 */
3056VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3057{
3058 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3059 PVM pVM = pUVM->pVM;
3060 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3061 return pVM->hm.s.fNestedPaging;
3062}
3063
3064
3065/**
3066 * Checks if virtualized APIC registers is enabled.
3067 *
3068 * When enabled this feature allows the hardware to access most of the
3069 * APIC registers in the virtual-APIC page without causing VM-exits. See
3070 * Intel spec. 29.1.1 "Virtualized APIC Registers".
3071 *
3072 * @returns true if virtualized APIC registers is enabled, otherwise
3073 * false.
3074 * @param pUVM The user mode VM handle.
3075 */
3076VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3077{
3078 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3079 PVM pVM = pUVM->pVM;
3080 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3081 return pVM->hm.s.fVirtApicRegs;
3082}
3083
3084
3085/**
3086 * Checks if APIC posted-interrupt processing is enabled.
3087 *
3088 * This returns whether we can deliver interrupts to the guest without
3089 * leaving guest-context by updating APIC state from host-context.
3090 *
3091 * @returns true if APIC posted-interrupt processing is enabled,
3092 * otherwise false.
3093 * @param pUVM The user mode VM handle.
3094 */
3095VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3096{
3097 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3098 PVM pVM = pUVM->pVM;
3099 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3100 return pVM->hm.s.fPostedIntrs;
3101}
3102
3103
3104/**
3105 * Checks if we are currently using VPID in VT-x mode.
3106 *
3107 * @returns true if VPID is being used, otherwise false.
3108 * @param pUVM The user mode VM handle.
3109 */
3110VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3111{
3112 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3113 PVM pVM = pUVM->pVM;
3114 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3115 return pVM->hm.s.vmx.fVpid;
3116}
3117
3118
3119/**
3120 * Checks if we are currently using VT-x unrestricted execution,
3121 * aka UX.
3122 *
3123 * @returns true if UX is being used, otherwise false.
3124 * @param pUVM The user mode VM handle.
3125 */
3126VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3127{
3128 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3129 PVM pVM = pUVM->pVM;
3130 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3131 return pVM->hm.s.vmx.fUnrestrictedGuest;
3132}
3133
3134
3135/**
3136 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3137 *
3138 * @returns true if an internal event is pending, otherwise false.
3139 * @param pVCpu The cross context virtual CPU structure.
3140 */
3141VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3142{
3143 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3144}
3145
3146
3147/**
3148 * Checks if the VMX-preemption timer is being used.
3149 *
3150 * @returns true if the VMX-preemption timer is being used, otherwise false.
3151 * @param pVM The cross context VM structure.
3152 */
3153VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3154{
3155 return HMIsEnabled(pVM)
3156 && pVM->hm.s.vmx.fEnabled
3157 && pVM->hm.s.vmx.fUsePreemptTimer;
3158}
3159
3160
3161/**
3162 * Restart an I/O instruction that was refused in ring-0
3163 *
3164 * @returns Strict VBox status code. Informational status codes other than the one documented
3165 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3166 * @retval VINF_SUCCESS Success.
3167 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3168 * status code must be passed on to EM.
3169 * @retval VERR_NOT_FOUND if no pending I/O instruction.
3170 *
3171 * @param pVM The cross context VM structure.
3172 * @param pVCpu The cross context virtual CPU structure.
3173 * @param pCtx Pointer to the guest CPU context.
3174 */
3175VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3176{
3177 /*
3178 * Check if we've got relevant data pending.
3179 */
3180 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3181 if (enmType == HMPENDINGIO_INVALID)
3182 return VERR_NOT_FOUND;
3183 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3184 if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
3185 return VERR_NOT_FOUND;
3186
3187 /*
3188 * Execute pending I/O.
3189 */
3190 VBOXSTRICTRC rcStrict;
3191 switch (enmType)
3192 {
3193 case HMPENDINGIO_PORT_READ:
3194 {
3195 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3196 uint32_t u32Val = 0;
3197
3198 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3199 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3200 if (IOM_SUCCESS(rcStrict))
3201 {
3202 /* Write back to the EAX register. */
3203 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3204 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3205 }
3206 break;
3207 }
3208
3209 default:
3210 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3211 }
3212
3213 if (IOM_SUCCESS(rcStrict))
3214 {
3215 /*
3216 * Check for I/O breakpoints.
3217 */
3218 uint32_t const uDr7 = pCtx->dr[7];
3219 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3220 && X86_DR7_ANY_RW_IO(uDr7)
3221 && (pCtx->cr4 & X86_CR4_DE))
3222 || DBGFBpIsHwIoArmed(pVM))
3223 {
3224 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3225 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3226 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3227 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3228 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3229 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
3230 rcStrict = rcStrict2;
3231 }
3232 }
3233 return rcStrict;
3234}
3235
3236
3237/**
3238 * Check fatal VT-x/AMD-V error and produce some meaningful
3239 * log release message.
3240 *
3241 * @param pVM The cross context VM structure.
3242 * @param iStatusCode VBox status code.
3243 */
3244VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3245{
3246 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3247 {
3248 PVMCPU pVCpu = &pVM->aCpus[i];
3249 switch (iStatusCode)
3250 {
3251 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3252 * might be getting inaccurate values for non-guru'ing EMTs. */
3253 case VERR_VMX_INVALID_VMCS_FIELD:
3254 break;
3255
3256 case VERR_VMX_INVALID_VMCS_PTR:
3257 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3258 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3259 pVCpu->hm.s.vmx.HCPhysVmcs));
3260 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3261 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3262 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3263 break;
3264
3265 case VERR_VMX_UNABLE_TO_START_VM:
3266 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3267 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3268 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3269
3270 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3271 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3272 {
3273 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3274 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3275 }
3276 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3277 {
3278 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3279 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3280 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3281 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3282 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3283 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3284 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3285 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3286 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3287 }
3288 /** @todo Log VM-entry event injection control fields
3289 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3290 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3291 break;
3292
3293 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3294 case VERR_VMX_INVALID_VMXON_PTR:
3295 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3296 case VERR_VMX_INVALID_GUEST_STATE:
3297 case VERR_VMX_UNEXPECTED_EXIT:
3298 case VERR_SVM_UNKNOWN_EXIT:
3299 case VERR_SVM_UNEXPECTED_EXIT:
3300 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3301 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3302 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3303 break;
3304 }
3305 }
3306
3307 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3308 {
3309 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3310 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3311 }
3312 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3313 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3314}
3315
3316
3317/**
3318 * Execute state save operation.
3319 *
3320 * @returns VBox status code.
3321 * @param pVM The cross context VM structure.
3322 * @param pSSM SSM operation handle.
3323 */
3324static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3325{
3326 int rc;
3327
3328 Log(("hmR3Save:\n"));
3329
3330 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3331 {
3332 /*
3333 * Save the basic bits - fortunately all the other things can be resynced on load.
3334 */
3335 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3336 AssertRCReturn(rc, rc);
3337 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3338 AssertRCReturn(rc, rc);
3339 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
3340 AssertRCReturn(rc, rc);
3341 /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
3342
3343 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3344 * perhaps not even that (the initial value of @c true is safe. */
3345 uint32_t u32Dummy = PGMMODE_REAL;
3346 rc = SSMR3PutU32(pSSM, u32Dummy);
3347 AssertRCReturn(rc, rc);
3348 rc = SSMR3PutU32(pSSM, u32Dummy);
3349 AssertRCReturn(rc, rc);
3350 rc = SSMR3PutU32(pSSM, u32Dummy);
3351 AssertRCReturn(rc, rc);
3352 }
3353
3354#ifdef VBOX_HM_WITH_GUEST_PATCHING
3355 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3356 AssertRCReturn(rc, rc);
3357 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3358 AssertRCReturn(rc, rc);
3359 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3360 AssertRCReturn(rc, rc);
3361
3362 /* Store all the guest patch records too. */
3363 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3364 AssertRCReturn(rc, rc);
3365
3366 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3367 {
3368 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3369
3370 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3371 AssertRCReturn(rc, rc);
3372
3373 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3374 AssertRCReturn(rc, rc);
3375
3376 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3377 AssertRCReturn(rc, rc);
3378
3379 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3380 AssertRCReturn(rc, rc);
3381
3382 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3383 AssertRCReturn(rc, rc);
3384
3385 AssertCompileSize(HMTPRINSTR, 4);
3386 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3387 AssertRCReturn(rc, rc);
3388
3389 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3390 AssertRCReturn(rc, rc);
3391
3392 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3393 AssertRCReturn(rc, rc);
3394
3395 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3396 AssertRCReturn(rc, rc);
3397
3398 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3399 AssertRCReturn(rc, rc);
3400 }
3401#endif
3402 return VINF_SUCCESS;
3403}
3404
3405
3406/**
3407 * Execute state load operation.
3408 *
3409 * @returns VBox status code.
3410 * @param pVM The cross context VM structure.
3411 * @param pSSM SSM operation handle.
3412 * @param uVersion Data layout version.
3413 * @param uPass The data pass.
3414 */
3415static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3416{
3417 int rc;
3418
3419 Log(("hmR3Load:\n"));
3420 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3421
3422 /*
3423 * Validate version.
3424 */
3425 if ( uVersion != HM_SAVED_STATE_VERSION
3426 && uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3427 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3428 {
3429 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3430 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3431 }
3432 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3433 {
3434 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3435 AssertRCReturn(rc, rc);
3436 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3437 AssertRCReturn(rc, rc);
3438 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3439 AssertRCReturn(rc, rc);
3440
3441 if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3442 {
3443 uint32_t val;
3444 /** @todo See note in hmR3Save(). */
3445 rc = SSMR3GetU32(pSSM, &val);
3446 AssertRCReturn(rc, rc);
3447 rc = SSMR3GetU32(pSSM, &val);
3448 AssertRCReturn(rc, rc);
3449 rc = SSMR3GetU32(pSSM, &val);
3450 AssertRCReturn(rc, rc);
3451 }
3452 }
3453#ifdef VBOX_HM_WITH_GUEST_PATCHING
3454 if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3455 {
3456 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3457 AssertRCReturn(rc, rc);
3458 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3459 AssertRCReturn(rc, rc);
3460 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3461 AssertRCReturn(rc, rc);
3462
3463 /* Fetch all TPR patch records. */
3464 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3465 AssertRCReturn(rc, rc);
3466
3467 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3468 {
3469 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3470
3471 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3472 AssertRCReturn(rc, rc);
3473
3474 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3475 AssertRCReturn(rc, rc);
3476
3477 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3478 AssertRCReturn(rc, rc);
3479
3480 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3481 AssertRCReturn(rc, rc);
3482
3483 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3484 AssertRCReturn(rc, rc);
3485
3486 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3487 AssertRCReturn(rc, rc);
3488
3489 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3490 pVM->hm.s.fTPRPatchingActive = true;
3491
3492 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3493
3494 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3495 AssertRCReturn(rc, rc);
3496
3497 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3498 AssertRCReturn(rc, rc);
3499
3500 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3501 AssertRCReturn(rc, rc);
3502
3503 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3504 AssertRCReturn(rc, rc);
3505
3506 Log(("hmR3Load: patch %d\n", i));
3507 Log(("Key = %x\n", pPatch->Core.Key));
3508 Log(("cbOp = %d\n", pPatch->cbOp));
3509 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3510 Log(("type = %d\n", pPatch->enmType));
3511 Log(("srcop = %d\n", pPatch->uSrcOperand));
3512 Log(("dstop = %d\n", pPatch->uDstOperand));
3513 Log(("cFaults = %d\n", pPatch->cFaults));
3514 Log(("target = %x\n", pPatch->pJumpTarget));
3515 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3516 AssertRC(rc);
3517 }
3518 }
3519#endif
3520
3521 return VINF_SUCCESS;
3522}
3523
3524
3525/**
3526 * Displays the guest VM-exit history.
3527 *
3528 * @param pVM The cross context VM structure.
3529 * @param pHlp The info helper functions.
3530 * @param pszArgs Arguments, ignored.
3531 */
3532static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3533{
3534 NOREF(pszArgs);
3535 PVMCPU pVCpu = VMMGetCpu(pVM);
3536 if (!pVCpu)
3537 pVCpu = &pVM->aCpus[0];
3538
3539 if (HMIsEnabled(pVM))
3540 {
3541 bool const fIsVtx = pVM->hm.s.vmx.fSupported;
3542 const char * const *papszDesc;
3543 unsigned cMaxExitDesc;
3544 if (fIsVtx)
3545 {
3546 cMaxExitDesc = MAX_EXITREASON_VTX;
3547 papszDesc = &g_apszVTxExitReasons[0];
3548 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x VM-exit history:\n", pVCpu->idCpu);
3549 }
3550 else
3551 {
3552 cMaxExitDesc = MAX_EXITREASON_AMDV;
3553 papszDesc = &g_apszAmdVExitReasons[0];
3554 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V #VMEXIT history:\n", pVCpu->idCpu);
3555 }
3556
3557 pHlp->pfnPrintf(pHlp, " idxExitHistoryFree = %u\n", pVCpu->hm.s.idxExitHistoryFree);
3558 unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
3559 pVCpu->hm.s.idxExitHistoryFree - 1 :
3560 RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
3561 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); i++)
3562 {
3563 uint16_t const uExit = pVCpu->hm.s.auExitHistory[i];
3564 const char *pszExit = NULL;
3565 if (uExit <= cMaxExitDesc)
3566 pszExit = papszDesc[uExit];
3567 else if (!fIsVtx)
3568 pszExit = hmSvmGetSpecialExitReasonDesc(uExit);
3569 else
3570 pszExit = NULL;
3571
3572 pHlp->pfnPrintf(pHlp, " auExitHistory[%2u] = 0x%04x %s %s\n", i, uExit, pszExit,
3573 idxLast == i ? "<-- Latest exit" : "");
3574 }
3575 pHlp->pfnPrintf(pHlp, "HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3576 }
3577 else
3578 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3579}
3580
3581
3582/**
3583 * Displays the HM pending event.
3584 *
3585 * @param pVM The cross context VM structure.
3586 * @param pHlp The info helper functions.
3587 * @param pszArgs Arguments, ignored.
3588 */
3589static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3590{
3591 NOREF(pszArgs);
3592 PVMCPU pVCpu = VMMGetCpu(pVM);
3593 if (!pVCpu)
3594 pVCpu = &pVM->aCpus[0];
3595
3596 if (HMIsEnabled(pVM))
3597 {
3598 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3599 if (pVCpu->hm.s.Event.fPending)
3600 {
3601 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3602 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3603 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3604 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3605 }
3606 }
3607 else
3608 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3609}
3610
Note: See TracBrowser for help on using the repository browser.

© 2024 Oracle Support Privacy / Do Not Sell My Info Terms of Use Trademark Policy Automated Access Etiquette