HM.cpp@ 70944

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1	/* $Id: HM.cpp 70918 2018-02-08 16:11:47Z vboxsync $ */
2	/** @file
3	* HM - Intel/AMD VM Hardware Support Manager.
4	*/
5
6	/*
7	* Copyright (C) 2006-2017 Oracle Corporation
8	*
9	* This file is part of VirtualBox Open Source Edition (OSE), as
10	* available from http://www.virtualbox.org. This file is free software;
11	* you can redistribute it and/or modify it under the terms of the GNU
12	* General Public License (GPL) as published by the Free Software
13	* Foundation, in version 2 as it comes in the "COPYING" file of the
14	* VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15	* hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16	*/
17
18	/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19	*
20	* The HM manages guest execution using the VT-x and AMD-V CPU hardware
21	* extensions.
22	*
23	* {summary of what HM does}
24	*
25	* Hardware assisted virtualization manager was originally abbreviated HWACCM,
26	* however that was cumbersome to write and parse for such a central component,
27	* so it was shortened to HM when refactoring the code in the 4.3 development
28	* cycle.
29	*
30	* {add sections with more details}
31	*
32	* @sa @ref grp_hm
33	*/
34
35
36	/*********************************************************************************************************************************
37	* Header Files *
38	*********************************************************************************************************************************/
39	#define LOG_GROUP LOG_GROUP_HM
40	#include <VBox/vmm/cpum.h>
41	#include <VBox/vmm/stam.h>
42	#include <VBox/vmm/mm.h>
43	#include <VBox/vmm/pdmapi.h>
44	#include <VBox/vmm/pgm.h>
45	#include <VBox/vmm/ssm.h>
46	#include <VBox/vmm/trpm.h>
47	#include <VBox/vmm/dbgf.h>
48	#include <VBox/vmm/iom.h>
49	#include <VBox/vmm/iem.h>
50	#include <VBox/vmm/patm.h>
51	#include <VBox/vmm/csam.h>
52	#include <VBox/vmm/selm.h>
53	#include <VBox/vmm/nem.h>
54	#ifdef VBOX_WITH_REM
55	# include <VBox/vmm/rem.h>
56	#endif
57	#include <VBox/vmm/hm_vmx.h>
58	#include <VBox/vmm/hm_svm.h>
59	#include "HMInternal.h"
60	#include <VBox/vmm/vm.h>
61	#include <VBox/vmm/uvm.h>
62	#include <VBox/err.h>
63	#include <VBox/param.h>
64
65	#include <iprt/assert.h>
66	#include <VBox/log.h>
67	#include <iprt/asm.h>
68	#include <iprt/asm-amd64-x86.h>
69	#include <iprt/env.h>
70	#include <iprt/thread.h>
71
72
73	/*********************************************************************************************************************************
74	* Global Variables *
75	*********************************************************************************************************************************/
76	#define EXIT_REASON(def, val, str) #def " - " #val " - " str
77	#define EXIT_REASON_NIL() NULL
78	/** Exit reason descriptions for VT-x, used to describe statistics. */
79	static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
80	{
81	EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
82	EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
83	EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
84	EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
85	EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
86	EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
87	EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
88	EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
89	EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
90	EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
91	EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
92	EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
93	EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
94	EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
95	EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
96	EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
97	EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
98	EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
99	EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
100	EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
101	EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
102	EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
103	EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
104	EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
105	EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
106	EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
107	EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
108	EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
109	EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
110	EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
111	EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
112	EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
113	EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
114	EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
115	EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
116	EXIT_REASON_NIL(),
117	EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
118	EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
119	EXIT_REASON_NIL(),
120	EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
121	EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
122	EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
123	EXIT_REASON_NIL(),
124	EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
125	EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
126	EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
127	EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
128	EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
129	EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
130	EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
131	EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
132	EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
133	EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
134	EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
135	EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
136	EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
137	EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
138	EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
139	EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
140	EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
141	EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instrunction."),
142	EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
143	EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
144	EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
145	EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
146	};
147	/** Array index of the last valid VT-x exit reason. */
148	#define MAX_EXITREASON_VTX 64
149
150	/** A partial list of Exit reason descriptions for AMD-V, used to describe
151	* statistics.
152	*
153	* @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
154	* this array doesn't contain the entire set of exit reasons, we
155	* handle them via hmSvmGetSpecialExitReasonDesc(). */
156	static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
157	{
158	EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
159	EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
160	EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
161	EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
162	EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
163	EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
164	EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
165	EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
166	EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
167	EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
168	EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
169	EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
170	EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
171	EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
172	EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
173	EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
174	EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
175	EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
176	EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
177	EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
178	EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
179	EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
180	EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
181	EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
182	EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
183	EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
184	EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
185	EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
186	EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
187	EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
188	EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
189	EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
190	EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
191	EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
192	EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
193	EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
194	EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
195	EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
196	EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
197	EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
198	EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
199	EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
200	EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
201	EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
202	EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
203	EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
204	EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
205	EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
206	EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
207	EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
208	EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
209	EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
210	EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
211	EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
212	EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
213	EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
214	EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
215	EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
216	EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
217	EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
218	EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
219	EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
220	EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
221	EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
222	EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
223	EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
224	EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
225	EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
226	EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
227	EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
228	EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
229	EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
230	EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
231	EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
232	EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
233	EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
234	EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
235	EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
236	EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
237	EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
238	EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
239	EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
240	EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
241	EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
242	EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
243	EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
244	EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
245	EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
246	EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
247	EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
248	EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
249	EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
250	EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
251	EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
252	EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
253	EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
254	EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
255	EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
256	EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
257	EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
258	EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
259	EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
260	EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR"),
261	EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR"),
262	EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
263	EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
264	EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
265	EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
266	EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
267	EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
268	EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
269	EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
270	EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
271	EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
272	EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
273	EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
274	EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
275	EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
276	EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
277	EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
278	EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
279	EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
280	EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
281	EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT accessing protected port."),
282	EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
283	EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
284	EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
285	EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
286	EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
287	EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
288	EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
289	EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
290	EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
291	EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
292	EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
293	EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
294	EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
295	EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
296	EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
297	EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
298	EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
299	EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
300	};
301	/** Array index of the last valid AMD-V exit reason. */
302	#define MAX_EXITREASON_AMDV 141
303
304	/** Special exit reasons not covered in the array above. */
305	#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
306	#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
307	#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
308
309	/**
310	* Gets the SVM exit reason if it's one of the reasons not present in the @c
311	* g_apszAmdVExitReasons array.
312	*
313	* @returns The exit reason or NULL if unknown.
314	* @param uExit The exit.
315	*/
316	DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
317	{
318	switch (uExit)
319	{
320	case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
321	case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
322	case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
323	}
324	return EXIT_REASON_NIL();
325	}
326	#undef EXIT_REASON_NIL
327	#undef EXIT_REASON
328
329	/** @def HMVMX_REPORT_FEATURE
330	* Reports VT-x feature to the release log.
331	*
332	* @param allowed1 Mask of allowed feature bits.
333	* @param disallowed0 Mask of disallowed feature bits.
334	* @param strdesc The description string to report.
335	* @param featflag Mask of the feature to report.
336	*/
337	#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
338	do { \
339	if ((allowed1) & (featflag)) \
340	{ \
341	if ((disallowed0) & (featflag)) \
342	LogRel(("HM: " strdesc " (must be set)\n")); \
343	else \
344	LogRel(("HM: " strdesc "\n")); \
345	} \
346	else \
347	LogRel(("HM: " strdesc " (must be cleared)\n")); \
348	} while (0)
349
350	/** @def HMVMX_REPORT_ALLOWED_FEATURE
351	* Reports an allowed VT-x feature to the release log.
352	*
353	* @param allowed1 Mask of allowed feature bits.
354	* @param strdesc The description string to report.
355	* @param featflag Mask of the feature to report.
356	*/
357	#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
358	do { \
359	if ((allowed1) & (featflag)) \
360	LogRel(("HM: " strdesc "\n")); \
361	else \
362	LogRel(("HM: " strdesc " not supported\n")); \
363	} while (0)
364
365	/** @def HMVMX_REPORT_MSR_CAPABILITY
366	* Reports MSR feature capability.
367	*
368	* @param msrcaps Mask of MSR feature bits.
369	* @param strdesc The description string to report.
370	* @param cap Mask of the feature to report.
371	*/
372	#define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
373	do { \
374	if ((msrcaps) & (cap)) \
375	LogRel(("HM: " strdesc "\n")); \
376	} while (0)
377
378
379	/*********************************************************************************************************************************
380	* Internal Functions *
381	*********************************************************************************************************************************/
382	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
383	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
384	static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
385	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
386	static int hmR3InitCPU(PVM pVM);
387	static int hmR3InitFinalizeR0(PVM pVM);
388	static int hmR3InitFinalizeR0Intel(PVM pVM);
389	static int hmR3InitFinalizeR0Amd(PVM pVM);
390	static int hmR3TermCPU(PVM pVM);
391
392
393
394	/**
395	* Initializes the HM.
396	*
397	* This is the very first component to really do init after CFGM so that we can
398	* establish the predominat execution engine for the VM prior to initializing
399	* other modules. It takes care of NEM initialization if needed (HM disabled or
400	* not available in HW).
401	*
402	* If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
403	* hypervisor API via NEM, and then back on raw-mode if that isn't available
404	* either. The fallback to raw-mode will not happen if /HM/HMForced is set
405	* (like for guest using SMP or 64-bit as well as for complicated guest like OS
406	* X, OS/2 and others).
407	*
408	* Note that a lot of the set up work is done in ring-0 and thus postponed till
409	* the ring-3 and ring-0 callback to HMR3InitCompleted.
410	*
411	* @returns VBox status code.
412	* @param pVM The cross context VM structure.
413	*
414	* @remarks Be careful with what we call here, since most of the VMM components
415	* are uninitialized.
416	*/
417	VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
418	{
419	LogFlow(("HMR3Init\n"));
420
421	/*
422	* Assert alignment and sizes.
423	*/
424	AssertCompileMemberAlignment(VM, hm.s, 32);
425	AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
426
427	/*
428	* Register the saved state data unit.
429	*/
430	int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
431	NULL, NULL, NULL,
432	NULL, hmR3Save, NULL,
433	NULL, hmR3Load, NULL);
434	if (RT_FAILURE(rc))
435	return rc;
436
437	/*
438	* Register info handlers.
439	*/
440	rc = DBGFR3InfoRegisterInternalEx(pVM, "exithistory", "Dumps the HM VM-exit history.", hmR3InfoExitHistory,
441	DBGFINFO_FLAGS_ALL_EMTS);
442	AssertRCReturn(rc, rc);
443
444	rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
445	DBGFINFO_FLAGS_ALL_EMTS);
446	AssertRCReturn(rc, rc);
447
448	/*
449	* Read configuration.
450	*/
451	PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
452
453	/*
454	* Validate the HM settings.
455	*/
456	rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
457	"HMForced"
458	"\|UseNEMInstead"
459	"\|FallbackToNEM"
460	"\|EnableNestedPaging"
461	"\|EnableUX"
462	"\|EnableLargePages"
463	"\|EnableVPID"
464	"\|IBPBOnVMExit"
465	"\|IBPBOnVMEntry"
466	"\|TPRPatchingEnabled"
467	"\|64bitEnabled"
468	"\|Exclusive"
469	"\|MaxResumeLoops"
470	"\|VmxPleGap"
471	"\|VmxPleWindow"
472	"\|UseVmxPreemptTimer"
473	"\|SvmPauseFilter"
474	"\|SvmPauseFilterThreshold"
475	"\|SvmVirtVmsaveVmload"
476	"\|SvmVGif",
477	"" /* pszValidNodes /, "HM" / pszWho /, 0 / uInstance */);
478	if (RT_FAILURE(rc))
479	return rc;
480
481	/** @cfgm{/HM/HMForced, bool, false}
482	* Forces hardware virtualization, no falling back on raw-mode. HM must be
483	* enabled, i.e. /HMEnabled must be true. */
484	bool fHMForced;
485	#ifdef VBOX_WITH_RAW_MODE
486	rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
487	AssertRCReturn(rc, rc);
488	AssertLogRelMsgReturn(!fHMForced \|\| pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
489	VERR_INVALID_PARAMETER);
490	# if defined(RT_OS_DARWIN)
491	if (pVM->fHMEnabled)
492	fHMForced = true;
493	# endif
494	AssertLogRelMsgReturn(pVM->cCpus == 1 \|\| pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
495	VERR_INVALID_PARAMETER);
496	if (pVM->cCpus > 1)
497	fHMForced = true;
498	#else /* !VBOX_WITH_RAW_MODE */
499	AssertRelease(pVM->fHMEnabled);
500	fHMForced = true;
501	#endif /* !VBOX_WITH_RAW_MODE */
502
503	/** @cfgm{/HM/UseNEMInstead, bool, true}
504	* Don't use HM, use NEM instead. */
505	bool fUseNEMInstead = false;
506	rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
507	AssertRCReturn(rc, rc);
508	if (fUseNEMInstead && pVM->fHMEnabled)
509	{
510	LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
511	pVM->fHMEnabled = false;
512	}
513
514	/** @cfgm{/HM/FallbackToNEM, bool, true}
515	* Enables fallback on NEM. */
516	bool fFallbackToNEM = true;
517	rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
518	AssertRCReturn(rc, rc);
519
520	/** @cfgm{/HM/EnableNestedPaging, bool, false}
521	* Enables nested paging (aka extended page tables). */
522	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
523	AssertRCReturn(rc, rc);
524
525	/** @cfgm{/HM/EnableUX, bool, true}
526	* Enables the VT-x unrestricted execution feature. */
527	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
528	AssertRCReturn(rc, rc);
529
530	/** @cfgm{/HM/EnableLargePages, bool, false}
531	* Enables using large pages (2 MB) for guest memory, thus saving on (nested)
532	* page table walking and maybe better TLB hit rate in some cases. */
533	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
534	AssertRCReturn(rc, rc);
535
536	/** @cfgm{/HM/EnableVPID, bool, false}
537	* Enables the VT-x VPID feature. */
538	rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
539	AssertRCReturn(rc, rc);
540
541	/** @cfgm{/HM/TPRPatchingEnabled, bool, false}
542	* Enables TPR patching for 32-bit windows guests with IO-APIC. */
543	rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
544	AssertRCReturn(rc, rc);
545
546	/** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
547	* Enables AMD64 cpu features.
548	* On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
549	* already have the support. */
550	#ifdef VBOX_ENABLE_64_BITS_GUESTS
551	rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
552	AssertLogRelRCReturn(rc, rc);
553	#else
554	pVM->hm.s.fAllow64BitGuests = false;
555	#endif
556
557	/** @cfgm{/HM/VmxPleGap, uint32_t, 0}
558	* The pause-filter exiting gap in TSC ticks. When the number of ticks between
559	* two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
560	* latest PAUSE instruction to be start of a new PAUSE loop.
561	*/
562	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
563	AssertRCReturn(rc, rc);
564
565	/** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
566	* The pause-filter exiting window in TSC ticks. When the number of ticks
567	* between the current PAUSE instruction and first PAUSE of a loop exceeds
568	* VmxPleWindow, a VM-exit is triggered.
569	*
570	* Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
571	*/
572	rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
573	AssertRCReturn(rc, rc);
574
575	/** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
576	* A counter that is decrement each time a PAUSE instruction is executed by the
577	* guest. When the counter is 0, a \#VMEXIT is triggered.
578	*/
579	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
580	AssertRCReturn(rc, rc);
581
582	/** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
583	* The pause filter threshold in ticks. When the elapsed time between two
584	* successive PAUSE instructions exceeds SvmPauseFilterThreshold, the PauseFilter
585	* count is reset to its initial value. However, if PAUSE is executed PauseFilter
586	* times within PauseFilterThreshold ticks, a VM-exit will be triggered.
587	*
588	* Setting both SvmPauseFilterCount and SvmPauseFilterCount to 0 disables
589	* pause-filter exiting.
590	*/
591	rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
592	AssertRCReturn(rc, rc);
593
594	/** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
595	* Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
596	* available. */
597	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
598	AssertRCReturn(rc, rc);
599
600	/** @cfgm{/HM/SvmVGif, bool, true}
601	* Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
602	* if it's available. */
603	rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
604	AssertRCReturn(rc, rc);
605
606	/** @cfgm{/HM/Exclusive, bool}
607	* Determines the init method for AMD-V and VT-x. If set to true, HM will do a
608	* global init for each host CPU. If false, we do local init each time we wish
609	* to execute guest code.
610	*
611	* On Windows, default is false due to the higher risk of conflicts with other
612	* hypervisors.
613	*
614	* On Mac OS X, this setting is ignored since the code does not handle local
615	* init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
616	*/
617	#if defined(RT_OS_DARWIN)
618	pVM->hm.s.fGlobalInit = true;
619	#else
620	rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
621	# if defined(RT_OS_WINDOWS)
622	false
623	# else
624	true
625	# endif
626	);
627	AssertLogRelRCReturn(rc, rc);
628	#endif
629
630	/** @cfgm{/HM/MaxResumeLoops, uint32_t}
631	* The number of times to resume guest execution before we forcibly return to
632	* ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
633	* determines the default value. */
634	rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
635	AssertLogRelRCReturn(rc, rc);
636
637	/** @cfgm{/HM/UseVmxPreemptTimer, bool}
638	* Whether to make use of the VMX-preemption timer feature of the CPU if it's
639	* available. */
640	rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
641	AssertLogRelRCReturn(rc, rc);
642
643	/** @cfgm{/HM/IBPBOnVMExit, bool}
644	* Costly paranoia setting. */
645	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
646	AssertLogRelRCReturn(rc, rc);
647
648	/** @cfgm{/HM/IBPBOnVMEntry, bool}
649	* Costly paranoia setting. */
650	rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
651	AssertLogRelRCReturn(rc, rc);
652
653	/*
654	* Check if VT-x or AMD-v support according to the users wishes.
655	*/
656	/** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
657	* VERR_SVM_IN_USE. */
658	if (pVM->fHMEnabled)
659	{
660	uint32_t fCaps;
661	rc = SUPR3QueryVTCaps(&fCaps);
662	if (RT_SUCCESS(rc))
663	{
664	if (fCaps & SUPVTCAPS_AMD_V)
665	{
666	LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
667	pVM->hm.s.svm.fSupported = true;
668	}
669	else if (fCaps & SUPVTCAPS_VT_X)
670	{
671	const char *pszWhy;
672	rc = SUPR3QueryVTxSupported(&pszWhy);
673	if (RT_SUCCESS(rc))
674	{
675	LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
676	fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
677	fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
678	(fCaps & (SUPVTCAPS_NESTED_PAGING \| SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
679	pVM->hm.s.vmx.fSupported = true;
680	}
681	else
682	{
683	/*
684	* Before failing, try fallback to NEM if we're allowed to do that.
685	*/
686	pVM->fHMEnabled = false;
687	if (fFallbackToNEM)
688	{
689	LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
690	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
691	if ( RT_SUCCESS(rc2)
692	&& pVM->fNEMActive)
693	rc = VINF_SUCCESS;
694	}
695	if (RT_FAILURE(rc))
696	{
697	if (fHMForced)
698	return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
699
700	/* Fall back to raw-mode. */
701	LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
702	}
703	}
704	}
705	else
706	AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
707	VERR_INTERNAL_ERROR_5);
708
709	/*
710	* Do we require a little bit or raw-mode for 64-bit guest execution?
711	*/
712	pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
713	&& pVM->fHMEnabled
714	&& pVM->hm.s.fAllow64BitGuests;
715
716	/*
717	* Disable nested paging and unrestricted guest execution now if they're
718	* configured so that CPUM can make decisions based on our configuration.
719	*/
720	Assert(!pVM->hm.s.fNestedPaging);
721	if (pVM->hm.s.fAllowNestedPaging)
722	{
723	if (fCaps & SUPVTCAPS_NESTED_PAGING)
724	pVM->hm.s.fNestedPaging = true;
725	else
726	pVM->hm.s.fAllowNestedPaging = false;
727	}
728
729	if (fCaps & SUPVTCAPS_VT_X)
730	{
731	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
732	if (pVM->hm.s.vmx.fAllowUnrestricted)
733	{
734	if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
735	&& pVM->hm.s.fNestedPaging)
736	pVM->hm.s.vmx.fUnrestrictedGuest = true;
737	else
738	pVM->hm.s.vmx.fAllowUnrestricted = false;
739	}
740	}
741	}
742	else
743	{
744	const char *pszMsg;
745	switch (rc)
746	{
747	case VERR_UNSUPPORTED_CPU:
748	pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained";
749	break;
750
751	case VERR_VMX_NO_VMX:
752	pszMsg = "VT-x is not available";
753	break;
754
755	case VERR_VMX_MSR_VMX_DISABLED:
756	pszMsg = "VT-x is disabled in the BIOS";
757	break;
758
759	case VERR_VMX_MSR_ALL_VMX_DISABLED:
760	pszMsg = "VT-x is disabled in the BIOS for all CPU modes";
761	break;
762
763	case VERR_VMX_MSR_LOCKING_FAILED:
764	pszMsg = "Failed to enable and lock VT-x features";
765	break;
766
767	case VERR_SVM_NO_SVM:
768	pszMsg = "AMD-V is not available";
769	break;
770
771	case VERR_SVM_DISABLED:
772	pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)";
773	break;
774
775	default:
776	return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
777	}
778
779	/*
780	* Before failing, try fallback to NEM if we're allowed to do that.
781	*/
782	pVM->fHMEnabled = false;
783	if (fFallbackToNEM)
784	{
785	LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
786	int rc2 = NEMR3Init(pVM, true /fFallback/, fHMForced);
787	if ( RT_SUCCESS(rc2)
788	&& pVM->fNEMActive)
789	rc = VINF_SUCCESS;
790	}
791	if (RT_FAILURE(rc))
792	{
793	if (fHMForced)
794	return VM_SET_ERROR(pVM, rc, pszMsg);
795
796	LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
797	}
798	}
799	}
800	/*
801	* If NEM is supposed to be used instead, initialize it instead.
802	*/
803	else if (fUseNEMInstead)
804	{
805	rc = NEMR3Init(pVM, false /fFallback/, fHMForced);
806	if (RT_FAILURE(rc))
807	return rc;
808	}
809
810	/* It's now OK to use the predicate function. */
811	pVM->fHMEnabledFixed = true;
812	return VINF_SUCCESS;
813	}
814
815
816	/**
817	* Initializes the per-VCPU HM.
818	*
819	* @returns VBox status code.
820	* @param pVM The cross context VM structure.
821	*/
822	static int hmR3InitCPU(PVM pVM)
823	{
824	LogFlow(("HMR3InitCPU\n"));
825
826	if (!HMIsEnabled(pVM))
827	return VINF_SUCCESS;
828
829	for (VMCPUID i = 0; i < pVM->cCpus; i++)
830	{
831	PVMCPU pVCpu = &pVM->aCpus[i];
832	pVCpu->hm.s.fActive = false;
833	}
834
835	#ifdef VBOX_WITH_STATISTICS
836	STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
837	STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
838	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
839	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
840	STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
841	#endif
842
843	/*
844	* Statistics.
845	*/
846	for (VMCPUID i = 0; i < pVM->cCpus; i++)
847	{
848	PVMCPU pVCpu = &pVM->aCpus[i];
849	int rc;
850
851	#ifdef VBOX_WITH_STATISTICS
852	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
853	"Profiling of RTMpPokeCpu",
854	"/PROF/CPU%d/HM/Poke", i);
855	AssertRC(rc);
856	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
857	"Profiling of poke wait",
858	"/PROF/CPU%d/HM/PokeWait", i);
859	AssertRC(rc);
860	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
861	"Profiling of poke wait when RTMpPokeCpu fails",
862	"/PROF/CPU%d/HM/PokeWaitFailed", i);
863	AssertRC(rc);
864	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
865	"Profiling of VMXR0RunGuestCode entry",
866	"/PROF/CPU%d/HM/StatEntry", i);
867	AssertRC(rc);
868	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
869	"Profiling of VMXR0RunGuestCode exit part 1",
870	"/PROF/CPU%d/HM/SwitchFromGC_1", i);
871	AssertRC(rc);
872	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
873	"Profiling of VMXR0RunGuestCode exit part 2",
874	"/PROF/CPU%d/HM/SwitchFromGC_2", i);
875	AssertRC(rc);
876
877	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
878	"I/O",
879	"/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
880	AssertRC(rc);
881	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
882	"MOV CRx",
883	"/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
884	AssertRC(rc);
885	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
886	"Exceptions, NMIs",
887	"/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
888	AssertRC(rc);
889
890	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
891	"Profiling of VMXR0LoadGuestState",
892	"/PROF/CPU%d/HM/StatLoadGuestState", i);
893	AssertRC(rc);
894	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
895	"Profiling of VMLAUNCH/VMRESUME.",
896	"/PROF/CPU%d/HM/InGC", i);
897	AssertRC(rc);
898
899	# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
900	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
901	STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
902	"/PROF/CPU%d/HM/Switcher3264", i);
903	AssertRC(rc);
904	# endif
905
906	# ifdef HM_PROFILE_EXIT_DISPATCH
907	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
908	STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
909	"/PROF/CPU%d/HM/ExitDispatch", i);
910	AssertRC(rc);
911	# endif
912
913	#endif
914	# define HM_REG_COUNTER(a, b, desc) \
915	rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
916	AssertRC(rc);
917
918	#ifdef VBOX_WITH_STATISTICS
919	HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
920	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
921	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
922	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
923	HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
924	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
925	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
926	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
927	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
928	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
929	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
930	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
931	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
932	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
933	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
934	HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
935	HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
936	HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
937	HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
938	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
939	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
940	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
941	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
942	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
943	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
944	HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
945	HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
946	HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
947	HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
948	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
949	HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
950	HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
951	HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
952	HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
953	HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
954	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
955	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
956	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
957	HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
958	HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
959	HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
960	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
961	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
962	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
963	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
964	HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
965	HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
966	#endif
967	HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
968	#ifdef VBOX_WITH_STATISTICS
969	HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
970	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
971	HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
972	HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
973	HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
974
975	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
976	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
977	HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
978	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
979	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
980	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
981	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
982	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
983	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
984	#endif
985	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
986	#ifdef VBOX_WITH_STATISTICS
987	HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
988
989	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
990	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
991	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
992	HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
993
994	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
995	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
996	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
997	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
998	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
999	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
1000	HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
1001	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
1002	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
1003	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
1004	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
1005	HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
1006	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
1007	HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
1008
1009	HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
1010	HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
1011	HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
1012
1013	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
1014	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
1015	HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
1016
1017	HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
1018	HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
1019
1020	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
1021	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
1022	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
1023	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
1024	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
1025	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
1026	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
1027	HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
1028
1029	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1030	HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
1031	HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
1032	#endif
1033
1034	for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
1035	{
1036	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1037	STAMUNIT_OCCURENCES, "Profiling of CRx writes",
1038	"/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
1039	AssertRC(rc);
1040	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1041	STAMUNIT_OCCURENCES, "Profiling of CRx reads",
1042	"/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
1043	AssertRC(rc);
1044	}
1045
1046	#undef HM_REG_COUNTER
1047
1048	pVCpu->hm.s.paStatExitReason = NULL;
1049
1050	rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(pVCpu->hm.s.paStatExitReason), 0 / uAlignment */, MM_TAG_HM,
1051	(void **)&pVCpu->hm.s.paStatExitReason);
1052	AssertRC(rc);
1053	if (RT_SUCCESS(rc))
1054	{
1055	const char const papszDesc = ASMIsIntelCpu() \|\| ASMIsViaCentaurCpu() ?
1056	&g_apszVTxExitReasons[0] : &g_apszAmdVExitReasons[0];
1057	for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1058	{
1059	if (papszDesc[j])
1060	{
1061	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1062	STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
1063	AssertRC(rc);
1064	}
1065	}
1066	rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1067	"Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
1068	AssertRC(rc);
1069	}
1070	pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
1071	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1072	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
1073	# else
1074	Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
1075	# endif
1076
1077	rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
1078	AssertRCReturn(rc, rc);
1079	pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1080	# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1081	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR \|\| !HMIsEnabled(pVM));
1082	# else
1083	Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1084	# endif
1085	for (unsigned j = 0; j < 255; j++)
1086	{
1087	STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1088	"Injected event.",
1089	(j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1090	}
1091
1092	#endif /* VBOX_WITH_STATISTICS */
1093	}
1094
1095	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1096	/*
1097	* Magic marker for searching in crash dumps.
1098	*/
1099	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1100	{
1101	PVMCPU pVCpu = &pVM->aCpus[i];
1102
1103	PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1104	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1105	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1106	}
1107	#endif
1108
1109	return VINF_SUCCESS;
1110	}
1111
1112
1113	/**
1114	* Called when a init phase has completed.
1115	*
1116	* @returns VBox status code.
1117	* @param pVM The cross context VM structure.
1118	* @param enmWhat The phase that completed.
1119	*/
1120	VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1121	{
1122	switch (enmWhat)
1123	{
1124	case VMINITCOMPLETED_RING3:
1125	return hmR3InitCPU(pVM);
1126	case VMINITCOMPLETED_RING0:
1127	return hmR3InitFinalizeR0(pVM);
1128	default:
1129	return VINF_SUCCESS;
1130	}
1131	}
1132
1133
1134	/**
1135	* Turns off normal raw mode features.
1136	*
1137	* @param pVM The cross context VM structure.
1138	*/
1139	static void hmR3DisableRawMode(PVM pVM)
1140	{
1141	/* Reinit the paging mode to force the new shadow mode. */
1142	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1143	{
1144	PVMCPU pVCpu = &pVM->aCpus[i];
1145
1146	PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1147	}
1148	}
1149
1150
1151	/**
1152	* Initialize VT-x or AMD-V.
1153	*
1154	* @returns VBox status code.
1155	* @param pVM The cross context VM structure.
1156	*/
1157	static int hmR3InitFinalizeR0(PVM pVM)
1158	{
1159	int rc;
1160
1161	if (!HMIsEnabled(pVM))
1162	return VINF_SUCCESS;
1163
1164	/*
1165	* Hack to allow users to work around broken BIOSes that incorrectly set
1166	* EFER.SVME, which makes us believe somebody else is already using AMD-V.
1167	*/
1168	if ( !pVM->hm.s.vmx.fSupported
1169	&& !pVM->hm.s.svm.fSupported
1170	&& pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
1171	&& RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1172	{
1173	LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1174	pVM->hm.s.svm.fSupported = true;
1175	pVM->hm.s.svm.fIgnoreInUseError = true;
1176	pVM->hm.s.lLastError = VINF_SUCCESS;
1177	}
1178
1179	/*
1180	* Report ring-0 init errors.
1181	*/
1182	if ( !pVM->hm.s.vmx.fSupported
1183	&& !pVM->hm.s.svm.fSupported)
1184	{
1185	LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
1186	LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1187	switch (pVM->hm.s.lLastError)
1188	{
1189	case VERR_VMX_IN_VMX_ROOT_MODE:
1190	return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1191	case VERR_VMX_NO_VMX:
1192	return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1193	case VERR_VMX_MSR_VMX_DISABLED:
1194	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1195	case VERR_VMX_MSR_ALL_VMX_DISABLED:
1196	return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1197	case VERR_VMX_MSR_LOCKING_FAILED:
1198	return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1199	case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1200	return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1201	case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1202	return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1203
1204	case VERR_SVM_IN_USE:
1205	return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1206	case VERR_SVM_NO_SVM:
1207	return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1208	case VERR_SVM_DISABLED:
1209	return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1210	}
1211	return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
1212	}
1213
1214	/*
1215	* Enable VT-x or AMD-V on all host CPUs.
1216	*/
1217	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_ENABLE, 0, NULL);
1218	if (RT_FAILURE(rc))
1219	{
1220	LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1221	HMR3CheckError(pVM, rc);
1222	return rc;
1223	}
1224
1225	/*
1226	* No TPR patching is required when the IO-APIC is not enabled for this VM.
1227	* (Main should have taken care of this already)
1228	*/
1229	if (!PDMHasIoApic(pVM))
1230	{
1231	Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1232	pVM->hm.s.fTprPatchingAllowed = false;
1233	}
1234
1235	/*
1236	* Sync options.
1237	*/
1238	/** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1239	* That will require a little bit of work, of course. */
1240	for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1241	{
1242	PVMCPU pVCpu = &pVM->aCpus[iCpu];
1243	PCPUMCTX pCpuCtx = CPUMQueryGuestCtxPtr(pVCpu);
1244	pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT \| CPUMCTX_WSF_IBPB_ENTRY);
1245	if (pVM->cpum.ro.HostFeatures.fIbpb)
1246	{
1247	if (pVM->hm.s.fIbpbOnVmExit)
1248	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_EXIT;
1249	if (pVM->hm.s.fIbpbOnVmEntry)
1250	pCpuCtx->fWorldSwitcher \|= CPUMCTX_WSF_IBPB_ENTRY;
1251	}
1252	if (iCpu == 0)
1253	LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%d fIbpbOnVmEntry=%d)\n",
1254	pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
1255	}
1256
1257	/*
1258	* Do the vendor specific initialization .
1259	* .
1260	* Note! We disable release log buffering here since we're doing relatively .
1261	* lot of logging and doesn't want to hit the disk with each LogRel .
1262	* statement.
1263	*/
1264	AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1265	bool fOldBuffered = RTLogRelSetBuffering(true /fBuffered/);
1266	if (pVM->hm.s.vmx.fSupported)
1267	rc = hmR3InitFinalizeR0Intel(pVM);
1268	else
1269	rc = hmR3InitFinalizeR0Amd(pVM);
1270	LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1271	RTLogRelSetBuffering(fOldBuffered);
1272	pVM->hm.s.fInitialized = true;
1273
1274	return rc;
1275	}
1276
1277
1278	/**
1279	* @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1280	*/
1281	static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1282	{
1283	NOREF(pVM);
1284	NOREF(pvAllocation);
1285	NOREF(GCPhysAllocation);
1286	}
1287
1288
1289	/**
1290	* Finish VT-x initialization (after ring-0 init).
1291	*
1292	* @returns VBox status code.
1293	* @param pVM The cross context VM structure.
1294	*/
1295	static int hmR3InitFinalizeR0Intel(PVM pVM)
1296	{
1297	int rc;
1298
1299	Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1300	AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1301
1302	uint64_t val;
1303	uint64_t zap;
1304
1305	LogRel(("HM: Using VT-x implementation 2.0\n"));
1306	LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1307	LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1308	LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1309	LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1310	if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1311	LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1312	LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1313	LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1314	LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1315	LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1316	LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1317	LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1318	LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1319	LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1320	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1321
1322	LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1323	val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1324	zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1325	HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1326	HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1327	HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1328	HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1329	HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1330
1331	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1332	val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1333	zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1334	HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1335	HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1336	HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1337	HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1338	HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1339	HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1340	HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1341	HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1342	HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1343	HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1344	HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1345	HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1346	HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1347	HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1348	HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1349	HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1350	HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1351	HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1352	HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1353	HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1354	HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1355	if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1356	{
1357	LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1358	val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1359	zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1360	HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1361	HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1362	HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1363	HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1364	HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1365	HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1366	HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1367	HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1368	HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1369	HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1370	HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1371	HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1372	HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1373	HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1374	HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1375	HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1376	HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1377	HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1378	HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1379	HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1380	HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1381	HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1382	}
1383
1384	LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1385	val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1386	zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1387	HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1388	HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1389	HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1390	HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1391	HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1392	HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1393	HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1394
1395	LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1396	val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1397	zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1398	HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1399	HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1400	HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1401	HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1402	HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1403	HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1404	HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1405	HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1406	HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1407
1408	if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1409	{
1410	val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1411	LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1412	HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1413	HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1414	HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1415	HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1416	HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1417	HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1418	HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1419	HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1420	HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1421	HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1422	HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1423	HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1424	HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1425	HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1426	HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1427	}
1428
1429	val = pVM->hm.s.vmx.Msrs.u64Misc;
1430	LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1431	if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1432	LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1433	else
1434	{
1435	LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1436	MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1437	}
1438
1439	LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1440	LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1441	LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1442	LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1443	LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1444	LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1445	LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1446	LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1447
1448	/* Paranoia */
1449	AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1450
1451	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1452	LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1453	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1454	LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1455
1456	val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1457	LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1458	LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1459
1460	val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1461	if (val)
1462	{
1463	LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
1464	HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1465	}
1466
1467	LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1468
1469	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1470	{
1471	LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1472	LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1473	}
1474
1475	/*
1476	* EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1477	*/
1478	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1479	\|\| (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1480	VERR_HM_IPE_1);
1481	AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1482	\|\| ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1483	&& pVM->hm.s.fNestedPaging),
1484	VERR_HM_IPE_1);
1485
1486	/*
1487	* Enable VPID if configured and supported.
1488	*/
1489	if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1490	pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1491
1492	#if 0
1493	/*
1494	* Enable APIC register virtualization and virtual-interrupt delivery if supported.
1495	*/
1496	if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1497	&& (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1498	pVM->hm.s.fVirtApicRegs = true;
1499
1500	/*
1501	* Enable posted-interrupt processing if supported.
1502	*/
1503	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1504	* here. */
1505	if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1506	&& (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1507	pVM->hm.s.fPostedIntrs = true;
1508	#endif
1509
1510	/*
1511	* Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1512	* RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1513	* in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1514	*/
1515	if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1516	&& CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1517	{
1518	CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1519	LogRel(("HM: Disabled RDTSCP\n"));
1520	}
1521
1522	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1523	{
1524	/* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1525	rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1526	if (RT_SUCCESS(rc))
1527	{
1528	/* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1529	Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1530	esp. Figure 20-5.*/
1531	ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1532	pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1533
1534	/* Bit set to 0 means software interrupts are redirected to the
1535	8086 program interrupt handler rather than switching to
1536	protected-mode handler. */
1537	memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1538
1539	/* Allow all port IO, so that port IO instructions do not cause
1540	exceptions and would instead cause a VM-exit (based on VT-x's
1541	IO bitmap which we currently configure to always cause an exit). */
1542	memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1543	((unsigned char )pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1544
1545	/*
1546	* Construct a 1024 element page directory with 4 MB pages for
1547	* the identity mapped page table used in real and protected mode
1548	* without paging with EPT.
1549	*/
1550	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char )pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE 3);
1551	for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1552	{
1553	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1554	pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u \|= X86_PDE4M_P \| X86_PDE4M_RW \| X86_PDE4M_US
1555	\| X86_PDE4M_A \| X86_PDE4M_D \| X86_PDE4M_PS
1556	\| X86_PDE4M_G;
1557	}
1558
1559	/* We convert it here every time as PCI regions could be reconfigured. */
1560	if (PDMVmmDevHeapIsEnabled(pVM))
1561	{
1562	RTGCPHYS GCPhys;
1563	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1564	AssertRCReturn(rc, rc);
1565	LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1566
1567	rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1568	AssertRCReturn(rc, rc);
1569	LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1570	}
1571	}
1572	else
1573	{
1574	LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1575	pVM->hm.s.vmx.pRealModeTSS = NULL;
1576	pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1577	return VMSetError(pVM, rc, RT_SRC_POS,
1578	"HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1579	}
1580	}
1581
1582	LogRel((pVM->hm.s.fAllow64BitGuests
1583	? "HM: Guest support: 32-bit and 64-bit\n"
1584	: "HM: Guest support: 32-bit only\n"));
1585
1586	/*
1587	* Call ring-0 to set up the VM.
1588	*/
1589	rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu /, VMMR0_DO_HM_SETUP_VM, 0 / u64Arg /, NULL / pReqHdr */);
1590	if (rc != VINF_SUCCESS)
1591	{
1592	AssertMsgFailed(("%Rrc\n", rc));
1593	LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1594	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1595	{
1596	PVMCPU pVCpu = &pVM->aCpus[i];
1597	LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1598	LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1599	}
1600	HMR3CheckError(pVM, rc);
1601	return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1602	}
1603
1604	LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1605	LogRel(("HM: Enabled VMX\n"));
1606	pVM->hm.s.vmx.fEnabled = true;
1607
1608	hmR3DisableRawMode(pVM); /** @todo make this go away! */
1609
1610	/*
1611	* Change the CPU features.
1612	*/
1613	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1614	if (pVM->hm.s.fAllow64BitGuests)
1615	{
1616	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1617	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1618	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1619	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1620	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1621	}
1622	/* Turn on NXE if PAE has been enabled and the host has turned on NXE
1623	(we reuse the host EFER in the switcher). */
1624	/** @todo this needs to be fixed properly!! */
1625	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1626	{
1627	if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1628	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1629	else
1630	LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1631	}
1632
1633	/*
1634	* Log configuration details.
1635	*/
1636	if (pVM->hm.s.fNestedPaging)
1637	{
1638	LogRel(("HM: Enabled nested paging\n"));
1639	if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1640	LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1641	else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1642	LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1643	else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1644	LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1645	else
1646	LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1647
1648	if (pVM->hm.s.vmx.fUnrestrictedGuest)
1649	LogRel(("HM: Enabled unrestricted guest execution\n"));
1650
1651	#if HC_ARCH_BITS == 64
1652	if (pVM->hm.s.fLargePages)
1653	{
1654	/* Use large (2 MB) pages for our EPT PDEs where possible. */
1655	PGMSetLargePageUsage(pVM, true);
1656	LogRel(("HM: Enabled large page support\n"));
1657	}
1658	#endif
1659	}
1660	else
1661	Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1662
1663	if (pVM->hm.s.fVirtApicRegs)
1664	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1665
1666	if (pVM->hm.s.fPostedIntrs)
1667	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1668
1669	if (pVM->hm.s.vmx.fVpid)
1670	{
1671	LogRel(("HM: Enabled VPID\n"));
1672	if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1673	LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1674	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1675	LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1676	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1677	LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1678	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1679	LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1680	else
1681	LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1682	}
1683	else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1684	LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1685
1686	if (pVM->hm.s.vmx.fUsePreemptTimer)
1687	LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1688	else
1689	LogRel(("HM: Disabled VMX-preemption timer\n"));
1690
1691	return VINF_SUCCESS;
1692	}
1693
1694
1695	/**
1696	* Finish AMD-V initialization (after ring-0 init).
1697	*
1698	* @returns VBox status code.
1699	* @param pVM The cross context VM structure.
1700	*/
1701	static int hmR3InitFinalizeR0Amd(PVM pVM)
1702	{
1703	Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1704
1705	LogRel(("HM: Using AMD-V implementation 2.0\n"));
1706
1707	uint32_t u32Family;
1708	uint32_t u32Model;
1709	uint32_t u32Stepping;
1710	if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1711	LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1712	LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1713	LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1714	LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1715	LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1716	LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1717	LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1718	LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1719
1720	/*
1721	* Enumerate AMD-V features.
1722	*/
1723	static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1724	{
1725	#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1726	HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1727	HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1728	HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1729	HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1730	HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1731	HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1732	HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1733	HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1734	HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1735	HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1736	HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1737	HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1738	HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1739	#undef HMSVM_REPORT_FEATURE
1740	};
1741
1742	uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1743	for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1744	if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1745	{
1746	LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1747	fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1748	}
1749	if (fSvmFeatures)
1750	for (unsigned iBit = 0; iBit < 32; iBit++)
1751	if (RT_BIT_32(iBit) & fSvmFeatures)
1752	LogRel(("HM: Reserved bit %u\n", iBit));
1753
1754	/*
1755	* SVM R0 code assumes if the decode-assist feature exists, NRIP feature exists too.
1756	*/
1757	AssertLogRelReturn( !(pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS)
1758	\|\| (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1759	VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO);
1760
1761	/*
1762	* Nested paging is determined in HMR3Init, verify the sanity of that.
1763	*/
1764	AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1765	\|\| (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1766	VERR_HM_IPE_1);
1767
1768	#if 0
1769	/** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1770	* here. */
1771	if (RTR0IsPostIpiSupport())
1772	pVM->hm.s.fPostedIntrs = true;
1773	#endif
1774
1775	/*
1776	* Call ring-0 to set up the VM.
1777	*/
1778	int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /idCpu/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1779	if (rc != VINF_SUCCESS)
1780	{
1781	AssertMsgFailed(("%Rrc\n", rc));
1782	LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1783	return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1784	}
1785
1786	LogRel(("HM: Enabled SVM\n"));
1787	pVM->hm.s.svm.fEnabled = true;
1788
1789	if (pVM->hm.s.fNestedPaging)
1790	{
1791	LogRel(("HM: Enabled nested paging\n"));
1792
1793	/*
1794	* Enable large pages (2 MB) if applicable.
1795	*/
1796	#if HC_ARCH_BITS == 64
1797	if (pVM->hm.s.fLargePages)
1798	{
1799	PGMSetLargePageUsage(pVM, true);
1800	LogRel(("HM: Enabled large page support\n"));
1801	}
1802	#endif
1803	}
1804
1805	if (pVM->hm.s.fVirtApicRegs)
1806	LogRel(("HM: Enabled APIC-register virtualization support\n"));
1807
1808	if (pVM->hm.s.fPostedIntrs)
1809	LogRel(("HM: Enabled posted-interrupt processing support\n"));
1810
1811	hmR3DisableRawMode(pVM);
1812
1813	/*
1814	* Change the CPU features.
1815	*/
1816	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1817	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1818	if (pVM->hm.s.fAllow64BitGuests)
1819	{
1820	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1821	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1822	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1823	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1824	}
1825	/* Turn on NXE if PAE has been enabled. */
1826	else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1827	CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1828
1829	LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1830
1831	LogRel((pVM->hm.s.fAllow64BitGuests
1832	? "HM: Guest support: 32-bit and 64-bit\n"
1833	: "HM: Guest support: 32-bit only\n"));
1834
1835	return VINF_SUCCESS;
1836	}
1837
1838
1839	/**
1840	* Applies relocations to data and code managed by this
1841	* component. This function will be called at init and
1842	* whenever the VMM need to relocate it self inside the GC.
1843	*
1844	* @param pVM The cross context VM structure.
1845	*/
1846	VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1847	{
1848	Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1849
1850	/* Fetch the current paging mode during the relocate callback during state loading. */
1851	if (VMR3GetState(pVM) == VMSTATE_LOADING)
1852	{
1853	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1854	{
1855	PVMCPU pVCpu = &pVM->aCpus[i];
1856	pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1857	}
1858	}
1859	#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1860	if (HMIsEnabled(pVM))
1861	{
1862	switch (PGMGetHostMode(pVM))
1863	{
1864	case PGMMODE_32_BIT:
1865	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1866	break;
1867
1868	case PGMMODE_PAE:
1869	case PGMMODE_PAE_NX:
1870	pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1871	break;
1872
1873	default:
1874	AssertFailed();
1875	break;
1876	}
1877	}
1878	#endif
1879	return;
1880	}
1881
1882
1883	/**
1884	* Notification callback which is called whenever there is a chance that a CR3
1885	* value might have changed.
1886	*
1887	* This is called by PGM.
1888	*
1889	* @param pVM The cross context VM structure.
1890	* @param pVCpu The cross context virtual CPU structure.
1891	* @param enmShadowMode New shadow paging mode.
1892	* @param enmGuestMode New guest paging mode.
1893	*/
1894	VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1895	{
1896	RT_NOREF_PV(pVM);
1897
1898	/* Ignore page mode changes during state loading. */
1899	if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1900	return;
1901
1902	pVCpu->hm.s.enmShadowMode = enmShadowMode;
1903
1904	/*
1905	* If the guest left protected mode VMX execution, we'll have to be
1906	* extra careful if/when the guest switches back to protected mode.
1907	*/
1908	if (enmGuestMode == PGMMODE_REAL)
1909	pVCpu->hm.s.vmx.fWasInRealMode = true;
1910
1911	Log4(("HMR3PagingModeChanged: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
1912	PGMGetModeName(enmShadowMode)));
1913	}
1914
1915
1916	/**
1917	* Terminates the HM.
1918	*
1919	* Termination means cleaning up and freeing all resources,
1920	* the VM itself is, at this point, powered off or suspended.
1921	*
1922	* @returns VBox status code.
1923	* @param pVM The cross context VM structure.
1924	*/
1925	VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1926	{
1927	if (pVM->hm.s.vmx.pRealModeTSS)
1928	{
1929	PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1930	pVM->hm.s.vmx.pRealModeTSS = 0;
1931	}
1932	hmR3TermCPU(pVM);
1933	return 0;
1934	}
1935
1936
1937	/**
1938	* Terminates the per-VCPU HM.
1939	*
1940	* @returns VBox status code.
1941	* @param pVM The cross context VM structure.
1942	*/
1943	static int hmR3TermCPU(PVM pVM)
1944	{
1945	for (VMCPUID i = 0; i < pVM->cCpus; i++)
1946	{
1947	PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1948
1949	#ifdef VBOX_WITH_STATISTICS
1950	if (pVCpu->hm.s.paStatExitReason)
1951	{
1952	MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1953	pVCpu->hm.s.paStatExitReason = NULL;
1954	pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1955	}
1956	if (pVCpu->hm.s.paStatInjectedIrqs)
1957	{
1958	MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1959	pVCpu->hm.s.paStatInjectedIrqs = NULL;
1960	pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1961	}
1962	#endif
1963
1964	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1965	memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1966	pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1967	pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1968	#endif
1969	}
1970	return 0;
1971	}
1972
1973
1974	/**
1975	* Resets a virtual CPU.
1976	*
1977	* Used by HMR3Reset and CPU hot plugging.
1978	*
1979	* @param pVCpu The cross context virtual CPU structure to reset.
1980	*/
1981	VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
1982	{
1983	/* Sync. entire state on VM reset R0-reentry. It's safe to reset
1984	the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
1985	HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT \| HM_CHANGED_ALL_GUEST);
1986
1987	pVCpu->hm.s.vmx.u32CR0Mask = 0;
1988	pVCpu->hm.s.vmx.u32CR4Mask = 0;
1989	pVCpu->hm.s.fActive = false;
1990	pVCpu->hm.s.Event.fPending = false;
1991	pVCpu->hm.s.vmx.fWasInRealMode = true;
1992	pVCpu->hm.s.vmx.u64MsrApicBase = 0;
1993	pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
1994
1995	/* Reset the contents of the read cache. */
1996	PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1997	for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
1998	pCache->Read.aFieldVal[j] = 0;
1999
2000	#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2001	/* Magic marker for searching in crash dumps. */
2002	strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
2003	pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2004	#endif
2005	}
2006
2007
2008	/**
2009	* The VM is being reset.
2010	*
2011	* For the HM component this means that any GDT/LDT/TSS monitors
2012	* needs to be removed.
2013	*
2014	* @param pVM The cross context VM structure.
2015	*/
2016	VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2017	{
2018	LogFlow(("HMR3Reset:\n"));
2019
2020	if (HMIsEnabled(pVM))
2021	hmR3DisableRawMode(pVM);
2022
2023	for (VMCPUID i = 0; i < pVM->cCpus; i++)
2024	{
2025	PVMCPU pVCpu = &pVM->aCpus[i];
2026
2027	HMR3ResetCpu(pVCpu);
2028	}
2029
2030	/* Clear all patch information. */
2031	pVM->hm.s.pGuestPatchMem = 0;
2032	pVM->hm.s.pFreeGuestPatchMem = 0;
2033	pVM->hm.s.cbGuestPatchMem = 0;
2034	pVM->hm.s.cPatches = 0;
2035	pVM->hm.s.PatchTree = 0;
2036	pVM->hm.s.fTPRPatchingActive = false;
2037	ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2038	}
2039
2040
2041	/**
2042	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2043	*
2044	* @returns VBox strict status code.
2045	* @param pVM The cross context VM structure.
2046	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2047	* @param pvUser Unused.
2048	*/
2049	static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2050	{
2051	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2052
2053	/* Only execute the handler on the VCPU the original patch request was issued. */
2054	if (pVCpu->idCpu != idCpu)
2055	return VINF_SUCCESS;
2056
2057	Log(("hmR3RemovePatches\n"));
2058	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2059	{
2060	uint8_t abInstr[15];
2061	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2062	RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2063	int rc;
2064
2065	#ifdef LOG_ENABLED
2066	char szOutput[256];
2067
2068	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2069	szOutput, sizeof(szOutput), NULL);
2070	if (RT_SUCCESS(rc))
2071	Log(("Patched instr: %s\n", szOutput));
2072	#endif
2073
2074	/* Check if the instruction is still the same. */
2075	rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2076	if (rc != VINF_SUCCESS)
2077	{
2078	Log(("Patched code removed? (rc=%Rrc0\n", rc));
2079	continue; /* swapped out or otherwise removed; skip it. */
2080	}
2081
2082	if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2083	{
2084	Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2085	continue; /* skip it. */
2086	}
2087
2088	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2089	AssertRC(rc);
2090
2091	#ifdef LOG_ENABLED
2092	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2093	szOutput, sizeof(szOutput), NULL);
2094	if (RT_SUCCESS(rc))
2095	Log(("Original instr: %s\n", szOutput));
2096	#endif
2097	}
2098	pVM->hm.s.cPatches = 0;
2099	pVM->hm.s.PatchTree = 0;
2100	pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2101	pVM->hm.s.fTPRPatchingActive = false;
2102	return VINF_SUCCESS;
2103	}
2104
2105
2106	/**
2107	* Worker for enabling patching in a VT-x/AMD-V guest.
2108	*
2109	* @returns VBox status code.
2110	* @param pVM The cross context VM structure.
2111	* @param idCpu VCPU to execute hmR3RemovePatches on.
2112	* @param pPatchMem Patch memory range.
2113	* @param cbPatchMem Size of the memory range.
2114	*/
2115	static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2116	{
2117	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2118	AssertRC(rc);
2119
2120	pVM->hm.s.pGuestPatchMem = pPatchMem;
2121	pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2122	pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2123	return VINF_SUCCESS;
2124	}
2125
2126
2127	/**
2128	* Enable patching in a VT-x/AMD-V guest
2129	*
2130	* @returns VBox status code.
2131	* @param pVM The cross context VM structure.
2132	* @param pPatchMem Patch memory range.
2133	* @param cbPatchMem Size of the memory range.
2134	*/
2135	VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2136	{
2137	VM_ASSERT_EMT(pVM);
2138	Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2139	if (pVM->cCpus > 1)
2140	{
2141	/* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2142	int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2143	(PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2144	AssertRC(rc);
2145	return rc;
2146	}
2147	return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2148	}
2149
2150
2151	/**
2152	* Disable patching in a VT-x/AMD-V guest.
2153	*
2154	* @returns VBox status code.
2155	* @param pVM The cross context VM structure.
2156	* @param pPatchMem Patch memory range.
2157	* @param cbPatchMem Size of the memory range.
2158	*/
2159	VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2160	{
2161	Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2162	RT_NOREF2(pPatchMem, cbPatchMem);
2163
2164	Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2165	Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2166
2167	/** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2168	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2169	(void *)(uintptr_t)VMMGetCpuId(pVM));
2170	AssertRC(rc);
2171
2172	pVM->hm.s.pGuestPatchMem = 0;
2173	pVM->hm.s.pFreeGuestPatchMem = 0;
2174	pVM->hm.s.cbGuestPatchMem = 0;
2175	pVM->hm.s.fTPRPatchingActive = false;
2176	return VINF_SUCCESS;
2177	}
2178
2179
2180	/**
2181	* Callback to patch a TPR instruction (vmmcall or mov cr8).
2182	*
2183	* @returns VBox strict status code.
2184	* @param pVM The cross context VM structure.
2185	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2186	* @param pvUser User specified CPU context.
2187	*
2188	*/
2189	static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2190	{
2191	/*
2192	* Only execute the handler on the VCPU the original patch request was
2193	* issued. (The other CPU(s) might not yet have switched to protected
2194	* mode, nor have the correct memory context.)
2195	*/
2196	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2197	if (pVCpu->idCpu != idCpu)
2198	return VINF_SUCCESS;
2199
2200	/*
2201	* We're racing other VCPUs here, so don't try patch the instruction twice
2202	* and make sure there is still room for our patch record.
2203	*/
2204	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2205	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2206	if (pPatch)
2207	{
2208	Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2209	return VINF_SUCCESS;
2210	}
2211	uint32_t const idx = pVM->hm.s.cPatches;
2212	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2213	{
2214	Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2215	return VINF_SUCCESS;
2216	}
2217	pPatch = &pVM->hm.s.aPatches[idx];
2218
2219	Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2220
2221	/*
2222	* Disassembler the instruction and get cracking.
2223	*/
2224	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2225	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2226	uint32_t cbOp;
2227	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2228	AssertRC(rc);
2229	if ( rc == VINF_SUCCESS
2230	&& pDis->pCurInstr->uOpcode == OP_MOV
2231	&& cbOp >= 3)
2232	{
2233	static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2234
2235	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2236	AssertRC(rc);
2237
2238	pPatch->cbOp = cbOp;
2239
2240	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2241	{
2242	/* write. */
2243	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2244	{
2245	pPatch->enmType = HMTPRINSTR_WRITE_REG;
2246	pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2247	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2248	}
2249	else
2250	{
2251	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2252	pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2253	pPatch->uSrcOperand = pDis->Param2.uValue;
2254	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2255	}
2256	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2257	AssertRC(rc);
2258
2259	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2260	pPatch->cbNewOp = sizeof(s_abVMMCall);
2261	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2262	}
2263	else
2264	{
2265	/*
2266	* TPR Read.
2267	*
2268	* Found:
2269	* mov eax, dword [fffe0080] (5 bytes)
2270	* Check if next instruction is:
2271	* shr eax, 4
2272	*/
2273	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2274
2275	uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2276	uint8_t const cbOpMmio = cbOp;
2277	uint64_t const uSavedRip = pCtx->rip;
2278
2279	pCtx->rip += cbOp;
2280	rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2281	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2282	pCtx->rip = uSavedRip;
2283
2284	if ( rc == VINF_SUCCESS
2285	&& pDis->pCurInstr->uOpcode == OP_SHR
2286	&& pDis->Param1.fUse == DISUSE_REG_GEN32
2287	&& pDis->Param1.Base.idxGenReg == idxMmioReg
2288	&& pDis->Param2.fUse == DISUSE_IMMEDIATE8
2289	&& pDis->Param2.uValue == 4
2290	&& cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2291	{
2292	uint8_t abInstr[15];
2293
2294	/* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2295	access CR8 in 32-bit mode and not cause a #VMEXIT. */
2296	rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2297	AssertRC(rc);
2298
2299	pPatch->cbOp = cbOpMmio + cbOp;
2300
2301	/* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2302	abInstr[0] = 0xF0;
2303	abInstr[1] = 0x0F;
2304	abInstr[2] = 0x20;
2305	abInstr[3] = 0xC0 \| pDis->Param1.Base.idxGenReg;
2306	for (unsigned i = 4; i < pPatch->cbOp; i++)
2307	abInstr[i] = 0x90; /* nop */
2308
2309	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2310	AssertRC(rc);
2311
2312	memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2313	pPatch->cbNewOp = pPatch->cbOp;
2314	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2315
2316	Log(("Acceptable read/shr candidate!\n"));
2317	pPatch->enmType = HMTPRINSTR_READ_SHR4;
2318	}
2319	else
2320	{
2321	pPatch->enmType = HMTPRINSTR_READ;
2322	pPatch->uDstOperand = idxMmioReg;
2323
2324	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2325	AssertRC(rc);
2326
2327	memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2328	pPatch->cbNewOp = sizeof(s_abVMMCall);
2329	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2330	Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2331	}
2332	}
2333
2334	pPatch->Core.Key = pCtx->eip;
2335	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2336	AssertRC(rc);
2337
2338	pVM->hm.s.cPatches++;
2339	return VINF_SUCCESS;
2340	}
2341
2342	/*
2343	* Save invalid patch, so we will not try again.
2344	*/
2345	Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2346	pPatch->Core.Key = pCtx->eip;
2347	pPatch->enmType = HMTPRINSTR_INVALID;
2348	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2349	AssertRC(rc);
2350	pVM->hm.s.cPatches++;
2351	STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2352	return VINF_SUCCESS;
2353	}
2354
2355
2356	/**
2357	* Callback to patch a TPR instruction (jump to generated code).
2358	*
2359	* @returns VBox strict status code.
2360	* @param pVM The cross context VM structure.
2361	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
2362	* @param pvUser User specified CPU context.
2363	*
2364	*/
2365	static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2366	{
2367	/*
2368	* Only execute the handler on the VCPU the original patch request was
2369	* issued. (The other CPU(s) might not yet have switched to protected
2370	* mode, nor have the correct memory context.)
2371	*/
2372	VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2373	if (pVCpu->idCpu != idCpu)
2374	return VINF_SUCCESS;
2375
2376	/*
2377	* We're racing other VCPUs here, so don't try patch the instruction twice
2378	* and make sure there is still room for our patch record.
2379	*/
2380	PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2381	PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2382	if (pPatch)
2383	{
2384	Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2385	return VINF_SUCCESS;
2386	}
2387	uint32_t const idx = pVM->hm.s.cPatches;
2388	if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2389	{
2390	Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2391	return VINF_SUCCESS;
2392	}
2393	pPatch = &pVM->hm.s.aPatches[idx];
2394
2395	Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2396	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2397
2398	/*
2399	* Disassemble the instruction and get cracking.
2400	*/
2401	PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2402	uint32_t cbOp;
2403	int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2404	AssertRC(rc);
2405	if ( rc == VINF_SUCCESS
2406	&& pDis->pCurInstr->uOpcode == OP_MOV
2407	&& cbOp >= 5)
2408	{
2409	uint8_t aPatch[64];
2410	uint32_t off = 0;
2411
2412	rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2413	AssertRC(rc);
2414
2415	pPatch->cbOp = cbOp;
2416	pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2417
2418	if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2419	{
2420	/*
2421	* TPR write:
2422	*
2423	* push ECX [51]
2424	* push EDX [52]
2425	* push EAX [50]
2426	* xor EDX,EDX [31 D2]
2427	* mov EAX,EAX [89 C0]
2428	* or
2429	* mov EAX,0000000CCh [B8 CC 00 00 00]
2430	* mov ECX,0C0000082h [B9 82 00 00 C0]
2431	* wrmsr [0F 30]
2432	* pop EAX [58]
2433	* pop EDX [5A]
2434	* pop ECX [59]
2435	* jmp return_address [E9 return_address]
2436	*
2437	*/
2438	bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2439
2440	aPatch[off++] = 0x51; /* push ecx */
2441	aPatch[off++] = 0x52; /* push edx */
2442	if (!fUsesEax)
2443	aPatch[off++] = 0x50; /* push eax */
2444	aPatch[off++] = 0x31; /* xor edx, edx */
2445	aPatch[off++] = 0xD2;
2446	if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2447	{
2448	if (!fUsesEax)
2449	{
2450	aPatch[off++] = 0x89; /* mov eax, src_reg */
2451	aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2452	}
2453	}
2454	else
2455	{
2456	Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2457	aPatch[off++] = 0xB8; /* mov eax, immediate */
2458	(uint32_t )&aPatch[off] = pDis->Param2.uValue;
2459	off += sizeof(uint32_t);
2460	}
2461	aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2462	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2463	off += sizeof(uint32_t);
2464
2465	aPatch[off++] = 0x0F; /* wrmsr */
2466	aPatch[off++] = 0x30;
2467	if (!fUsesEax)
2468	aPatch[off++] = 0x58; /* pop eax */
2469	aPatch[off++] = 0x5A; /* pop edx */
2470	aPatch[off++] = 0x59; /* pop ecx */
2471	}
2472	else
2473	{
2474	/*
2475	* TPR read:
2476	*
2477	* push ECX [51]
2478	* push EDX [52]
2479	* push EAX [50]
2480	* mov ECX,0C0000082h [B9 82 00 00 C0]
2481	* rdmsr [0F 32]
2482	* mov EAX,EAX [89 C0]
2483	* pop EAX [58]
2484	* pop EDX [5A]
2485	* pop ECX [59]
2486	* jmp return_address [E9 return_address]
2487	*
2488	*/
2489	Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2490
2491	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2492	aPatch[off++] = 0x51; /* push ecx */
2493	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2494	aPatch[off++] = 0x52; /* push edx */
2495	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2496	aPatch[off++] = 0x50; /* push eax */
2497
2498	aPatch[off++] = 0x31; /* xor edx, edx */
2499	aPatch[off++] = 0xD2;
2500
2501	aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2502	(uint32_t )&aPatch[off] = MSR_K8_LSTAR;
2503	off += sizeof(uint32_t);
2504
2505	aPatch[off++] = 0x0F; /* rdmsr */
2506	aPatch[off++] = 0x32;
2507
2508	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2509	{
2510	aPatch[off++] = 0x89; /* mov dst_reg, eax */
2511	aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2512	}
2513
2514	if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2515	aPatch[off++] = 0x58; /* pop eax */
2516	if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2517	aPatch[off++] = 0x5A; /* pop edx */
2518	if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2519	aPatch[off++] = 0x59; /* pop ecx */
2520	}
2521	aPatch[off++] = 0xE9; /* jmp return_address */
2522	(RTRCUINTPTR )&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2523	off += sizeof(RTRCUINTPTR);
2524
2525	if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2526	{
2527	/* Write new code to the patch buffer. */
2528	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2529	AssertRC(rc);
2530
2531	#ifdef LOG_ENABLED
2532	uint32_t cbCurInstr;
2533	for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2534	GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2535	GCPtrInstr += RT_MAX(cbCurInstr, 1))
2536	{
2537	char szOutput[256];
2538	rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2539	szOutput, sizeof(szOutput), &cbCurInstr);
2540	if (RT_SUCCESS(rc))
2541	Log(("Patch instr %s\n", szOutput));
2542	else
2543	Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2544	}
2545	#endif
2546
2547	pPatch->aNewOpcode[0] = 0xE9;
2548	(RTRCUINTPTR )&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2549
2550	/* Overwrite the TPR instruction with a jump. */
2551	rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2552	AssertRC(rc);
2553
2554	DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2555
2556	pVM->hm.s.pFreeGuestPatchMem += off;
2557	pPatch->cbNewOp = 5;
2558
2559	pPatch->Core.Key = pCtx->eip;
2560	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2561	AssertRC(rc);
2562
2563	pVM->hm.s.cPatches++;
2564	pVM->hm.s.fTPRPatchingActive = true;
2565	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2566	return VINF_SUCCESS;
2567	}
2568
2569	Log(("Ran out of space in our patch buffer!\n"));
2570	}
2571	else
2572	Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2573
2574
2575	/*
2576	* Save invalid patch, so we will not try again.
2577	*/
2578	pPatch = &pVM->hm.s.aPatches[idx];
2579	pPatch->Core.Key = pCtx->eip;
2580	pPatch->enmType = HMTPRINSTR_INVALID;
2581	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2582	AssertRC(rc);
2583	pVM->hm.s.cPatches++;
2584	STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2585	return VINF_SUCCESS;
2586	}
2587
2588
2589	/**
2590	* Attempt to patch TPR mmio instructions.
2591	*
2592	* @returns VBox status code.
2593	* @param pVM The cross context VM structure.
2594	* @param pVCpu The cross context virtual CPU structure.
2595	* @param pCtx Pointer to the guest CPU context.
2596	*/
2597	VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2598	{
2599	NOREF(pCtx);
2600	int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2601	pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2602	(void *)(uintptr_t)pVCpu->idCpu);
2603	AssertRC(rc);
2604	return rc;
2605	}
2606
2607
2608	/**
2609	* Checks if a code selector (CS) is suitable for execution
2610	* within VMX when unrestricted execution isn't available.
2611	*
2612	* @returns true if selector is suitable for VMX, otherwise
2613	* false.
2614	* @param pSel Pointer to the selector to check (CS).
2615	* @param uStackDpl The CPL, aka the DPL of the stack segment.
2616	*/
2617	static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2618	{
2619	/*
2620	* Segment must be an accessed code segment, it must be present and it must
2621	* be usable.
2622	* Note! These are all standard requirements and if CS holds anything else
2623	* we've got buggy code somewhere!
2624	*/
2625	AssertCompile(X86DESCATTR_TYPE == 0xf);
2626	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86DESCATTR_UNUSABLE))
2627	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_CODE \| X86DESCATTR_DT \| X86DESCATTR_P),
2628	("%#x\n", pSel->Attr.u),
2629	false);
2630
2631	/* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2632	must equal SS.DPL for non-confroming segments.
2633	Note! This is also a hard requirement like above. */
2634	AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2635	? pSel->Attr.n.u2Dpl <= uStackDpl
2636	: pSel->Attr.n.u2Dpl == uStackDpl,
2637	("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2638	false);
2639
2640	/*
2641	* The following two requirements are VT-x specific:
2642	* - G bit must be set if any high limit bits are set.
2643	* - G bit must be clear if any low limit bits are clear.
2644	*/
2645	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
2646	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity) )
2647	return true;
2648	return false;
2649	}
2650
2651
2652	/**
2653	* Checks if a data selector (DS/ES/FS/GS) is suitable for
2654	* execution within VMX when unrestricted execution isn't
2655	* available.
2656	*
2657	* @returns true if selector is suitable for VMX, otherwise
2658	* false.
2659	* @param pSel Pointer to the selector to check
2660	* (DS/ES/FS/GS).
2661	*/
2662	static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2663	{
2664	/*
2665	* Unusable segments are OK. These days they should be marked as such, as
2666	* but as an alternative we for old saved states and AMD<->VT-x migration
2667	* we also treat segments with all the attributes cleared as unusable.
2668	*/
2669	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
2670	return true;
2671
2672	/** @todo tighten these checks. Will require CPUM load adjusting. */
2673
2674	/* Segment must be accessed. */
2675	if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2676	{
2677	/* Code segments must also be readable. */
2678	if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2679	\|\| (pSel->Attr.u & X86_SEL_TYPE_READ))
2680	{
2681	/* The S bit must be set. */
2682	if (pSel->Attr.n.u1DescType)
2683	{
2684	/* Except for conforming segments, DPL >= RPL. */
2685	if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2686	\|\| pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2687	{
2688	/* Segment must be present. */
2689	if (pSel->Attr.n.u1Present)
2690	{
2691	/*
2692	* The following two requirements are VT-x specific:
2693	* - G bit must be set if any high limit bits are set.
2694	* - G bit must be clear if any low limit bits are clear.
2695	*/
2696	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
2697	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity) )
2698	return true;
2699	}
2700	}
2701	}
2702	}
2703	}
2704
2705	return false;
2706	}
2707
2708
2709	/**
2710	* Checks if the stack selector (SS) is suitable for execution
2711	* within VMX when unrestricted execution isn't available.
2712	*
2713	* @returns true if selector is suitable for VMX, otherwise
2714	* false.
2715	* @param pSel Pointer to the selector to check (SS).
2716	*/
2717	static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2718	{
2719	/*
2720	* Unusable segments are OK. These days they should be marked as such, as
2721	* but as an alternative we for old saved states and AMD<->VT-x migration
2722	* we also treat segments with all the attributes cleared as unusable.
2723	*/
2724	/** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2725	if (pSel->Attr.n.u1Unusable \|\| !pSel->Attr.u)
2726	return true;
2727
2728	/*
2729	* Segment must be an accessed writable segment, it must be present.
2730	* Note! These are all standard requirements and if SS holds anything else
2731	* we've got buggy code somewhere!
2732	*/
2733	AssertCompile(X86DESCATTR_TYPE == 0xf);
2734	AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P \| X86_SEL_TYPE_CODE))
2735	== (X86_SEL_TYPE_ACCESSED \| X86_SEL_TYPE_WRITE \| X86DESCATTR_DT \| X86DESCATTR_P),
2736	("%#x\n", pSel->Attr.u),
2737	false);
2738
2739	/* DPL must equal RPL.
2740	Note! This is also a hard requirement like above. */
2741	AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2742	("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2743	false);
2744
2745	/*
2746	* The following two requirements are VT-x specific:
2747	* - G bit must be set if any high limit bits are set.
2748	* - G bit must be clear if any low limit bits are clear.
2749	*/
2750	if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 \|\| pSel->Attr.n.u1Granularity)
2751	&& ((pSel->u32Limit & 0x00000fff) == 0x00000fff \|\| !pSel->Attr.n.u1Granularity) )
2752	return true;
2753	return false;
2754	}
2755
2756
2757	/**
2758	* Force execution of the current IO code in the recompiler.
2759	*
2760	* @returns VBox status code.
2761	* @param pVM The cross context VM structure.
2762	* @param pCtx Partial VM execution context.
2763	*/
2764	VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2765	{
2766	PVMCPU pVCpu = VMMGetCpu(pVM);
2767
2768	Assert(HMIsEnabled(pVM));
2769	Log(("HMR3EmulateIoBlock\n"));
2770
2771	/* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2772	if (HMCanEmulateIoBlockEx(pCtx))
2773	{
2774	Log(("HMR3EmulateIoBlock -> enabled\n"));
2775	pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2776	pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2777	pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2778	return VINF_EM_RESCHEDULE_REM;
2779	}
2780	return VINF_SUCCESS;
2781	}
2782
2783
2784	/**
2785	* Checks if we can currently use hardware accelerated raw mode.
2786	*
2787	* @returns true if we can currently use hardware acceleration, otherwise false.
2788	* @param pVM The cross context VM structure.
2789	* @param pCtx Partial VM execution context.
2790	*/
2791	VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2792	{
2793	PVMCPU pVCpu = VMMGetCpu(pVM);
2794
2795	Assert(HMIsEnabled(pVM));
2796
2797	#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
2798	if (CPUMIsGuestInNestedHwVirtMode(pCtx))
2799	{
2800	Log(("HMR3CanExecuteGuest: In nested-guest mode - returning false"));
2801	return false;
2802	}
2803	#endif
2804
2805	/* If we're still executing the IO code, then return false. */
2806	if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2807	&& pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2808	&& pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2809	&& pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2810	return false;
2811
2812	pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2813
2814	/* AMD-V supports real & protected mode with or without paging. */
2815	if (pVM->hm.s.svm.fEnabled)
2816	{
2817	pVCpu->hm.s.fActive = true;
2818	return true;
2819	}
2820
2821	pVCpu->hm.s.fActive = false;
2822
2823	/* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2824	Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2825	\|\| (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2826
2827	bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest \|\| PDMVmmDevHeapIsEnabled(pVM);
2828	if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2829	{
2830	/*
2831	* The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2832	* guest execution feature is missing (VT-x only).
2833	*/
2834	if (fSupportsRealMode)
2835	{
2836	if (CPUMIsGuestInRealModeEx(pCtx))
2837	{
2838	/* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2839	* bases and limits, i.e. limit must be 64K and base must be selector * 16.
2840	* If this is not true, we cannot execute real mode as V86 and have to fall
2841	* back to emulation.
2842	*/
2843	if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2844	\|\| pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2845	\|\| pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2846	\|\| pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2847	\|\| pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2848	\|\| pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2849	{
2850	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2851	return false;
2852	}
2853	if ( (pCtx->cs.u32Limit != 0xffff)
2854	\|\| (pCtx->ds.u32Limit != 0xffff)
2855	\|\| (pCtx->es.u32Limit != 0xffff)
2856	\|\| (pCtx->ss.u32Limit != 0xffff)
2857	\|\| (pCtx->fs.u32Limit != 0xffff)
2858	\|\| (pCtx->gs.u32Limit != 0xffff))
2859	{
2860	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2861	return false;
2862	}
2863	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2864	}
2865	else
2866	{
2867	/* Verify the requirements for executing code in protected
2868	mode. VT-x can't handle the CPU state right after a switch
2869	from real to protected mode. (all sorts of RPL & DPL assumptions). */
2870	if (pVCpu->hm.s.vmx.fWasInRealMode)
2871	{
2872	/** @todo If guest is in V86 mode, these checks should be different! */
2873	if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2874	{
2875	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2876	return false;
2877	}
2878	if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2879	\|\| !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2880	\|\| !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2881	\|\| !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2882	\|\| !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2883	\|\| !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2884	{
2885	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2886	return false;
2887	}
2888	}
2889	/* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2890	if (pCtx->gdtr.cbGdt)
2891	{
2892	if ((pCtx->tr.Sel \| X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2893	{
2894	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2895	return false;
2896	}
2897	else if ((pCtx->ldtr.Sel \| X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2898	{
2899	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2900	return false;
2901	}
2902	}
2903	STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2904	}
2905	}
2906	else
2907	{
2908	if ( !CPUMIsGuestInLongModeEx(pCtx)
2909	&& !pVM->hm.s.vmx.fUnrestrictedGuest)
2910	{
2911	if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real and protected mode without paging - stored in the VMM device heap */
2912	\|\| CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2913	return false;
2914
2915	/* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2916	if (pCtx->idtr.pIdt == 0 \|\| pCtx->idtr.cbIdt == 0 \|\| pCtx->tr.Sel == 0)
2917	return false;
2918
2919	/* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2920	/* Windows XP; switch to protected mode; all selectors are marked not present in the
2921	* hidden registers (possible recompiler bug; see load_seg_vm) */
2922	if (pCtx->cs.Attr.n.u1Present == 0)
2923	return false;
2924	if (pCtx->ss.Attr.n.u1Present == 0)
2925	return false;
2926
2927	/* Windows XP: possible same as above, but new recompiler requires new heuristics?
2928	VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2929	/** @todo This check is actually wrong, it doesn't take the direction of the
2930	* stack segment into account. But, it does the job for now. */
2931	if (pCtx->rsp >= pCtx->ss.u32Limit)
2932	return false;
2933	}
2934	}
2935	}
2936
2937	if (pVM->hm.s.vmx.fEnabled)
2938	{
2939	uint32_t mask;
2940
2941	/* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2942	mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2943	/* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2944	mask &= ~X86_CR0_NE;
2945
2946	if (fSupportsRealMode)
2947	{
2948	/* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2949	mask &= ~(X86_CR0_PG\|X86_CR0_PE);
2950	}
2951	else
2952	{
2953	/* We support protected mode without paging using identity mapping. */
2954	mask &= ~X86_CR0_PG;
2955	}
2956	if ((pCtx->cr0 & mask) != mask)
2957	return false;
2958
2959	/* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2960	mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2961	if ((pCtx->cr0 & mask) != 0)
2962	return false;
2963
2964	/* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2965	mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2966	mask &= ~X86_CR4_VMXE;
2967	if ((pCtx->cr4 & mask) != mask)
2968	return false;
2969
2970	/* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2971	mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2972	if ((pCtx->cr4 & mask) != 0)
2973	return false;
2974
2975	pVCpu->hm.s.fActive = true;
2976	return true;
2977	}
2978
2979	return false;
2980	}
2981
2982
2983	/**
2984	* Checks if we need to reschedule due to VMM device heap changes.
2985	*
2986	* @returns true if a reschedule is required, otherwise false.
2987	* @param pVM The cross context VM structure.
2988	* @param pCtx VM execution context.
2989	*/
2990	VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
2991	{
2992	/*
2993	* The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
2994	* when the unrestricted guest execution feature is missing (VT-x only).
2995	*/
2996	if ( pVM->hm.s.vmx.fEnabled
2997	&& !pVM->hm.s.vmx.fUnrestrictedGuest
2998	&& CPUMIsGuestInRealModeEx(pCtx)
2999	&& !PDMVmmDevHeapIsEnabled(pVM))
3000	{
3001	return true;
3002	}
3003
3004	return false;
3005	}
3006
3007
3008	/**
3009	* Noticiation callback from DBGF when interrupt breakpoints or generic debug
3010	* event settings changes.
3011	*
3012	* DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
3013	* function is just updating the VM globals.
3014	*
3015	* @param pVM The VM cross context VM structure.
3016	* @thread EMT(0)
3017	*/
3018	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
3019	{
3020	/* Interrupts. */
3021	bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
3022	\|\| pVM->dbgf.ro.cHardIntBreakpoints > 0;
3023
3024	/* CPU Exceptions. */
3025	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
3026	!fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
3027	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3028	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3029
3030	/* Common VM exits. */
3031	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
3032	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
3033	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3034	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3035
3036	/* Vendor specific VM exits. */
3037	if (HMR3IsVmxEnabled(pVM->pUVM))
3038	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
3039	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
3040	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3041	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3042	else
3043	for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
3044	!fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
3045	enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3046	fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3047
3048	/* Done. */
3049	pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
3050	}
3051
3052
3053	/**
3054	* Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
3055	*
3056	* HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
3057	* per CPU settings.
3058	*
3059	* @param pVM The VM cross context VM structure.
3060	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3061	*/
3062	VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
3063	{
3064	pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction \| pVM->hm.s.fUseDebugLoop;
3065	}
3066
3067
3068	/**
3069	* Notification from EM about a rescheduling into hardware assisted execution
3070	* mode.
3071	*
3072	* @param pVCpu The cross context virtual CPU structure of the calling EMT.
3073	*/
3074	VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
3075	{
3076	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3077	}
3078
3079
3080	/**
3081	* Notification from EM about returning from instruction emulation (REM / EM).
3082	*
3083	* @param pVCpu The cross context virtual CPU structure.
3084	*/
3085	VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
3086	{
3087	HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3088	}
3089
3090
3091	/**
3092	* Checks if we are currently using hardware acceleration.
3093	*
3094	* @returns true if hardware acceleration is being used, otherwise false.
3095	* @param pVCpu The cross context virtual CPU structure.
3096	*/
3097	VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
3098	{
3099	return pVCpu->hm.s.fActive;
3100	}
3101
3102
3103	/**
3104	* External interface for querying whether hardware acceleration is enabled.
3105	*
3106	* @returns true if VT-x or AMD-V is being used, otherwise false.
3107	* @param pUVM The user mode VM handle.
3108	* @sa HMIsEnabled, HMIsEnabledNotMacro.
3109	*/
3110	VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
3111	{
3112	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3113	PVM pVM = pUVM->pVM;
3114	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3115	return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
3116	}
3117
3118
3119	/**
3120	* External interface for querying whether VT-x is being used.
3121	*
3122	* @returns true if VT-x is being used, otherwise false.
3123	* @param pUVM The user mode VM handle.
3124	* @sa HMR3IsSvmEnabled, HMIsEnabled
3125	*/
3126	VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
3127	{
3128	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3129	PVM pVM = pUVM->pVM;
3130	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3131	return pVM->hm.s.vmx.fEnabled
3132	&& pVM->hm.s.vmx.fSupported
3133	&& pVM->fHMEnabled;
3134	}
3135
3136
3137	/**
3138	* External interface for querying whether AMD-V is being used.
3139	*
3140	* @returns true if VT-x is being used, otherwise false.
3141	* @param pUVM The user mode VM handle.
3142	* @sa HMR3IsVmxEnabled, HMIsEnabled
3143	*/
3144	VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3145	{
3146	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3147	PVM pVM = pUVM->pVM;
3148	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3149	return pVM->hm.s.svm.fEnabled
3150	&& pVM->hm.s.svm.fSupported
3151	&& pVM->fHMEnabled;
3152	}
3153
3154
3155	/**
3156	* Checks if we are currently using nested paging.
3157	*
3158	* @returns true if nested paging is being used, otherwise false.
3159	* @param pUVM The user mode VM handle.
3160	*/
3161	VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3162	{
3163	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3164	PVM pVM = pUVM->pVM;
3165	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3166	return pVM->hm.s.fNestedPaging;
3167	}
3168
3169
3170	/**
3171	* Checks if virtualized APIC registers is enabled.
3172	*
3173	* When enabled this feature allows the hardware to access most of the
3174	* APIC registers in the virtual-APIC page without causing VM-exits. See
3175	* Intel spec. 29.1.1 "Virtualized APIC Registers".
3176	*
3177	* @returns true if virtualized APIC registers is enabled, otherwise
3178	* false.
3179	* @param pUVM The user mode VM handle.
3180	*/
3181	VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3182	{
3183	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3184	PVM pVM = pUVM->pVM;
3185	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3186	return pVM->hm.s.fVirtApicRegs;
3187	}
3188
3189
3190	/**
3191	* Checks if APIC posted-interrupt processing is enabled.
3192	*
3193	* This returns whether we can deliver interrupts to the guest without
3194	* leaving guest-context by updating APIC state from host-context.
3195	*
3196	* @returns true if APIC posted-interrupt processing is enabled,
3197	* otherwise false.
3198	* @param pUVM The user mode VM handle.
3199	*/
3200	VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3201	{
3202	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3203	PVM pVM = pUVM->pVM;
3204	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3205	return pVM->hm.s.fPostedIntrs;
3206	}
3207
3208
3209	/**
3210	* Checks if we are currently using VPID in VT-x mode.
3211	*
3212	* @returns true if VPID is being used, otherwise false.
3213	* @param pUVM The user mode VM handle.
3214	*/
3215	VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3216	{
3217	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3218	PVM pVM = pUVM->pVM;
3219	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3220	return pVM->hm.s.vmx.fVpid;
3221	}
3222
3223
3224	/**
3225	* Checks if we are currently using VT-x unrestricted execution,
3226	* aka UX.
3227	*
3228	* @returns true if UX is being used, otherwise false.
3229	* @param pUVM The user mode VM handle.
3230	*/
3231	VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3232	{
3233	UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3234	PVM pVM = pUVM->pVM;
3235	VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3236	return pVM->hm.s.vmx.fUnrestrictedGuest;
3237	}
3238
3239
3240	/**
3241	* Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3242	*
3243	* @returns true if an internal event is pending, otherwise false.
3244	* @param pVCpu The cross context virtual CPU structure.
3245	*/
3246	VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3247	{
3248	return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3249	}
3250
3251
3252	/**
3253	* Checks if the VMX-preemption timer is being used.
3254	*
3255	* @returns true if the VMX-preemption timer is being used, otherwise false.
3256	* @param pVM The cross context VM structure.
3257	*/
3258	VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3259	{
3260	return HMIsEnabled(pVM)
3261	&& pVM->hm.s.vmx.fEnabled
3262	&& pVM->hm.s.vmx.fUsePreemptTimer;
3263	}
3264
3265
3266	/**
3267	* Restart an I/O instruction that was refused in ring-0
3268	*
3269	* @returns Strict VBox status code. Informational status codes other than the one documented
3270	* here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3271	* @retval VINF_SUCCESS Success.
3272	* @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3273	* status code must be passed on to EM.
3274	* @retval VERR_NOT_FOUND if no pending I/O instruction.
3275	*
3276	* @param pVM The cross context VM structure.
3277	* @param pVCpu The cross context virtual CPU structure.
3278	* @param pCtx Pointer to the guest CPU context.
3279	*/
3280	VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3281	{
3282	/*
3283	* Check if we've got relevant data pending.
3284	*/
3285	HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3286	if (enmType == HMPENDINGIO_INVALID)
3287	return VERR_NOT_FOUND;
3288	pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3289	if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
3290	return VERR_NOT_FOUND;
3291
3292	/*
3293	* Execute pending I/O.
3294	*/
3295	VBOXSTRICTRC rcStrict;
3296	switch (enmType)
3297	{
3298	case HMPENDINGIO_PORT_READ:
3299	{
3300	uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3301	uint32_t u32Val = 0;
3302
3303	rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3304	pVCpu->hm.s.PendingIO.s.Port.cbSize);
3305	if (IOM_SUCCESS(rcStrict))
3306	{
3307	/* Write back to the EAX register. */
3308	pCtx->eax = (pCtx->eax & ~uAndVal) \| (u32Val & uAndVal);
3309	pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3310	}
3311	break;
3312	}
3313
3314	default:
3315	AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3316	}
3317
3318	if (IOM_SUCCESS(rcStrict))
3319	{
3320	/*
3321	* Check for I/O breakpoints.
3322	*/
3323	uint32_t const uDr7 = pCtx->dr[7];
3324	if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3325	&& X86_DR7_ANY_RW_IO(uDr7)
3326	&& (pCtx->cr4 & X86_CR4_DE))
3327	\|\| DBGFBpIsHwIoArmed(pVM))
3328	{
3329	VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3330	pVCpu->hm.s.PendingIO.s.Port.cbSize);
3331	if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3332	rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3333	/* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3334	else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS \|\| rcStrict2 < rcStrict))
3335	rcStrict = rcStrict2;
3336	}
3337	}
3338	return rcStrict;
3339	}
3340
3341
3342	/**
3343	* Check fatal VT-x/AMD-V error and produce some meaningful
3344	* log release message.
3345	*
3346	* @param pVM The cross context VM structure.
3347	* @param iStatusCode VBox status code.
3348	*/
3349	VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3350	{
3351	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3352	{
3353	PVMCPU pVCpu = &pVM->aCpus[i];
3354	switch (iStatusCode)
3355	{
3356	/** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3357	* might be getting inaccurate values for non-guru'ing EMTs. */
3358	case VERR_VMX_INVALID_VMCS_FIELD:
3359	break;
3360
3361	case VERR_VMX_INVALID_VMCS_PTR:
3362	LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3363	LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3364	pVCpu->hm.s.vmx.HCPhysVmcs));
3365	LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3366	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3367	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3368	break;
3369
3370	case VERR_VMX_UNABLE_TO_START_VM:
3371	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3372	LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3373	LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3374
3375	if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3376	\|\| pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3377	{
3378	LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3379	LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3380	}
3381	else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3382	{
3383	LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3384	LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3385	LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3386	LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3387	LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3388	LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3389	LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3390	LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3391	LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3392	}
3393	/** @todo Log VM-entry event injection control fields
3394	* VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3395	* and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3396	break;
3397
3398	/* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3399	case VERR_VMX_INVALID_VMXON_PTR:
3400	case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3401	case VERR_VMX_INVALID_GUEST_STATE:
3402	case VERR_VMX_UNEXPECTED_EXIT:
3403	case VERR_SVM_UNKNOWN_EXIT:
3404	case VERR_SVM_UNEXPECTED_EXIT:
3405	case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3406	case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3407	case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3408	break;
3409	}
3410	}
3411
3412	if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3413	{
3414	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3415	LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3416	}
3417	else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3418	LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3419	}
3420
3421
3422	/**
3423	* Execute state save operation.
3424	*
3425	* @returns VBox status code.
3426	* @param pVM The cross context VM structure.
3427	* @param pSSM SSM operation handle.
3428	*/
3429	static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3430	{
3431	int rc;
3432
3433	Log(("hmR3Save:\n"));
3434
3435	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3436	{
3437	/*
3438	* Save the basic bits - fortunately all the other things can be resynced on load.
3439	*/
3440	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3441	AssertRCReturn(rc, rc);
3442	rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3443	AssertRCReturn(rc, rc);
3444	rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
3445	AssertRCReturn(rc, rc);
3446	/** @todo Shouldn't we be saving GCPtrFaultAddress too? */
3447
3448	/** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3449	* perhaps not even that (the initial value of @c true is safe. */
3450	uint32_t u32Dummy = PGMMODE_REAL;
3451	rc = SSMR3PutU32(pSSM, u32Dummy);
3452	AssertRCReturn(rc, rc);
3453	rc = SSMR3PutU32(pSSM, u32Dummy);
3454	AssertRCReturn(rc, rc);
3455	rc = SSMR3PutU32(pSSM, u32Dummy);
3456	AssertRCReturn(rc, rc);
3457	}
3458
3459	#ifdef VBOX_HM_WITH_GUEST_PATCHING
3460	rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3461	AssertRCReturn(rc, rc);
3462	rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3463	AssertRCReturn(rc, rc);
3464	rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3465	AssertRCReturn(rc, rc);
3466
3467	/* Store all the guest patch records too. */
3468	rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3469	AssertRCReturn(rc, rc);
3470
3471	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3472	{
3473	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3474
3475	rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3476	AssertRCReturn(rc, rc);
3477
3478	rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3479	AssertRCReturn(rc, rc);
3480
3481	rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3482	AssertRCReturn(rc, rc);
3483
3484	rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3485	AssertRCReturn(rc, rc);
3486
3487	rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3488	AssertRCReturn(rc, rc);
3489
3490	AssertCompileSize(HMTPRINSTR, 4);
3491	rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3492	AssertRCReturn(rc, rc);
3493
3494	rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3495	AssertRCReturn(rc, rc);
3496
3497	rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3498	AssertRCReturn(rc, rc);
3499
3500	rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3501	AssertRCReturn(rc, rc);
3502
3503	rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3504	AssertRCReturn(rc, rc);
3505	}
3506	#endif
3507	return VINF_SUCCESS;
3508	}
3509
3510
3511	/**
3512	* Execute state load operation.
3513	*
3514	* @returns VBox status code.
3515	* @param pVM The cross context VM structure.
3516	* @param pSSM SSM operation handle.
3517	* @param uVersion Data layout version.
3518	* @param uPass The data pass.
3519	*/
3520	static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3521	{
3522	int rc;
3523
3524	Log(("hmR3Load:\n"));
3525	Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3526
3527	/*
3528	* Validate version.
3529	*/
3530	if ( uVersion != HM_SAVED_STATE_VERSION
3531	&& uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3532	&& uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3533	{
3534	AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3535	return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3536	}
3537	for (VMCPUID i = 0; i < pVM->cCpus; i++)
3538	{
3539	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3540	AssertRCReturn(rc, rc);
3541	rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3542	AssertRCReturn(rc, rc);
3543	rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3544	AssertRCReturn(rc, rc);
3545
3546	if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3547	{
3548	uint32_t val;
3549	/** @todo See note in hmR3Save(). */
3550	rc = SSMR3GetU32(pSSM, &val);
3551	AssertRCReturn(rc, rc);
3552	rc = SSMR3GetU32(pSSM, &val);
3553	AssertRCReturn(rc, rc);
3554	rc = SSMR3GetU32(pSSM, &val);
3555	AssertRCReturn(rc, rc);
3556	}
3557	}
3558	#ifdef VBOX_HM_WITH_GUEST_PATCHING
3559	if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3560	{
3561	rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3562	AssertRCReturn(rc, rc);
3563	rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3564	AssertRCReturn(rc, rc);
3565	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3566	AssertRCReturn(rc, rc);
3567
3568	/* Fetch all TPR patch records. */
3569	rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3570	AssertRCReturn(rc, rc);
3571
3572	for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3573	{
3574	PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3575
3576	rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3577	AssertRCReturn(rc, rc);
3578
3579	rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3580	AssertRCReturn(rc, rc);
3581
3582	rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3583	AssertRCReturn(rc, rc);
3584
3585	rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3586	AssertRCReturn(rc, rc);
3587
3588	rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3589	AssertRCReturn(rc, rc);
3590
3591	rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3592	AssertRCReturn(rc, rc);
3593
3594	if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3595	pVM->hm.s.fTPRPatchingActive = true;
3596
3597	Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT \|\| pVM->hm.s.fTPRPatchingActive == false);
3598
3599	rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3600	AssertRCReturn(rc, rc);
3601
3602	rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3603	AssertRCReturn(rc, rc);
3604
3605	rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3606	AssertRCReturn(rc, rc);
3607
3608	rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3609	AssertRCReturn(rc, rc);
3610
3611	Log(("hmR3Load: patch %d\n", i));
3612	Log(("Key = %x\n", pPatch->Core.Key));
3613	Log(("cbOp = %d\n", pPatch->cbOp));
3614	Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3615	Log(("type = %d\n", pPatch->enmType));
3616	Log(("srcop = %d\n", pPatch->uSrcOperand));
3617	Log(("dstop = %d\n", pPatch->uDstOperand));
3618	Log(("cFaults = %d\n", pPatch->cFaults));
3619	Log(("target = %x\n", pPatch->pJumpTarget));
3620	rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3621	AssertRC(rc);
3622	}
3623	}
3624	#endif
3625
3626	return VINF_SUCCESS;
3627	}
3628
3629
3630	/**
3631	* Displays the guest VM-exit history.
3632	*
3633	* @param pVM The cross context VM structure.
3634	* @param pHlp The info helper functions.
3635	* @param pszArgs Arguments, ignored.
3636	*/
3637	static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3638	{
3639	NOREF(pszArgs);
3640	PVMCPU pVCpu = VMMGetCpu(pVM);
3641	if (!pVCpu)
3642	pVCpu = &pVM->aCpus[0];
3643
3644	if (HMIsEnabled(pVM))
3645	{
3646	bool const fIsVtx = pVM->hm.s.vmx.fSupported;
3647	const char * const *papszDesc;
3648	unsigned cMaxExitDesc;
3649	if (fIsVtx)
3650	{
3651	cMaxExitDesc = MAX_EXITREASON_VTX;
3652	papszDesc = &g_apszVTxExitReasons[0];
3653	pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x VM-exit history:\n", pVCpu->idCpu);
3654	}
3655	else
3656	{
3657	cMaxExitDesc = MAX_EXITREASON_AMDV;
3658	papszDesc = &g_apszAmdVExitReasons[0];
3659	pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V #VMEXIT history:\n", pVCpu->idCpu);
3660	}
3661
3662	pHlp->pfnPrintf(pHlp, " idxExitHistoryFree = %u\n", pVCpu->hm.s.idxExitHistoryFree);
3663	unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
3664	pVCpu->hm.s.idxExitHistoryFree - 1 :
3665	RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
3666	for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); i++)
3667	{
3668	uint16_t const uExit = pVCpu->hm.s.auExitHistory[i];
3669	const char *pszExit = NULL;
3670	if (uExit <= cMaxExitDesc)
3671	pszExit = papszDesc[uExit];
3672	else if (!fIsVtx)
3673	pszExit = hmSvmGetSpecialExitReasonDesc(uExit);
3674	else
3675	pszExit = NULL;
3676
3677	pHlp->pfnPrintf(pHlp, " auExitHistory[%2u] = 0x%04x %s %s\n", i, uExit, pszExit,
3678	idxLast == i ? "<-- Latest exit" : "");
3679	}
3680	pHlp->pfnPrintf(pHlp, "HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3681	}
3682	else
3683	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3684	}
3685
3686
3687	/**
3688	* Displays the HM pending event.
3689	*
3690	* @param pVM The cross context VM structure.
3691	* @param pHlp The info helper functions.
3692	* @param pszArgs Arguments, ignored.
3693	*/
3694	static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3695	{
3696	NOREF(pszArgs);
3697	PVMCPU pVCpu = VMMGetCpu(pVM);
3698	if (!pVCpu)
3699	pVCpu = &pVM->aCpus[0];
3700
3701	if (HMIsEnabled(pVM))
3702	{
3703	pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3704	if (pVCpu->hm.s.Event.fPending)
3705	{
3706	pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3707	pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3708	pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3709	pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3710	}
3711	}
3712	else
3713	pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3714	}
3715

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source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 70944

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