VirtualBox

source: vbox/trunk/src/VBox/VMM/VMMR3/HM.cpp@ 71409

Last change on this file since 71409 was 71382, checked in by vboxsync, 7 years ago

VMM/HM: Nit.

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1/* $Id: HM.cpp 71382 2018-03-20 08:44:03Z vboxsync $ */
2/** @file
3 * HM - Intel/AMD VM Hardware Support Manager.
4 */
5
6/*
7 * Copyright (C) 2006-2017 Oracle Corporation
8 *
9 * This file is part of VirtualBox Open Source Edition (OSE), as
10 * available from http://www.virtualbox.org. This file is free software;
11 * you can redistribute it and/or modify it under the terms of the GNU
12 * General Public License (GPL) as published by the Free Software
13 * Foundation, in version 2 as it comes in the "COPYING" file of the
14 * VirtualBox OSE distribution. VirtualBox OSE is distributed in the
15 * hope that it will be useful, but WITHOUT ANY WARRANTY of any kind.
16 */
17
18/** @page pg_hm HM - Hardware Assisted Virtualization Manager
19 *
20 * The HM manages guest execution using the VT-x and AMD-V CPU hardware
21 * extensions.
22 *
23 * {summary of what HM does}
24 *
25 * Hardware assisted virtualization manager was originally abbreviated HWACCM,
26 * however that was cumbersome to write and parse for such a central component,
27 * so it was shortened to HM when refactoring the code in the 4.3 development
28 * cycle.
29 *
30 * {add sections with more details}
31 *
32 * @sa @ref grp_hm
33 */
34
35
36/*********************************************************************************************************************************
37* Header Files *
38*********************************************************************************************************************************/
39#define LOG_GROUP LOG_GROUP_HM
40#include <VBox/vmm/cpum.h>
41#include <VBox/vmm/stam.h>
42#include <VBox/vmm/mm.h>
43#include <VBox/vmm/pdmapi.h>
44#include <VBox/vmm/pgm.h>
45#include <VBox/vmm/ssm.h>
46#include <VBox/vmm/trpm.h>
47#include <VBox/vmm/dbgf.h>
48#include <VBox/vmm/iom.h>
49#include <VBox/vmm/iem.h>
50#include <VBox/vmm/patm.h>
51#include <VBox/vmm/csam.h>
52#include <VBox/vmm/selm.h>
53#include <VBox/vmm/nem.h>
54#ifdef VBOX_WITH_REM
55# include <VBox/vmm/rem.h>
56#endif
57#include <VBox/vmm/hm_vmx.h>
58#include <VBox/vmm/hm_svm.h>
59#include "HMInternal.h"
60#include <VBox/vmm/vm.h>
61#include <VBox/vmm/uvm.h>
62#include <VBox/err.h>
63#include <VBox/param.h>
64
65#include <iprt/assert.h>
66#include <VBox/log.h>
67#include <iprt/asm.h>
68#include <iprt/asm-amd64-x86.h>
69#include <iprt/env.h>
70#include <iprt/thread.h>
71
72
73/*********************************************************************************************************************************
74* Global Variables *
75*********************************************************************************************************************************/
76#define EXIT_REASON(def, val, str) #def " - " #val " - " str
77#define EXIT_REASON_NIL() NULL
78/** Exit reason descriptions for VT-x, used to describe statistics. */
79static const char * const g_apszVTxExitReasons[MAX_EXITREASON_STAT] =
80{
81 EXIT_REASON(VMX_EXIT_XCPT_OR_NMI , 0, "Exception or non-maskable interrupt (NMI)."),
82 EXIT_REASON(VMX_EXIT_EXT_INT , 1, "External interrupt."),
83 EXIT_REASON(VMX_EXIT_TRIPLE_FAULT , 2, "Triple fault."),
84 EXIT_REASON(VMX_EXIT_INIT_SIGNAL , 3, "INIT signal."),
85 EXIT_REASON(VMX_EXIT_SIPI , 4, "Start-up IPI (SIPI)."),
86 EXIT_REASON(VMX_EXIT_IO_SMI_IRQ , 5, "I/O system-management interrupt (SMI)."),
87 EXIT_REASON(VMX_EXIT_SMI_IRQ , 6, "Other SMI."),
88 EXIT_REASON(VMX_EXIT_INT_WINDOW , 7, "Interrupt window."),
89 EXIT_REASON(VMX_EXIT_NMI_WINDOW , 8, "NMI window."),
90 EXIT_REASON(VMX_EXIT_TASK_SWITCH , 9, "Task switch."),
91 EXIT_REASON(VMX_EXIT_CPUID , 10, "CPUID instruction."),
92 EXIT_REASON(VMX_EXIT_GETSEC , 11, "GETSEC instrunction."),
93 EXIT_REASON(VMX_EXIT_HLT , 12, "HLT instruction."),
94 EXIT_REASON(VMX_EXIT_INVD , 13, "INVD instruction."),
95 EXIT_REASON(VMX_EXIT_INVLPG , 14, "INVLPG instruction."),
96 EXIT_REASON(VMX_EXIT_RDPMC , 15, "RDPMCinstruction."),
97 EXIT_REASON(VMX_EXIT_RDTSC , 16, "RDTSC instruction."),
98 EXIT_REASON(VMX_EXIT_RSM , 17, "RSM instruction in SMM."),
99 EXIT_REASON(VMX_EXIT_VMCALL , 18, "VMCALL instruction."),
100 EXIT_REASON(VMX_EXIT_VMCLEAR , 19, "VMCLEAR instruction."),
101 EXIT_REASON(VMX_EXIT_VMLAUNCH , 20, "VMLAUNCH instruction."),
102 EXIT_REASON(VMX_EXIT_VMPTRLD , 21, "VMPTRLD instruction."),
103 EXIT_REASON(VMX_EXIT_VMPTRST , 22, "VMPTRST instruction."),
104 EXIT_REASON(VMX_EXIT_VMREAD , 23, "VMREAD instruction."),
105 EXIT_REASON(VMX_EXIT_VMRESUME , 24, "VMRESUME instruction."),
106 EXIT_REASON(VMX_EXIT_VMWRITE , 25, "VMWRITE instruction."),
107 EXIT_REASON(VMX_EXIT_VMXOFF , 26, "VMXOFF instruction."),
108 EXIT_REASON(VMX_EXIT_VMXON , 27, "VMXON instruction."),
109 EXIT_REASON(VMX_EXIT_MOV_CRX , 28, "Control-register accesses."),
110 EXIT_REASON(VMX_EXIT_MOV_DRX , 29, "Debug-register accesses."),
111 EXIT_REASON(VMX_EXIT_PORT_IO , 30, "I/O instruction."),
112 EXIT_REASON(VMX_EXIT_RDMSR , 31, "RDMSR instruction."),
113 EXIT_REASON(VMX_EXIT_WRMSR , 32, "WRMSR instruction."),
114 EXIT_REASON(VMX_EXIT_ERR_INVALID_GUEST_STATE, 33, "VM-entry failure due to invalid guest state."),
115 EXIT_REASON(VMX_EXIT_ERR_MSR_LOAD , 34, "VM-entry failure due to MSR loading."),
116 EXIT_REASON_NIL(),
117 EXIT_REASON(VMX_EXIT_MWAIT , 36, "MWAIT instruction."),
118 EXIT_REASON(VMX_EXIT_MTF , 37, "Monitor Trap Flag."),
119 EXIT_REASON_NIL(),
120 EXIT_REASON(VMX_EXIT_MONITOR , 39, "MONITOR instruction."),
121 EXIT_REASON(VMX_EXIT_PAUSE , 40, "PAUSE instruction."),
122 EXIT_REASON(VMX_EXIT_ERR_MACHINE_CHECK , 41, "VM-entry failure due to machine-check."),
123 EXIT_REASON_NIL(),
124 EXIT_REASON(VMX_EXIT_TPR_BELOW_THRESHOLD , 43, "TPR below threshold (MOV to CR8)."),
125 EXIT_REASON(VMX_EXIT_APIC_ACCESS , 44, "APIC access."),
126 EXIT_REASON(VMX_EXIT_VIRTUALIZED_EOI , 45, "Virtualized EOI."),
127 EXIT_REASON(VMX_EXIT_XDTR_ACCESS , 46, "GDTR/IDTR access using LGDT/SGDT/LIDT/SIDT."),
128 EXIT_REASON(VMX_EXIT_TR_ACCESS , 47, "LDTR/TR access using LLDT/SLDT/LTR/STR."),
129 EXIT_REASON(VMX_EXIT_EPT_VIOLATION , 48, "EPT violation."),
130 EXIT_REASON(VMX_EXIT_EPT_MISCONFIG , 49, "EPT misconfiguration."),
131 EXIT_REASON(VMX_EXIT_INVEPT , 50, "INVEPT instruction."),
132 EXIT_REASON(VMX_EXIT_RDTSCP , 51, "RDTSCP instruction."),
133 EXIT_REASON(VMX_EXIT_PREEMPT_TIMER , 52, "VMX-preemption timer expired."),
134 EXIT_REASON(VMX_EXIT_INVVPID , 53, "INVVPID instruction."),
135 EXIT_REASON(VMX_EXIT_WBINVD , 54, "WBINVD instruction."),
136 EXIT_REASON(VMX_EXIT_XSETBV , 55, "XSETBV instruction."),
137 EXIT_REASON(VMX_EXIT_APIC_WRITE , 56, "APIC write completed to virtual-APIC page."),
138 EXIT_REASON(VMX_EXIT_RDRAND , 57, "RDRAND instruction."),
139 EXIT_REASON(VMX_EXIT_INVPCID , 58, "INVPCID instruction."),
140 EXIT_REASON(VMX_EXIT_VMFUNC , 59, "VMFUNC instruction."),
141 EXIT_REASON(VMX_EXIT_ENCLS , 60, "ENCLS instrunction."),
142 EXIT_REASON(VMX_EXIT_RDSEED , 61, "RDSEED instruction."),
143 EXIT_REASON(VMX_EXIT_PML_FULL , 62, "Page-modification log full."),
144 EXIT_REASON(VMX_EXIT_XSAVES , 63, "XSAVES instruction."),
145 EXIT_REASON(VMX_EXIT_XRSTORS , 64, "XRSTORS instruction.")
146};
147/** Array index of the last valid VT-x exit reason. */
148#define MAX_EXITREASON_VTX 64
149
150/** A partial list of Exit reason descriptions for AMD-V, used to describe
151 * statistics.
152 *
153 * @note AMD-V have annoyingly large gaps (e.g. \#NPF VMEXIT comes at 1024),
154 * this array doesn't contain the entire set of exit reasons, we
155 * handle them via hmSvmGetSpecialExitReasonDesc(). */
156static const char * const g_apszAmdVExitReasons[MAX_EXITREASON_STAT] =
157{
158 EXIT_REASON(SVM_EXIT_READ_CR0 , 0, "Read CR0."),
159 EXIT_REASON(SVM_EXIT_READ_CR1 , 1, "Read CR1."),
160 EXIT_REASON(SVM_EXIT_READ_CR2 , 2, "Read CR2."),
161 EXIT_REASON(SVM_EXIT_READ_CR3 , 3, "Read CR3."),
162 EXIT_REASON(SVM_EXIT_READ_CR4 , 4, "Read CR4."),
163 EXIT_REASON(SVM_EXIT_READ_CR5 , 5, "Read CR5."),
164 EXIT_REASON(SVM_EXIT_READ_CR6 , 6, "Read CR6."),
165 EXIT_REASON(SVM_EXIT_READ_CR7 , 7, "Read CR7."),
166 EXIT_REASON(SVM_EXIT_READ_CR8 , 8, "Read CR8."),
167 EXIT_REASON(SVM_EXIT_READ_CR9 , 9, "Read CR9."),
168 EXIT_REASON(SVM_EXIT_READ_CR10 , 10, "Read CR10."),
169 EXIT_REASON(SVM_EXIT_READ_CR11 , 11, "Read CR11."),
170 EXIT_REASON(SVM_EXIT_READ_CR12 , 12, "Read CR12."),
171 EXIT_REASON(SVM_EXIT_READ_CR13 , 13, "Read CR13."),
172 EXIT_REASON(SVM_EXIT_READ_CR14 , 14, "Read CR14."),
173 EXIT_REASON(SVM_EXIT_READ_CR15 , 15, "Read CR15."),
174 EXIT_REASON(SVM_EXIT_WRITE_CR0 , 16, "Write CR0."),
175 EXIT_REASON(SVM_EXIT_WRITE_CR1 , 17, "Write CR1."),
176 EXIT_REASON(SVM_EXIT_WRITE_CR2 , 18, "Write CR2."),
177 EXIT_REASON(SVM_EXIT_WRITE_CR3 , 19, "Write CR3."),
178 EXIT_REASON(SVM_EXIT_WRITE_CR4 , 20, "Write CR4."),
179 EXIT_REASON(SVM_EXIT_WRITE_CR5 , 21, "Write CR5."),
180 EXIT_REASON(SVM_EXIT_WRITE_CR6 , 22, "Write CR6."),
181 EXIT_REASON(SVM_EXIT_WRITE_CR7 , 23, "Write CR7."),
182 EXIT_REASON(SVM_EXIT_WRITE_CR8 , 24, "Write CR8."),
183 EXIT_REASON(SVM_EXIT_WRITE_CR9 , 25, "Write CR9."),
184 EXIT_REASON(SVM_EXIT_WRITE_CR10 , 26, "Write CR10."),
185 EXIT_REASON(SVM_EXIT_WRITE_CR11 , 27, "Write CR11."),
186 EXIT_REASON(SVM_EXIT_WRITE_CR12 , 28, "Write CR12."),
187 EXIT_REASON(SVM_EXIT_WRITE_CR13 , 29, "Write CR13."),
188 EXIT_REASON(SVM_EXIT_WRITE_CR14 , 30, "Write CR14."),
189 EXIT_REASON(SVM_EXIT_WRITE_CR15 , 31, "Write CR15."),
190 EXIT_REASON(SVM_EXIT_READ_DR0 , 32, "Read DR0."),
191 EXIT_REASON(SVM_EXIT_READ_DR1 , 33, "Read DR1."),
192 EXIT_REASON(SVM_EXIT_READ_DR2 , 34, "Read DR2."),
193 EXIT_REASON(SVM_EXIT_READ_DR3 , 35, "Read DR3."),
194 EXIT_REASON(SVM_EXIT_READ_DR4 , 36, "Read DR4."),
195 EXIT_REASON(SVM_EXIT_READ_DR5 , 37, "Read DR5."),
196 EXIT_REASON(SVM_EXIT_READ_DR6 , 38, "Read DR6."),
197 EXIT_REASON(SVM_EXIT_READ_DR7 , 39, "Read DR7."),
198 EXIT_REASON(SVM_EXIT_READ_DR8 , 40, "Read DR8."),
199 EXIT_REASON(SVM_EXIT_READ_DR9 , 41, "Read DR9."),
200 EXIT_REASON(SVM_EXIT_READ_DR10 , 42, "Read DR10."),
201 EXIT_REASON(SVM_EXIT_READ_DR11 , 43, "Read DR11"),
202 EXIT_REASON(SVM_EXIT_READ_DR12 , 44, "Read DR12."),
203 EXIT_REASON(SVM_EXIT_READ_DR13 , 45, "Read DR13."),
204 EXIT_REASON(SVM_EXIT_READ_DR14 , 46, "Read DR14."),
205 EXIT_REASON(SVM_EXIT_READ_DR15 , 47, "Read DR15."),
206 EXIT_REASON(SVM_EXIT_WRITE_DR0 , 48, "Write DR0."),
207 EXIT_REASON(SVM_EXIT_WRITE_DR1 , 49, "Write DR1."),
208 EXIT_REASON(SVM_EXIT_WRITE_DR2 , 50, "Write DR2."),
209 EXIT_REASON(SVM_EXIT_WRITE_DR3 , 51, "Write DR3."),
210 EXIT_REASON(SVM_EXIT_WRITE_DR4 , 52, "Write DR4."),
211 EXIT_REASON(SVM_EXIT_WRITE_DR5 , 53, "Write DR5."),
212 EXIT_REASON(SVM_EXIT_WRITE_DR6 , 54, "Write DR6."),
213 EXIT_REASON(SVM_EXIT_WRITE_DR7 , 55, "Write DR7."),
214 EXIT_REASON(SVM_EXIT_WRITE_DR8 , 56, "Write DR8."),
215 EXIT_REASON(SVM_EXIT_WRITE_DR9 , 57, "Write DR9."),
216 EXIT_REASON(SVM_EXIT_WRITE_DR10 , 58, "Write DR10."),
217 EXIT_REASON(SVM_EXIT_WRITE_DR11 , 59, "Write DR11."),
218 EXIT_REASON(SVM_EXIT_WRITE_DR12 , 60, "Write DR12."),
219 EXIT_REASON(SVM_EXIT_WRITE_DR13 , 61, "Write DR13."),
220 EXIT_REASON(SVM_EXIT_WRITE_DR14 , 62, "Write DR14."),
221 EXIT_REASON(SVM_EXIT_WRITE_DR15 , 63, "Write DR15."),
222 EXIT_REASON(SVM_EXIT_EXCEPTION_0 , 64, "Exception Vector 0 (#DE)."),
223 EXIT_REASON(SVM_EXIT_EXCEPTION_1 , 65, "Exception Vector 1 (#DB)."),
224 EXIT_REASON(SVM_EXIT_EXCEPTION_2 , 66, "Exception Vector 2 (#NMI)."),
225 EXIT_REASON(SVM_EXIT_EXCEPTION_3 , 67, "Exception Vector 3 (#BP)."),
226 EXIT_REASON(SVM_EXIT_EXCEPTION_4 , 68, "Exception Vector 4 (#OF)."),
227 EXIT_REASON(SVM_EXIT_EXCEPTION_5 , 69, "Exception Vector 5 (#BR)."),
228 EXIT_REASON(SVM_EXIT_EXCEPTION_6 , 70, "Exception Vector 6 (#UD)."),
229 EXIT_REASON(SVM_EXIT_EXCEPTION_7 , 71, "Exception Vector 7 (#NM)."),
230 EXIT_REASON(SVM_EXIT_EXCEPTION_8 , 72, "Exception Vector 8 (#DF)."),
231 EXIT_REASON(SVM_EXIT_EXCEPTION_9 , 73, "Exception Vector 9 (#CO_SEG_OVERRUN)."),
232 EXIT_REASON(SVM_EXIT_EXCEPTION_A , 74, "Exception Vector 10 (#TS)."),
233 EXIT_REASON(SVM_EXIT_EXCEPTION_B , 75, "Exception Vector 11 (#NP)."),
234 EXIT_REASON(SVM_EXIT_EXCEPTION_C , 76, "Exception Vector 12 (#SS)."),
235 EXIT_REASON(SVM_EXIT_EXCEPTION_D , 77, "Exception Vector 13 (#GP)."),
236 EXIT_REASON(SVM_EXIT_EXCEPTION_E , 78, "Exception Vector 14 (#PF)."),
237 EXIT_REASON(SVM_EXIT_EXCEPTION_F , 79, "Exception Vector 15 (0x0f)."),
238 EXIT_REASON(SVM_EXIT_EXCEPTION_10 , 80, "Exception Vector 16 (#MF)."),
239 EXIT_REASON(SVM_EXIT_EXCEPTION_11 , 81, "Exception Vector 17 (#AC)."),
240 EXIT_REASON(SVM_EXIT_EXCEPTION_12 , 82, "Exception Vector 18 (#MC)."),
241 EXIT_REASON(SVM_EXIT_EXCEPTION_13 , 83, "Exception Vector 19 (#XF)."),
242 EXIT_REASON(SVM_EXIT_EXCEPTION_14 , 84, "Exception Vector 20 (0x14)."),
243 EXIT_REASON(SVM_EXIT_EXCEPTION_15 , 85, "Exception Vector 22 (0x15)."),
244 EXIT_REASON(SVM_EXIT_EXCEPTION_16 , 86, "Exception Vector 22 (0x16)."),
245 EXIT_REASON(SVM_EXIT_EXCEPTION_17 , 87, "Exception Vector 23 (0x17)."),
246 EXIT_REASON(SVM_EXIT_EXCEPTION_18 , 88, "Exception Vector 24 (0x18)."),
247 EXIT_REASON(SVM_EXIT_EXCEPTION_19 , 89, "Exception Vector 25 (0x19)."),
248 EXIT_REASON(SVM_EXIT_EXCEPTION_1A , 90, "Exception Vector 26 (0x1A)."),
249 EXIT_REASON(SVM_EXIT_EXCEPTION_1B , 91, "Exception Vector 27 (0x1B)."),
250 EXIT_REASON(SVM_EXIT_EXCEPTION_1C , 92, "Exception Vector 28 (0x1C)."),
251 EXIT_REASON(SVM_EXIT_EXCEPTION_1D , 93, "Exception Vector 29 (0x1D)."),
252 EXIT_REASON(SVM_EXIT_EXCEPTION_1E , 94, "Exception Vector 30 (0x1E)."),
253 EXIT_REASON(SVM_EXIT_EXCEPTION_1F , 95, "Exception Vector 31 (0x1F)."),
254 EXIT_REASON(SVM_EXIT_INTR , 96, "Physical maskable interrupt (host)."),
255 EXIT_REASON(SVM_EXIT_NMI , 97, "Physical non-maskable interrupt (host)."),
256 EXIT_REASON(SVM_EXIT_SMI , 98, "System management interrupt (host)."),
257 EXIT_REASON(SVM_EXIT_INIT , 99, "Physical INIT signal (host)."),
258 EXIT_REASON(SVM_EXIT_VINTR , 100, "Virtual interrupt-window exit."),
259 EXIT_REASON(SVM_EXIT_CR0_SEL_WRITE, 101, "Write to CR0 that changed any bits other than CR0.TS or CR0.MP."),
260 EXIT_REASON(SVM_EXIT_IDTR_READ , 102, "Read IDTR"),
261 EXIT_REASON(SVM_EXIT_GDTR_READ , 103, "Read GDTR"),
262 EXIT_REASON(SVM_EXIT_LDTR_READ , 104, "Read LDTR."),
263 EXIT_REASON(SVM_EXIT_TR_READ , 105, "Read TR."),
264 EXIT_REASON(SVM_EXIT_IDTR_WRITE , 106, "Write IDTR."),
265 EXIT_REASON(SVM_EXIT_GDTR_WRITE , 107, "Write GDTR."),
266 EXIT_REASON(SVM_EXIT_LDTR_WRITE , 108, "Write LDTR."),
267 EXIT_REASON(SVM_EXIT_TR_WRITE , 109, "Write TR."),
268 EXIT_REASON(SVM_EXIT_RDTSC , 110, "RDTSC instruction."),
269 EXIT_REASON(SVM_EXIT_RDPMC , 111, "RDPMC instruction."),
270 EXIT_REASON(SVM_EXIT_PUSHF , 112, "PUSHF instruction."),
271 EXIT_REASON(SVM_EXIT_POPF , 113, "POPF instruction."),
272 EXIT_REASON(SVM_EXIT_CPUID , 114, "CPUID instruction."),
273 EXIT_REASON(SVM_EXIT_RSM , 115, "RSM instruction."),
274 EXIT_REASON(SVM_EXIT_IRET , 116, "IRET instruction."),
275 EXIT_REASON(SVM_EXIT_SWINT , 117, "Software interrupt (INTn instructions)."),
276 EXIT_REASON(SVM_EXIT_INVD , 118, "INVD instruction."),
277 EXIT_REASON(SVM_EXIT_PAUSE , 119, "PAUSE instruction."),
278 EXIT_REASON(SVM_EXIT_HLT , 120, "HLT instruction."),
279 EXIT_REASON(SVM_EXIT_INVLPG , 121, "INVLPG instruction."),
280 EXIT_REASON(SVM_EXIT_INVLPGA , 122, "INVLPGA instruction."),
281 EXIT_REASON(SVM_EXIT_IOIO , 123, "IN/OUT accessing protected port."),
282 EXIT_REASON(SVM_EXIT_MSR , 124, "RDMSR or WRMSR access to protected MSR."),
283 EXIT_REASON(SVM_EXIT_TASK_SWITCH , 125, "Task switch."),
284 EXIT_REASON(SVM_EXIT_FERR_FREEZE , 126, "Legacy FPU handling enabled; CPU frozen in an x87/mmx instr. waiting for interrupt."),
285 EXIT_REASON(SVM_EXIT_SHUTDOWN , 127, "Shutdown."),
286 EXIT_REASON(SVM_EXIT_VMRUN , 128, "VMRUN instruction."),
287 EXIT_REASON(SVM_EXIT_VMMCALL , 129, "VMCALL instruction."),
288 EXIT_REASON(SVM_EXIT_VMLOAD , 130, "VMLOAD instruction."),
289 EXIT_REASON(SVM_EXIT_VMSAVE , 131, "VMSAVE instruction."),
290 EXIT_REASON(SVM_EXIT_STGI , 132, "STGI instruction."),
291 EXIT_REASON(SVM_EXIT_CLGI , 133, "CLGI instruction."),
292 EXIT_REASON(SVM_EXIT_SKINIT , 134, "SKINIT instruction."),
293 EXIT_REASON(SVM_EXIT_RDTSCP , 135, "RDTSCP instruction."),
294 EXIT_REASON(SVM_EXIT_ICEBP , 136, "ICEBP instruction."),
295 EXIT_REASON(SVM_EXIT_WBINVD , 137, "WBINVD instruction."),
296 EXIT_REASON(SVM_EXIT_MONITOR , 138, "MONITOR instruction."),
297 EXIT_REASON(SVM_EXIT_MWAIT , 139, "MWAIT instruction."),
298 EXIT_REASON(SVM_EXIT_MWAIT_ARMED , 140, "MWAIT instruction when armed."),
299 EXIT_REASON(SVM_EXIT_XSETBV , 141, "XSETBV instruction."),
300};
301/** Array index of the last valid AMD-V exit reason. */
302#define MAX_EXITREASON_AMDV 141
303
304/** Special exit reasons not covered in the array above. */
305#define SVM_EXIT_REASON_NPF EXIT_REASON(SVM_EXIT_NPF , 1024, "Nested Page Fault.")
306#define SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI EXIT_REASON(SVM_EXIT_AVIC_INCOMPLETE_IPI, 1025, "AVIC - Incomplete IPI delivery.")
307#define SVM_EXIT_REASON_AVIC_NOACCEL EXIT_REASON(SVM_EXIT_AVIC_NOACCEL , 1026, "AVIC - Unhandled register.")
308
309/**
310 * Gets the SVM exit reason if it's one of the reasons not present in the @c
311 * g_apszAmdVExitReasons array.
312 *
313 * @returns The exit reason or NULL if unknown.
314 * @param uExit The exit.
315 */
316DECLINLINE(const char *) hmSvmGetSpecialExitReasonDesc(uint16_t uExit)
317{
318 switch (uExit)
319 {
320 case SVM_EXIT_NPF: return SVM_EXIT_REASON_NPF;
321 case SVM_EXIT_AVIC_INCOMPLETE_IPI: return SVM_EXIT_REASON_AVIC_INCOMPLETE_IPI;
322 case SVM_EXIT_AVIC_NOACCEL: return SVM_EXIT_REASON_AVIC_NOACCEL;
323 }
324 return EXIT_REASON_NIL();
325}
326#undef EXIT_REASON_NIL
327#undef EXIT_REASON
328
329/** @def HMVMX_REPORT_FEATURE
330 * Reports VT-x feature to the release log.
331 *
332 * @param allowed1 Mask of allowed feature bits.
333 * @param disallowed0 Mask of disallowed feature bits.
334 * @param strdesc The description string to report.
335 * @param featflag Mask of the feature to report.
336 */
337#define HMVMX_REPORT_FEATURE(allowed1, disallowed0, strdesc, featflag) \
338 do { \
339 if ((allowed1) & (featflag)) \
340 { \
341 if ((disallowed0) & (featflag)) \
342 LogRel(("HM: " strdesc " (must be set)\n")); \
343 else \
344 LogRel(("HM: " strdesc "\n")); \
345 } \
346 else \
347 LogRel(("HM: " strdesc " (must be cleared)\n")); \
348 } while (0)
349
350/** @def HMVMX_REPORT_ALLOWED_FEATURE
351 * Reports an allowed VT-x feature to the release log.
352 *
353 * @param allowed1 Mask of allowed feature bits.
354 * @param strdesc The description string to report.
355 * @param featflag Mask of the feature to report.
356 */
357#define HMVMX_REPORT_ALLOWED_FEATURE(allowed1, strdesc, featflag) \
358 do { \
359 if ((allowed1) & (featflag)) \
360 LogRel(("HM: " strdesc "\n")); \
361 else \
362 LogRel(("HM: " strdesc " not supported\n")); \
363 } while (0)
364
365/** @def HMVMX_REPORT_MSR_CAPABILITY
366 * Reports MSR feature capability.
367 *
368 * @param msrcaps Mask of MSR feature bits.
369 * @param strdesc The description string to report.
370 * @param cap Mask of the feature to report.
371 */
372#define HMVMX_REPORT_MSR_CAPABILITY(msrcaps, strdesc, cap) \
373 do { \
374 if ((msrcaps) & (cap)) \
375 LogRel(("HM: " strdesc "\n")); \
376 } while (0)
377
378
379/*********************************************************************************************************************************
380* Internal Functions *
381*********************************************************************************************************************************/
382static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM);
383static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass);
384static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
385static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
386static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs);
387static int hmR3InitCPU(PVM pVM);
388static int hmR3InitFinalizeR0(PVM pVM);
389static int hmR3InitFinalizeR0Intel(PVM pVM);
390static int hmR3InitFinalizeR0Amd(PVM pVM);
391static int hmR3TermCPU(PVM pVM);
392
393
394
395/**
396 * Initializes the HM.
397 *
398 * This is the very first component to really do init after CFGM so that we can
399 * establish the predominat execution engine for the VM prior to initializing
400 * other modules. It takes care of NEM initialization if needed (HM disabled or
401 * not available in HW).
402 *
403 * If VT-x or AMD-V hardware isn't available, HM will try fall back on a native
404 * hypervisor API via NEM, and then back on raw-mode if that isn't available
405 * either. The fallback to raw-mode will not happen if /HM/HMForced is set
406 * (like for guest using SMP or 64-bit as well as for complicated guest like OS
407 * X, OS/2 and others).
408 *
409 * Note that a lot of the set up work is done in ring-0 and thus postponed till
410 * the ring-3 and ring-0 callback to HMR3InitCompleted.
411 *
412 * @returns VBox status code.
413 * @param pVM The cross context VM structure.
414 *
415 * @remarks Be careful with what we call here, since most of the VMM components
416 * are uninitialized.
417 */
418VMMR3_INT_DECL(int) HMR3Init(PVM pVM)
419{
420 LogFlow(("HMR3Init\n"));
421
422 /*
423 * Assert alignment and sizes.
424 */
425 AssertCompileMemberAlignment(VM, hm.s, 32);
426 AssertCompile(sizeof(pVM->hm.s) <= sizeof(pVM->hm.padding));
427
428 /*
429 * Register the saved state data unit.
430 */
431 int rc = SSMR3RegisterInternal(pVM, "HWACCM", 0, HM_SAVED_STATE_VERSION, sizeof(HM),
432 NULL, NULL, NULL,
433 NULL, hmR3Save, NULL,
434 NULL, hmR3Load, NULL);
435 if (RT_FAILURE(rc))
436 return rc;
437
438 /*
439 * Register info handlers.
440 */
441 rc = DBGFR3InfoRegisterInternalEx(pVM, "exithistory", "Dumps the HM VM-exit history.", hmR3InfoExitHistory,
442 DBGFINFO_FLAGS_ALL_EMTS);
443 AssertRCReturn(rc, rc);
444
445 rc = DBGFR3InfoRegisterInternalEx(pVM, "hmeventpending", "Dumps the pending HM event.", hmR3InfoEventPending,
446 DBGFINFO_FLAGS_ALL_EMTS);
447 AssertRCReturn(rc, rc);
448
449 rc = DBGFR3InfoRegisterInternalEx(pVM, "svmvmcbcache", "Dumps the HM SVM nested-guest VMCB cache.",
450 hmR3InfoSvmNstGstVmcbCache, DBGFINFO_FLAGS_ALL_EMTS);
451 AssertRCReturn(rc, rc);
452
453 /*
454 * Read configuration.
455 */
456 PCFGMNODE pCfgHm = CFGMR3GetChild(CFGMR3GetRoot(pVM), "HM/");
457
458 /*
459 * Validate the HM settings.
460 */
461 rc = CFGMR3ValidateConfig(pCfgHm, "/HM/",
462 "HMForced"
463 "|UseNEMInstead"
464 "|FallbackToNEM"
465 "|EnableNestedPaging"
466 "|EnableUX"
467 "|EnableLargePages"
468 "|EnableVPID"
469 "|IBPBOnVMExit"
470 "|IBPBOnVMEntry"
471 "|SpecCtrlByHost"
472 "|TPRPatchingEnabled"
473 "|64bitEnabled"
474 "|Exclusive"
475 "|MaxResumeLoops"
476 "|VmxPleGap"
477 "|VmxPleWindow"
478 "|UseVmxPreemptTimer"
479 "|SvmPauseFilter"
480 "|SvmPauseFilterThreshold"
481 "|SvmVirtVmsaveVmload"
482 "|SvmVGif",
483 "" /* pszValidNodes */, "HM" /* pszWho */, 0 /* uInstance */);
484 if (RT_FAILURE(rc))
485 return rc;
486
487 /** @cfgm{/HM/HMForced, bool, false}
488 * Forces hardware virtualization, no falling back on raw-mode. HM must be
489 * enabled, i.e. /HMEnabled must be true. */
490 bool fHMForced;
491#ifdef VBOX_WITH_RAW_MODE
492 rc = CFGMR3QueryBoolDef(pCfgHm, "HMForced", &fHMForced, false);
493 AssertRCReturn(rc, rc);
494 AssertLogRelMsgReturn(!fHMForced || pVM->fHMEnabled, ("Configuration error: HM forced but not enabled!\n"),
495 VERR_INVALID_PARAMETER);
496# if defined(RT_OS_DARWIN)
497 if (pVM->fHMEnabled)
498 fHMForced = true;
499# endif
500 AssertLogRelMsgReturn(pVM->cCpus == 1 || pVM->fHMEnabled, ("Configuration error: SMP requires HM to be enabled!\n"),
501 VERR_INVALID_PARAMETER);
502 if (pVM->cCpus > 1)
503 fHMForced = true;
504#else /* !VBOX_WITH_RAW_MODE */
505 AssertRelease(pVM->fHMEnabled);
506 fHMForced = true;
507#endif /* !VBOX_WITH_RAW_MODE */
508
509 /** @cfgm{/HM/UseNEMInstead, bool, true}
510 * Don't use HM, use NEM instead. */
511 bool fUseNEMInstead = false;
512 rc = CFGMR3QueryBoolDef(pCfgHm, "UseNEMInstead", &fUseNEMInstead, false);
513 AssertRCReturn(rc, rc);
514 if (fUseNEMInstead && pVM->fHMEnabled)
515 {
516 LogRel(("HM: Setting fHMEnabled to false because fUseNEMInstead is set.\n"));
517 pVM->fHMEnabled = false;
518 }
519
520 /** @cfgm{/HM/FallbackToNEM, bool, true}
521 * Enables fallback on NEM. */
522 bool fFallbackToNEM = true;
523 rc = CFGMR3QueryBoolDef(pCfgHm, "FallbackToNEM", &fFallbackToNEM, true);
524 AssertRCReturn(rc, rc);
525
526 /** @cfgm{/HM/EnableNestedPaging, bool, false}
527 * Enables nested paging (aka extended page tables). */
528 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableNestedPaging", &pVM->hm.s.fAllowNestedPaging, false);
529 AssertRCReturn(rc, rc);
530
531 /** @cfgm{/HM/EnableUX, bool, true}
532 * Enables the VT-x unrestricted execution feature. */
533 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableUX", &pVM->hm.s.vmx.fAllowUnrestricted, true);
534 AssertRCReturn(rc, rc);
535
536 /** @cfgm{/HM/EnableLargePages, bool, false}
537 * Enables using large pages (2 MB) for guest memory, thus saving on (nested)
538 * page table walking and maybe better TLB hit rate in some cases. */
539 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableLargePages", &pVM->hm.s.fLargePages, false);
540 AssertRCReturn(rc, rc);
541
542 /** @cfgm{/HM/EnableVPID, bool, false}
543 * Enables the VT-x VPID feature. */
544 rc = CFGMR3QueryBoolDef(pCfgHm, "EnableVPID", &pVM->hm.s.vmx.fAllowVpid, false);
545 AssertRCReturn(rc, rc);
546
547 /** @cfgm{/HM/TPRPatchingEnabled, bool, false}
548 * Enables TPR patching for 32-bit windows guests with IO-APIC. */
549 rc = CFGMR3QueryBoolDef(pCfgHm, "TPRPatchingEnabled", &pVM->hm.s.fTprPatchingAllowed, false);
550 AssertRCReturn(rc, rc);
551
552 /** @cfgm{/HM/64bitEnabled, bool, 32-bit:false, 64-bit:true}
553 * Enables AMD64 cpu features.
554 * On 32-bit hosts this isn't default and require host CPU support. 64-bit hosts
555 * already have the support. */
556#ifdef VBOX_ENABLE_64_BITS_GUESTS
557 rc = CFGMR3QueryBoolDef(pCfgHm, "64bitEnabled", &pVM->hm.s.fAllow64BitGuests, HC_ARCH_BITS == 64);
558 AssertLogRelRCReturn(rc, rc);
559#else
560 pVM->hm.s.fAllow64BitGuests = false;
561#endif
562
563 /** @cfgm{/HM/VmxPleGap, uint32_t, 0}
564 * The pause-filter exiting gap in TSC ticks. When the number of ticks between
565 * two successive PAUSE instructions exceeds VmxPleGap, the CPU considers the
566 * latest PAUSE instruction to be start of a new PAUSE loop.
567 */
568 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleGap", &pVM->hm.s.vmx.cPleGapTicks, 0);
569 AssertRCReturn(rc, rc);
570
571 /** @cfgm{/HM/VmxPleWindow, uint32_t, 0}
572 * The pause-filter exiting window in TSC ticks. When the number of ticks
573 * between the current PAUSE instruction and first PAUSE of a loop exceeds
574 * VmxPleWindow, a VM-exit is triggered.
575 *
576 * Setting VmxPleGap and VmxPleGap to 0 disables pause-filter exiting.
577 */
578 rc = CFGMR3QueryU32Def(pCfgHm, "VmxPleWindow", &pVM->hm.s.vmx.cPleWindowTicks, 0);
579 AssertRCReturn(rc, rc);
580
581 /** @cfgm{/HM/SvmPauseFilterCount, uint16_t, 0}
582 * A counter that is decrement each time a PAUSE instruction is executed by the
583 * guest. When the counter is 0, a \#VMEXIT is triggered.
584 */
585 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilter", &pVM->hm.s.svm.cPauseFilter, 0);
586 AssertRCReturn(rc, rc);
587
588 /** @cfgm{/HM/SvmPauseFilterThreshold, uint16_t, 0}
589 * The pause filter threshold in ticks. When the elapsed time between two
590 * successive PAUSE instructions exceeds SvmPauseFilterThreshold, the PauseFilter
591 * count is reset to its initial value. However, if PAUSE is executed PauseFilter
592 * times within PauseFilterThreshold ticks, a VM-exit will be triggered.
593 *
594 * Setting both SvmPauseFilterCount and SvmPauseFilterCount to 0 disables
595 * pause-filter exiting.
596 */
597 rc = CFGMR3QueryU16Def(pCfgHm, "SvmPauseFilterThreshold", &pVM->hm.s.svm.cPauseFilterThresholdTicks, 0);
598 AssertRCReturn(rc, rc);
599
600 /** @cfgm{/HM/SvmVirtVmsaveVmload, bool, true}
601 * Whether to make use of virtualized VMSAVE/VMLOAD feature of the CPU if it's
602 * available. */
603 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVirtVmsaveVmload", &pVM->hm.s.svm.fVirtVmsaveVmload, true);
604 AssertRCReturn(rc, rc);
605
606 /** @cfgm{/HM/SvmVGif, bool, true}
607 * Whether to make use of Virtual GIF (Global Interrupt Flag) feature of the CPU
608 * if it's available. */
609 rc = CFGMR3QueryBoolDef(pCfgHm, "SvmVGif", &pVM->hm.s.svm.fVGif, true);
610 AssertRCReturn(rc, rc);
611
612 /** @cfgm{/HM/Exclusive, bool}
613 * Determines the init method for AMD-V and VT-x. If set to true, HM will do a
614 * global init for each host CPU. If false, we do local init each time we wish
615 * to execute guest code.
616 *
617 * On Windows, default is false due to the higher risk of conflicts with other
618 * hypervisors.
619 *
620 * On Mac OS X, this setting is ignored since the code does not handle local
621 * init when it utilizes the OS provided VT-x function, SUPR0EnableVTx().
622 */
623#if defined(RT_OS_DARWIN)
624 pVM->hm.s.fGlobalInit = true;
625#else
626 rc = CFGMR3QueryBoolDef(pCfgHm, "Exclusive", &pVM->hm.s.fGlobalInit,
627# if defined(RT_OS_WINDOWS)
628 false
629# else
630 true
631# endif
632 );
633 AssertLogRelRCReturn(rc, rc);
634#endif
635
636 /** @cfgm{/HM/MaxResumeLoops, uint32_t}
637 * The number of times to resume guest execution before we forcibly return to
638 * ring-3. The return value of RTThreadPreemptIsPendingTrusty in ring-0
639 * determines the default value. */
640 rc = CFGMR3QueryU32Def(pCfgHm, "MaxResumeLoops", &pVM->hm.s.cMaxResumeLoops, 0 /* set by R0 later */);
641 AssertLogRelRCReturn(rc, rc);
642
643 /** @cfgm{/HM/UseVmxPreemptTimer, bool}
644 * Whether to make use of the VMX-preemption timer feature of the CPU if it's
645 * available. */
646 rc = CFGMR3QueryBoolDef(pCfgHm, "UseVmxPreemptTimer", &pVM->hm.s.vmx.fUsePreemptTimer, true);
647 AssertLogRelRCReturn(rc, rc);
648
649 /** @cfgm{/HM/IBPBOnVMExit, bool}
650 * Costly paranoia setting. */
651 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMExit", &pVM->hm.s.fIbpbOnVmExit, false);
652 AssertLogRelRCReturn(rc, rc);
653
654 /** @cfgm{/HM/IBPBOnVMEntry, bool}
655 * Costly paranoia setting. */
656 rc = CFGMR3QueryBoolDef(pCfgHm, "IBPBOnVMEntry", &pVM->hm.s.fIbpbOnVmEntry, false);
657 AssertLogRelRCReturn(rc, rc);
658
659 /** @cfgm{/HM/SpecCtrlByHost, bool}
660 * Another expensive paranoia setting. */
661 rc = CFGMR3QueryBoolDef(pCfgHm, "SpecCtrlByHost", &pVM->hm.s.fSpecCtrlByHost, false);
662 AssertLogRelRCReturn(rc, rc);
663
664 /*
665 * Check if VT-x or AMD-v support according to the users wishes.
666 */
667 /** @todo SUPR3QueryVTCaps won't catch VERR_VMX_IN_VMX_ROOT_MODE or
668 * VERR_SVM_IN_USE. */
669 if (pVM->fHMEnabled)
670 {
671 uint32_t fCaps;
672 rc = SUPR3QueryVTCaps(&fCaps);
673 if (RT_SUCCESS(rc))
674 {
675 if (fCaps & SUPVTCAPS_AMD_V)
676 {
677 LogRel(("HM: HMR3Init: AMD-V%s\n", fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : ""));
678 pVM->hm.s.svm.fSupported = true;
679 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
680 }
681 else if (fCaps & SUPVTCAPS_VT_X)
682 {
683 const char *pszWhy;
684 rc = SUPR3QueryVTxSupported(&pszWhy);
685 if (RT_SUCCESS(rc))
686 {
687 LogRel(("HM: HMR3Init: VT-x%s%s%s\n",
688 fCaps & SUPVTCAPS_NESTED_PAGING ? " w/ nested paging" : "",
689 fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST ? " and unrestricted guest execution" : "",
690 (fCaps & (SUPVTCAPS_NESTED_PAGING | SUPVTCAPS_VTX_UNRESTRICTED_GUEST)) ? " hw support" : ""));
691 pVM->hm.s.vmx.fSupported = true;
692 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_HW_VIRT);
693 }
694 else
695 {
696 /*
697 * Before failing, try fallback to NEM if we're allowed to do that.
698 */
699 pVM->fHMEnabled = false;
700 Assert(pVM->bMainExecutionEngine == VM_EXEC_ENGINE_NOT_SET);
701 if (fFallbackToNEM)
702 {
703 LogRel(("HM: HMR3Init: Attempting fall back to NEM: The host kernel does not support VT-x - %s\n", pszWhy));
704 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
705
706 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
707 if ( RT_SUCCESS(rc2)
708 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
709 rc = VINF_SUCCESS;
710 }
711 if (RT_FAILURE(rc))
712 {
713 if (fHMForced)
714 return VMSetError(pVM, rc, RT_SRC_POS, "The host kernel does not support VT-x: %s\n", pszWhy);
715
716 /* Fall back to raw-mode. */
717 LogRel(("HM: HMR3Init: Falling back to raw-mode: The host kernel does not support VT-x - %s\n", pszWhy));
718 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
719 }
720 }
721 }
722 else
723 AssertLogRelMsgFailedReturn(("SUPR3QueryVTCaps didn't return either AMD-V or VT-x flag set (%#x)!\n", fCaps),
724 VERR_INTERNAL_ERROR_5);
725
726 /*
727 * Do we require a little bit or raw-mode for 64-bit guest execution?
728 */
729 pVM->fHMNeedRawModeCtx = HC_ARCH_BITS == 32
730 && pVM->fHMEnabled
731 && pVM->hm.s.fAllow64BitGuests;
732
733 /*
734 * Disable nested paging and unrestricted guest execution now if they're
735 * configured so that CPUM can make decisions based on our configuration.
736 */
737 Assert(!pVM->hm.s.fNestedPaging);
738 if (pVM->hm.s.fAllowNestedPaging)
739 {
740 if (fCaps & SUPVTCAPS_NESTED_PAGING)
741 pVM->hm.s.fNestedPaging = true;
742 else
743 pVM->hm.s.fAllowNestedPaging = false;
744 }
745
746 if (fCaps & SUPVTCAPS_VT_X)
747 {
748 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
749 if (pVM->hm.s.vmx.fAllowUnrestricted)
750 {
751 if ( (fCaps & SUPVTCAPS_VTX_UNRESTRICTED_GUEST)
752 && pVM->hm.s.fNestedPaging)
753 pVM->hm.s.vmx.fUnrestrictedGuest = true;
754 else
755 pVM->hm.s.vmx.fAllowUnrestricted = false;
756 }
757 }
758 }
759 else
760 {
761 const char *pszMsg;
762 switch (rc)
763 {
764 case VERR_UNSUPPORTED_CPU: pszMsg = "Unknown CPU, VT-x or AMD-v features cannot be ascertained"; break;
765 case VERR_VMX_NO_VMX: pszMsg = "VT-x is not available"; break;
766 case VERR_VMX_MSR_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS"; break;
767 case VERR_VMX_MSR_ALL_VMX_DISABLED: pszMsg = "VT-x is disabled in the BIOS for all CPU modes"; break;
768 case VERR_VMX_MSR_LOCKING_FAILED: pszMsg = "Failed to enable and lock VT-x features"; break;
769 case VERR_SVM_NO_SVM: pszMsg = "AMD-V is not available"; break;
770 case VERR_SVM_DISABLED: pszMsg = "AMD-V is disabled in the BIOS (or by the host OS)"; break;
771 default:
772 return VMSetError(pVM, rc, RT_SRC_POS, "SUPR3QueryVTCaps failed with %Rrc", rc);
773 }
774
775 /*
776 * Before failing, try fallback to NEM if we're allowed to do that.
777 */
778 pVM->fHMEnabled = false;
779 if (fFallbackToNEM)
780 {
781 LogRel(("HM: HMR3Init: Attempting fall back to NEM: %s\n", pszMsg));
782 int rc2 = NEMR3Init(pVM, true /*fFallback*/, fHMForced);
783 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
784 if ( RT_SUCCESS(rc2)
785 && pVM->bMainExecutionEngine != VM_EXEC_ENGINE_NOT_SET)
786 rc = VINF_SUCCESS;
787 }
788 if (RT_FAILURE(rc))
789 {
790 if (fHMForced)
791 return VM_SET_ERROR(pVM, rc, pszMsg);
792
793 LogRel(("HM: HMR3Init: Falling back to raw-mode: %s\n", pszMsg));
794 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
795 }
796 }
797 }
798 else
799 {
800 /*
801 * Disabled HM mean raw-mode, unless NEM is supposed to be used.
802 */
803 if (!fUseNEMInstead)
804 VM_SET_MAIN_EXECUTION_ENGINE(pVM, VM_EXEC_ENGINE_RAW_MODE);
805 else
806 {
807 rc = NEMR3Init(pVM, false /*fFallback*/, true);
808 ASMCompilerBarrier(); /* NEMR3Init may have changed bMainExecutionEngine. */
809 if (RT_FAILURE(rc))
810 return rc;
811 }
812 }
813
814 return VINF_SUCCESS;
815}
816
817
818/**
819 * Initializes the per-VCPU HM.
820 *
821 * @returns VBox status code.
822 * @param pVM The cross context VM structure.
823 */
824static int hmR3InitCPU(PVM pVM)
825{
826 LogFlow(("HMR3InitCPU\n"));
827
828 if (!HMIsEnabled(pVM))
829 return VINF_SUCCESS;
830
831 for (VMCPUID i = 0; i < pVM->cCpus; i++)
832 {
833 PVMCPU pVCpu = &pVM->aCpus[i];
834 pVCpu->hm.s.fActive = false;
835 }
836
837#ifdef VBOX_WITH_STATISTICS
838 STAM_REG(pVM, &pVM->hm.s.StatTprPatchSuccess, STAMTYPE_COUNTER, "/HM/TPR/Patch/Success", STAMUNIT_OCCURENCES, "Number of times an instruction was successfully patched.");
839 STAM_REG(pVM, &pVM->hm.s.StatTprPatchFailure, STAMTYPE_COUNTER, "/HM/TPR/Patch/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful patch attempts.");
840 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessCr8, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessCR8",STAMUNIT_OCCURENCES, "Number of instruction replacements by MOV CR8.");
841 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceSuccessVmc, STAMTYPE_COUNTER, "/HM/TPR/Replace/SuccessVMC",STAMUNIT_OCCURENCES, "Number of instruction replacements by VMMCALL.");
842 STAM_REG(pVM, &pVM->hm.s.StatTprReplaceFailure, STAMTYPE_COUNTER, "/HM/TPR/Replace/Failed", STAMUNIT_OCCURENCES, "Number of unsuccessful replace attempts.");
843#endif
844
845 /*
846 * Statistics.
847 */
848 for (VMCPUID i = 0; i < pVM->cCpus; i++)
849 {
850 PVMCPU pVCpu = &pVM->aCpus[i];
851 int rc;
852
853#ifdef VBOX_WITH_STATISTICS
854 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
855 "Profiling of RTMpPokeCpu",
856 "/PROF/CPU%d/HM/Poke", i);
857 AssertRC(rc);
858 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPoke, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
859 "Profiling of poke wait",
860 "/PROF/CPU%d/HM/PokeWait", i);
861 AssertRC(rc);
862 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatSpinPokeFailed, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
863 "Profiling of poke wait when RTMpPokeCpu fails",
864 "/PROF/CPU%d/HM/PokeWaitFailed", i);
865 AssertRC(rc);
866 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatEntry, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
867 "Profiling of VMXR0RunGuestCode entry",
868 "/PROF/CPU%d/HM/StatEntry", i);
869 AssertRC(rc);
870 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit1, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
871 "Profiling of VMXR0RunGuestCode exit part 1",
872 "/PROF/CPU%d/HM/SwitchFromGC_1", i);
873 AssertRC(rc);
874 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExit2, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
875 "Profiling of VMXR0RunGuestCode exit part 2",
876 "/PROF/CPU%d/HM/SwitchFromGC_2", i);
877 AssertRC(rc);
878
879 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitIO, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
880 "I/O",
881 "/PROF/CPU%d/HM/SwitchFromGC_2/IO", i);
882 AssertRC(rc);
883 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitMovCRx, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
884 "MOV CRx",
885 "/PROF/CPU%d/HM/SwitchFromGC_2/MovCRx", i);
886 AssertRC(rc);
887 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitXcptNmi, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
888 "Exceptions, NMIs",
889 "/PROF/CPU%d/HM/SwitchFromGC_2/XcptNmi", i);
890 AssertRC(rc);
891
892 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatLoadGuestState, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
893 "Profiling of VMXR0LoadGuestState",
894 "/PROF/CPU%d/HM/StatLoadGuestState", i);
895 AssertRC(rc);
896 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatInGC, STAMTYPE_PROFILE, STAMVISIBILITY_USED, STAMUNIT_TICKS_PER_CALL,
897 "Profiling of VMLAUNCH/VMRESUME.",
898 "/PROF/CPU%d/HM/InGC", i);
899 AssertRC(rc);
900
901# if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
902 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatWorldSwitch3264, STAMTYPE_PROFILE, STAMVISIBILITY_USED,
903 STAMUNIT_TICKS_PER_CALL, "Profiling of the 32/64 switcher.",
904 "/PROF/CPU%d/HM/Switcher3264", i);
905 AssertRC(rc);
906# endif
907
908# ifdef HM_PROFILE_EXIT_DISPATCH
909 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitDispatch, STAMTYPE_PROFILE_ADV, STAMVISIBILITY_USED,
910 STAMUNIT_TICKS_PER_CALL, "Profiling the dispatching of exit handlers.",
911 "/PROF/CPU%d/HM/ExitDispatch", i);
912 AssertRC(rc);
913# endif
914
915#endif
916# define HM_REG_COUNTER(a, b, desc) \
917 rc = STAMR3RegisterF(pVM, a, STAMTYPE_COUNTER, STAMVISIBILITY_ALWAYS, STAMUNIT_OCCURENCES, desc, b, i); \
918 AssertRC(rc);
919
920#ifdef VBOX_WITH_STATISTICS
921 HM_REG_COUNTER(&pVCpu->hm.s.StatExitAll, "/HM/CPU%d/Exit/All", "Exits (total).");
922 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowNM, "/HM/CPU%d/Exit/Trap/Shw/#NM", "Shadow #NM (device not available, no math co-processor) exception.");
923 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNM, "/HM/CPU%d/Exit/Trap/Gst/#NM", "Guest #NM (device not available, no math co-processor) exception.");
924 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPF, "/HM/CPU%d/Exit/Trap/Shw/#PF", "Shadow #PF (page fault) exception.");
925 HM_REG_COUNTER(&pVCpu->hm.s.StatExitShadowPFEM, "/HM/CPU%d/Exit/Trap/Shw/#PF-EM", "#PF (page fault) exception going back to ring-3 for emulating the instruction.");
926 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestPF, "/HM/CPU%d/Exit/Trap/Gst/#PF", "Guest #PF (page fault) exception.");
927 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestUD, "/HM/CPU%d/Exit/Trap/Gst/#UD", "Guest #UD (undefined opcode) exception.");
928 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestSS, "/HM/CPU%d/Exit/Trap/Gst/#SS", "Guest #SS (stack-segment fault) exception.");
929 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestNP, "/HM/CPU%d/Exit/Trap/Gst/#NP", "Guest #NP (segment not present) exception.");
930 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestGP, "/HM/CPU%d/Exit/Trap/Gst/#GP", "Guest #GP (general protection) exception.");
931 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestMF, "/HM/CPU%d/Exit/Trap/Gst/#MF", "Guest #MF (x87 FPU error, math fault) exception.");
932 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDE, "/HM/CPU%d/Exit/Trap/Gst/#DE", "Guest #DE (divide error) exception.");
933 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestDB, "/HM/CPU%d/Exit/Trap/Gst/#DB", "Guest #DB (debug) exception.");
934 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestBP, "/HM/CPU%d/Exit/Trap/Gst/#BP", "Guest #BP (breakpoint) exception.");
935 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXF, "/HM/CPU%d/Exit/Trap/Gst/#XF", "Guest #XF (extended math fault, SIMD FPU) exception.");
936 HM_REG_COUNTER(&pVCpu->hm.s.StatExitGuestXcpUnk, "/HM/CPU%d/Exit/Trap/Gst/Other", "Other guest exceptions.");
937 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvlpg, "/HM/CPU%d/Exit/Instr/Invlpg", "Guest attempted to execute INVLPG.");
938 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInvd, "/HM/CPU%d/Exit/Instr/Invd", "Guest attempted to execute INVD.");
939 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWbinvd, "/HM/CPU%d/Exit/Instr/Wbinvd", "Guest attempted to execute WBINVD.");
940 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPause, "/HM/CPU%d/Exit/Instr/Pause", "Guest attempted to execute PAUSE.");
941 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCpuid, "/HM/CPU%d/Exit/Instr/Cpuid", "Guest attempted to execute CPUID.");
942 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtsc, "/HM/CPU%d/Exit/Instr/Rdtsc", "Guest attempted to execute RDTSC.");
943 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdtscp, "/HM/CPU%d/Exit/Instr/Rdtscp", "Guest attempted to execute RDTSCP.");
944 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdpmc, "/HM/CPU%d/Exit/Instr/Rdpmc", "Guest attempted to execute RDPMC.");
945 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdrand, "/HM/CPU%d/Exit/Instr/Rdrand", "Guest attempted to execute RDRAND.");
946 HM_REG_COUNTER(&pVCpu->hm.s.StatExitRdmsr, "/HM/CPU%d/Exit/Instr/Rdmsr", "Guest attempted to execute RDMSR.");
947 HM_REG_COUNTER(&pVCpu->hm.s.StatExitWrmsr, "/HM/CPU%d/Exit/Instr/Wrmsr", "Guest attempted to execute WRMSR.");
948 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMwait, "/HM/CPU%d/Exit/Instr/Mwait", "Guest attempted to execute MWAIT.");
949 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMonitor, "/HM/CPU%d/Exit/Instr/Monitor", "Guest attempted to execute MONITOR.");
950 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxWrite, "/HM/CPU%d/Exit/Instr/DR/Write", "Guest attempted to write a debug register.");
951 HM_REG_COUNTER(&pVCpu->hm.s.StatExitDRxRead, "/HM/CPU%d/Exit/Instr/DR/Read", "Guest attempted to read a debug register.");
952 HM_REG_COUNTER(&pVCpu->hm.s.StatExitClts, "/HM/CPU%d/Exit/Instr/CLTS", "Guest attempted to execute CLTS.");
953 HM_REG_COUNTER(&pVCpu->hm.s.StatExitLmsw, "/HM/CPU%d/Exit/Instr/LMSW", "Guest attempted to execute LMSW.");
954 HM_REG_COUNTER(&pVCpu->hm.s.StatExitCli, "/HM/CPU%d/Exit/Instr/Cli", "Guest attempted to execute CLI.");
955 HM_REG_COUNTER(&pVCpu->hm.s.StatExitSti, "/HM/CPU%d/Exit/Instr/Sti", "Guest attempted to execute STI.");
956 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPushf, "/HM/CPU%d/Exit/Instr/Pushf", "Guest attempted to execute PUSHF.");
957 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPopf, "/HM/CPU%d/Exit/Instr/Popf", "Guest attempted to execute POPF.");
958 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIret, "/HM/CPU%d/Exit/Instr/Iret", "Guest attempted to execute IRET.");
959 HM_REG_COUNTER(&pVCpu->hm.s.StatExitInt, "/HM/CPU%d/Exit/Instr/Int", "Guest attempted to execute INT.");
960 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHlt, "/HM/CPU%d/Exit/Instr/Hlt", "Guest attempted to execute HLT.");
961 HM_REG_COUNTER(&pVCpu->hm.s.StatExitXdtrAccess, "/HM/CPU%d/Exit/Instr/XdtrAccess", "Guest attempted to access descriptor table register (GDTR, IDTR, LDTR).");
962 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOWrite, "/HM/CPU%d/Exit/IO/Write", "I/O write.");
963 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIORead, "/HM/CPU%d/Exit/IO/Read", "I/O read.");
964 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringWrite, "/HM/CPU%d/Exit/IO/WriteString", "String I/O write.");
965 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIOStringRead, "/HM/CPU%d/Exit/IO/ReadString", "String I/O read.");
966 HM_REG_COUNTER(&pVCpu->hm.s.StatExitIntWindow, "/HM/CPU%d/Exit/IntWindow", "Interrupt-window exit. Guest is ready to receive interrupts again.");
967 HM_REG_COUNTER(&pVCpu->hm.s.StatExitExtInt, "/HM/CPU%d/Exit/ExtInt", "Host interrupt received.");
968#endif
969 HM_REG_COUNTER(&pVCpu->hm.s.StatExitHostNmiInGC, "/HM/CPU%d/Exit/HostNmiInGC", "Host NMI received while in guest context.");
970#ifdef VBOX_WITH_STATISTICS
971 HM_REG_COUNTER(&pVCpu->hm.s.StatExitPreemptTimer, "/HM/CPU%d/Exit/PreemptTimer", "VMX-preemption timer expired.");
972 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTprBelowThreshold, "/HM/CPU%d/Exit/TprBelowThreshold", "TPR lowered below threshold by the guest.");
973 HM_REG_COUNTER(&pVCpu->hm.s.StatExitTaskSwitch, "/HM/CPU%d/Exit/TaskSwitch", "Guest attempted a task switch.");
974 HM_REG_COUNTER(&pVCpu->hm.s.StatExitMtf, "/HM/CPU%d/Exit/MonitorTrapFlag", "Monitor Trap Flag.");
975 HM_REG_COUNTER(&pVCpu->hm.s.StatExitApicAccess, "/HM/CPU%d/Exit/ApicAccess", "APIC access. Guest attempted to access memory at a physical address on the APIC-access page.");
976
977 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchTprMaskedIrq, "/HM/CPU%d/Switch/TprMaskedIrq", "PDMGetInterrupt() signals TPR masks pending Irq.");
978 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchGuestIrq, "/HM/CPU%d/Switch/IrqPending", "PDMGetInterrupt() cleared behind our back!?!.");
979 HM_REG_COUNTER(&pVCpu->hm.s.StatPendingHostIrq, "/HM/CPU%d/Switch/PendingHostIrq", "Exit to ring-3 due to pending host interrupt before executing guest code.");
980 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHmToR3FF, "/HM/CPU%d/Switch/HmToR3FF", "Exit to ring-3 due to pending timers, EMT rendezvous, critical section etc.");
981 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchExitToR3, "/HM/CPU%d/Switch/ExitToR3", "Exit to ring-3 (total).");
982 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchLongJmpToR3, "/HM/CPU%d/Switch/LongJmpToR3", "Longjump to ring-3.");
983 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchMaxResumeLoops, "/HM/CPU%d/Switch/MaxResumeToR3", "Maximum VMRESUME inner-loop counter reached.");
984 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchHltToR3, "/HM/CPU%d/Switch/HltToR3", "HLT causing us to go to ring-3.");
985 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchApicAccessToR3, "/HM/CPU%d/Switch/ApicAccessToR3", "APIC access causing us to go to ring-3.");
986#endif
987 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreempt, "/HM/CPU%d/Switch/Preempting", "EMT has been preempted while in HM context.");
988#ifdef VBOX_WITH_STATISTICS
989 HM_REG_COUNTER(&pVCpu->hm.s.StatSwitchPreemptSaveHostState, "/HM/CPU%d/Switch/SaveHostState", "Preemption caused us to resave host state.");
990
991 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectInterrupt, "/HM/CPU%d/EventInject/Interrupt", "Injected an external interrupt into the guest.");
992 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectXcpt, "/HM/CPU%d/EventInject/Trap", "Injected an exception into the guest.");
993 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingReflect, "/HM/CPU%d/EventInject/PendingReflect", "Reflecting an exception (or #DF) caused due to event injection.");
994 HM_REG_COUNTER(&pVCpu->hm.s.StatInjectPendingInterpret, "/HM/CPU%d/EventInject/PendingInterpret", "Falling to interpreter for handling exception caused due to event injection.");
995
996 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPage, "/HM/CPU%d/Flush/Page", "Invalidating a guest page on all guest CPUs.");
997 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPageManual, "/HM/CPU%d/Flush/Page/Virt", "Invalidating a guest page using guest-virtual address.");
998 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushPhysPageManual, "/HM/CPU%d/Flush/Page/Phys", "Invalidating a guest page using guest-physical address.");
999 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlb, "/HM/CPU%d/Flush/TLB", "Forcing a full guest-TLB flush (ring-0).");
1000 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbManual, "/HM/CPU%d/Flush/TLB/Manual", "Request a full guest-TLB flush.");
1001 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/CpuSwitch", "Forcing a full guest-TLB flush due to host-CPU reschedule or ASID-limit hit by another guest-VCPU.");
1002 HM_REG_COUNTER(&pVCpu->hm.s.StatNoFlushTlbWorldSwitch, "/HM/CPU%d/Flush/TLB/Skipped", "No TLB flushing required.");
1003 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushEntire, "/HM/CPU%d/Flush/TLB/Entire", "Flush the entire TLB (host + guest).");
1004 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushAsid, "/HM/CPU%d/Flush/TLB/ASID", "Flushed guest-TLB entries for the current VPID.");
1005 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushNestedPaging, "/HM/CPU%d/Flush/TLB/NestedPaging", "Flushed guest-TLB entries for the current EPT.");
1006 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgVirt, "/HM/CPU%d/Flush/TLB/InvlpgVirt", "Invalidated a guest-TLB entry for a guest-virtual address.");
1007 HM_REG_COUNTER(&pVCpu->hm.s.StatFlushTlbInvlpgPhys, "/HM/CPU%d/Flush/TLB/InvlpgPhys", "Currently not possible, flushes entire guest-TLB.");
1008 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdown, "/HM/CPU%d/Flush/Shootdown/Page", "Inter-VCPU request to flush queued guest page.");
1009 HM_REG_COUNTER(&pVCpu->hm.s.StatTlbShootdownFlush, "/HM/CPU%d/Flush/Shootdown/TLB", "Inter-VCPU request to flush entire guest-TLB.");
1010
1011 HM_REG_COUNTER(&pVCpu->hm.s.StatTscParavirt, "/HM/CPU%d/TSC/Paravirt", "Paravirtualized TSC in effect.");
1012 HM_REG_COUNTER(&pVCpu->hm.s.StatTscOffset, "/HM/CPU%d/TSC/Offset", "TSC offsetting is in effect.");
1013 HM_REG_COUNTER(&pVCpu->hm.s.StatTscIntercept, "/HM/CPU%d/TSC/Intercept", "Intercept TSC accesses.");
1014
1015 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxArmed, "/HM/CPU%d/Debug/Armed", "Loaded guest-debug state while loading guest-state.");
1016 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxContextSwitch, "/HM/CPU%d/Debug/ContextSwitch", "Loaded guest-debug state on MOV DRx.");
1017 HM_REG_COUNTER(&pVCpu->hm.s.StatDRxIoCheck, "/HM/CPU%d/Debug/IOCheck", "Checking for I/O breakpoint.");
1018
1019 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadMinimal, "/HM/CPU%d/Load/Minimal", "VM-entry loading minimal guest-state.");
1020 HM_REG_COUNTER(&pVCpu->hm.s.StatLoadFull, "/HM/CPU%d/Load/Full", "VM-entry loading the full guest-state.");
1021
1022 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelBase, "/HM/CPU%d/VMXCheck/RMSelBase", "Could not use VMX due to unsuitable real-mode selector base.");
1023 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit, "/HM/CPU%d/VMXCheck/RMSelLimit", "Could not use VMX due to unsuitable real-mode selector limit.");
1024 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckRmOk, "/HM/CPU%d/VMXCheck/VMX_RM", "VMX execution in real (V86) mode OK.");
1025 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadSel, "/HM/CPU%d/VMXCheck/Selector", "Could not use VMX due to unsuitable selector.");
1026 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadRpl, "/HM/CPU%d/VMXCheck/RPL", "Could not use VMX due to unsuitable RPL.");
1027 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadLdt, "/HM/CPU%d/VMXCheck/LDT", "Could not use VMX due to unsuitable LDT.");
1028 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckBadTr, "/HM/CPU%d/VMXCheck/TR", "Could not use VMX due to unsuitable TR.");
1029 HM_REG_COUNTER(&pVCpu->hm.s.StatVmxCheckPmOk, "/HM/CPU%d/VMXCheck/VMX_PM", "VMX execution in protected mode OK.");
1030
1031#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1032 HM_REG_COUNTER(&pVCpu->hm.s.StatFpu64SwitchBack, "/HM/CPU%d/Switch64/Fpu", "Saving guest FPU/XMM state.");
1033 HM_REG_COUNTER(&pVCpu->hm.s.StatDebug64SwitchBack, "/HM/CPU%d/Switch64/Debug", "Saving guest debug state.");
1034#endif
1035
1036 for (unsigned j = 0; j < RT_ELEMENTS(pVCpu->hm.s.StatExitCRxWrite); j++)
1037 {
1038 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxWrite[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1039 STAMUNIT_OCCURENCES, "Profiling of CRx writes",
1040 "/HM/CPU%d/Exit/Instr/CR/Write/%x", i, j);
1041 AssertRC(rc);
1042 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitCRxRead[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1043 STAMUNIT_OCCURENCES, "Profiling of CRx reads",
1044 "/HM/CPU%d/Exit/Instr/CR/Read/%x", i, j);
1045 AssertRC(rc);
1046 }
1047
1048#undef HM_REG_COUNTER
1049
1050 const char *const *papszDesc = ASMIsIntelCpu() || ASMIsViaCentaurCpu() ? &g_apszVTxExitReasons[0]
1051 : &g_apszAmdVExitReasons[0];
1052
1053 /*
1054 * Guest Exit reason stats.
1055 */
1056 pVCpu->hm.s.paStatExitReason = NULL;
1057 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatExitReason), 0 /* uAlignment */, MM_TAG_HM,
1058 (void **)&pVCpu->hm.s.paStatExitReason);
1059 AssertRCReturn(rc, rc);
1060 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1061 {
1062 if (papszDesc[j])
1063 {
1064 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1065 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/Exit/Reason/%02x", i, j);
1066 AssertRCReturn(rc, rc);
1067 }
1068 }
1069 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1070 "Nested page fault", "/HM/CPU%d/Exit/Reason/#NPF", i);
1071 AssertRCReturn(rc, rc);
1072 pVCpu->hm.s.paStatExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatExitReason);
1073# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1074 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1075# else
1076 Assert(pVCpu->hm.s.paStatExitReasonR0 != NIL_RTR0PTR);
1077# endif
1078
1079#ifdef VBOX_WITH_NESTED_HWVIRT
1080 /*
1081 * Nested-guest Exit reason stats.
1082 */
1083 pVCpu->hm.s.paStatNestedExitReason = NULL;
1084 rc = MMHyperAlloc(pVM, MAX_EXITREASON_STAT * sizeof(*pVCpu->hm.s.paStatNestedExitReason), 0 /* uAlignment */, MM_TAG_HM,
1085 (void **)&pVCpu->hm.s.paStatNestedExitReason);
1086 AssertRCReturn(rc, rc);
1087 for (int j = 0; j < MAX_EXITREASON_STAT; j++)
1088 {
1089 if (papszDesc[j])
1090 {
1091 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatNestedExitReason[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1092 STAMUNIT_OCCURENCES, papszDesc[j], "/HM/CPU%d/NestedExit/Reason/%02x", i, j);
1093 AssertRC(rc);
1094 }
1095 }
1096 rc = STAMR3RegisterF(pVM, &pVCpu->hm.s.StatNestedExitReasonNpf, STAMTYPE_COUNTER, STAMVISIBILITY_USED,
1097 STAMUNIT_OCCURENCES, "Nested page fault", "/HM/CPU%d/NestedExit/Reason/#NPF", i);
1098 AssertRCReturn(rc, rc);
1099 pVCpu->hm.s.paStatNestedExitReasonR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatNestedExitReason);
1100# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1101 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1102# else
1103 Assert(pVCpu->hm.s.paStatNestedExitReasonR0 != NIL_RTR0PTR);
1104# endif
1105#endif
1106
1107 /*
1108 * Injected events stats.
1109 */
1110 rc = MMHyperAlloc(pVM, sizeof(STAMCOUNTER) * 256, 8, MM_TAG_HM, (void **)&pVCpu->hm.s.paStatInjectedIrqs);
1111 AssertRCReturn(rc, rc);
1112 pVCpu->hm.s.paStatInjectedIrqsR0 = MMHyperR3ToR0(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1113# ifdef VBOX_WITH_2X_4GB_ADDR_SPACE
1114 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR || !HMIsEnabled(pVM));
1115# else
1116 Assert(pVCpu->hm.s.paStatInjectedIrqsR0 != NIL_RTR0PTR);
1117# endif
1118 for (unsigned j = 0; j < 255; j++)
1119 {
1120 STAMR3RegisterF(pVM, &pVCpu->hm.s.paStatInjectedIrqs[j], STAMTYPE_COUNTER, STAMVISIBILITY_USED, STAMUNIT_OCCURENCES,
1121 "Injected event.",
1122 (j < 0x20) ? "/HM/CPU%d/EventInject/InjectTrap/%02X" : "/HM/CPU%d/EventInject/InjectIRQ/%02X", i, j);
1123 }
1124
1125#endif /* VBOX_WITH_STATISTICS */
1126 }
1127
1128#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1129 /*
1130 * Magic marker for searching in crash dumps.
1131 */
1132 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1133 {
1134 PVMCPU pVCpu = &pVM->aCpus[i];
1135
1136 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
1137 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
1138 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
1139 }
1140#endif
1141
1142 return VINF_SUCCESS;
1143}
1144
1145
1146/**
1147 * Called when a init phase has completed.
1148 *
1149 * @returns VBox status code.
1150 * @param pVM The cross context VM structure.
1151 * @param enmWhat The phase that completed.
1152 */
1153VMMR3_INT_DECL(int) HMR3InitCompleted(PVM pVM, VMINITCOMPLETED enmWhat)
1154{
1155 switch (enmWhat)
1156 {
1157 case VMINITCOMPLETED_RING3:
1158 return hmR3InitCPU(pVM);
1159 case VMINITCOMPLETED_RING0:
1160 return hmR3InitFinalizeR0(pVM);
1161 default:
1162 return VINF_SUCCESS;
1163 }
1164}
1165
1166
1167/**
1168 * Turns off normal raw mode features.
1169 *
1170 * @param pVM The cross context VM structure.
1171 */
1172static void hmR3DisableRawMode(PVM pVM)
1173{
1174 /* Reinit the paging mode to force the new shadow mode. */
1175 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1176 {
1177 PVMCPU pVCpu = &pVM->aCpus[i];
1178
1179 PGMR3ChangeMode(pVM, pVCpu, PGMMODE_REAL);
1180 }
1181}
1182
1183
1184/**
1185 * Initialize VT-x or AMD-V.
1186 *
1187 * @returns VBox status code.
1188 * @param pVM The cross context VM structure.
1189 */
1190static int hmR3InitFinalizeR0(PVM pVM)
1191{
1192 int rc;
1193
1194 if (!HMIsEnabled(pVM))
1195 return VINF_SUCCESS;
1196
1197 /*
1198 * Hack to allow users to work around broken BIOSes that incorrectly set
1199 * EFER.SVME, which makes us believe somebody else is already using AMD-V.
1200 */
1201 if ( !pVM->hm.s.vmx.fSupported
1202 && !pVM->hm.s.svm.fSupported
1203 && pVM->hm.s.lLastError == VERR_SVM_IN_USE /* implies functional AMD-V */
1204 && RTEnvExist("VBOX_HWVIRTEX_IGNORE_SVM_IN_USE"))
1205 {
1206 LogRel(("HM: VBOX_HWVIRTEX_IGNORE_SVM_IN_USE active!\n"));
1207 pVM->hm.s.svm.fSupported = true;
1208 pVM->hm.s.svm.fIgnoreInUseError = true;
1209 pVM->hm.s.lLastError = VINF_SUCCESS;
1210 }
1211
1212 /*
1213 * Report ring-0 init errors.
1214 */
1215 if ( !pVM->hm.s.vmx.fSupported
1216 && !pVM->hm.s.svm.fSupported)
1217 {
1218 LogRel(("HM: Failed to initialize VT-x / AMD-V: %Rrc\n", pVM->hm.s.lLastError));
1219 LogRel(("HM: VMX MSR_IA32_FEATURE_CONTROL=%RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1220 switch (pVM->hm.s.lLastError)
1221 {
1222 case VERR_VMX_IN_VMX_ROOT_MODE:
1223 return VM_SET_ERROR(pVM, VERR_VMX_IN_VMX_ROOT_MODE, "VT-x is being used by another hypervisor");
1224 case VERR_VMX_NO_VMX:
1225 return VM_SET_ERROR(pVM, VERR_VMX_NO_VMX, "VT-x is not available");
1226 case VERR_VMX_MSR_VMX_DISABLED:
1227 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_DISABLED, "VT-x is disabled in the BIOS");
1228 case VERR_VMX_MSR_ALL_VMX_DISABLED:
1229 return VM_SET_ERROR(pVM, VERR_VMX_MSR_ALL_VMX_DISABLED, "VT-x is disabled in the BIOS for all CPU modes");
1230 case VERR_VMX_MSR_LOCKING_FAILED:
1231 return VM_SET_ERROR(pVM, VERR_VMX_MSR_LOCKING_FAILED, "Failed to lock VT-x features while trying to enable VT-x");
1232 case VERR_VMX_MSR_VMX_ENABLE_FAILED:
1233 return VM_SET_ERROR(pVM, VERR_VMX_MSR_VMX_ENABLE_FAILED, "Failed to enable VT-x features");
1234 case VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED:
1235 return VM_SET_ERROR(pVM, VERR_VMX_MSR_SMX_VMX_ENABLE_FAILED, "Failed to enable VT-x features in SMX mode");
1236
1237 case VERR_SVM_IN_USE:
1238 return VM_SET_ERROR(pVM, VERR_SVM_IN_USE, "AMD-V is being used by another hypervisor");
1239 case VERR_SVM_NO_SVM:
1240 return VM_SET_ERROR(pVM, VERR_SVM_NO_SVM, "AMD-V is not available");
1241 case VERR_SVM_DISABLED:
1242 return VM_SET_ERROR(pVM, VERR_SVM_DISABLED, "AMD-V is disabled in the BIOS");
1243 }
1244 return VMSetError(pVM, pVM->hm.s.lLastError, RT_SRC_POS, "HM ring-0 init failed: %Rrc", pVM->hm.s.lLastError);
1245 }
1246
1247 /*
1248 * Enable VT-x or AMD-V on all host CPUs.
1249 */
1250 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_ENABLE, 0, NULL);
1251 if (RT_FAILURE(rc))
1252 {
1253 LogRel(("HM: Failed to enable, error %Rrc\n", rc));
1254 HMR3CheckError(pVM, rc);
1255 return rc;
1256 }
1257
1258 /*
1259 * No TPR patching is required when the IO-APIC is not enabled for this VM.
1260 * (Main should have taken care of this already)
1261 */
1262 if (!PDMHasIoApic(pVM))
1263 {
1264 Assert(!pVM->hm.s.fTprPatchingAllowed); /* paranoia */
1265 pVM->hm.s.fTprPatchingAllowed = false;
1266 }
1267
1268 /*
1269 * Sync options.
1270 */
1271 /** @todo Move this out of of CPUMCTX and into some ring-0 only HM structure.
1272 * That will require a little bit of work, of course. */
1273 for (VMCPUID iCpu = 0; iCpu < pVM->cCpus; iCpu++)
1274 {
1275 PVMCPU pVCpu = &pVM->aCpus[iCpu];
1276 PCPUMCTX pCpuCtx = CPUMQueryGuestCtxPtr(pVCpu);
1277 pCpuCtx->fWorldSwitcher &= ~(CPUMCTX_WSF_IBPB_EXIT | CPUMCTX_WSF_IBPB_ENTRY);
1278 if (pVM->cpum.ro.HostFeatures.fIbpb)
1279 {
1280 if (pVM->hm.s.fIbpbOnVmExit)
1281 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_EXIT;
1282 if (pVM->hm.s.fIbpbOnVmEntry)
1283 pCpuCtx->fWorldSwitcher |= CPUMCTX_WSF_IBPB_ENTRY;
1284 }
1285 if (iCpu == 0)
1286 LogRel(("HM: fWorldSwitcher=%#x (fIbpbOnVmExit=%RTbool fIbpbOnVmEntry=%RTbool)\n",
1287 pCpuCtx->fWorldSwitcher, pVM->hm.s.fIbpbOnVmExit, pVM->hm.s.fIbpbOnVmEntry));
1288 }
1289
1290 /*
1291 * Do the vendor specific initialization
1292 *
1293 * Note! We disable release log buffering here since we're doing relatively
1294 * lot of logging and doesn't want to hit the disk with each LogRel
1295 * statement.
1296 */
1297 AssertLogRelReturn(!pVM->hm.s.fInitialized, VERR_HM_IPE_5);
1298 bool fOldBuffered = RTLogRelSetBuffering(true /*fBuffered*/);
1299 if (pVM->hm.s.vmx.fSupported)
1300 rc = hmR3InitFinalizeR0Intel(pVM);
1301 else
1302 rc = hmR3InitFinalizeR0Amd(pVM);
1303 LogRel(("HM: VT-x/AMD-V init method: %s\n", (pVM->hm.s.fGlobalInit) ? "GLOBAL" : "LOCAL"));
1304 RTLogRelSetBuffering(fOldBuffered);
1305 pVM->hm.s.fInitialized = true;
1306
1307 return rc;
1308}
1309
1310
1311/**
1312 * @callback_method_impl{FNPDMVMMDEVHEAPNOTIFY}
1313 */
1314static DECLCALLBACK(void) hmR3VmmDevHeapNotify(PVM pVM, void *pvAllocation, RTGCPHYS GCPhysAllocation)
1315{
1316 NOREF(pVM);
1317 NOREF(pvAllocation);
1318 NOREF(GCPhysAllocation);
1319}
1320
1321
1322/**
1323 * Finish VT-x initialization (after ring-0 init).
1324 *
1325 * @returns VBox status code.
1326 * @param pVM The cross context VM structure.
1327 */
1328static int hmR3InitFinalizeR0Intel(PVM pVM)
1329{
1330 int rc;
1331
1332 Log(("pVM->hm.s.vmx.fSupported = %d\n", pVM->hm.s.vmx.fSupported));
1333 AssertLogRelReturn(pVM->hm.s.vmx.Msrs.u64FeatureCtrl != 0, VERR_HM_IPE_4);
1334
1335 uint64_t val;
1336 uint64_t zap;
1337
1338 LogRel(("HM: Using VT-x implementation 2.0\n"));
1339 LogRel(("HM: Host CR4 = %#RX64\n", pVM->hm.s.vmx.u64HostCr4));
1340 LogRel(("HM: Host EFER = %#RX64\n", pVM->hm.s.vmx.u64HostEfer));
1341 LogRel(("HM: MSR_IA32_SMM_MONITOR_CTL = %#RX64\n", pVM->hm.s.vmx.u64HostSmmMonitorCtl));
1342 LogRel(("HM: MSR_IA32_FEATURE_CONTROL = %#RX64\n", pVM->hm.s.vmx.Msrs.u64FeatureCtrl));
1343 if (!(pVM->hm.s.vmx.Msrs.u64FeatureCtrl & MSR_IA32_FEATURE_CONTROL_LOCK))
1344 LogRel(("HM: IA32_FEATURE_CONTROL lock bit not set, possibly bad hardware!\n"));
1345 LogRel(("HM: MSR_IA32_VMX_BASIC_INFO = %#RX64\n", pVM->hm.s.vmx.Msrs.u64BasicInfo));
1346 LogRel(("HM: VMCS id = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_ID(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1347 LogRel(("HM: VMCS size = %u bytes\n", MSR_IA32_VMX_BASIC_INFO_VMCS_SIZE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1348 LogRel(("HM: VMCS physical address limit = %s\n", MSR_IA32_VMX_BASIC_INFO_VMCS_PHYS_WIDTH(pVM->hm.s.vmx.Msrs.u64BasicInfo) ? "< 4 GB" : "None"));
1349 LogRel(("HM: VMCS memory type = %#x\n", MSR_IA32_VMX_BASIC_INFO_VMCS_MEM_TYPE(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1350 LogRel(("HM: Dual-monitor treatment support = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_DUAL_MON(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1351 LogRel(("HM: OUTS & INS instruction-info = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_VMCS_INS_OUTS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1352 LogRel(("HM: Supports true capability MSRs = %RTbool\n", MSR_IA32_VMX_BASIC_INFO_TRUE_CONTROLS(pVM->hm.s.vmx.Msrs.u64BasicInfo)));
1353 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1354
1355 LogRel(("HM: MSR_IA32_VMX_PINBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxPinCtls.u));
1356 val = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1;
1357 zap = pVM->hm.s.vmx.Msrs.VmxPinCtls.n.disallowed0;
1358 HMVMX_REPORT_FEATURE(val, zap, "EXT_INT_EXIT", VMX_VMCS_CTRL_PIN_EXEC_EXT_INT_EXIT);
1359 HMVMX_REPORT_FEATURE(val, zap, "NMI_EXIT", VMX_VMCS_CTRL_PIN_EXEC_NMI_EXIT);
1360 HMVMX_REPORT_FEATURE(val, zap, "VIRTUAL_NMI", VMX_VMCS_CTRL_PIN_EXEC_VIRTUAL_NMI);
1361 HMVMX_REPORT_FEATURE(val, zap, "PREEMPT_TIMER", VMX_VMCS_CTRL_PIN_EXEC_PREEMPT_TIMER);
1362 HMVMX_REPORT_FEATURE(val, zap, "POSTED_INTR", VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR);
1363
1364 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls.u));
1365 val = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1;
1366 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls.n.disallowed0;
1367 HMVMX_REPORT_FEATURE(val, zap, "INT_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INT_WINDOW_EXIT);
1368 HMVMX_REPORT_FEATURE(val, zap, "USE_TSC_OFFSETTING", VMX_VMCS_CTRL_PROC_EXEC_USE_TSC_OFFSETTING);
1369 HMVMX_REPORT_FEATURE(val, zap, "HLT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_HLT_EXIT);
1370 HMVMX_REPORT_FEATURE(val, zap, "INVLPG_EXIT", VMX_VMCS_CTRL_PROC_EXEC_INVLPG_EXIT);
1371 HMVMX_REPORT_FEATURE(val, zap, "MWAIT_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MWAIT_EXIT);
1372 HMVMX_REPORT_FEATURE(val, zap, "RDPMC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDPMC_EXIT);
1373 HMVMX_REPORT_FEATURE(val, zap, "RDTSC_EXIT", VMX_VMCS_CTRL_PROC_EXEC_RDTSC_EXIT);
1374 HMVMX_REPORT_FEATURE(val, zap, "CR3_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_LOAD_EXIT);
1375 HMVMX_REPORT_FEATURE(val, zap, "CR3_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR3_STORE_EXIT);
1376 HMVMX_REPORT_FEATURE(val, zap, "CR8_LOAD_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_LOAD_EXIT);
1377 HMVMX_REPORT_FEATURE(val, zap, "CR8_STORE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_CR8_STORE_EXIT);
1378 HMVMX_REPORT_FEATURE(val, zap, "USE_TPR_SHADOW", VMX_VMCS_CTRL_PROC_EXEC_USE_TPR_SHADOW);
1379 HMVMX_REPORT_FEATURE(val, zap, "NMI_WINDOW_EXIT", VMX_VMCS_CTRL_PROC_EXEC_NMI_WINDOW_EXIT);
1380 HMVMX_REPORT_FEATURE(val, zap, "MOV_DR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MOV_DR_EXIT);
1381 HMVMX_REPORT_FEATURE(val, zap, "UNCOND_IO_EXIT", VMX_VMCS_CTRL_PROC_EXEC_UNCOND_IO_EXIT);
1382 HMVMX_REPORT_FEATURE(val, zap, "USE_IO_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_IO_BITMAPS);
1383 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_TRAP_FLAG", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_TRAP_FLAG);
1384 HMVMX_REPORT_FEATURE(val, zap, "USE_MSR_BITMAPS", VMX_VMCS_CTRL_PROC_EXEC_USE_MSR_BITMAPS);
1385 HMVMX_REPORT_FEATURE(val, zap, "MONITOR_EXIT", VMX_VMCS_CTRL_PROC_EXEC_MONITOR_EXIT);
1386 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_EXIT", VMX_VMCS_CTRL_PROC_EXEC_PAUSE_EXIT);
1387 HMVMX_REPORT_FEATURE(val, zap, "USE_SECONDARY_EXEC_CTRL", VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL);
1388 if (pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1389 {
1390 LogRel(("HM: MSR_IA32_VMX_PROCBASED_CTLS2 = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxProcCtls2.u));
1391 val = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1;
1392 zap = pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.disallowed0;
1393 HMVMX_REPORT_FEATURE(val, zap, "VIRT_APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_APIC);
1394 HMVMX_REPORT_FEATURE(val, zap, "EPT", VMX_VMCS_CTRL_PROC_EXEC2_EPT);
1395 HMVMX_REPORT_FEATURE(val, zap, "DESCRIPTOR_TABLE_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_DESCRIPTOR_TABLE_EXIT);
1396 HMVMX_REPORT_FEATURE(val, zap, "RDTSCP", VMX_VMCS_CTRL_PROC_EXEC2_RDTSCP);
1397 HMVMX_REPORT_FEATURE(val, zap, "VIRT_X2APIC", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_X2APIC);
1398 HMVMX_REPORT_FEATURE(val, zap, "VPID", VMX_VMCS_CTRL_PROC_EXEC2_VPID);
1399 HMVMX_REPORT_FEATURE(val, zap, "WBINVD_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_WBINVD_EXIT);
1400 HMVMX_REPORT_FEATURE(val, zap, "UNRESTRICTED_GUEST", VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST);
1401 HMVMX_REPORT_FEATURE(val, zap, "APIC_REG_VIRT", VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT);
1402 HMVMX_REPORT_FEATURE(val, zap, "VIRT_INTR_DELIVERY", VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY);
1403 HMVMX_REPORT_FEATURE(val, zap, "PAUSE_LOOP_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_PAUSE_LOOP_EXIT);
1404 HMVMX_REPORT_FEATURE(val, zap, "RDRAND_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDRAND_EXIT);
1405 HMVMX_REPORT_FEATURE(val, zap, "INVPCID", VMX_VMCS_CTRL_PROC_EXEC2_INVPCID);
1406 HMVMX_REPORT_FEATURE(val, zap, "VMFUNC", VMX_VMCS_CTRL_PROC_EXEC2_VMFUNC);
1407 HMVMX_REPORT_FEATURE(val, zap, "VMCS_SHADOWING", VMX_VMCS_CTRL_PROC_EXEC2_VMCS_SHADOWING);
1408 HMVMX_REPORT_FEATURE(val, zap, "ENCLS_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_ENCLS_EXIT);
1409 HMVMX_REPORT_FEATURE(val, zap, "RDSEED_EXIT", VMX_VMCS_CTRL_PROC_EXEC2_RDSEED_EXIT);
1410 HMVMX_REPORT_FEATURE(val, zap, "PML", VMX_VMCS_CTRL_PROC_EXEC2_PML);
1411 HMVMX_REPORT_FEATURE(val, zap, "EPT_VE", VMX_VMCS_CTRL_PROC_EXEC2_EPT_VE);
1412 HMVMX_REPORT_FEATURE(val, zap, "CONCEAL_FROM_PT", VMX_VMCS_CTRL_PROC_EXEC2_CONCEAL_FROM_PT);
1413 HMVMX_REPORT_FEATURE(val, zap, "XSAVES_XRSTORS", VMX_VMCS_CTRL_PROC_EXEC2_XSAVES_XRSTORS);
1414 HMVMX_REPORT_FEATURE(val, zap, "TSC_SCALING", VMX_VMCS_CTRL_PROC_EXEC2_TSC_SCALING);
1415 }
1416
1417 LogRel(("HM: MSR_IA32_VMX_ENTRY_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxEntry.u));
1418 val = pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1;
1419 zap = pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0;
1420 HMVMX_REPORT_FEATURE(val, zap, "LOAD_DEBUG", VMX_VMCS_CTRL_ENTRY_LOAD_DEBUG);
1421 HMVMX_REPORT_FEATURE(val, zap, "IA32E_MODE_GUEST", VMX_VMCS_CTRL_ENTRY_IA32E_MODE_GUEST);
1422 HMVMX_REPORT_FEATURE(val, zap, "ENTRY_SMM", VMX_VMCS_CTRL_ENTRY_ENTRY_SMM);
1423 HMVMX_REPORT_FEATURE(val, zap, "DEACTIVATE_DUALMON", VMX_VMCS_CTRL_ENTRY_DEACTIVATE_DUALMON);
1424 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PERF_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PERF_MSR);
1425 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_PAT_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_PAT_MSR);
1426 HMVMX_REPORT_FEATURE(val, zap, "LOAD_GUEST_EFER_MSR", VMX_VMCS_CTRL_ENTRY_LOAD_GUEST_EFER_MSR);
1427
1428 LogRel(("HM: MSR_IA32_VMX_EXIT_CTLS = %#RX64\n", pVM->hm.s.vmx.Msrs.VmxExit.u));
1429 val = pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1;
1430 zap = pVM->hm.s.vmx.Msrs.VmxExit.n.disallowed0;
1431 HMVMX_REPORT_FEATURE(val, zap, "SAVE_DEBUG", VMX_VMCS_CTRL_EXIT_SAVE_DEBUG);
1432 HMVMX_REPORT_FEATURE(val, zap, "HOST_ADDR_SPACE_SIZE", VMX_VMCS_CTRL_EXIT_HOST_ADDR_SPACE_SIZE);
1433 HMVMX_REPORT_FEATURE(val, zap, "LOAD_PERF_MSR", VMX_VMCS_CTRL_EXIT_LOAD_PERF_MSR);
1434 HMVMX_REPORT_FEATURE(val, zap, "ACK_EXT_INT", VMX_VMCS_CTRL_EXIT_ACK_EXT_INT);
1435 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_PAT_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_PAT_MSR);
1436 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_PAT_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_PAT_MSR);
1437 HMVMX_REPORT_FEATURE(val, zap, "SAVE_GUEST_EFER_MSR", VMX_VMCS_CTRL_EXIT_SAVE_GUEST_EFER_MSR);
1438 HMVMX_REPORT_FEATURE(val, zap, "LOAD_HOST_EFER_MSR", VMX_VMCS_CTRL_EXIT_LOAD_HOST_EFER_MSR);
1439 HMVMX_REPORT_FEATURE(val, zap, "SAVE_VMX_PREEMPT_TIMER", VMX_VMCS_CTRL_EXIT_SAVE_VMX_PREEMPT_TIMER);
1440
1441 if (pVM->hm.s.vmx.Msrs.u64EptVpidCaps)
1442 {
1443 val = pVM->hm.s.vmx.Msrs.u64EptVpidCaps;
1444 LogRel(("HM: MSR_IA32_VMX_EPT_VPID_CAP = %#RX64\n", val));
1445 HMVMX_REPORT_MSR_CAPABILITY(val, "RWX_X_ONLY", MSR_IA32_VMX_EPT_VPID_CAP_RWX_X_ONLY);
1446 HMVMX_REPORT_MSR_CAPABILITY(val, "PAGE_WALK_LENGTH_4", MSR_IA32_VMX_EPT_VPID_CAP_PAGE_WALK_LENGTH_4);
1447 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_UC", MSR_IA32_VMX_EPT_VPID_CAP_EMT_UC);
1448 HMVMX_REPORT_MSR_CAPABILITY(val, "EMT_WB", MSR_IA32_VMX_EPT_VPID_CAP_EMT_WB);
1449 HMVMX_REPORT_MSR_CAPABILITY(val, "PDE_2M", MSR_IA32_VMX_EPT_VPID_CAP_PDE_2M);
1450 HMVMX_REPORT_MSR_CAPABILITY(val, "PDPTE_1G", MSR_IA32_VMX_EPT_VPID_CAP_PDPTE_1G);
1451 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT);
1452 HMVMX_REPORT_MSR_CAPABILITY(val, "EPT_ACCESS_DIRTY", MSR_IA32_VMX_EPT_VPID_CAP_EPT_ACCESS_DIRTY);
1453 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_SINGLE_CONTEXT);
1454 HMVMX_REPORT_MSR_CAPABILITY(val, "INVEPT_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVEPT_ALL_CONTEXTS);
1455 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID);
1456 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_INDIV_ADDR", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_INDIV_ADDR);
1457 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT);
1458 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_ALL_CONTEXTS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_ALL_CONTEXTS);
1459 HMVMX_REPORT_MSR_CAPABILITY(val, "INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS", MSR_IA32_VMX_EPT_VPID_CAP_INVVPID_SINGLE_CONTEXT_RETAIN_GLOBALS);
1460 }
1461
1462 val = pVM->hm.s.vmx.Msrs.u64Misc;
1463 LogRel(("HM: MSR_IA32_VMX_MISC = %#RX64\n", val));
1464 if (MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val) == pVM->hm.s.vmx.cPreemptTimerShift)
1465 LogRel(("HM: PREEMPT_TSC_BIT = %#x\n", MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val)));
1466 else
1467 {
1468 LogRel(("HM: PREEMPT_TSC_BIT = %#x - erratum detected, using %#x instead\n",
1469 MSR_IA32_VMX_MISC_PREEMPT_TSC_BIT(val), pVM->hm.s.vmx.cPreemptTimerShift));
1470 }
1471
1472 LogRel(("HM: STORE_EFERLMA_VMEXIT = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_STORE_EFERLMA_VMEXIT(val))));
1473 LogRel(("HM: ACTIVITY_STATES = %#x\n", MSR_IA32_VMX_MISC_ACTIVITY_STATES(val)));
1474 LogRel(("HM: CR3_TARGET = %#x\n", MSR_IA32_VMX_MISC_CR3_TARGET(val)));
1475 LogRel(("HM: MAX_MSR = %u\n", MSR_IA32_VMX_MISC_MAX_MSR(val)));
1476 LogRel(("HM: RDMSR_SMBASE_MSR_SMM = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_RDMSR_SMBASE_MSR_SMM(val))));
1477 LogRel(("HM: SMM_MONITOR_CTL_B2 = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_SMM_MONITOR_CTL_B2(val))));
1478 LogRel(("HM: VMWRITE_VMEXIT_INFO = %RTbool\n", RT_BOOL(MSR_IA32_VMX_MISC_VMWRITE_VMEXIT_INFO(val))));
1479 LogRel(("HM: MSEG_ID = %#x\n", MSR_IA32_VMX_MISC_MSEG_ID(val)));
1480
1481 /* Paranoia */
1482 AssertRelease(MSR_IA32_VMX_MISC_MAX_MSR(pVM->hm.s.vmx.Msrs.u64Misc) >= 512);
1483
1484 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed0));
1485 LogRel(("HM: MSR_IA32_VMX_CR0_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr0Fixed1));
1486 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED0 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed0));
1487 LogRel(("HM: MSR_IA32_VMX_CR4_FIXED1 = %#RX64\n", pVM->hm.s.vmx.Msrs.u64Cr4Fixed1));
1488
1489 val = pVM->hm.s.vmx.Msrs.u64VmcsEnum;
1490 LogRel(("HM: MSR_IA32_VMX_VMCS_ENUM = %#RX64\n", val));
1491 LogRel(("HM: HIGHEST_INDEX = %#x\n", MSR_IA32_VMX_VMCS_ENUM_HIGHEST_INDEX(val)));
1492
1493 val = pVM->hm.s.vmx.Msrs.u64Vmfunc;
1494 if (val)
1495 {
1496 LogRel(("HM: MSR_IA32_VMX_VMFUNC = %#RX64\n", val));
1497 HMVMX_REPORT_ALLOWED_FEATURE(val, "EPTP_SWITCHING", VMX_VMCS_CTRL_VMFUNC_EPTP_SWITCHING);
1498 }
1499
1500 LogRel(("HM: APIC-access page physaddr = %#RHp\n", pVM->hm.s.vmx.HCPhysApicAccess));
1501
1502 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1503 {
1504 LogRel(("HM: VCPU%3d: MSR bitmap physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysMsrBitmap));
1505 LogRel(("HM: VCPU%3d: VMCS physaddr = %#RHp\n", i, pVM->aCpus[i].hm.s.vmx.HCPhysVmcs));
1506 }
1507
1508 /*
1509 * EPT and unhampered guest execution are determined in HMR3Init, verify the sanity of that.
1510 */
1511 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1512 || (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_EPT),
1513 VERR_HM_IPE_1);
1514 AssertLogRelReturn( !pVM->hm.s.vmx.fUnrestrictedGuest
1515 || ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_UNRESTRICTED_GUEST)
1516 && pVM->hm.s.fNestedPaging),
1517 VERR_HM_IPE_1);
1518
1519 /*
1520 * Enable VPID if configured and supported.
1521 */
1522 if (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VPID)
1523 pVM->hm.s.vmx.fVpid = pVM->hm.s.vmx.fAllowVpid;
1524
1525#if 0
1526 /*
1527 * Enable APIC register virtualization and virtual-interrupt delivery if supported.
1528 */
1529 if ( (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_APIC_REG_VIRT)
1530 && (pVM->hm.s.vmx.Msrs.VmxProcCtls2.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC2_VIRT_INTR_DELIVERY))
1531 pVM->hm.s.fVirtApicRegs = true;
1532
1533 /*
1534 * Enable posted-interrupt processing if supported.
1535 */
1536 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1537 * here. */
1538 if ( (pVM->hm.s.vmx.Msrs.VmxPinCtls.n.allowed1 & VMX_VMCS_CTRL_PIN_EXEC_POSTED_INTR)
1539 && (pVM->hm.s.vmx.Msrs.VmxExit.n.allowed1 & VMX_VMCS_CTRL_EXIT_ACK_EXT_INT))
1540 pVM->hm.s.fPostedIntrs = true;
1541#endif
1542
1543 /*
1544 * Disallow RDTSCP in the guest if there is no secondary process-based VM execution controls as otherwise
1545 * RDTSCP would cause a #UD. There might be no CPUs out there where this happens, as RDTSCP was introduced
1546 * in Nehalems and secondary VM exec. controls should be supported in all of them, but nonetheless it's Intel...
1547 */
1548 if ( !(pVM->hm.s.vmx.Msrs.VmxProcCtls.n.allowed1 & VMX_VMCS_CTRL_PROC_EXEC_USE_SECONDARY_EXEC_CTRL)
1549 && CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP))
1550 {
1551 CPUMR3ClearGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_RDTSCP);
1552 LogRel(("HM: Disabled RDTSCP\n"));
1553 }
1554
1555 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
1556 {
1557 /* Allocate three pages for the TSS we need for real mode emulation. (2 pages for the IO bitmap) */
1558 rc = PDMR3VmmDevHeapAlloc(pVM, HM_VTX_TOTAL_DEVHEAP_MEM, hmR3VmmDevHeapNotify, (RTR3PTR *)&pVM->hm.s.vmx.pRealModeTSS);
1559 if (RT_SUCCESS(rc))
1560 {
1561 /* The IO bitmap starts right after the virtual interrupt redirection bitmap.
1562 Refer Intel spec. 20.3.3 "Software Interrupt Handling in Virtual-8086 mode"
1563 esp. Figure 20-5.*/
1564 ASMMemZero32(pVM->hm.s.vmx.pRealModeTSS, sizeof(*pVM->hm.s.vmx.pRealModeTSS));
1565 pVM->hm.s.vmx.pRealModeTSS->offIoBitmap = sizeof(*pVM->hm.s.vmx.pRealModeTSS);
1566
1567 /* Bit set to 0 means software interrupts are redirected to the
1568 8086 program interrupt handler rather than switching to
1569 protected-mode handler. */
1570 memset(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap, 0, sizeof(pVM->hm.s.vmx.pRealModeTSS->IntRedirBitmap));
1571
1572 /* Allow all port IO, so that port IO instructions do not cause
1573 exceptions and would instead cause a VM-exit (based on VT-x's
1574 IO bitmap which we currently configure to always cause an exit). */
1575 memset(pVM->hm.s.vmx.pRealModeTSS + 1, 0, PAGE_SIZE * 2);
1576 *((unsigned char *)pVM->hm.s.vmx.pRealModeTSS + HM_VTX_TSS_SIZE - 2) = 0xff;
1577
1578 /*
1579 * Construct a 1024 element page directory with 4 MB pages for
1580 * the identity mapped page table used in real and protected mode
1581 * without paging with EPT.
1582 */
1583 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = (PX86PD)((char *)pVM->hm.s.vmx.pRealModeTSS + PAGE_SIZE * 3);
1584 for (uint32_t i = 0; i < X86_PG_ENTRIES; i++)
1585 {
1586 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u = _4M * i;
1587 pVM->hm.s.vmx.pNonPagingModeEPTPageTable->a[i].u |= X86_PDE4M_P | X86_PDE4M_RW | X86_PDE4M_US
1588 | X86_PDE4M_A | X86_PDE4M_D | X86_PDE4M_PS
1589 | X86_PDE4M_G;
1590 }
1591
1592 /* We convert it here every time as PCI regions could be reconfigured. */
1593 if (PDMVmmDevHeapIsEnabled(pVM))
1594 {
1595 RTGCPHYS GCPhys;
1596 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pRealModeTSS, &GCPhys);
1597 AssertRCReturn(rc, rc);
1598 LogRel(("HM: Real Mode TSS guest physaddr = %#RGp\n", GCPhys));
1599
1600 rc = PDMVmmDevHeapR3ToGCPhys(pVM, pVM->hm.s.vmx.pNonPagingModeEPTPageTable, &GCPhys);
1601 AssertRCReturn(rc, rc);
1602 LogRel(("HM: Non-Paging Mode EPT CR3 = %#RGp\n", GCPhys));
1603 }
1604 }
1605 else
1606 {
1607 LogRel(("HM: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)\n", rc));
1608 pVM->hm.s.vmx.pRealModeTSS = NULL;
1609 pVM->hm.s.vmx.pNonPagingModeEPTPageTable = NULL;
1610 return VMSetError(pVM, rc, RT_SRC_POS,
1611 "HM failure: No real mode VT-x support (PDMR3VMMDevHeapAlloc returned %Rrc)", rc);
1612 }
1613 }
1614
1615 LogRel((pVM->hm.s.fAllow64BitGuests
1616 ? "HM: Guest support: 32-bit and 64-bit\n"
1617 : "HM: Guest support: 32-bit only\n"));
1618
1619 /*
1620 * Call ring-0 to set up the VM.
1621 */
1622 rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /* idCpu */, VMMR0_DO_HM_SETUP_VM, 0 /* u64Arg */, NULL /* pReqHdr */);
1623 if (rc != VINF_SUCCESS)
1624 {
1625 AssertMsgFailed(("%Rrc\n", rc));
1626 LogRel(("HM: VMX setup failed with rc=%Rrc!\n", rc));
1627 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1628 {
1629 PVMCPU pVCpu = &pVM->aCpus[i];
1630 LogRel(("HM: CPU[%u] Last instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
1631 LogRel(("HM: CPU[%u] HM error %#x (%u)\n", i, pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError));
1632 }
1633 HMR3CheckError(pVM, rc);
1634 return VMSetError(pVM, rc, RT_SRC_POS, "VT-x setup failed: %Rrc", rc);
1635 }
1636
1637 LogRel(("HM: Supports VMCS EFER fields = %RTbool\n", pVM->hm.s.vmx.fSupportsVmcsEfer));
1638 LogRel(("HM: Enabled VMX\n"));
1639 pVM->hm.s.vmx.fEnabled = true;
1640
1641 hmR3DisableRawMode(pVM); /** @todo make this go away! */
1642
1643 /*
1644 * Change the CPU features.
1645 */
1646 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1647 if (pVM->hm.s.fAllow64BitGuests)
1648 {
1649 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1650 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1651 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL); /* 64 bits only on Intel CPUs */
1652 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1653 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1654 }
1655 /* Turn on NXE if PAE has been enabled *and* the host has turned on NXE
1656 (we reuse the host EFER in the switcher). */
1657 /** @todo this needs to be fixed properly!! */
1658 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1659 {
1660 if (pVM->hm.s.vmx.u64HostEfer & MSR_K6_EFER_NXE)
1661 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1662 else
1663 LogRel(("HM: NX not enabled on the host, unavailable to PAE guest\n"));
1664 }
1665
1666 /*
1667 * Log configuration details.
1668 */
1669 if (pVM->hm.s.fNestedPaging)
1670 {
1671 LogRel(("HM: Enabled nested paging\n"));
1672 if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_SINGLE_CONTEXT)
1673 LogRel(("HM: EPT flush type = VMXFLUSHEPT_SINGLE_CONTEXT\n"));
1674 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_ALL_CONTEXTS)
1675 LogRel(("HM: EPT flush type = VMXFLUSHEPT_ALL_CONTEXTS\n"));
1676 else if (pVM->hm.s.vmx.enmFlushEpt == VMXFLUSHEPT_NOT_SUPPORTED)
1677 LogRel(("HM: EPT flush type = VMXFLUSHEPT_NOT_SUPPORTED\n"));
1678 else
1679 LogRel(("HM: EPT flush type = %d\n", pVM->hm.s.vmx.enmFlushEpt));
1680
1681 if (pVM->hm.s.vmx.fUnrestrictedGuest)
1682 LogRel(("HM: Enabled unrestricted guest execution\n"));
1683
1684#if HC_ARCH_BITS == 64
1685 if (pVM->hm.s.fLargePages)
1686 {
1687 /* Use large (2 MB) pages for our EPT PDEs where possible. */
1688 PGMSetLargePageUsage(pVM, true);
1689 LogRel(("HM: Enabled large page support\n"));
1690 }
1691#endif
1692 }
1693 else
1694 Assert(!pVM->hm.s.vmx.fUnrestrictedGuest);
1695
1696 if (pVM->hm.s.fVirtApicRegs)
1697 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1698
1699 if (pVM->hm.s.fPostedIntrs)
1700 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1701
1702 if (pVM->hm.s.vmx.fVpid)
1703 {
1704 LogRel(("HM: Enabled VPID\n"));
1705 if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_INDIV_ADDR)
1706 LogRel(("HM: VPID flush type = VMXFLUSHVPID_INDIV_ADDR\n"));
1707 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT)
1708 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT\n"));
1709 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_ALL_CONTEXTS)
1710 LogRel(("HM: VPID flush type = VMXFLUSHVPID_ALL_CONTEXTS\n"));
1711 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS)
1712 LogRel(("HM: VPID flush type = VMXFLUSHVPID_SINGLE_CONTEXT_RETAIN_GLOBALS\n"));
1713 else
1714 LogRel(("HM: VPID flush type = %d\n", pVM->hm.s.vmx.enmFlushVpid));
1715 }
1716 else if (pVM->hm.s.vmx.enmFlushVpid == VMXFLUSHVPID_NOT_SUPPORTED)
1717 LogRel(("HM: Ignoring VPID capabilities of CPU\n"));
1718
1719 if (pVM->hm.s.vmx.fUsePreemptTimer)
1720 LogRel(("HM: Enabled VMX-preemption timer (cPreemptTimerShift=%u)\n", pVM->hm.s.vmx.cPreemptTimerShift));
1721 else
1722 LogRel(("HM: Disabled VMX-preemption timer\n"));
1723
1724 return VINF_SUCCESS;
1725}
1726
1727
1728/**
1729 * Finish AMD-V initialization (after ring-0 init).
1730 *
1731 * @returns VBox status code.
1732 * @param pVM The cross context VM structure.
1733 */
1734static int hmR3InitFinalizeR0Amd(PVM pVM)
1735{
1736 Log(("pVM->hm.s.svm.fSupported = %d\n", pVM->hm.s.svm.fSupported));
1737
1738 LogRel(("HM: Using AMD-V implementation 2.0\n"));
1739
1740 uint32_t u32Family;
1741 uint32_t u32Model;
1742 uint32_t u32Stepping;
1743 if (HMAmdIsSubjectToErratum170(&u32Family, &u32Model, &u32Stepping))
1744 LogRel(("HM: AMD Cpu with erratum 170 family %#x model %#x stepping %#x\n", u32Family, u32Model, u32Stepping));
1745 LogRel(("HM: Max resume loops = %u\n", pVM->hm.s.cMaxResumeLoops));
1746 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureECX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureECX));
1747 LogRel(("HM: CPUID 0x80000001.u32AMDFeatureEDX = %#RX32\n", pVM->hm.s.cpuid.u32AMDFeatureEDX));
1748 LogRel(("HM: AMD HWCR MSR = %#RX64\n", pVM->hm.s.svm.u64MsrHwcr));
1749 LogRel(("HM: AMD-V revision = %#x\n", pVM->hm.s.svm.u32Rev));
1750 LogRel(("HM: AMD-V max ASID = %RU32\n", pVM->hm.s.uMaxAsid));
1751 LogRel(("HM: AMD-V features = %#x\n", pVM->hm.s.svm.u32Features));
1752
1753 /*
1754 * Enumerate AMD-V features.
1755 */
1756 static const struct { uint32_t fFlag; const char *pszName; } s_aSvmFeatures[] =
1757 {
1758#define HMSVM_REPORT_FEATURE(a_StrDesc, a_Define) { a_Define, a_StrDesc }
1759 HMSVM_REPORT_FEATURE("NESTED_PAGING", X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1760 HMSVM_REPORT_FEATURE("LBR_VIRT", X86_CPUID_SVM_FEATURE_EDX_LBR_VIRT),
1761 HMSVM_REPORT_FEATURE("SVM_LOCK", X86_CPUID_SVM_FEATURE_EDX_SVM_LOCK),
1762 HMSVM_REPORT_FEATURE("NRIP_SAVE", X86_CPUID_SVM_FEATURE_EDX_NRIP_SAVE),
1763 HMSVM_REPORT_FEATURE("TSC_RATE_MSR", X86_CPUID_SVM_FEATURE_EDX_TSC_RATE_MSR),
1764 HMSVM_REPORT_FEATURE("VMCB_CLEAN", X86_CPUID_SVM_FEATURE_EDX_VMCB_CLEAN),
1765 HMSVM_REPORT_FEATURE("FLUSH_BY_ASID", X86_CPUID_SVM_FEATURE_EDX_FLUSH_BY_ASID),
1766 HMSVM_REPORT_FEATURE("DECODE_ASSISTS", X86_CPUID_SVM_FEATURE_EDX_DECODE_ASSISTS),
1767 HMSVM_REPORT_FEATURE("PAUSE_FILTER", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER),
1768 HMSVM_REPORT_FEATURE("PAUSE_FILTER_THRESHOLD", X86_CPUID_SVM_FEATURE_EDX_PAUSE_FILTER_THRESHOLD),
1769 HMSVM_REPORT_FEATURE("AVIC", X86_CPUID_SVM_FEATURE_EDX_AVIC),
1770 HMSVM_REPORT_FEATURE("VIRT_VMSAVE_VMLOAD", X86_CPUID_SVM_FEATURE_EDX_VIRT_VMSAVE_VMLOAD),
1771 HMSVM_REPORT_FEATURE("VGIF", X86_CPUID_SVM_FEATURE_EDX_VGIF),
1772#undef HMSVM_REPORT_FEATURE
1773 };
1774
1775 uint32_t fSvmFeatures = pVM->hm.s.svm.u32Features;
1776 for (unsigned i = 0; i < RT_ELEMENTS(s_aSvmFeatures); i++)
1777 if (fSvmFeatures & s_aSvmFeatures[i].fFlag)
1778 {
1779 LogRel(("HM: %s\n", s_aSvmFeatures[i].pszName));
1780 fSvmFeatures &= ~s_aSvmFeatures[i].fFlag;
1781 }
1782 if (fSvmFeatures)
1783 for (unsigned iBit = 0; iBit < 32; iBit++)
1784 if (RT_BIT_32(iBit) & fSvmFeatures)
1785 LogRel(("HM: Reserved bit %u\n", iBit));
1786
1787 /*
1788 * Nested paging is determined in HMR3Init, verify the sanity of that.
1789 */
1790 AssertLogRelReturn( !pVM->hm.s.fNestedPaging
1791 || (pVM->hm.s.svm.u32Features & X86_CPUID_SVM_FEATURE_EDX_NESTED_PAGING),
1792 VERR_HM_IPE_1);
1793
1794#if 0
1795 /** @todo Add and query IPRT API for host OS support for posted-interrupt IPI
1796 * here. */
1797 if (RTR0IsPostIpiSupport())
1798 pVM->hm.s.fPostedIntrs = true;
1799#endif
1800
1801 /*
1802 * Call ring-0 to set up the VM.
1803 */
1804 int rc = SUPR3CallVMMR0Ex(pVM->pVMR0, 0 /*idCpu*/, VMMR0_DO_HM_SETUP_VM, 0, NULL);
1805 if (rc != VINF_SUCCESS)
1806 {
1807 AssertMsgFailed(("%Rrc\n", rc));
1808 LogRel(("HM: AMD-V setup failed with rc=%Rrc!\n", rc));
1809 return VMSetError(pVM, rc, RT_SRC_POS, "AMD-V setup failed: %Rrc", rc);
1810 }
1811
1812 LogRel(("HM: Enabled SVM\n"));
1813 pVM->hm.s.svm.fEnabled = true;
1814
1815 if (pVM->hm.s.fNestedPaging)
1816 {
1817 LogRel(("HM: Enabled nested paging\n"));
1818
1819 /*
1820 * Enable large pages (2 MB) if applicable.
1821 */
1822#if HC_ARCH_BITS == 64
1823 if (pVM->hm.s.fLargePages)
1824 {
1825 PGMSetLargePageUsage(pVM, true);
1826 LogRel(("HM: Enabled large page support\n"));
1827 }
1828#endif
1829 }
1830
1831 if (pVM->hm.s.fVirtApicRegs)
1832 LogRel(("HM: Enabled APIC-register virtualization support\n"));
1833
1834 if (pVM->hm.s.fPostedIntrs)
1835 LogRel(("HM: Enabled posted-interrupt processing support\n"));
1836
1837 hmR3DisableRawMode(pVM);
1838
1839 /*
1840 * Change the CPU features.
1841 */
1842 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SEP);
1843 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_SYSCALL);
1844 if (pVM->hm.s.fAllow64BitGuests)
1845 {
1846 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE);
1847 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LONG_MODE);
1848 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1849 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_LAHF);
1850 }
1851 /* Turn on NXE if PAE has been enabled. */
1852 else if (CPUMR3GetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_PAE))
1853 CPUMR3SetGuestCpuIdFeature(pVM, CPUMCPUIDFEATURE_NX);
1854
1855 LogRel(("HM: %s TPR patching\n", (pVM->hm.s.fTprPatchingAllowed) ? "Enabled" : "Disabled"));
1856
1857 LogRel((pVM->hm.s.fAllow64BitGuests
1858 ? "HM: Guest support: 32-bit and 64-bit\n"
1859 : "HM: Guest support: 32-bit only\n"));
1860
1861 return VINF_SUCCESS;
1862}
1863
1864
1865/**
1866 * Applies relocations to data and code managed by this
1867 * component. This function will be called at init and
1868 * whenever the VMM need to relocate it self inside the GC.
1869 *
1870 * @param pVM The cross context VM structure.
1871 */
1872VMMR3_INT_DECL(void) HMR3Relocate(PVM pVM)
1873{
1874 Log(("HMR3Relocate to %RGv\n", MMHyperGetArea(pVM, 0)));
1875
1876 /* Fetch the current paging mode during the relocate callback during state loading. */
1877 if (VMR3GetState(pVM) == VMSTATE_LOADING)
1878 {
1879 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1880 {
1881 PVMCPU pVCpu = &pVM->aCpus[i];
1882 pVCpu->hm.s.enmShadowMode = PGMGetShadowMode(pVCpu);
1883 }
1884 }
1885#if HC_ARCH_BITS == 32 && defined(VBOX_ENABLE_64_BITS_GUESTS)
1886 if (HMIsEnabled(pVM))
1887 {
1888 switch (PGMGetHostMode(pVM))
1889 {
1890 case PGMMODE_32_BIT:
1891 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_32_TO_AMD64);
1892 break;
1893
1894 case PGMMODE_PAE:
1895 case PGMMODE_PAE_NX:
1896 pVM->hm.s.pfnHost32ToGuest64R0 = VMMR3GetHostToGuestSwitcher(pVM, VMMSWITCHER_PAE_TO_AMD64);
1897 break;
1898
1899 default:
1900 AssertFailed();
1901 break;
1902 }
1903 }
1904#endif
1905 return;
1906}
1907
1908
1909/**
1910 * Notification callback which is called whenever there is a chance that a CR3
1911 * value might have changed.
1912 *
1913 * This is called by PGM.
1914 *
1915 * @param pVM The cross context VM structure.
1916 * @param pVCpu The cross context virtual CPU structure.
1917 * @param enmShadowMode New shadow paging mode.
1918 * @param enmGuestMode New guest paging mode.
1919 */
1920VMMR3_INT_DECL(void) HMR3PagingModeChanged(PVM pVM, PVMCPU pVCpu, PGMMODE enmShadowMode, PGMMODE enmGuestMode)
1921{
1922 RT_NOREF_PV(pVM);
1923
1924 /* Ignore page mode changes during state loading. */
1925 if (VMR3GetState(pVCpu->pVMR3) == VMSTATE_LOADING)
1926 return;
1927
1928 pVCpu->hm.s.enmShadowMode = enmShadowMode;
1929
1930 /*
1931 * If the guest left protected mode VMX execution, we'll have to be
1932 * extra careful if/when the guest switches back to protected mode.
1933 */
1934 if (enmGuestMode == PGMMODE_REAL)
1935 pVCpu->hm.s.vmx.fWasInRealMode = true;
1936
1937 Log4(("HMR3PagingModeChanged: Guest paging mode '%s', shadow paging mode '%s'\n", PGMGetModeName(enmGuestMode),
1938 PGMGetModeName(enmShadowMode)));
1939}
1940
1941
1942/**
1943 * Terminates the HM.
1944 *
1945 * Termination means cleaning up and freeing all resources,
1946 * the VM itself is, at this point, powered off or suspended.
1947 *
1948 * @returns VBox status code.
1949 * @param pVM The cross context VM structure.
1950 */
1951VMMR3_INT_DECL(int) HMR3Term(PVM pVM)
1952{
1953 if (pVM->hm.s.vmx.pRealModeTSS)
1954 {
1955 PDMR3VmmDevHeapFree(pVM, pVM->hm.s.vmx.pRealModeTSS);
1956 pVM->hm.s.vmx.pRealModeTSS = 0;
1957 }
1958 hmR3TermCPU(pVM);
1959 return 0;
1960}
1961
1962
1963/**
1964 * Terminates the per-VCPU HM.
1965 *
1966 * @returns VBox status code.
1967 * @param pVM The cross context VM structure.
1968 */
1969static int hmR3TermCPU(PVM pVM)
1970{
1971 for (VMCPUID i = 0; i < pVM->cCpus; i++)
1972 {
1973 PVMCPU pVCpu = &pVM->aCpus[i]; NOREF(pVCpu);
1974
1975#ifdef VBOX_WITH_STATISTICS
1976 if (pVCpu->hm.s.paStatExitReason)
1977 {
1978 MMHyperFree(pVM, pVCpu->hm.s.paStatExitReason);
1979 pVCpu->hm.s.paStatExitReason = NULL;
1980 pVCpu->hm.s.paStatExitReasonR0 = NIL_RTR0PTR;
1981 }
1982 if (pVCpu->hm.s.paStatInjectedIrqs)
1983 {
1984 MMHyperFree(pVM, pVCpu->hm.s.paStatInjectedIrqs);
1985 pVCpu->hm.s.paStatInjectedIrqs = NULL;
1986 pVCpu->hm.s.paStatInjectedIrqsR0 = NIL_RTR0PTR;
1987 }
1988#endif
1989
1990#ifdef VBOX_WITH_CRASHDUMP_MAGIC
1991 memset(pVCpu->hm.s.vmx.VMCSCache.aMagic, 0, sizeof(pVCpu->hm.s.vmx.VMCSCache.aMagic));
1992 pVCpu->hm.s.vmx.VMCSCache.uMagic = 0;
1993 pVCpu->hm.s.vmx.VMCSCache.uPos = 0xffffffff;
1994#endif
1995 }
1996 return 0;
1997}
1998
1999
2000/**
2001 * Resets a virtual CPU.
2002 *
2003 * Used by HMR3Reset and CPU hot plugging.
2004 *
2005 * @param pVCpu The cross context virtual CPU structure to reset.
2006 */
2007VMMR3_INT_DECL(void) HMR3ResetCpu(PVMCPU pVCpu)
2008{
2009 /* Sync. entire state on VM reset R0-reentry. It's safe to reset
2010 the HM flags here, all other EMTs are in ring-3. See VMR3Reset(). */
2011 HMCPU_CF_RESET_TO(pVCpu, HM_CHANGED_HOST_CONTEXT | HM_CHANGED_ALL_GUEST);
2012
2013 pVCpu->hm.s.vmx.u32CR0Mask = 0;
2014 pVCpu->hm.s.vmx.u32CR4Mask = 0;
2015 pVCpu->hm.s.fActive = false;
2016 pVCpu->hm.s.Event.fPending = false;
2017 pVCpu->hm.s.vmx.fWasInRealMode = true;
2018 pVCpu->hm.s.vmx.u64MsrApicBase = 0;
2019 pVCpu->hm.s.vmx.fSwitchedTo64on32 = false;
2020
2021 /* Reset the contents of the read cache. */
2022 PVMCSCACHE pCache = &pVCpu->hm.s.vmx.VMCSCache;
2023 for (unsigned j = 0; j < pCache->Read.cValidEntries; j++)
2024 pCache->Read.aFieldVal[j] = 0;
2025
2026#ifdef VBOX_WITH_CRASHDUMP_MAGIC
2027 /* Magic marker for searching in crash dumps. */
2028 strcpy((char *)pCache->aMagic, "VMCSCACHE Magic");
2029 pCache->uMagic = UINT64_C(0xDEADBEEFDEADBEEF);
2030#endif
2031}
2032
2033
2034/**
2035 * The VM is being reset.
2036 *
2037 * For the HM component this means that any GDT/LDT/TSS monitors
2038 * needs to be removed.
2039 *
2040 * @param pVM The cross context VM structure.
2041 */
2042VMMR3_INT_DECL(void) HMR3Reset(PVM pVM)
2043{
2044 LogFlow(("HMR3Reset:\n"));
2045
2046 if (HMIsEnabled(pVM))
2047 hmR3DisableRawMode(pVM);
2048
2049 for (VMCPUID i = 0; i < pVM->cCpus; i++)
2050 {
2051 PVMCPU pVCpu = &pVM->aCpus[i];
2052
2053 HMR3ResetCpu(pVCpu);
2054 }
2055
2056 /* Clear all patch information. */
2057 pVM->hm.s.pGuestPatchMem = 0;
2058 pVM->hm.s.pFreeGuestPatchMem = 0;
2059 pVM->hm.s.cbGuestPatchMem = 0;
2060 pVM->hm.s.cPatches = 0;
2061 pVM->hm.s.PatchTree = 0;
2062 pVM->hm.s.fTPRPatchingActive = false;
2063 ASMMemZero32(pVM->hm.s.aPatches, sizeof(pVM->hm.s.aPatches));
2064}
2065
2066
2067/**
2068 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2069 *
2070 * @returns VBox strict status code.
2071 * @param pVM The cross context VM structure.
2072 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2073 * @param pvUser Unused.
2074 */
2075static DECLCALLBACK(VBOXSTRICTRC) hmR3RemovePatches(PVM pVM, PVMCPU pVCpu, void *pvUser)
2076{
2077 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2078
2079 /* Only execute the handler on the VCPU the original patch request was issued. */
2080 if (pVCpu->idCpu != idCpu)
2081 return VINF_SUCCESS;
2082
2083 Log(("hmR3RemovePatches\n"));
2084 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
2085 {
2086 uint8_t abInstr[15];
2087 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
2088 RTGCPTR pInstrGC = (RTGCPTR)pPatch->Core.Key;
2089 int rc;
2090
2091#ifdef LOG_ENABLED
2092 char szOutput[256];
2093
2094 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2095 szOutput, sizeof(szOutput), NULL);
2096 if (RT_SUCCESS(rc))
2097 Log(("Patched instr: %s\n", szOutput));
2098#endif
2099
2100 /* Check if the instruction is still the same. */
2101 rc = PGMPhysSimpleReadGCPtr(pVCpu, abInstr, pInstrGC, pPatch->cbNewOp);
2102 if (rc != VINF_SUCCESS)
2103 {
2104 Log(("Patched code removed? (rc=%Rrc0\n", rc));
2105 continue; /* swapped out or otherwise removed; skip it. */
2106 }
2107
2108 if (memcmp(abInstr, pPatch->aNewOpcode, pPatch->cbNewOp))
2109 {
2110 Log(("Patched instruction was changed! (rc=%Rrc0\n", rc));
2111 continue; /* skip it. */
2112 }
2113
2114 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pInstrGC, pPatch->aOpcode, pPatch->cbOp);
2115 AssertRC(rc);
2116
2117#ifdef LOG_ENABLED
2118 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, CPUMGetGuestCS(pVCpu), pInstrGC, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2119 szOutput, sizeof(szOutput), NULL);
2120 if (RT_SUCCESS(rc))
2121 Log(("Original instr: %s\n", szOutput));
2122#endif
2123 }
2124 pVM->hm.s.cPatches = 0;
2125 pVM->hm.s.PatchTree = 0;
2126 pVM->hm.s.pFreeGuestPatchMem = pVM->hm.s.pGuestPatchMem;
2127 pVM->hm.s.fTPRPatchingActive = false;
2128 return VINF_SUCCESS;
2129}
2130
2131
2132/**
2133 * Worker for enabling patching in a VT-x/AMD-V guest.
2134 *
2135 * @returns VBox status code.
2136 * @param pVM The cross context VM structure.
2137 * @param idCpu VCPU to execute hmR3RemovePatches on.
2138 * @param pPatchMem Patch memory range.
2139 * @param cbPatchMem Size of the memory range.
2140 */
2141static int hmR3EnablePatching(PVM pVM, VMCPUID idCpu, RTRCPTR pPatchMem, unsigned cbPatchMem)
2142{
2143 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches, (void *)(uintptr_t)idCpu);
2144 AssertRC(rc);
2145
2146 pVM->hm.s.pGuestPatchMem = pPatchMem;
2147 pVM->hm.s.pFreeGuestPatchMem = pPatchMem;
2148 pVM->hm.s.cbGuestPatchMem = cbPatchMem;
2149 return VINF_SUCCESS;
2150}
2151
2152
2153/**
2154 * Enable patching in a VT-x/AMD-V guest
2155 *
2156 * @returns VBox status code.
2157 * @param pVM The cross context VM structure.
2158 * @param pPatchMem Patch memory range.
2159 * @param cbPatchMem Size of the memory range.
2160 */
2161VMMR3_INT_DECL(int) HMR3EnablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2162{
2163 VM_ASSERT_EMT(pVM);
2164 Log(("HMR3EnablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2165 if (pVM->cCpus > 1)
2166 {
2167 /* We own the IOM lock here and could cause a deadlock by waiting for a VCPU that is blocking on the IOM lock. */
2168 int rc = VMR3ReqCallNoWait(pVM, VMCPUID_ANY_QUEUE,
2169 (PFNRT)hmR3EnablePatching, 4, pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2170 AssertRC(rc);
2171 return rc;
2172 }
2173 return hmR3EnablePatching(pVM, VMMGetCpuId(pVM), (RTRCPTR)pPatchMem, cbPatchMem);
2174}
2175
2176
2177/**
2178 * Disable patching in a VT-x/AMD-V guest.
2179 *
2180 * @returns VBox status code.
2181 * @param pVM The cross context VM structure.
2182 * @param pPatchMem Patch memory range.
2183 * @param cbPatchMem Size of the memory range.
2184 */
2185VMMR3_INT_DECL(int) HMR3DisablePatching(PVM pVM, RTGCPTR pPatchMem, unsigned cbPatchMem)
2186{
2187 Log(("HMR3DisablePatching %RGv size %x\n", pPatchMem, cbPatchMem));
2188 RT_NOREF2(pPatchMem, cbPatchMem);
2189
2190 Assert(pVM->hm.s.pGuestPatchMem == pPatchMem);
2191 Assert(pVM->hm.s.cbGuestPatchMem == cbPatchMem);
2192
2193 /** @todo Potential deadlock when other VCPUs are waiting on the IOM lock (we own it)!! */
2194 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE, hmR3RemovePatches,
2195 (void *)(uintptr_t)VMMGetCpuId(pVM));
2196 AssertRC(rc);
2197
2198 pVM->hm.s.pGuestPatchMem = 0;
2199 pVM->hm.s.pFreeGuestPatchMem = 0;
2200 pVM->hm.s.cbGuestPatchMem = 0;
2201 pVM->hm.s.fTPRPatchingActive = false;
2202 return VINF_SUCCESS;
2203}
2204
2205
2206/**
2207 * Callback to patch a TPR instruction (vmmcall or mov cr8).
2208 *
2209 * @returns VBox strict status code.
2210 * @param pVM The cross context VM structure.
2211 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2212 * @param pvUser User specified CPU context.
2213 *
2214 */
2215static DECLCALLBACK(VBOXSTRICTRC) hmR3ReplaceTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2216{
2217 /*
2218 * Only execute the handler on the VCPU the original patch request was
2219 * issued. (The other CPU(s) might not yet have switched to protected
2220 * mode, nor have the correct memory context.)
2221 */
2222 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2223 if (pVCpu->idCpu != idCpu)
2224 return VINF_SUCCESS;
2225
2226 /*
2227 * We're racing other VCPUs here, so don't try patch the instruction twice
2228 * and make sure there is still room for our patch record.
2229 */
2230 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2231 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2232 if (pPatch)
2233 {
2234 Log(("hmR3ReplaceTprInstr: already patched %RGv\n", pCtx->rip));
2235 return VINF_SUCCESS;
2236 }
2237 uint32_t const idx = pVM->hm.s.cPatches;
2238 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2239 {
2240 Log(("hmR3ReplaceTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2241 return VINF_SUCCESS;
2242 }
2243 pPatch = &pVM->hm.s.aPatches[idx];
2244
2245 Log(("hmR3ReplaceTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2246
2247 /*
2248 * Disassembler the instruction and get cracking.
2249 */
2250 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3ReplaceTprInstr");
2251 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2252 uint32_t cbOp;
2253 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2254 AssertRC(rc);
2255 if ( rc == VINF_SUCCESS
2256 && pDis->pCurInstr->uOpcode == OP_MOV
2257 && cbOp >= 3)
2258 {
2259 static uint8_t const s_abVMMCall[3] = { 0x0f, 0x01, 0xd9 };
2260
2261 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2262 AssertRC(rc);
2263
2264 pPatch->cbOp = cbOp;
2265
2266 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2267 {
2268 /* write. */
2269 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2270 {
2271 pPatch->enmType = HMTPRINSTR_WRITE_REG;
2272 pPatch->uSrcOperand = pDis->Param2.Base.idxGenReg;
2273 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_REG %u\n", pDis->Param2.Base.idxGenReg));
2274 }
2275 else
2276 {
2277 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2278 pPatch->enmType = HMTPRINSTR_WRITE_IMM;
2279 pPatch->uSrcOperand = pDis->Param2.uValue;
2280 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_WRITE_IMM %#llx\n", pDis->Param2.uValue));
2281 }
2282 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2283 AssertRC(rc);
2284
2285 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2286 pPatch->cbNewOp = sizeof(s_abVMMCall);
2287 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2288 }
2289 else
2290 {
2291 /*
2292 * TPR Read.
2293 *
2294 * Found:
2295 * mov eax, dword [fffe0080] (5 bytes)
2296 * Check if next instruction is:
2297 * shr eax, 4
2298 */
2299 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2300
2301 uint8_t const idxMmioReg = pDis->Param1.Base.idxGenReg;
2302 uint8_t const cbOpMmio = cbOp;
2303 uint64_t const uSavedRip = pCtx->rip;
2304
2305 pCtx->rip += cbOp;
2306 rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2307 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Following read");
2308 pCtx->rip = uSavedRip;
2309
2310 if ( rc == VINF_SUCCESS
2311 && pDis->pCurInstr->uOpcode == OP_SHR
2312 && pDis->Param1.fUse == DISUSE_REG_GEN32
2313 && pDis->Param1.Base.idxGenReg == idxMmioReg
2314 && pDis->Param2.fUse == DISUSE_IMMEDIATE8
2315 && pDis->Param2.uValue == 4
2316 && cbOpMmio + cbOp < sizeof(pVM->hm.s.aPatches[idx].aOpcode))
2317 {
2318 uint8_t abInstr[15];
2319
2320 /* Replacing the two instructions above with an AMD-V specific lock-prefixed 32-bit MOV CR8 instruction so as to
2321 access CR8 in 32-bit mode and not cause a #VMEXIT. */
2322 rc = PGMPhysSimpleReadGCPtr(pVCpu, &pPatch->aOpcode, pCtx->rip, cbOpMmio + cbOp);
2323 AssertRC(rc);
2324
2325 pPatch->cbOp = cbOpMmio + cbOp;
2326
2327 /* 0xF0, 0x0F, 0x20, 0xC0 = mov eax, cr8 */
2328 abInstr[0] = 0xF0;
2329 abInstr[1] = 0x0F;
2330 abInstr[2] = 0x20;
2331 abInstr[3] = 0xC0 | pDis->Param1.Base.idxGenReg;
2332 for (unsigned i = 4; i < pPatch->cbOp; i++)
2333 abInstr[i] = 0x90; /* nop */
2334
2335 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, abInstr, pPatch->cbOp);
2336 AssertRC(rc);
2337
2338 memcpy(pPatch->aNewOpcode, abInstr, pPatch->cbOp);
2339 pPatch->cbNewOp = pPatch->cbOp;
2340 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessCr8);
2341
2342 Log(("Acceptable read/shr candidate!\n"));
2343 pPatch->enmType = HMTPRINSTR_READ_SHR4;
2344 }
2345 else
2346 {
2347 pPatch->enmType = HMTPRINSTR_READ;
2348 pPatch->uDstOperand = idxMmioReg;
2349
2350 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->rip, s_abVMMCall, sizeof(s_abVMMCall));
2351 AssertRC(rc);
2352
2353 memcpy(pPatch->aNewOpcode, s_abVMMCall, sizeof(s_abVMMCall));
2354 pPatch->cbNewOp = sizeof(s_abVMMCall);
2355 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceSuccessVmc);
2356 Log(("hmR3ReplaceTprInstr: HMTPRINSTR_READ %u\n", pPatch->uDstOperand));
2357 }
2358 }
2359
2360 pPatch->Core.Key = pCtx->eip;
2361 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2362 AssertRC(rc);
2363
2364 pVM->hm.s.cPatches++;
2365 return VINF_SUCCESS;
2366 }
2367
2368 /*
2369 * Save invalid patch, so we will not try again.
2370 */
2371 Log(("hmR3ReplaceTprInstr: Failed to patch instr!\n"));
2372 pPatch->Core.Key = pCtx->eip;
2373 pPatch->enmType = HMTPRINSTR_INVALID;
2374 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2375 AssertRC(rc);
2376 pVM->hm.s.cPatches++;
2377 STAM_COUNTER_INC(&pVM->hm.s.StatTprReplaceFailure);
2378 return VINF_SUCCESS;
2379}
2380
2381
2382/**
2383 * Callback to patch a TPR instruction (jump to generated code).
2384 *
2385 * @returns VBox strict status code.
2386 * @param pVM The cross context VM structure.
2387 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
2388 * @param pvUser User specified CPU context.
2389 *
2390 */
2391static DECLCALLBACK(VBOXSTRICTRC) hmR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, void *pvUser)
2392{
2393 /*
2394 * Only execute the handler on the VCPU the original patch request was
2395 * issued. (The other CPU(s) might not yet have switched to protected
2396 * mode, nor have the correct memory context.)
2397 */
2398 VMCPUID idCpu = (VMCPUID)(uintptr_t)pvUser;
2399 if (pVCpu->idCpu != idCpu)
2400 return VINF_SUCCESS;
2401
2402 /*
2403 * We're racing other VCPUs here, so don't try patch the instruction twice
2404 * and make sure there is still room for our patch record.
2405 */
2406 PCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
2407 PHMTPRPATCH pPatch = (PHMTPRPATCH)RTAvloU32Get(&pVM->hm.s.PatchTree, (AVLOU32KEY)pCtx->eip);
2408 if (pPatch)
2409 {
2410 Log(("hmR3PatchTprInstr: already patched %RGv\n", pCtx->rip));
2411 return VINF_SUCCESS;
2412 }
2413 uint32_t const idx = pVM->hm.s.cPatches;
2414 if (idx >= RT_ELEMENTS(pVM->hm.s.aPatches))
2415 {
2416 Log(("hmR3PatchTprInstr: no available patch slots (%RGv)\n", pCtx->rip));
2417 return VINF_SUCCESS;
2418 }
2419 pPatch = &pVM->hm.s.aPatches[idx];
2420
2421 Log(("hmR3PatchTprInstr: rip=%RGv idxPatch=%u\n", pCtx->rip, idx));
2422 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "hmR3PatchTprInstr");
2423
2424 /*
2425 * Disassemble the instruction and get cracking.
2426 */
2427 PDISCPUSTATE pDis = &pVCpu->hm.s.DisState;
2428 uint32_t cbOp;
2429 int rc = EMInterpretDisasCurrent(pVM, pVCpu, pDis, &cbOp);
2430 AssertRC(rc);
2431 if ( rc == VINF_SUCCESS
2432 && pDis->pCurInstr->uOpcode == OP_MOV
2433 && cbOp >= 5)
2434 {
2435 uint8_t aPatch[64];
2436 uint32_t off = 0;
2437
2438 rc = PGMPhysSimpleReadGCPtr(pVCpu, pPatch->aOpcode, pCtx->rip, cbOp);
2439 AssertRC(rc);
2440
2441 pPatch->cbOp = cbOp;
2442 pPatch->enmType = HMTPRINSTR_JUMP_REPLACEMENT;
2443
2444 if (pDis->Param1.fUse == DISUSE_DISPLACEMENT32)
2445 {
2446 /*
2447 * TPR write:
2448 *
2449 * push ECX [51]
2450 * push EDX [52]
2451 * push EAX [50]
2452 * xor EDX,EDX [31 D2]
2453 * mov EAX,EAX [89 C0]
2454 * or
2455 * mov EAX,0000000CCh [B8 CC 00 00 00]
2456 * mov ECX,0C0000082h [B9 82 00 00 C0]
2457 * wrmsr [0F 30]
2458 * pop EAX [58]
2459 * pop EDX [5A]
2460 * pop ECX [59]
2461 * jmp return_address [E9 return_address]
2462 *
2463 */
2464 bool fUsesEax = (pDis->Param2.fUse == DISUSE_REG_GEN32 && pDis->Param2.Base.idxGenReg == DISGREG_EAX);
2465
2466 aPatch[off++] = 0x51; /* push ecx */
2467 aPatch[off++] = 0x52; /* push edx */
2468 if (!fUsesEax)
2469 aPatch[off++] = 0x50; /* push eax */
2470 aPatch[off++] = 0x31; /* xor edx, edx */
2471 aPatch[off++] = 0xD2;
2472 if (pDis->Param2.fUse == DISUSE_REG_GEN32)
2473 {
2474 if (!fUsesEax)
2475 {
2476 aPatch[off++] = 0x89; /* mov eax, src_reg */
2477 aPatch[off++] = MAKE_MODRM(3, pDis->Param2.Base.idxGenReg, DISGREG_EAX);
2478 }
2479 }
2480 else
2481 {
2482 Assert(pDis->Param2.fUse == DISUSE_IMMEDIATE32);
2483 aPatch[off++] = 0xB8; /* mov eax, immediate */
2484 *(uint32_t *)&aPatch[off] = pDis->Param2.uValue;
2485 off += sizeof(uint32_t);
2486 }
2487 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2488 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2489 off += sizeof(uint32_t);
2490
2491 aPatch[off++] = 0x0F; /* wrmsr */
2492 aPatch[off++] = 0x30;
2493 if (!fUsesEax)
2494 aPatch[off++] = 0x58; /* pop eax */
2495 aPatch[off++] = 0x5A; /* pop edx */
2496 aPatch[off++] = 0x59; /* pop ecx */
2497 }
2498 else
2499 {
2500 /*
2501 * TPR read:
2502 *
2503 * push ECX [51]
2504 * push EDX [52]
2505 * push EAX [50]
2506 * mov ECX,0C0000082h [B9 82 00 00 C0]
2507 * rdmsr [0F 32]
2508 * mov EAX,EAX [89 C0]
2509 * pop EAX [58]
2510 * pop EDX [5A]
2511 * pop ECX [59]
2512 * jmp return_address [E9 return_address]
2513 *
2514 */
2515 Assert(pDis->Param1.fUse == DISUSE_REG_GEN32);
2516
2517 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2518 aPatch[off++] = 0x51; /* push ecx */
2519 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2520 aPatch[off++] = 0x52; /* push edx */
2521 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2522 aPatch[off++] = 0x50; /* push eax */
2523
2524 aPatch[off++] = 0x31; /* xor edx, edx */
2525 aPatch[off++] = 0xD2;
2526
2527 aPatch[off++] = 0xB9; /* mov ecx, 0xc0000082 */
2528 *(uint32_t *)&aPatch[off] = MSR_K8_LSTAR;
2529 off += sizeof(uint32_t);
2530
2531 aPatch[off++] = 0x0F; /* rdmsr */
2532 aPatch[off++] = 0x32;
2533
2534 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2535 {
2536 aPatch[off++] = 0x89; /* mov dst_reg, eax */
2537 aPatch[off++] = MAKE_MODRM(3, DISGREG_EAX, pDis->Param1.Base.idxGenReg);
2538 }
2539
2540 if (pDis->Param1.Base.idxGenReg != DISGREG_EAX)
2541 aPatch[off++] = 0x58; /* pop eax */
2542 if (pDis->Param1.Base.idxGenReg != DISGREG_EDX )
2543 aPatch[off++] = 0x5A; /* pop edx */
2544 if (pDis->Param1.Base.idxGenReg != DISGREG_ECX)
2545 aPatch[off++] = 0x59; /* pop ecx */
2546 }
2547 aPatch[off++] = 0xE9; /* jmp return_address */
2548 *(RTRCUINTPTR *)&aPatch[off] = ((RTRCUINTPTR)pCtx->eip + cbOp) - ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem + off + 4);
2549 off += sizeof(RTRCUINTPTR);
2550
2551 if (pVM->hm.s.pFreeGuestPatchMem + off <= pVM->hm.s.pGuestPatchMem + pVM->hm.s.cbGuestPatchMem)
2552 {
2553 /* Write new code to the patch buffer. */
2554 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pVM->hm.s.pFreeGuestPatchMem, aPatch, off);
2555 AssertRC(rc);
2556
2557#ifdef LOG_ENABLED
2558 uint32_t cbCurInstr;
2559 for (RTGCPTR GCPtrInstr = pVM->hm.s.pFreeGuestPatchMem;
2560 GCPtrInstr < pVM->hm.s.pFreeGuestPatchMem + off;
2561 GCPtrInstr += RT_MAX(cbCurInstr, 1))
2562 {
2563 char szOutput[256];
2564 rc = DBGFR3DisasInstrEx(pVM->pUVM, pVCpu->idCpu, pCtx->cs.Sel, GCPtrInstr, DBGF_DISAS_FLAGS_DEFAULT_MODE,
2565 szOutput, sizeof(szOutput), &cbCurInstr);
2566 if (RT_SUCCESS(rc))
2567 Log(("Patch instr %s\n", szOutput));
2568 else
2569 Log(("%RGv: rc=%Rrc\n", GCPtrInstr, rc));
2570 }
2571#endif
2572
2573 pPatch->aNewOpcode[0] = 0xE9;
2574 *(RTRCUINTPTR *)&pPatch->aNewOpcode[1] = ((RTRCUINTPTR)pVM->hm.s.pFreeGuestPatchMem) - ((RTRCUINTPTR)pCtx->eip + 5);
2575
2576 /* Overwrite the TPR instruction with a jump. */
2577 rc = PGMPhysSimpleWriteGCPtr(pVCpu, pCtx->eip, pPatch->aNewOpcode, 5);
2578 AssertRC(rc);
2579
2580 DBGFR3_DISAS_INSTR_CUR_LOG(pVCpu, "Jump");
2581
2582 pVM->hm.s.pFreeGuestPatchMem += off;
2583 pPatch->cbNewOp = 5;
2584
2585 pPatch->Core.Key = pCtx->eip;
2586 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2587 AssertRC(rc);
2588
2589 pVM->hm.s.cPatches++;
2590 pVM->hm.s.fTPRPatchingActive = true;
2591 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchSuccess);
2592 return VINF_SUCCESS;
2593 }
2594
2595 Log(("Ran out of space in our patch buffer!\n"));
2596 }
2597 else
2598 Log(("hmR3PatchTprInstr: Failed to patch instr!\n"));
2599
2600
2601 /*
2602 * Save invalid patch, so we will not try again.
2603 */
2604 pPatch = &pVM->hm.s.aPatches[idx];
2605 pPatch->Core.Key = pCtx->eip;
2606 pPatch->enmType = HMTPRINSTR_INVALID;
2607 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
2608 AssertRC(rc);
2609 pVM->hm.s.cPatches++;
2610 STAM_COUNTER_INC(&pVM->hm.s.StatTprPatchFailure);
2611 return VINF_SUCCESS;
2612}
2613
2614
2615/**
2616 * Attempt to patch TPR mmio instructions.
2617 *
2618 * @returns VBox status code.
2619 * @param pVM The cross context VM structure.
2620 * @param pVCpu The cross context virtual CPU structure.
2621 * @param pCtx Pointer to the guest CPU context.
2622 */
2623VMMR3_INT_DECL(int) HMR3PatchTprInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
2624{
2625 NOREF(pCtx);
2626 int rc = VMMR3EmtRendezvous(pVM, VMMEMTRENDEZVOUS_FLAGS_TYPE_ONE_BY_ONE,
2627 pVM->hm.s.pGuestPatchMem ? hmR3PatchTprInstr : hmR3ReplaceTprInstr,
2628 (void *)(uintptr_t)pVCpu->idCpu);
2629 AssertRC(rc);
2630 return rc;
2631}
2632
2633
2634/**
2635 * Checks if a code selector (CS) is suitable for execution
2636 * within VMX when unrestricted execution isn't available.
2637 *
2638 * @returns true if selector is suitable for VMX, otherwise
2639 * false.
2640 * @param pSel Pointer to the selector to check (CS).
2641 * @param uStackDpl The CPL, aka the DPL of the stack segment.
2642 */
2643static bool hmR3IsCodeSelectorOkForVmx(PCPUMSELREG pSel, unsigned uStackDpl)
2644{
2645 /*
2646 * Segment must be an accessed code segment, it must be present and it must
2647 * be usable.
2648 * Note! These are all standard requirements and if CS holds anything else
2649 * we've got buggy code somewhere!
2650 */
2651 AssertCompile(X86DESCATTR_TYPE == 0xf);
2652 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P | X86DESCATTR_UNUSABLE))
2653 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_CODE | X86DESCATTR_DT | X86DESCATTR_P),
2654 ("%#x\n", pSel->Attr.u),
2655 false);
2656
2657 /* For conforming segments, CS.DPL must be <= SS.DPL, while CS.DPL
2658 must equal SS.DPL for non-confroming segments.
2659 Note! This is also a hard requirement like above. */
2660 AssertMsgReturn( pSel->Attr.n.u4Type & X86_SEL_TYPE_CONF
2661 ? pSel->Attr.n.u2Dpl <= uStackDpl
2662 : pSel->Attr.n.u2Dpl == uStackDpl,
2663 ("u4Type=%#x u2Dpl=%u uStackDpl=%u\n", pSel->Attr.n.u4Type, pSel->Attr.n.u2Dpl, uStackDpl),
2664 false);
2665
2666 /*
2667 * The following two requirements are VT-x specific:
2668 * - G bit must be set if any high limit bits are set.
2669 * - G bit must be clear if any low limit bits are clear.
2670 */
2671 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2672 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2673 return true;
2674 return false;
2675}
2676
2677
2678/**
2679 * Checks if a data selector (DS/ES/FS/GS) is suitable for
2680 * execution within VMX when unrestricted execution isn't
2681 * available.
2682 *
2683 * @returns true if selector is suitable for VMX, otherwise
2684 * false.
2685 * @param pSel Pointer to the selector to check
2686 * (DS/ES/FS/GS).
2687 */
2688static bool hmR3IsDataSelectorOkForVmx(PCPUMSELREG pSel)
2689{
2690 /*
2691 * Unusable segments are OK. These days they should be marked as such, as
2692 * but as an alternative we for old saved states and AMD<->VT-x migration
2693 * we also treat segments with all the attributes cleared as unusable.
2694 */
2695 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2696 return true;
2697
2698 /** @todo tighten these checks. Will require CPUM load adjusting. */
2699
2700 /* Segment must be accessed. */
2701 if (pSel->Attr.u & X86_SEL_TYPE_ACCESSED)
2702 {
2703 /* Code segments must also be readable. */
2704 if ( !(pSel->Attr.u & X86_SEL_TYPE_CODE)
2705 || (pSel->Attr.u & X86_SEL_TYPE_READ))
2706 {
2707 /* The S bit must be set. */
2708 if (pSel->Attr.n.u1DescType)
2709 {
2710 /* Except for conforming segments, DPL >= RPL. */
2711 if ( pSel->Attr.n.u2Dpl >= (pSel->Sel & X86_SEL_RPL)
2712 || pSel->Attr.n.u4Type >= X86_SEL_TYPE_ER_ACC)
2713 {
2714 /* Segment must be present. */
2715 if (pSel->Attr.n.u1Present)
2716 {
2717 /*
2718 * The following two requirements are VT-x specific:
2719 * - G bit must be set if any high limit bits are set.
2720 * - G bit must be clear if any low limit bits are clear.
2721 */
2722 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2723 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2724 return true;
2725 }
2726 }
2727 }
2728 }
2729 }
2730
2731 return false;
2732}
2733
2734
2735/**
2736 * Checks if the stack selector (SS) is suitable for execution
2737 * within VMX when unrestricted execution isn't available.
2738 *
2739 * @returns true if selector is suitable for VMX, otherwise
2740 * false.
2741 * @param pSel Pointer to the selector to check (SS).
2742 */
2743static bool hmR3IsStackSelectorOkForVmx(PCPUMSELREG pSel)
2744{
2745 /*
2746 * Unusable segments are OK. These days they should be marked as such, as
2747 * but as an alternative we for old saved states and AMD<->VT-x migration
2748 * we also treat segments with all the attributes cleared as unusable.
2749 */
2750 /** @todo r=bird: actually all zeroes isn't gonna cut it... SS.DPL == CPL. */
2751 if (pSel->Attr.n.u1Unusable || !pSel->Attr.u)
2752 return true;
2753
2754 /*
2755 * Segment must be an accessed writable segment, it must be present.
2756 * Note! These are all standard requirements and if SS holds anything else
2757 * we've got buggy code somewhere!
2758 */
2759 AssertCompile(X86DESCATTR_TYPE == 0xf);
2760 AssertMsgReturn( (pSel->Attr.u & (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P | X86_SEL_TYPE_CODE))
2761 == (X86_SEL_TYPE_ACCESSED | X86_SEL_TYPE_WRITE | X86DESCATTR_DT | X86DESCATTR_P),
2762 ("%#x\n", pSel->Attr.u),
2763 false);
2764
2765 /* DPL must equal RPL.
2766 Note! This is also a hard requirement like above. */
2767 AssertMsgReturn(pSel->Attr.n.u2Dpl == (pSel->Sel & X86_SEL_RPL),
2768 ("u2Dpl=%u Sel=%#x\n", pSel->Attr.n.u2Dpl, pSel->Sel),
2769 false);
2770
2771 /*
2772 * The following two requirements are VT-x specific:
2773 * - G bit must be set if any high limit bits are set.
2774 * - G bit must be clear if any low limit bits are clear.
2775 */
2776 if ( ((pSel->u32Limit & 0xfff00000) == 0x00000000 || pSel->Attr.n.u1Granularity)
2777 && ((pSel->u32Limit & 0x00000fff) == 0x00000fff || !pSel->Attr.n.u1Granularity) )
2778 return true;
2779 return false;
2780}
2781
2782
2783/**
2784 * Force execution of the current IO code in the recompiler.
2785 *
2786 * @returns VBox status code.
2787 * @param pVM The cross context VM structure.
2788 * @param pCtx Partial VM execution context.
2789 */
2790VMMR3_INT_DECL(int) HMR3EmulateIoBlock(PVM pVM, PCPUMCTX pCtx)
2791{
2792 PVMCPU pVCpu = VMMGetCpu(pVM);
2793
2794 Assert(HMIsEnabled(pVM));
2795 Log(("HMR3EmulateIoBlock\n"));
2796
2797 /* This is primarily intended to speed up Grub, so we don't care about paged protected mode. */
2798 if (HMCanEmulateIoBlockEx(pCtx))
2799 {
2800 Log(("HMR3EmulateIoBlock -> enabled\n"));
2801 pVCpu->hm.s.EmulateIoBlock.fEnabled = true;
2802 pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip = pCtx->rip;
2803 pVCpu->hm.s.EmulateIoBlock.cr0 = pCtx->cr0;
2804 return VINF_EM_RESCHEDULE_REM;
2805 }
2806 return VINF_SUCCESS;
2807}
2808
2809
2810/**
2811 * Checks if we can currently use hardware accelerated raw mode.
2812 *
2813 * @returns true if we can currently use hardware acceleration, otherwise false.
2814 * @param pVM The cross context VM structure.
2815 * @param pCtx Partial VM execution context.
2816 */
2817VMMR3DECL(bool) HMR3CanExecuteGuest(PVM pVM, PCPUMCTX pCtx)
2818{
2819 PVMCPU pVCpu = VMMGetCpu(pVM);
2820
2821 Assert(HMIsEnabled(pVM));
2822
2823#ifdef VBOX_WITH_NESTED_HWVIRT_ONLY_IN_IEM
2824 if (CPUMIsGuestInNestedHwVirtMode(pCtx))
2825 {
2826 Log(("HMR3CanExecuteGuest: In nested-guest mode - returning false"));
2827 return false;
2828 }
2829#endif
2830
2831 /* If we're still executing the IO code, then return false. */
2832 if ( RT_UNLIKELY(pVCpu->hm.s.EmulateIoBlock.fEnabled)
2833 && pCtx->rip < pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip + 0x200
2834 && pCtx->rip > pVCpu->hm.s.EmulateIoBlock.GCPtrFunctionEip - 0x200
2835 && pCtx->cr0 == pVCpu->hm.s.EmulateIoBlock.cr0)
2836 return false;
2837
2838 pVCpu->hm.s.EmulateIoBlock.fEnabled = false;
2839
2840 /* AMD-V supports real & protected mode with or without paging. */
2841 if (pVM->hm.s.svm.fEnabled)
2842 {
2843 pVCpu->hm.s.fActive = true;
2844 return true;
2845 }
2846
2847 pVCpu->hm.s.fActive = false;
2848
2849 /* Note! The context supplied by REM is partial. If we add more checks here, be sure to verify that REM provides this info! */
2850 Assert( (pVM->hm.s.vmx.fUnrestrictedGuest && !pVM->hm.s.vmx.pRealModeTSS)
2851 || (!pVM->hm.s.vmx.fUnrestrictedGuest && pVM->hm.s.vmx.pRealModeTSS));
2852
2853 bool fSupportsRealMode = pVM->hm.s.vmx.fUnrestrictedGuest || PDMVmmDevHeapIsEnabled(pVM);
2854 if (!pVM->hm.s.vmx.fUnrestrictedGuest)
2855 {
2856 /*
2857 * The VMM device heap is a requirement for emulating real mode or protected mode without paging with the unrestricted
2858 * guest execution feature is missing (VT-x only).
2859 */
2860 if (fSupportsRealMode)
2861 {
2862 if (CPUMIsGuestInRealModeEx(pCtx))
2863 {
2864 /* In V86 mode (VT-x or not), the CPU enforces real-mode compatible selector
2865 * bases and limits, i.e. limit must be 64K and base must be selector * 16.
2866 * If this is not true, we cannot execute real mode as V86 and have to fall
2867 * back to emulation.
2868 */
2869 if ( pCtx->cs.Sel != (pCtx->cs.u64Base >> 4)
2870 || pCtx->ds.Sel != (pCtx->ds.u64Base >> 4)
2871 || pCtx->es.Sel != (pCtx->es.u64Base >> 4)
2872 || pCtx->ss.Sel != (pCtx->ss.u64Base >> 4)
2873 || pCtx->fs.Sel != (pCtx->fs.u64Base >> 4)
2874 || pCtx->gs.Sel != (pCtx->gs.u64Base >> 4))
2875 {
2876 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelBase);
2877 return false;
2878 }
2879 if ( (pCtx->cs.u32Limit != 0xffff)
2880 || (pCtx->ds.u32Limit != 0xffff)
2881 || (pCtx->es.u32Limit != 0xffff)
2882 || (pCtx->ss.u32Limit != 0xffff)
2883 || (pCtx->fs.u32Limit != 0xffff)
2884 || (pCtx->gs.u32Limit != 0xffff))
2885 {
2886 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRmSelLimit);
2887 return false;
2888 }
2889 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckRmOk);
2890 }
2891 else
2892 {
2893 /* Verify the requirements for executing code in protected
2894 mode. VT-x can't handle the CPU state right after a switch
2895 from real to protected mode. (all sorts of RPL & DPL assumptions). */
2896 if (pVCpu->hm.s.vmx.fWasInRealMode)
2897 {
2898 /** @todo If guest is in V86 mode, these checks should be different! */
2899 if ((pCtx->cs.Sel & X86_SEL_RPL) != (pCtx->ss.Sel & X86_SEL_RPL))
2900 {
2901 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadRpl);
2902 return false;
2903 }
2904 if ( !hmR3IsCodeSelectorOkForVmx(&pCtx->cs, pCtx->ss.Attr.n.u2Dpl)
2905 || !hmR3IsDataSelectorOkForVmx(&pCtx->ds)
2906 || !hmR3IsDataSelectorOkForVmx(&pCtx->es)
2907 || !hmR3IsDataSelectorOkForVmx(&pCtx->fs)
2908 || !hmR3IsDataSelectorOkForVmx(&pCtx->gs)
2909 || !hmR3IsStackSelectorOkForVmx(&pCtx->ss))
2910 {
2911 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadSel);
2912 return false;
2913 }
2914 }
2915 /* VT-x also chokes on invalid TR or LDTR selectors (minix). */
2916 if (pCtx->gdtr.cbGdt)
2917 {
2918 if ((pCtx->tr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2919 {
2920 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadTr);
2921 return false;
2922 }
2923 else if ((pCtx->ldtr.Sel | X86_SEL_RPL_LDT) > pCtx->gdtr.cbGdt)
2924 {
2925 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckBadLdt);
2926 return false;
2927 }
2928 }
2929 STAM_COUNTER_INC(&pVCpu->hm.s.StatVmxCheckPmOk);
2930 }
2931 }
2932 else
2933 {
2934 if ( !CPUMIsGuestInLongModeEx(pCtx)
2935 && !pVM->hm.s.vmx.fUnrestrictedGuest)
2936 {
2937 if ( !pVM->hm.s.fNestedPaging /* Requires a fake PD for real *and* protected mode without paging - stored in the VMM device heap */
2938 || CPUMIsGuestInRealModeEx(pCtx)) /* Requires a fake TSS for real mode - stored in the VMM device heap */
2939 return false;
2940
2941 /* Too early for VT-x; Solaris guests will fail with a guru meditation otherwise; same for XP. */
2942 if (pCtx->idtr.pIdt == 0 || pCtx->idtr.cbIdt == 0 || pCtx->tr.Sel == 0)
2943 return false;
2944
2945 /* The guest is about to complete the switch to protected mode. Wait a bit longer. */
2946 /* Windows XP; switch to protected mode; all selectors are marked not present in the
2947 * hidden registers (possible recompiler bug; see load_seg_vm) */
2948 if (pCtx->cs.Attr.n.u1Present == 0)
2949 return false;
2950 if (pCtx->ss.Attr.n.u1Present == 0)
2951 return false;
2952
2953 /* Windows XP: possible same as above, but new recompiler requires new heuristics?
2954 VT-x doesn't seem to like something about the guest state and this stuff avoids it. */
2955 /** @todo This check is actually wrong, it doesn't take the direction of the
2956 * stack segment into account. But, it does the job for now. */
2957 if (pCtx->rsp >= pCtx->ss.u32Limit)
2958 return false;
2959 }
2960 }
2961 }
2962
2963 if (pVM->hm.s.vmx.fEnabled)
2964 {
2965 uint32_t mask;
2966
2967 /* if bit N is set in cr0_fixed0, then it must be set in the guest's cr0. */
2968 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr0Fixed0;
2969 /* Note: We ignore the NE bit here on purpose; see vmmr0\hmr0.cpp for details. */
2970 mask &= ~X86_CR0_NE;
2971
2972 if (fSupportsRealMode)
2973 {
2974 /* Note: We ignore the PE & PG bits here on purpose; we emulate real and protected mode without paging. */
2975 mask &= ~(X86_CR0_PG|X86_CR0_PE);
2976 }
2977 else
2978 {
2979 /* We support protected mode without paging using identity mapping. */
2980 mask &= ~X86_CR0_PG;
2981 }
2982 if ((pCtx->cr0 & mask) != mask)
2983 return false;
2984
2985 /* if bit N is cleared in cr0_fixed1, then it must be zero in the guest's cr0. */
2986 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr0Fixed1;
2987 if ((pCtx->cr0 & mask) != 0)
2988 return false;
2989
2990 /* if bit N is set in cr4_fixed0, then it must be set in the guest's cr4. */
2991 mask = (uint32_t)pVM->hm.s.vmx.Msrs.u64Cr4Fixed0;
2992 mask &= ~X86_CR4_VMXE;
2993 if ((pCtx->cr4 & mask) != mask)
2994 return false;
2995
2996 /* if bit N is cleared in cr4_fixed1, then it must be zero in the guest's cr4. */
2997 mask = (uint32_t)~pVM->hm.s.vmx.Msrs.u64Cr4Fixed1;
2998 if ((pCtx->cr4 & mask) != 0)
2999 return false;
3000
3001 pVCpu->hm.s.fActive = true;
3002 return true;
3003 }
3004
3005 return false;
3006}
3007
3008
3009/**
3010 * Checks if we need to reschedule due to VMM device heap changes.
3011 *
3012 * @returns true if a reschedule is required, otherwise false.
3013 * @param pVM The cross context VM structure.
3014 * @param pCtx VM execution context.
3015 */
3016VMMR3_INT_DECL(bool) HMR3IsRescheduleRequired(PVM pVM, PCPUMCTX pCtx)
3017{
3018 /*
3019 * The VMM device heap is a requirement for emulating real-mode or protected-mode without paging
3020 * when the unrestricted guest execution feature is missing (VT-x only).
3021 */
3022 if ( pVM->hm.s.vmx.fEnabled
3023 && !pVM->hm.s.vmx.fUnrestrictedGuest
3024 && CPUMIsGuestInRealModeEx(pCtx)
3025 && !PDMVmmDevHeapIsEnabled(pVM))
3026 {
3027 return true;
3028 }
3029
3030 return false;
3031}
3032
3033
3034/**
3035 * Noticiation callback from DBGF when interrupt breakpoints or generic debug
3036 * event settings changes.
3037 *
3038 * DBGF will call HMR3NotifyDebugEventChangedPerCpu on each CPU afterwards, this
3039 * function is just updating the VM globals.
3040 *
3041 * @param pVM The VM cross context VM structure.
3042 * @thread EMT(0)
3043 */
3044VMMR3_INT_DECL(void) HMR3NotifyDebugEventChanged(PVM pVM)
3045{
3046 /* Interrupts. */
3047 bool fUseDebugLoop = pVM->dbgf.ro.cSoftIntBreakpoints > 0
3048 || pVM->dbgf.ro.cHardIntBreakpoints > 0;
3049
3050 /* CPU Exceptions. */
3051 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_XCPT_FIRST;
3052 !fUseDebugLoop && enmEvent <= DBGFEVENT_XCPT_LAST;
3053 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3054 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3055
3056 /* Common VM exits. */
3057 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_FIRST;
3058 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_LAST_COMMON;
3059 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3060 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3061
3062 /* Vendor specific VM exits. */
3063 if (HMR3IsVmxEnabled(pVM->pUVM))
3064 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_VMX_FIRST;
3065 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_VMX_LAST;
3066 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3067 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3068 else
3069 for (DBGFEVENTTYPE enmEvent = DBGFEVENT_EXIT_SVM_FIRST;
3070 !fUseDebugLoop && enmEvent <= DBGFEVENT_EXIT_SVM_LAST;
3071 enmEvent = (DBGFEVENTTYPE)(enmEvent + 1))
3072 fUseDebugLoop = DBGF_IS_EVENT_ENABLED(pVM, enmEvent);
3073
3074 /* Done. */
3075 pVM->hm.s.fUseDebugLoop = fUseDebugLoop;
3076}
3077
3078
3079/**
3080 * Follow up notification callback to HMR3NotifyDebugEventChanged for each CPU.
3081 *
3082 * HM uses this to combine the decision made by HMR3NotifyDebugEventChanged with
3083 * per CPU settings.
3084 *
3085 * @param pVM The VM cross context VM structure.
3086 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3087 */
3088VMMR3_INT_DECL(void) HMR3NotifyDebugEventChangedPerCpu(PVM pVM, PVMCPU pVCpu)
3089{
3090 pVCpu->hm.s.fUseDebugLoop = pVCpu->hm.s.fSingleInstruction | pVM->hm.s.fUseDebugLoop;
3091}
3092
3093
3094/**
3095 * Notification from EM about a rescheduling into hardware assisted execution
3096 * mode.
3097 *
3098 * @param pVCpu The cross context virtual CPU structure of the calling EMT.
3099 */
3100VMMR3_INT_DECL(void) HMR3NotifyScheduled(PVMCPU pVCpu)
3101{
3102 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3103}
3104
3105
3106/**
3107 * Notification from EM about returning from instruction emulation (REM / EM).
3108 *
3109 * @param pVCpu The cross context virtual CPU structure.
3110 */
3111VMMR3_INT_DECL(void) HMR3NotifyEmulated(PVMCPU pVCpu)
3112{
3113 HMCPU_CF_SET(pVCpu, HM_CHANGED_ALL_GUEST);
3114}
3115
3116
3117/**
3118 * Checks if we are currently using hardware acceleration.
3119 *
3120 * @returns true if hardware acceleration is being used, otherwise false.
3121 * @param pVCpu The cross context virtual CPU structure.
3122 */
3123VMMR3_INT_DECL(bool) HMR3IsActive(PVMCPU pVCpu)
3124{
3125 return pVCpu->hm.s.fActive;
3126}
3127
3128
3129/**
3130 * External interface for querying whether hardware acceleration is enabled.
3131 *
3132 * @returns true if VT-x or AMD-V is being used, otherwise false.
3133 * @param pUVM The user mode VM handle.
3134 * @sa HMIsEnabled, HMIsEnabledNotMacro.
3135 */
3136VMMR3DECL(bool) HMR3IsEnabled(PUVM pUVM)
3137{
3138 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3139 PVM pVM = pUVM->pVM;
3140 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3141 return pVM->fHMEnabled; /* Don't use the macro as the GUI may query us very very early. */
3142}
3143
3144
3145/**
3146 * External interface for querying whether VT-x is being used.
3147 *
3148 * @returns true if VT-x is being used, otherwise false.
3149 * @param pUVM The user mode VM handle.
3150 * @sa HMR3IsSvmEnabled, HMIsEnabled
3151 */
3152VMMR3DECL(bool) HMR3IsVmxEnabled(PUVM pUVM)
3153{
3154 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3155 PVM pVM = pUVM->pVM;
3156 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3157 return pVM->hm.s.vmx.fEnabled
3158 && pVM->hm.s.vmx.fSupported
3159 && pVM->fHMEnabled;
3160}
3161
3162
3163/**
3164 * External interface for querying whether AMD-V is being used.
3165 *
3166 * @returns true if VT-x is being used, otherwise false.
3167 * @param pUVM The user mode VM handle.
3168 * @sa HMR3IsVmxEnabled, HMIsEnabled
3169 */
3170VMMR3DECL(bool) HMR3IsSvmEnabled(PUVM pUVM)
3171{
3172 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3173 PVM pVM = pUVM->pVM;
3174 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3175 return pVM->hm.s.svm.fEnabled
3176 && pVM->hm.s.svm.fSupported
3177 && pVM->fHMEnabled;
3178}
3179
3180
3181/**
3182 * Checks if we are currently using nested paging.
3183 *
3184 * @returns true if nested paging is being used, otherwise false.
3185 * @param pUVM The user mode VM handle.
3186 */
3187VMMR3DECL(bool) HMR3IsNestedPagingActive(PUVM pUVM)
3188{
3189 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3190 PVM pVM = pUVM->pVM;
3191 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3192 return pVM->hm.s.fNestedPaging;
3193}
3194
3195
3196/**
3197 * Checks if virtualized APIC registers is enabled.
3198 *
3199 * When enabled this feature allows the hardware to access most of the
3200 * APIC registers in the virtual-APIC page without causing VM-exits. See
3201 * Intel spec. 29.1.1 "Virtualized APIC Registers".
3202 *
3203 * @returns true if virtualized APIC registers is enabled, otherwise
3204 * false.
3205 * @param pUVM The user mode VM handle.
3206 */
3207VMMR3DECL(bool) HMR3IsVirtApicRegsEnabled(PUVM pUVM)
3208{
3209 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3210 PVM pVM = pUVM->pVM;
3211 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3212 return pVM->hm.s.fVirtApicRegs;
3213}
3214
3215
3216/**
3217 * Checks if APIC posted-interrupt processing is enabled.
3218 *
3219 * This returns whether we can deliver interrupts to the guest without
3220 * leaving guest-context by updating APIC state from host-context.
3221 *
3222 * @returns true if APIC posted-interrupt processing is enabled,
3223 * otherwise false.
3224 * @param pUVM The user mode VM handle.
3225 */
3226VMMR3DECL(bool) HMR3IsPostedIntrsEnabled(PUVM pUVM)
3227{
3228 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3229 PVM pVM = pUVM->pVM;
3230 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3231 return pVM->hm.s.fPostedIntrs;
3232}
3233
3234
3235/**
3236 * Checks if we are currently using VPID in VT-x mode.
3237 *
3238 * @returns true if VPID is being used, otherwise false.
3239 * @param pUVM The user mode VM handle.
3240 */
3241VMMR3DECL(bool) HMR3IsVpidActive(PUVM pUVM)
3242{
3243 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3244 PVM pVM = pUVM->pVM;
3245 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3246 return pVM->hm.s.vmx.fVpid;
3247}
3248
3249
3250/**
3251 * Checks if we are currently using VT-x unrestricted execution,
3252 * aka UX.
3253 *
3254 * @returns true if UX is being used, otherwise false.
3255 * @param pUVM The user mode VM handle.
3256 */
3257VMMR3DECL(bool) HMR3IsUXActive(PUVM pUVM)
3258{
3259 UVM_ASSERT_VALID_EXT_RETURN(pUVM, false);
3260 PVM pVM = pUVM->pVM;
3261 VM_ASSERT_VALID_EXT_RETURN(pVM, false);
3262 return pVM->hm.s.vmx.fUnrestrictedGuest;
3263}
3264
3265
3266/**
3267 * Checks if internal events are pending. In that case we are not allowed to dispatch interrupts.
3268 *
3269 * @returns true if an internal event is pending, otherwise false.
3270 * @param pVCpu The cross context virtual CPU structure.
3271 */
3272VMMR3_INT_DECL(bool) HMR3IsEventPending(PVMCPU pVCpu)
3273{
3274 return HMIsEnabled(pVCpu->pVMR3) && pVCpu->hm.s.Event.fPending;
3275}
3276
3277
3278/**
3279 * Checks if the VMX-preemption timer is being used.
3280 *
3281 * @returns true if the VMX-preemption timer is being used, otherwise false.
3282 * @param pVM The cross context VM structure.
3283 */
3284VMMR3_INT_DECL(bool) HMR3IsVmxPreemptionTimerUsed(PVM pVM)
3285{
3286 return HMIsEnabled(pVM)
3287 && pVM->hm.s.vmx.fEnabled
3288 && pVM->hm.s.vmx.fUsePreemptTimer;
3289}
3290
3291
3292/**
3293 * Restart an I/O instruction that was refused in ring-0
3294 *
3295 * @returns Strict VBox status code. Informational status codes other than the one documented
3296 * here are to be treated as internal failure. Use IOM_SUCCESS() to check for success.
3297 * @retval VINF_SUCCESS Success.
3298 * @retval VINF_EM_FIRST-VINF_EM_LAST Success with some exceptions (see IOM_SUCCESS()), the
3299 * status code must be passed on to EM.
3300 * @retval VERR_NOT_FOUND if no pending I/O instruction.
3301 *
3302 * @param pVM The cross context VM structure.
3303 * @param pVCpu The cross context virtual CPU structure.
3304 * @param pCtx Pointer to the guest CPU context.
3305 */
3306VMMR3_INT_DECL(VBOXSTRICTRC) HMR3RestartPendingIOInstr(PVM pVM, PVMCPU pVCpu, PCPUMCTX pCtx)
3307{
3308 /*
3309 * Check if we've got relevant data pending.
3310 */
3311 HMPENDINGIO enmType = pVCpu->hm.s.PendingIO.enmType;
3312 if (enmType == HMPENDINGIO_INVALID)
3313 return VERR_NOT_FOUND;
3314 pVCpu->hm.s.PendingIO.enmType = HMPENDINGIO_INVALID;
3315 if (pVCpu->hm.s.PendingIO.GCPtrRip != pCtx->rip)
3316 return VERR_NOT_FOUND;
3317
3318 /*
3319 * Execute pending I/O.
3320 */
3321 VBOXSTRICTRC rcStrict;
3322 switch (enmType)
3323 {
3324 case HMPENDINGIO_PORT_READ:
3325 {
3326 uint32_t uAndVal = pVCpu->hm.s.PendingIO.s.Port.uAndVal;
3327 uint32_t u32Val = 0;
3328
3329 rcStrict = IOMIOPortRead(pVM, pVCpu, pVCpu->hm.s.PendingIO.s.Port.uPort, &u32Val,
3330 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3331 if (IOM_SUCCESS(rcStrict))
3332 {
3333 /* Write back to the EAX register. */
3334 pCtx->eax = (pCtx->eax & ~uAndVal) | (u32Val & uAndVal);
3335 pCtx->rip = pVCpu->hm.s.PendingIO.GCPtrRipNext;
3336 }
3337 break;
3338 }
3339
3340 default:
3341 AssertLogRelFailedReturn(VERR_HM_UNKNOWN_IO_INSTRUCTION);
3342 }
3343
3344 if (IOM_SUCCESS(rcStrict))
3345 {
3346 /*
3347 * Check for I/O breakpoints.
3348 */
3349 uint32_t const uDr7 = pCtx->dr[7];
3350 if ( ( (uDr7 & X86_DR7_ENABLED_MASK)
3351 && X86_DR7_ANY_RW_IO(uDr7)
3352 && (pCtx->cr4 & X86_CR4_DE))
3353 || DBGFBpIsHwIoArmed(pVM))
3354 {
3355 VBOXSTRICTRC rcStrict2 = DBGFBpCheckIo(pVM, pVCpu, pCtx, pVCpu->hm.s.PendingIO.s.Port.uPort,
3356 pVCpu->hm.s.PendingIO.s.Port.cbSize);
3357 if (rcStrict2 == VINF_EM_RAW_GUEST_TRAP)
3358 rcStrict2 = TRPMAssertTrap(pVCpu, X86_XCPT_DB, TRPM_TRAP);
3359 /* rcStrict is VINF_SUCCESS or in [VINF_EM_FIRST..VINF_EM_LAST]. */
3360 else if (rcStrict2 != VINF_SUCCESS && (rcStrict == VINF_SUCCESS || rcStrict2 < rcStrict))
3361 rcStrict = rcStrict2;
3362 }
3363 }
3364 return rcStrict;
3365}
3366
3367
3368/**
3369 * Check fatal VT-x/AMD-V error and produce some meaningful
3370 * log release message.
3371 *
3372 * @param pVM The cross context VM structure.
3373 * @param iStatusCode VBox status code.
3374 */
3375VMMR3_INT_DECL(void) HMR3CheckError(PVM pVM, int iStatusCode)
3376{
3377 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3378 {
3379 PVMCPU pVCpu = &pVM->aCpus[i];
3380 switch (iStatusCode)
3381 {
3382 /** @todo r=ramshankar: Are all EMTs out of ring-0 at this point!? If not, we
3383 * might be getting inaccurate values for non-guru'ing EMTs. */
3384 case VERR_VMX_INVALID_VMCS_FIELD:
3385 break;
3386
3387 case VERR_VMX_INVALID_VMCS_PTR:
3388 LogRel(("HM: VERR_VMX_INVALID_VMCS_PTR:\n"));
3389 LogRel(("HM: CPU[%u] Current pointer %#RGp vs %#RGp\n", i, pVCpu->hm.s.vmx.LastError.u64VMCSPhys,
3390 pVCpu->hm.s.vmx.HCPhysVmcs));
3391 LogRel(("HM: CPU[%u] Current VMCS version %#x\n", i, pVCpu->hm.s.vmx.LastError.u32VMCSRevision));
3392 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3393 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3394 break;
3395
3396 case VERR_VMX_UNABLE_TO_START_VM:
3397 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM:\n"));
3398 LogRel(("HM: CPU[%u] Instruction error %#x\n", i, pVCpu->hm.s.vmx.LastError.u32InstrError));
3399 LogRel(("HM: CPU[%u] Exit reason %#x\n", i, pVCpu->hm.s.vmx.LastError.u32ExitReason));
3400
3401 if ( pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMLAUCH_NON_CLEAR_VMCS
3402 || pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMRESUME_NON_LAUNCHED_VMCS)
3403 {
3404 LogRel(("HM: CPU[%u] Entered Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idEnteredCpu));
3405 LogRel(("HM: CPU[%u] Current Host Cpu %u\n", i, pVCpu->hm.s.vmx.LastError.idCurrentCpu));
3406 }
3407 else if (pVM->aCpus[i].hm.s.vmx.LastError.u32InstrError == VMX_ERROR_VMENTRY_INVALID_CONTROL_FIELDS)
3408 {
3409 LogRel(("HM: CPU[%u] PinCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32PinCtls));
3410 LogRel(("HM: CPU[%u] ProcCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls));
3411 LogRel(("HM: CPU[%u] ProcCtls2 %#RX32\n", i, pVCpu->hm.s.vmx.u32ProcCtls2));
3412 LogRel(("HM: CPU[%u] EntryCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32EntryCtls));
3413 LogRel(("HM: CPU[%u] ExitCtls %#RX32\n", i, pVCpu->hm.s.vmx.u32ExitCtls));
3414 LogRel(("HM: CPU[%u] HCPhysMsrBitmap %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysMsrBitmap));
3415 LogRel(("HM: CPU[%u] HCPhysGuestMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysGuestMsr));
3416 LogRel(("HM: CPU[%u] HCPhysHostMsr %#RHp\n", i, pVCpu->hm.s.vmx.HCPhysHostMsr));
3417 LogRel(("HM: CPU[%u] cMsrs %u\n", i, pVCpu->hm.s.vmx.cMsrs));
3418 }
3419 /** @todo Log VM-entry event injection control fields
3420 * VMX_VMCS_CTRL_ENTRY_IRQ_INFO, VMX_VMCS_CTRL_ENTRY_EXCEPTION_ERRCODE
3421 * and VMX_VMCS_CTRL_ENTRY_INSTR_LENGTH from the VMCS. */
3422 break;
3423
3424 /* The guru will dump the HM error and exit history. Nothing extra to report for these errors. */
3425 case VERR_VMX_INVALID_VMXON_PTR:
3426 case VERR_HM_UNSUPPORTED_CPU_FEATURE_COMBO:
3427 case VERR_VMX_INVALID_GUEST_STATE:
3428 case VERR_VMX_UNEXPECTED_EXIT:
3429 case VERR_SVM_UNKNOWN_EXIT:
3430 case VERR_SVM_UNEXPECTED_EXIT:
3431 case VERR_SVM_UNEXPECTED_PATCH_TYPE:
3432 case VERR_SVM_UNEXPECTED_XCPT_EXIT:
3433 case VERR_VMX_UNEXPECTED_INTERRUPTION_EXIT_TYPE:
3434 break;
3435 }
3436 }
3437
3438 if (iStatusCode == VERR_VMX_UNABLE_TO_START_VM)
3439 {
3440 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry allowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.allowed1));
3441 LogRel(("HM: VERR_VMX_UNABLE_TO_START_VM: VM-entry disallowed %#RX32\n", pVM->hm.s.vmx.Msrs.VmxEntry.n.disallowed0));
3442 }
3443 else if (iStatusCode == VERR_VMX_INVALID_VMXON_PTR)
3444 LogRel(("HM: HCPhysVmxEnableError = %#RHp\n", pVM->hm.s.vmx.HCPhysVmxEnableError));
3445}
3446
3447
3448/**
3449 * Execute state save operation.
3450 *
3451 * @returns VBox status code.
3452 * @param pVM The cross context VM structure.
3453 * @param pSSM SSM operation handle.
3454 */
3455static DECLCALLBACK(int) hmR3Save(PVM pVM, PSSMHANDLE pSSM)
3456{
3457 int rc;
3458
3459 Log(("hmR3Save:\n"));
3460
3461 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3462 {
3463 /*
3464 * Save the basic bits - fortunately all the other things can be resynced on load.
3465 */
3466 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.fPending);
3467 AssertRCReturn(rc, rc);
3468 rc = SSMR3PutU32(pSSM, pVM->aCpus[i].hm.s.Event.u32ErrCode);
3469 AssertRCReturn(rc, rc);
3470 rc = SSMR3PutU64(pSSM, pVM->aCpus[i].hm.s.Event.u64IntInfo);
3471 AssertRCReturn(rc, rc);
3472 /** @todo Shouldn't we be saving GCPtrFaultAddress too? */
3473
3474 /** @todo We only need to save pVM->aCpus[i].hm.s.vmx.fWasInRealMode and
3475 * perhaps not even that (the initial value of @c true is safe. */
3476 uint32_t u32Dummy = PGMMODE_REAL;
3477 rc = SSMR3PutU32(pSSM, u32Dummy);
3478 AssertRCReturn(rc, rc);
3479 rc = SSMR3PutU32(pSSM, u32Dummy);
3480 AssertRCReturn(rc, rc);
3481 rc = SSMR3PutU32(pSSM, u32Dummy);
3482 AssertRCReturn(rc, rc);
3483 }
3484
3485#ifdef VBOX_HM_WITH_GUEST_PATCHING
3486 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pGuestPatchMem);
3487 AssertRCReturn(rc, rc);
3488 rc = SSMR3PutGCPtr(pSSM, pVM->hm.s.pFreeGuestPatchMem);
3489 AssertRCReturn(rc, rc);
3490 rc = SSMR3PutU32(pSSM, pVM->hm.s.cbGuestPatchMem);
3491 AssertRCReturn(rc, rc);
3492
3493 /* Store all the guest patch records too. */
3494 rc = SSMR3PutU32(pSSM, pVM->hm.s.cPatches);
3495 AssertRCReturn(rc, rc);
3496
3497 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3498 {
3499 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3500
3501 rc = SSMR3PutU32(pSSM, pPatch->Core.Key);
3502 AssertRCReturn(rc, rc);
3503
3504 rc = SSMR3PutMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3505 AssertRCReturn(rc, rc);
3506
3507 rc = SSMR3PutU32(pSSM, pPatch->cbOp);
3508 AssertRCReturn(rc, rc);
3509
3510 rc = SSMR3PutMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3511 AssertRCReturn(rc, rc);
3512
3513 rc = SSMR3PutU32(pSSM, pPatch->cbNewOp);
3514 AssertRCReturn(rc, rc);
3515
3516 AssertCompileSize(HMTPRINSTR, 4);
3517 rc = SSMR3PutU32(pSSM, (uint32_t)pPatch->enmType);
3518 AssertRCReturn(rc, rc);
3519
3520 rc = SSMR3PutU32(pSSM, pPatch->uSrcOperand);
3521 AssertRCReturn(rc, rc);
3522
3523 rc = SSMR3PutU32(pSSM, pPatch->uDstOperand);
3524 AssertRCReturn(rc, rc);
3525
3526 rc = SSMR3PutU32(pSSM, pPatch->pJumpTarget);
3527 AssertRCReturn(rc, rc);
3528
3529 rc = SSMR3PutU32(pSSM, pPatch->cFaults);
3530 AssertRCReturn(rc, rc);
3531 }
3532#endif
3533 return VINF_SUCCESS;
3534}
3535
3536
3537/**
3538 * Execute state load operation.
3539 *
3540 * @returns VBox status code.
3541 * @param pVM The cross context VM structure.
3542 * @param pSSM SSM operation handle.
3543 * @param uVersion Data layout version.
3544 * @param uPass The data pass.
3545 */
3546static DECLCALLBACK(int) hmR3Load(PVM pVM, PSSMHANDLE pSSM, uint32_t uVersion, uint32_t uPass)
3547{
3548 int rc;
3549
3550 Log(("hmR3Load:\n"));
3551 Assert(uPass == SSM_PASS_FINAL); NOREF(uPass);
3552
3553 /*
3554 * Validate version.
3555 */
3556 if ( uVersion != HM_SAVED_STATE_VERSION
3557 && uVersion != HM_SAVED_STATE_VERSION_NO_PATCHING
3558 && uVersion != HM_SAVED_STATE_VERSION_2_0_X)
3559 {
3560 AssertMsgFailed(("hmR3Load: Invalid version uVersion=%d!\n", uVersion));
3561 return VERR_SSM_UNSUPPORTED_DATA_UNIT_VERSION;
3562 }
3563 for (VMCPUID i = 0; i < pVM->cCpus; i++)
3564 {
3565 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.fPending);
3566 AssertRCReturn(rc, rc);
3567 rc = SSMR3GetU32(pSSM, &pVM->aCpus[i].hm.s.Event.u32ErrCode);
3568 AssertRCReturn(rc, rc);
3569 rc = SSMR3GetU64(pSSM, &pVM->aCpus[i].hm.s.Event.u64IntInfo);
3570 AssertRCReturn(rc, rc);
3571
3572 if (uVersion >= HM_SAVED_STATE_VERSION_NO_PATCHING)
3573 {
3574 uint32_t val;
3575 /** @todo See note in hmR3Save(). */
3576 rc = SSMR3GetU32(pSSM, &val);
3577 AssertRCReturn(rc, rc);
3578 rc = SSMR3GetU32(pSSM, &val);
3579 AssertRCReturn(rc, rc);
3580 rc = SSMR3GetU32(pSSM, &val);
3581 AssertRCReturn(rc, rc);
3582 }
3583 }
3584#ifdef VBOX_HM_WITH_GUEST_PATCHING
3585 if (uVersion > HM_SAVED_STATE_VERSION_NO_PATCHING)
3586 {
3587 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pGuestPatchMem);
3588 AssertRCReturn(rc, rc);
3589 rc = SSMR3GetGCPtr(pSSM, &pVM->hm.s.pFreeGuestPatchMem);
3590 AssertRCReturn(rc, rc);
3591 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cbGuestPatchMem);
3592 AssertRCReturn(rc, rc);
3593
3594 /* Fetch all TPR patch records. */
3595 rc = SSMR3GetU32(pSSM, &pVM->hm.s.cPatches);
3596 AssertRCReturn(rc, rc);
3597
3598 for (unsigned i = 0; i < pVM->hm.s.cPatches; i++)
3599 {
3600 PHMTPRPATCH pPatch = &pVM->hm.s.aPatches[i];
3601
3602 rc = SSMR3GetU32(pSSM, &pPatch->Core.Key);
3603 AssertRCReturn(rc, rc);
3604
3605 rc = SSMR3GetMem(pSSM, pPatch->aOpcode, sizeof(pPatch->aOpcode));
3606 AssertRCReturn(rc, rc);
3607
3608 rc = SSMR3GetU32(pSSM, &pPatch->cbOp);
3609 AssertRCReturn(rc, rc);
3610
3611 rc = SSMR3GetMem(pSSM, pPatch->aNewOpcode, sizeof(pPatch->aNewOpcode));
3612 AssertRCReturn(rc, rc);
3613
3614 rc = SSMR3GetU32(pSSM, &pPatch->cbNewOp);
3615 AssertRCReturn(rc, rc);
3616
3617 rc = SSMR3GetU32(pSSM, (uint32_t *)&pPatch->enmType);
3618 AssertRCReturn(rc, rc);
3619
3620 if (pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT)
3621 pVM->hm.s.fTPRPatchingActive = true;
3622
3623 Assert(pPatch->enmType == HMTPRINSTR_JUMP_REPLACEMENT || pVM->hm.s.fTPRPatchingActive == false);
3624
3625 rc = SSMR3GetU32(pSSM, &pPatch->uSrcOperand);
3626 AssertRCReturn(rc, rc);
3627
3628 rc = SSMR3GetU32(pSSM, &pPatch->uDstOperand);
3629 AssertRCReturn(rc, rc);
3630
3631 rc = SSMR3GetU32(pSSM, &pPatch->cFaults);
3632 AssertRCReturn(rc, rc);
3633
3634 rc = SSMR3GetU32(pSSM, &pPatch->pJumpTarget);
3635 AssertRCReturn(rc, rc);
3636
3637 Log(("hmR3Load: patch %d\n", i));
3638 Log(("Key = %x\n", pPatch->Core.Key));
3639 Log(("cbOp = %d\n", pPatch->cbOp));
3640 Log(("cbNewOp = %d\n", pPatch->cbNewOp));
3641 Log(("type = %d\n", pPatch->enmType));
3642 Log(("srcop = %d\n", pPatch->uSrcOperand));
3643 Log(("dstop = %d\n", pPatch->uDstOperand));
3644 Log(("cFaults = %d\n", pPatch->cFaults));
3645 Log(("target = %x\n", pPatch->pJumpTarget));
3646 rc = RTAvloU32Insert(&pVM->hm.s.PatchTree, &pPatch->Core);
3647 AssertRC(rc);
3648 }
3649 }
3650#endif
3651
3652 return VINF_SUCCESS;
3653}
3654
3655
3656/**
3657 * Displays the guest VM-exit history.
3658 *
3659 * @param pVM The cross context VM structure.
3660 * @param pHlp The info helper functions.
3661 * @param pszArgs Arguments, ignored.
3662 */
3663static DECLCALLBACK(void) hmR3InfoExitHistory(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3664{
3665 NOREF(pszArgs);
3666 PVMCPU pVCpu = VMMGetCpu(pVM);
3667 if (!pVCpu)
3668 pVCpu = &pVM->aCpus[0];
3669
3670 if (HMIsEnabled(pVM))
3671 {
3672 bool const fIsVtx = pVM->hm.s.vmx.fSupported;
3673 const char * const *papszDesc;
3674 unsigned cMaxExitDesc;
3675 if (fIsVtx)
3676 {
3677 cMaxExitDesc = MAX_EXITREASON_VTX;
3678 papszDesc = &g_apszVTxExitReasons[0];
3679 pHlp->pfnPrintf(pHlp, "CPU[%u]: VT-x VM-exit history:\n", pVCpu->idCpu);
3680 }
3681 else
3682 {
3683 cMaxExitDesc = MAX_EXITREASON_AMDV;
3684 papszDesc = &g_apszAmdVExitReasons[0];
3685 pHlp->pfnPrintf(pHlp, "CPU[%u]: AMD-V #VMEXIT history:\n", pVCpu->idCpu);
3686 }
3687
3688 pHlp->pfnPrintf(pHlp, " idxExitHistoryFree = %u\n", pVCpu->hm.s.idxExitHistoryFree);
3689 unsigned const idxLast = pVCpu->hm.s.idxExitHistoryFree > 0 ?
3690 pVCpu->hm.s.idxExitHistoryFree - 1 :
3691 RT_ELEMENTS(pVCpu->hm.s.auExitHistory) - 1;
3692 for (unsigned i = 0; i < RT_ELEMENTS(pVCpu->hm.s.auExitHistory); i++)
3693 {
3694 uint16_t const uExit = pVCpu->hm.s.auExitHistory[i];
3695 const char *pszExit = NULL;
3696 if (uExit <= cMaxExitDesc)
3697 pszExit = papszDesc[uExit];
3698 else if (!fIsVtx)
3699 pszExit = hmSvmGetSpecialExitReasonDesc(uExit);
3700 else
3701 pszExit = NULL;
3702
3703 pHlp->pfnPrintf(pHlp, " auExitHistory[%2u] = 0x%04x %s %s\n", i, uExit, pszExit,
3704 idxLast == i ? "<-- Latest exit" : "");
3705 }
3706 pHlp->pfnPrintf(pHlp, "HM error = %#x (%u)\n", pVCpu->hm.s.u32HMError, pVCpu->hm.s.u32HMError);
3707 }
3708 else
3709 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3710}
3711
3712
3713/**
3714 * Displays the HM pending event.
3715 *
3716 * @param pVM The cross context VM structure.
3717 * @param pHlp The info helper functions.
3718 * @param pszArgs Arguments, ignored.
3719 */
3720static DECLCALLBACK(void) hmR3InfoEventPending(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3721{
3722 NOREF(pszArgs);
3723 PVMCPU pVCpu = VMMGetCpu(pVM);
3724 if (!pVCpu)
3725 pVCpu = &pVM->aCpus[0];
3726
3727 if (HMIsEnabled(pVM))
3728 {
3729 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM event (fPending=%RTbool)\n", pVCpu->idCpu, pVCpu->hm.s.Event.fPending);
3730 if (pVCpu->hm.s.Event.fPending)
3731 {
3732 pHlp->pfnPrintf(pHlp, " u64IntInfo = %#RX64\n", pVCpu->hm.s.Event.u64IntInfo);
3733 pHlp->pfnPrintf(pHlp, " u32ErrCode = %#RX64\n", pVCpu->hm.s.Event.u32ErrCode);
3734 pHlp->pfnPrintf(pHlp, " cbInstr = %u bytes\n", pVCpu->hm.s.Event.cbInstr);
3735 pHlp->pfnPrintf(pHlp, " GCPtrFaultAddress = %#RGp\n", pVCpu->hm.s.Event.GCPtrFaultAddress);
3736 }
3737 }
3738 else
3739 pHlp->pfnPrintf(pHlp, "HM is not enabled for this VM!\n");
3740}
3741
3742
3743/**
3744 * Displays the SVM nested-guest VMCB cache.
3745 *
3746 * @param pVM The cross context VM structure.
3747 * @param pHlp The info helper functions.
3748 * @param pszArgs Arguments, ignored.
3749 */
3750static DECLCALLBACK(void) hmR3InfoSvmNstGstVmcbCache(PVM pVM, PCDBGFINFOHLP pHlp, const char *pszArgs)
3751{
3752 NOREF(pszArgs);
3753 PVMCPU pVCpu = VMMGetCpu(pVM);
3754 if (!pVCpu)
3755 pVCpu = &pVM->aCpus[0];
3756
3757 bool const fSvmEnabled = HMR3IsSvmEnabled(pVM->pUVM);
3758 if ( fSvmEnabled
3759 && pVM->cpum.ro.GuestFeatures.fSvm)
3760 {
3761 PCCPUMCTX pCtx = CPUMQueryGuestCtxPtr(pVCpu);
3762 PCSVMNESTEDVMCBCACHE pVmcbNstGstCache = &pVCpu->hm.s.svm.NstGstVmcbCache;
3763 pHlp->pfnPrintf(pHlp, "CPU[%u]: HM SVM nested-guest VMCB cache\n", pVCpu->idCpu);
3764 pHlp->pfnPrintf(pHlp, " fHMCachedVmcb = %#RTbool\n", pCtx->hwvirt.svm.fHMCachedVmcb);
3765 pHlp->pfnPrintf(pHlp, " u16InterceptRdCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdCRx);
3766 pHlp->pfnPrintf(pHlp, " u16InterceptWrCRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrCRx);
3767 pHlp->pfnPrintf(pHlp, " u16InterceptRdDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptRdDRx);
3768 pHlp->pfnPrintf(pHlp, " u16InterceptWrDRx = %#RX16\n", pVmcbNstGstCache->u16InterceptWrDRx);
3769 pHlp->pfnPrintf(pHlp, " u32InterceptXcpt = %#RX32\n", pVmcbNstGstCache->u32InterceptXcpt);
3770 pHlp->pfnPrintf(pHlp, " u64InterceptCtrl = %#RX64\n", pVmcbNstGstCache->u64InterceptCtrl);
3771 pHlp->pfnPrintf(pHlp, " u64IOPMPhysAddr = %#RX64\n", pVmcbNstGstCache->u64IOPMPhysAddr);
3772 pHlp->pfnPrintf(pHlp, " u64MSRPMPhysAddr = %#RX64\n", pVmcbNstGstCache->u64MSRPMPhysAddr);
3773 pHlp->pfnPrintf(pHlp, " u64TSCOffset = %#RX64\n", pVmcbNstGstCache->u64TSCOffset);
3774 pHlp->pfnPrintf(pHlp, " u32VmcbCleanBits = %#RX32\n", pVmcbNstGstCache->u32VmcbCleanBits);
3775 pHlp->pfnPrintf(pHlp, " TLBCtrl = %#RX64\n", pVmcbNstGstCache->TLBCtrl);
3776 pHlp->pfnPrintf(pHlp, " u32ASID = %#RX64\n", pVmcbNstGstCache->TLBCtrl.n.u32ASID);
3777 pHlp->pfnPrintf(pHlp, " u8TLBFlush = %#RX64\n", pVmcbNstGstCache->TLBCtrl.n.u8TLBFlush);
3778 pHlp->pfnPrintf(pHlp, " u1NestedPaging = %RTbool\n", pVmcbNstGstCache->u1NestedPaging);
3779 pHlp->pfnPrintf(pHlp, " u1LbrVirt = %RTbool\n", pVmcbNstGstCache->u1LbrVirt);
3780 pHlp->pfnPrintf(pHlp, " u64CR0 = %#RX64\n", pVmcbNstGstCache->u64CR0);
3781 pHlp->pfnPrintf(pHlp, " u64CR3 = %#RX64\n", pVmcbNstGstCache->u64CR3);
3782 pHlp->pfnPrintf(pHlp, " u64CR4 = %#RX64\n", pVmcbNstGstCache->u64CR4);
3783 pHlp->pfnPrintf(pHlp, " u64EFER = %#RX64\n", pVmcbNstGstCache->u64EFER);
3784 pHlp->pfnPrintf(pHlp, " u64DBGCTL = %#RX64\n", pVmcbNstGstCache->u64DBGCTL);
3785 pHlp->pfnPrintf(pHlp, " fVIntrMasking = %RTbool\n", pVmcbNstGstCache->fVIntrMasking);
3786 }
3787 else
3788 {
3789 if (!fSvmEnabled)
3790 pHlp->pfnPrintf(pHlp, "HM SVM is not enabled for this VM!\n");
3791 else
3792 pHlp->pfnPrintf(pHlp, "SVM feature is not exposed to the guest!\n");
3793 }
3794}
3795
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